5 Pages, 101 KB, Original
Dual J-K flip-flop with set and reset, high-performance silicon-gate CMOS
6 Pages, 94 KB, Original
6 Pages, 94 KB, Original
4 Pages, 652 KB, Scan
Dual JK Flip Flop With Set and Reset Plastic Sop Surface Mount
1 Pages, 33 KB, Original
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
1 Pages, 33 KB, Original
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
1 Pages, 33 KB, Original
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
1 Pages, 33 KB, Original
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
1 Pages, 33 KB, Original
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
20 Pages, 789 KB, Original
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SO Bulk
20 Pages, 789 KB, Original
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SO T/R
15 Pages, 91 KB, Original
IC DUAL JK F-F NEG-EDGE 16SOIC - 74HC112D,652
15 Pages, 91 KB, Original
IC DUAL JK F-F NEG-EDGE 16SOIC - 74HC112D,652
15 Pages, 91 KB, Original
IC FLIP FLOP DUAL JK NEG 16SOIC - 74HC112D,653
15 Pages, 91 KB, Original
IC DUAL JK F-F NEG-EDGE 16-SSOP - 74HC112DB,112
15 Pages, 91 KB, Original
IC DUAL JK F-F NEG-EDGE 16-SSOP - 74HC112DB,112
15 Pages, 91 KB, Original
IC DUAL JK F-F NEG-EDGE 16SSOP - 74HC112DB,118
15 Pages, 91 KB, Original
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; F<sub>max</sub>: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V
15 Pages, 91 KB, Original
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; F<sub>max</sub>: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V
15 Pages, 91 KB, Original
dual JK flip-flop with set and reset negative-edge trigger
15 Pages, 91 KB, Original
dual JK flip-flop with set and reset negative-edge trigger
6 Pages, 49 KB, Original
17 Pages, 624 KB, Original
IC DUAL F-F W/CLR/PRESET 16-SOIC - SN74HC112D
17 Pages, 624 KB, Original
IC FLIP FLOP DUAL JK NEG 16-SOIC - SN74HC112DE4
17 Pages, 624 KB, Original
IC FLIP FLOP JK TYPE DUAL 16SOIC - SN74HC112DG4
17 Pages, 624 KB, Original
IC DUAL JK NEG-EDG-TRG F-F16SOIC - SN74HC112DR
17 Pages, 624 KB, Original
IC FLIP FLOP DUAL JK NEG 16-SOIC - SN74HC112DRE4
17 Pages, 624 KB, Original
IC FLIP FLOP JK TYPE DUAL 16SOIC - SN74HC112DRG4
17 Pages, 624 KB, Original
IC FLIP FLOP DUAL JK NEG 16-SOIC - SN74HC112DT
17 Pages, 624 KB, Original
IC FLIP FLOP DUAL JK NEG 16-SOIC - SN74HC112DTE4
17 Pages, 624 KB, Original
IC FLIP FLOP JK TYPE DUAL 16SOIC - SN74HC112DTG4