1. General description
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop . It features
individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has
complementary nQ and nQ outputs. The set and reset are asynchron ous active LOW
inputs and operate independently of the clock input. The J and K inputs control the state
changes of the flip-flops as described in the mode select function table. The J and K
inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for
predictable operation. Inputs include cla mp diodes that enable the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features and benefits
Input levels:
For 74HC112: CMOS level
For 74HCT112: TTL level
Asynchronous set and rese t
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 20 0 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Ordering information
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 3 — 9 August 2016 Product data sheet
Ta ble 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC112D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT112D
74HC112DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width
5.3 mm SOT338-1
74HCT112DB
74HC112PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT112PW
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 2 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
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Fig 3. Logic diagra m (one f lip -flop)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 3 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration for SO16 Fig 5. Pin configuration for (T)SSOP16
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Table 2. Pin description
Symbol Pin Description
1CP, 2CP 1, 13 clock input (HIGH-to-LOW; edge-triggered)
1K, 2K 2, 12 data input
1J, 2J 3, 11 data input
1SD, 2SD 4, 10 set input (active LOW)
1Q, 2Q 5, 9 true flip-flop output
1Q, 2Q 6, 7 complement flip-flop output
GND 8 ground (0 V)
1RD, 2RD 15, 14 reset input (active LOW)
VCC 16 supply voltage
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 4 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
6. Functional description
[1] If nSD and nRD simultaneously go from LOW-to-HIGH, the output states are unpredictable.
H = HIGH voltage level
h = HIGH voltage level one set-up time before the HIGH-to-LOW clock transition
L = LOW voltage level
l = LOW voltage level one set-up time before the HIGH-to-LOW clock transition
q = lowercase letters indicate the state of the referenced output one set-up time before the HIGH-to-LOW clock transition
X = don’t care
= HIGH-to-LOW clock transition
7. Limiting values
[1] For SO16 packages: above 70 C, the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 C, the value of Ptot derates linearly with 5.5 mW/K.
Table 3. F un ction selection[1]
Operating modes Input Output
nSDnRDnCP nJ nK nQ nQ
Asynchronous set L H X X X H L
Asynchronous reset H L X X X L H
Undetermined L L X X X H L
Toggle H H hhqq
Load 0 (reset) H H lhLH
Load 1 (set) H H hl HL
Hold no change H H llqq
Table 4. L imiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current 0.5 V < VO< VCC +0.5V - 25 mA
ICC supply current - +50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation SO16 and (T)SSOP16 packages [1] -500mW
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 5 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC112 74HCT112 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC112
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND; VCC =6.0V - - 0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V - - 4.0 - 40 - 80 A
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 6 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
CIinput
capacitance -3.5 - - - - - pF
74HCT112
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 5.5 V - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND; VCC =5.5V - - 0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =5.5V - - 4.0 - 40 - 80 A
ICC additional
supply current per input pin; VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
nSD inputs - 50 180 - 225 - 245 A
nK inputs - 60 216 - 270 - 294 A
nRD inputs - 65 236 - 293 - 319 A
nJ, and nCP inputs - 100 360 - 450 - 490 A
CIinput
capacitance -3.5 - - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 7 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
74HC112
tpd propagation
delay nCP to nQ; see Figure 6 [2]
VCC = 2.0 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC =5V; C
L=15pF - 17 - - - - - ns
VCC = 6.0 V - 16 30 - 37 - 45 ns
nCP to nQ; see Figure 6
VCC = 2.0 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC =5V; C
L=15pF - 17 - - - - - ns
VCC = 6.0 V - 16 30 - 37 - 45 ns
nRD to nQ, nQ;
see Figure 7
VCC = 2.0 V - 58 180 - 225 - 270 ns
VCC = 4.5 V - 21 36 - 45 - 54 ns
VCC =5V; C
L=15pF - 18 - - - - - ns
VCC = 6.0 V - 17 31 - 38 - 46 ns
nSD to nQ, nQ;
see Figure 7
VCC = 2.0 V - 50 155 - 295 - 235 ns
VCC = 4.5 V - 18 31 - 39 - 47 ns
VCC =5V; C
L=15pF - 15 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 40 ns
tttransition
time nQ, nQ; see Figure 6 [3]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tWpulse width nCP HIGH or LOW;
see Figure 6
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
nSD, nRD LOW;
see Figure 7
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 8 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
trec recovery time nRD to nCP; see Figure 7
VCC = 2.0 V 80 22 - 125 - 150 - ns
VCC = 4.5 V 16 8 - 25 - 30 - ns
VCC = 6.0 V 14 6 - 21 - 26 - ns
nSD to nCP; see Figure 7
VCC = 2.0 V 80 19 - 100 - 120 - ns
VCC = 4.5 V 16 7- 20 - 24 - ns
VCC = 6.0 V 14 6- 17 - 20 - ns
tsu set-up time nJ and nK to nCP;
see Figure 6
VCC = 2.0 V 80 19 - 100 - 120 - ns
VCC = 4.5 V 16 7 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
thhold time nJ and nK to nC P;
see Figure 6
VCC = 2.0 V 0 11 - 0 - 0 - ns
VCC = 4.5 V 0 4- 0 - 0 - ns
VCC = 6.0 V 0 3- 0 - 0 - ns
fmax maximum
frequency nCP; see Figure 6
VCC = 2.0 V 6 20 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 60 - 24 - 20 - MHz
VCC =5V; C
L=15pF - 66 - - - - - MHz
VCC = 6.0 V 35 71 - 28 - 24 - MHz
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[4] -27- - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 9 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
74HCT112
tpd propagation
delay nCP to nQ; see Figure 6 [2]
VCC = 4.5 V - 21 35 - 44 - 53 ns
VCC =5V; C
L=15pF - 19 - - - - - ns
nCP to nQ; see Figure 6 [2]
VCC = 4.5 V - 23 40 - 50 - 60 ns
VCC =5V; C
L=15pF - 19 - - - - - ns
nRD to nQ, nQ;
see Figure 7
VCC = 4.5 V - 22 37 - 46 - 56 ns
VCC =5V; C
L=15pF - 19 - - - - - ns
nSD to nQ, nQ;
see Figure 7
VCC = 4.5 V - 18 32 - 40 - 48 ns
VCC =5V; C
L=15pF - 15 - - - - - ns
tttransition
time nQ, nQ; see Figure 6 [3]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width nCP HIGH or LOW;
see Figure 6
VCC = 4.5 V 16 8 - 20 - 24 - ns
nSD, nRD LOW;
see Figure 7
VCC = 4.5 V 18 10 - 23 - 27 - ns
trec recovery time nRD to nCP; see Figure 7
VCC = 4.5 V 20 11 - 25 - 30 - ns
nSD to nCP; see Figure 7
VCC = 4.5 V 20 8- 25 - 30 - ns
tsu set-up time nJ and nK to nCP;
see Figure 6
VCC = 4.5 V 16 7 - 20 - 24 - ns
thhold time nJ and nK to nC P;
see Figure 6
VCC = 4.5 V 0 7- 0 - 0 - ns
fmax maximum
frequency nCP; see Figure 6
VCC = 4.5 V 30 64 - 24 - 20 - MHz
VCC =5V; C
L=15pF - 70 - - - - - MHz
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 10 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTLH.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[4] -30- - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 11 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Clock propagation delays, output transition time, pulse width, set-up, hold times, and maximum
frequency
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 12 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Set and reset propagation delays, pulse widths and recovery time
DDD
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Table 8. Mea surement points
Type Input Output
VMVM
74HC112 0.5VCC 0.5VCC
74HCT112 1.3 V 1.3 V
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 13 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 8. Test circuit for measuring switching times
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Table 9. Test data
Type Input Load Test
VItr, tfCL
74HC112 VCC 6ns 15pF, 50 pF t
PLH, tPHL
74HCT112 3 V 6 ns 15 pF, 50 pF tPLH, tPHL
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 14 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
12. Package outline
Fig 9. Package outline SOT109-1 (SO16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 15 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
Fig 10. Package outline SOT338-1 (SSOP16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 16 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
Fig 11. Package outline SOT403-1 (TSSOP16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 17 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
13. Abbreviations
14. Revision history
Table 10 . Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sh eet status Change notice Supersedes
74HC_HCT112 v.3 20160809 Product data sheet - 74HC_HCT112_CNV v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Type numbers 74HC112N and 74HCT112N removed.
74HC_HCT112_CNV v.2 19980610 Product specification - -
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 18 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsisten cy or conf lict with the short dat a sheet, the
full data sheet shall pre va il.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however ,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associa ted with their
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74HC_HCT112 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 9 August 2016 19 of 20
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without Nexperia’s warranty of the
product for such au tomotive applications, use and specifi cations, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting from customer design an d
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Translations — A non-English (translated) versio n of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74HC112; 74HCT112
Dual JK flip-flop with set and r eset; negative-edge trigger
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions . . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Contact information. . . . . . . . . . . . . . . . . . . . . 19
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
09 August 2016
