TECHNICAL DATA
107
Dual J-K Flip-Flop
wi th Set and Reset
High-Perform ance Silicon-Gate C MOS
The IN74HC112 is identical in pinout to the LS/ALS112. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
IN74HC112
ORDERING INFORMATION
IN74HC112N Plastic
IN74HC112D SOIC
TA = -55° to 125° C for all packages
FUNCTION TABLE
Inputs Outputs
Set Reset Clock J K Q Q
LH XXXHL
HL XXXLH
LL XXXL
*L*
H H L L No Change
HH LHLH
HH HLHL
H H H H Toggle
H H L X X No Cha nge
H H H X X No Cha nge
H H X X No Change
* Both output will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
PIN ASSIGNMENT
IN74HC112
108
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types -55 +125 °C
tr, tfInput Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
Thi s device contains p rote ction c ircuitr y to guard a gainst damage due to hi gh static voltage s or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
IN74HC112
109
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C≤125
°CUnit
VIH Minimum High-Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Max imum Low -
Level Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH Minimum High-Level
Output Voltage VIN=VIH or VIL
IOUT ≤ 20 µA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA 4.5
6.0 3.98
5.48 3.84
5.34 3.7
5.2
VOL Max imum Low-Level
Output Voltage VIN= VIL or VIH
IOUT ≤ 20 µA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIL or VIH
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA 4.5
6.0 0.26
0.26 0.33
0.33 0.4
0.4
IIN Maximum Inpu t
Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiesc ent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA6.0 4.0 40 80 µA
IN74HC112
110
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
-55°C≤85°C≤125°CUnit
fmax Maximum Clock Fr equency (5 0% Duty Cycle)
(Figures 1 and 4) 2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH, tPHL Maximum Prop agation Delay, Clock to Q or Q
(Figures 1 and 4) 2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tPLH, tPHL Maximum Propagation Delay , Reset to Q or Q
(Figures 2 and 4) 2.0
4.5
6.0
155
31
26
195
39
33
235
47
40
ns
tPLH, tPHL Maximum Propagation Delay ,Set to Q or Q
(Figures 2 and 4) 2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4) 2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Flip-Flop) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumpti on: PD=CPDVCC2f+ICCVCC
35 pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C to-5 5°C≤85°C≤125°CUnit
tSU Minimum Setup Time,J or K
to Clock (Fi gure 3) 2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
thMinimum Ho ld Time, Clock
to J or K (Figure 3) 2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
trec Minimum Recovery Time, Set
or Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
twMinimum Pulse Width, Clo ck
(Figure 1) 2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
twMinimum Pulse Width, Set or
Reset (Figure 2) 2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tfMaximum Input Rise and Fall
Times ( F igure 1) 2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
IN74HC112
111
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
