SL74HC112
System Logic
Semiconductor
SLS
Dual J-K Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The SL74HC112 is identical in pinout to the LS/ALS112. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC112N Plastic
SL74HC112D SOIC
TA = -55° to 125° C for all packages
FUNCTION TABLE
Inputs Outputs
Set Reset Clock J K Q Q
L H X X X H L
H L X X X L H
L L X X X L* L*
H H L L No Change
H H L H L H
H H H L H L
H H H H Toggle
H H L X X No Change
H H H X X No Change
H H X X No Change
* Both output will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
PIN ASSIGNMENT
SL74HC112
System Logic
Semiconductor
SLS
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC).
Unused outputs must be left open.
SL74HC112
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C ≤125
°C Unit
VIH Minimum High-Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA 2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Maximum Low -Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA 2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH Minimum High-Level
Output Voltage VIN=VIH or VIL
IOUT ≤ 20 µA 2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL Maximum Low-Level
Output Voltage VIN= VIL or VIH
IOUT ≤ 20 µA 2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIL or VIH
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN Maximum Input
Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA 6.0 4.0 40 80 µA
SL74HC112
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
-55°C ≤85°C ≤125°C Unit
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4) 2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4) 2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tPLH, tPHL Maximum Propagation Delay , Reset to Q or Q
(Figures 2 and 4) 2.0
4.5
6.0
155
31
26
195
39
33
235
47
40
ns
tPLH, tPHL Maximum Propagation Delay ,Set to Q or Q (Figures
2 and 4) 2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4) 2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Flip-Flop) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC 35 pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C to-55°C ≤85°C ≤125°C Unit
tSU Minimum Setup Time,J or K to
Clock (Figure 3) 2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th Minimum Hold Time, Clock to
J or K (Figure 3) 2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
trec Minimum Recovery Time, Set
or Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tw Minimum Pulse Width, Clock
(Figure 1) 2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw Minimum Pulse Width, Set or
Reset (Figure 2) 2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf Maximum Input Rise and Fall
Times (Figure 1) 2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
SL74HC112
System Logic
Semiconductor
SLS
6.0 400 400 400
SL74HC112
System Logic
Semiconductor
SLS
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
