For additional information and latest specifications, see our website: www.triquint.com 3
Data Sheet NetLight 1417G5 and 1417H5-Type
March 2003 ATM/SONET/SDH Transceivers with Clock Recovery
Transmitter
11 VCCT Transmitter Power Supply. NA
12 VEET Transmitter Signal Ground. NA
13 TDIS Transmitter Disable. LVTTL
14 TD+ Transmitter Data In. PECL
15 TD– Transmitter Data In Bar. PECL
16 VEET Transmitter Signal Ground. NA
17 BMON(–) Laser Diode Bias Current Monitor—Negative End. The laser bias current
is accessible as a dc-voltage by measuring the voltage developed across pins
17 and 18.
NA
18 BMON(+) Laser Diode Bias Current Monitor—Positive End. See pin 17 description. NA
19 PMON(–) Laser Diode Optical Power Monitor—Negative End. The back-facet diode
monitor current is accessible as a dc-voltage by measuring the voltage devel-
oped across pins 19 and 20.
NA
20 PMON(+) Laser Diode Optical Power Monitor—Positive End. See pin 19 description. NA
Pin
Number Symbol Name/Description Logic
Family
Electrostatic Discharge
Caution: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow EIA ® stan-
dard EIA-625.
Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD. TriQuint employs a human-body model (HBM) for
ESD-susceptibility testing and protection-design evalu-
ation. ESD voltage thresholds are dependent on the
critical parameters used to define the model. A stan-
dard HBM (resistance = 1.5 kΩ, capacitance = 100 pF)
is widely used and, therefore, can be used for compari-
son purposes. The HBM ESD threshold established for
the 1417G5 and 1417H5 transceivers is ±1000 V.
Application Information
The 1417 receiver section is a highly sensitive fiber-
optic receiver. Although the data outputs are digital
logic levels (PECL), the device should be thought of as
an analog component. When laying out system appli-
cation boards, the 1417 transceiver should receive the
same type of consideration one would give to a sensi-
tive analog component.
Printed-Wiring Board Layout Considerations
A fiber-optic receiver employs a very high-gain, wide-
bandwidth transimpedance amplifier. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the receiver is operating near its sensi-
tivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor-
mance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printed-
wiring board.
At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multi-
layer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.
Multilayer construction also permits the routing of sen-
sitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitter inputs and clock lines
should be routed as far away as possible from the
receiver pins.
Pin Information (continued)
Table 1. Transceiver Pin Descriptions (continued)