General Description
The MAX15012/MAX15013 high-frequency, 175V half-
bridge, n-channel MOSFET drivers drive high- and low-
side MOSFETs in high-voltage applications. These
drivers are independently controlled and their 35ns typ-
ical propagation delay, from input to output, are
matched to within 2ns (typ). The high-voltage operation
with very low and matched propagation delay between
drivers, and high source/sink current capabilities make
these devices suitable for the high-power, high-fre-
quency telecom power converters. A reliable on-chip
bootstrap diode connected between VDD and BST
eliminates the need for an external discrete diode.
The MAX15012A/C and MAX15013A/C offer both nonin-
verting drivers (see the Selector Guide). The
MAX15012B/D and MAX15013B/D offer a noninverting
high-side driver and an inverting low-side driver. The
MAX15012A/B/C/D feature CMOS (VDD/2) logic inputs.
The MAX15013A/B/C/D feature TTL logic inputs. The
drivers are available in the industry-standard 8-pin SO
footprint and pin configuration and a thermally
enhanced 8-pin SO package. All devices operate over
the -40°C to +125°C automotive temperature range.
Applications
Telecom Half-Bridge Power Supplies
Two-Switch Forward Converters
Full-Bridge Converters
Active-Clamp Forward Converters
Power-Supply Modules
Motor Control
Features
♦HIP2100/HIP2101 Pin Compatible (MAX15012A/C
and MAX15013A/C)
♦Up to 175V Input Operation
♦8V to 12.6V VDD Input Voltage Range
♦2A Peak Source and Sink Current Drive Capability
♦35ns Typical Propagation Delay
♦Guaranteed 8ns Propagation Delay Matching
Between Drivers
♦Up to 500kHz Switching Frequency
♦Available in CMOS (VDD/2) or TTL Logic-Level
Inputs with Hysteresis
♦Up to 14V Logic Inputs Independent of Input
Voltage
♦Low 2.5pF Input Capacitance
♦Low 70µA Supply Current
♦Versions Available with Combination of
Noninverting and Inverting Drivers (MAX15012B/D
and MAX15013B/D)
♦Available in Industry-Standard 8-Pin SO and
Thermally Enhanced SO Packages
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
________________________________________________________________ Maxim Integrated Products 1
PART TEMP RANGE PIN-
PACKAGE
PKG
CODE
MAX15012AASA+ -40°C to +125°C 8 SO S8-5
MAX15012BASA+ -40°C to +125°C 8 SO S8-5
MAX15012CASA+* -40°C to +125°C 8 SO-EP** S8E+14
MAX15012DASA+* -40°C to +125°C 8 SO-EP** S8E+14
Ordering Information
PART HIGH-SIDE DRIVER LOW-SIDE DRIVER LOGIC LEVELS PIN COMPATIBLE
MAX15012AASA+ Noninverting Noninverting CMOS (VDD/2) HIP 2100IB
MAX15012BASA+ Noninverting Inverting CMOS (VDD/2) —
MAX15012CASA+ Noninverting Noninverting CMOS (VDD/2) HIP 2100IB
MAX15012DASA+ Noninverting Inverting CMOS (VDD/2) —
MAX15013AASA+ Noninverting Noninverting TTL HIP 2101IB
MAX15013BASA+ Noninverting Inverting TTL —
MAX15013CASA+ Noninverting Noninverting TTL HIP 2101IB
MAX15013DASA+ Noninverting Inverting TTL —
Selector Guide
19-0530; Rev 1; 12/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ordering Information continued at end of data sheet.
+Denotes lead-free package.
*Future product—contact factory for availability.
**EP = Exposed pad.
Pin Configurations and Typical Operating Circuit appear at
the end of data sheet.
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = VBST = +8V to +12.6V, VHS = GND = 0V, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at VDD =
VBST = +12V and TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND, unless otherwise noted.)
VDD, IN_H, IN_L......................................................-0.3V to +14V
DL...............................................................-0.3V to (VDD + 0.3V)
HS............................................................................-5V to +180V
DH to HS.....................................................-0.3V to (VDD + 0.3V)
BST to HS ...............................................................-0.3V to +14V
dV/dt at HS ........................................................................50V/ns
Continuous Power Dissipation (TA= +70°C)
8-Pin SO (derate 5.9mW/°C above +70°C)...............470.6mW
8-Pin SO-EP (derate 19.2mW/°C above +70°C) .....1538.5mW
Junction-to-Case Thermal Resistance (θJC)(Note 1)
8-Pin SO .......................................................................40°C/W
8-Pin SO-EP....................................................................6°C/W
Junction-to-Ambient Thermal Resistance (θJA)(Note 1)
8-Pin SO .....................................................................170°C/W
8-Pin SO-EP..................................................................52°C/W
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
POWER SUPPLIES
Operating Supply Voltage VDD (Notes 3 and 4) 8.0
12.6
V
VDD Quiescent Supply Current
(No Switching) IDD IN_H = IN_L = GND (for A/C versions),
IN_H = GND, IN_L = VDD (for B/D versions)
70
140
µA
VDD Operating Supply Current IDDO fSW = 500kHz, VDD = +12V 3 mA
BST Quiescent Supply Current IBST IN_H = IN_L = GND (for A/C versions),
IN_H = GND, IN_L = VDD (for B/D versions)
15 40 µA
BST Operating Supply Current IBSTO fSW = 500kHz, VDD = VBST = +12V 3 mA
UVLO (VDD to GND)
UVLOVDD
VDD rising 6.5 7.3 8.0 V
UVLO (BST to HS)
UVLOBST
BST rising 6.0 6.9 7.8 V
UVLO Hysteresis 0.5 V
LOGIC INPUT
MAX15012_, CMOS (VDD/2) version 0.67 x
VDD
0.55 x
VDD
Input-Logic High VIH_
MAX15013_, TTL version 2
1.65
V
MAX15012_, CMOS (VDD/2) version 0.4 x
VDD
0.33 x
VDD
Input-Logic Low VIL_
MAX15013_, TTL version 1.4 0.8
V
MAX15012_, CMOS (VDD/2) version 1.6
Logic-Input Hysteresis VHYS MAX15013_, TTL version
0.25
V
*Per JEDEC 51 Standard Multilayer board.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JE5D51-7, using a four-
layer board. For detailed information on package thermal considerations, see www.maxim-ic.com/thermal-tutorial.
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VBST = +8V to +12.6V, VHS = GND = 0V, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at VDD =
VBST = +12V and TA= +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VIN_L = VDD for MAX15012B/MAX15012D/
MAX15013B/MAX15013D
VIN_H = 0V
Logic-Input Current I_IN
VIN_L = 0V for MAX15012A/MAX15012C/
MAX15013A/MAX15013C
-1
+0.001
+1 µA
IN_H to GND
IN_L to VDD for MAX15012B/MAX15012D/
MAX15013B/MAX15013D
Input Resistance RIN
IN_L to GND for MAX15012A/MAX15012C/
MAX15013A/MAX15013C
1MΩ
Input Capacitance CIN 2.5 pF
HIGH-SIDE GATE DRIVER
HS Maximum Voltage
VHS_MAX
VDD ≤ 10.5V (Note 4)
175
V
BST Maximum Voltage
VBST_MAX
VDD ≤ 10.5V (Note 4)
189
V
TA = +25°C 2.5 3.3
Driver Output Resistance
(Sourcing)
RON_HP
VDD = 12V, IDH = 100mA
(sourcing) TA = +125°C 3.5 4.6 Ω
TA = +25°C 2.1 2.8
Driver Output Resistance
(Sinking)
RON_HN
VDD = 12V, IDH = 100mA
(sinking) TA = +125°C 3.2 4.2 Ω
DH Reverse Current (Latchup
Protection) (Note 5)
400
mA
Power-Off Pulldown Clamp
Voltage
VBST = 0V or floating, IDH = 1mA (sinking) 0.94 1.16
V
Peak Output Current (Sourcing) CL = 10nF, VDH = 0V 2 A
Peak Output Current (Sinking)
IDH_PEAK
CL = 10nF, VDH = 12V 2 A
LOW-SIDE GATE DRIVER
TA = +25°C 2.5 3.3
Driver Output Resistance
(Sourcing)
RON_LP
VDD = 12V, IDL = 100mA
(sourcing) TA = +125°C 3.5 4.6 Ω
TA = +25°C 2.1 2.8
Driver Output Resistance
(Sinking)
RON_LN
VDD = 12V, IDL = 100mA
(sinking) TA = +125°C 3.2 4.2 Ω
Reverse Current at DL (Latchup
Protection) (Note 5)
400
mA
Power-Off Pulldown Clamp
Voltage VDD = 0V or floating, IDL = 1mA (sinking)
0.95 1.16
V
Peak Output Current (Sourcing) IPK_LP CL = 10nF, VDL = 0V 2 A
Peak Output Current (Sinking) IPK_LN CL = 10nF, VDL = 12V 2 A
Forward Voltage Drop VFIBST = 100mA
0.91 1.11
V
Turn-On and Turn-Off Time tRIBST = 100mA 40 ns
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
4 _______________________________________________________________________________________
Note 2: All devices are 100% tested at TA= +125°C. Limits over temperature are guaranteed by design.
Note 3: Ensure that the VDD-to-GND or BST-to-HS transient voltage does not exceed 13.2V.
Note 4: Maximum operating supply voltage (VDD) reduces linearly from 12.6V to 10.5V with its maximum voltage (VHS_MAX) increasing
from 125V to 175V. See the Typical Operating Characteristics and Applications Information sections.
Note 5: Guaranteed by design, not production tested.
Note 6: See the Minimum Input Pulse Width section.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VBST = +8V to +12.6V, VHS = GND = 0V, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at VDD =
VBST = +12V and TA= +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
SWITCHING CHARACTERISTICS FOR HIGH- AND LOW-SIDE DRIVERS (VDD = VBST = +12V)
CL = 1000pF 7
CL = 5000pF 33
Rise Time tR
CL = 10,000pF 65
ns
CL = 1000pF 7
CL = 5000pF 33Fall Time tF
CL = 10,000pF 65
ns
CMOS 30 55
Turn-On Propagation Delay Time
tD_ON Figure 1, CL = 1000pF
(Note 5) TTL 35 63 ns
CMOS 30 55
Turn-Off Propagation Delay Time
tD_OFF Figure 1, CL = 1000pF
(Note 5) TTL 35 63 ns
Delay Matching Between Driver-
Low and Driver-High tMATCH CL = 1000pF, Figure 1 (Note 5) 2 8 ns
Internal Nonoverlap 1ns
VDD = VBST = 12V
135
Minimum Pulse Width Input Logic
(Note 6) tPW-min VDD = VBST = 8V
170
ns
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
_______________________________________________________________________________________ 5
UNDERVOLTAGE LOCKOUT
(VDD AND VBST RISING) vs. TEMPERATURE
MAX15012/13 toc01
TEMPERATURE (°C)
UVLO (V)
1109565 80-10 5 20 35 50-25
6.6
6.7
6.8
6.9
7.0
7.1
7.2
7.3
7.4
7.5
6.5
-40 125
UVLOVDD
UVLOBST
VDD AND BST UNDERVOLTAGE LOCKOUT
HYSTERESIS vs. TEMPERATURE
MAX15012/13 toc02
TEMPERATURE (°C)
UVLO HYSTERESIS (V)
1109565 80-10 5 20 35 50-25
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
-40 125
UVLOBST
HYSTERESIS
UVLOVDD
HYSTERESIS
IDD vs. VDD
MAX15012/13 toc03
4ms/div
VDD
2V/div
IDD
50μA/div
0μA
0V
IN_H = GND
IN_L = VDD
IDDO + IBSTO vs. VDD
(fSW = 250kHz)
MAX15012/13 toc04
VDD (V)
IDDO + IBSTO (mA)
1210 11345678912
1.0
0.8
0.6
0.4
0.2
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
0
013
0
60
40
20
80
100
120
140
160
180
200
0.5 0.70.6 0.8 0.9 1.0 1.1
INTERNAL BST DIODE
(I-V) CHARACTERISTICS
MAX15012/13 toc05
VDD - VBST (V)
IDIODE (mA)
TA = +125°C
TA = +25°C
TA = 0°C
TA = -40°C
0
60
40
20
80
100
120
140
160
0426
810 12
VDD QUIESCENT CURRENT
vs. VDD (NO SWITCHING)
MAX15012/13 toc06
VDD (V)
IDD (μA)
TA = -40°C
TA = +25°C
VDD = VBST
VHS = GND
IN_H = GND
IN_L = VDD
TA = +125°C
0
6
3
9
12
15
18
21
0426810153 7 9 1112131415
BST QUIESCENT CURRENT
vs. BST VOLTAGE
MAX15012/13 toc07
VBST (V)
IBST (μA)
VBST = VDD + 1V,
NO SWITCHING
TA = +125°C
TA = -40°C, TA = 0°C, TA = +25°C
Typical Operating Characteristics
(Typical values are at VDD = VBST = +12V and TA= +25°C, unless otherwise specified.)
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
6 _______________________________________________________________________________________
VDD AND BST OPERATING SUPPLY
CURRENT vs. FREQUENCY
MAX15012/13 toc08
FREQUENCY (kHz)
IDDO + IBSTO (mA)
900700 800200 300 400 500 600100
1
2
3
4
5
6
7
8
9
10
0
0 1000
CL = 0
DH OR DL OUTPUT LOW VOLTAGE
vs. TEMPERATURE
MAX15012/13 toc09
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (V)
1109565 80-10 520 35 50-25
0.12
0.14
0.16
0.18
0.20
0.24
0.28
0.32
0.34
0.22
0.26
0.30
0.10
-40 125
SINKING 100mA
DH OR DL FALL TIME
vs. TEMPERATURE (CLOAD = 10nF)
MAX15012/13 toc12
TEMPERATURE (°C)
tF (ns)
1109565 80-10 5 20 35 50-25
10
20
30
40
50
70
110
100
90
120
60
80
0
-40 125
VDD = VBST = 8V
VDD = VBST = 12V
DH OR DL RISE PROPAGATION DELAY
vs. TEMPERATURE
MAX15012/13 toc13
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
1109565 80-10 5 20 35 50-25
5
10
15
20
25
35
55
60
30
45
50
40
0
-40 125
DH
DL
PEAK DH AND DL
SOURCE/SINK CURRENT
MAX15012/13 toc10
1μs/div
DH OR DL
5V/div
SINK AND SOURCE
CURRENT
2A/div
CL = 100nF
DH OR DL RISE TIME
vs. TEMPERATURE (CL = 10nF)
MAX15012/13 toc11
TEMPERATURE (°C)
tR (ns)
1109565 80-10 5 20 35 50-25
12
24
36
48
60
84
108
120
72
96
0
-40 125
VDD = VBST = 8V
VDD = VBST = 12V
Typical Operating Characteristics (continued)
(Typical values are at VDD = VBST = +12V and TA= +25°C, unless otherwise specified.)
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
_______________________________________________________________________________________ 7
DH OR DL FALL PROPAGATION DELAY
vs. TEMPERATURE
MAX15012/13 toc14
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
1109565 80-10 520 35 50-25
5
10
15
20
25
35
55
60
30
45
50
40
0
-40 125
DH
DL
VHS_MAX vs. VDD_MAX
MAX15012/13 toc15
VDD_MAX (V)
VHS_MAX (V)
10.5
175
125
0
8 12.6
DELAY MATCHING (DH/DL RISING)
MAX15012/13 toc16
10ns/div
INPUT
5V/div
DH/DL
5V/div
CL = 0
DELAY MATCHING (DH/DL FALLING)
MAX15012/13 toc17
10ns/div
CL = 0
INPUT
5V/div
DH/DL
5V/div
DH/DL RESPONSE TO VDD GLITCH
MAX15012/13 toc18
40μs/div
DH
10V/div
DL
10V/div
VDD
10V/div
INPUT
5V/div
Typical Operating Characteristics (continued)
(Typical values are at VDD = VBST = +12V and TA= +25°C, unless otherwise specified.)
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
8 _______________________________________________________________________________________
Figure 1. Timing Characteristics for Noninverting and Inverting Logic Inputs
VIH
VIL
90%
10%
tF
IN_H
DH
tD_ON3
tD_OFF3
VIH
VIL
90%
10%
VIH
VIL
tR
tR
tF
IN_L
(MAX15012A/C
MAX15013A/C)
IN_L
(MAX15012B/D
MAX15013B/D)
DL
tD_ON1
tD_ON2
tD_OFF2
tD_OFF1
tMATCH = (tD_ON3 - tD_ON1) or (tD_OFF3 - tD_OFF1) FOR "A/C" VERSION
tMATCH = (tD_ON3 - tD_ON2) or (tD_OFF3 - tD_OFF2) FOR "B/D" VERSION
PIN NAME FUNCTION
1V
DD Power Input. Bypass VDD to GND with a parallel combination of 0.1µF and 1µF ceramic capacitors.
2 BST Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.
3 DH High-Side-Gate Driver Output. Driver output for the high-side MOSFET gate.
4 HS Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.
5 IN_H High-Side Noninverting Logic Input
6 IN_L Low-Side Noninverting Logic Input (MAX15012A/C and MAX15013A/C). Low-side inverting logic
input (MAX15012B/D and MAX15013B/D).
7 GND Ground. Use GND as a return path to the DL driver output and IN_H/IN_L inputs.
8 DL Low-Side-Gate Driver Output. Drives low-side MOSFET gate.
—EP
Exposed Pad. Internally connected to GND. Externally connect the exposed pad to a large ground
plane to aid in heat dissipation (MAX15012C/D and MAX15013C/D only).
Pin Description
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
_______________________________________________________________________________________ 9
Detailed Description
The MAX15012/MAX15013 are 175V/2A high-speed,
half-bridge MOSFET drivers that operate from a supply
voltage of +8V to +12.6V. The drivers are intended to
drive a high-side switch without any isolation device
like an optocoupler or drive transformer. The high-side
driver is controlled by a TTL/CMOS logic signal refer-
enced to ground. The 2A source and sink drive capa-
bility is achieved by using low RDS_ON, p- and
n-channel driver output stages. The BiCMOS process
allows extremely fast rise/fall times and low propaga-
tion delays. The typical propagation delay from the
logic-input signal to the driver output is 35ns with a
matched propagation delay of 2ns typical. Matching
these propagation delays is as important as the
absolute value of the delay itself. The high 175V input
voltage range allows plenty of margin above the 100V
transient specification per telecom standards.
The maximum operating supply voltage (VDD) must be
reduced linearly from 12.6V to 10.5V when the maxi-
mum voltage (VHS_MAX) increases from 125V to 175V.
See the Typical Operating Characteristics.
Undervoltage Lockout
Both the high- and low-side drivers feature undervolt-
age lockout (UVLO). The low-side driver’s UVLOLOW
threshold is referenced to GND and pulls both driver
outputs low when VDD falls below 6.8V. The high-side
driver has its own UVLO threshold (UVLOHIGH), refer-
enced to HS, and pulls DH low when BST falls below
6.4V with respect to HS.
During turn-on, once VDD rises above its UVLO thresh-
old, DL starts switching and follows the IN_L logic input.
At this time, the bootstrap capacitor is not charged and
the BST-to-HS voltage is below UVLOBST. For synchro-
nous buck and half-bridge converter topologies, the
bootstrap capacitor can charge up in one cycle and nor-
mal operation begins in a few microseconds after the
BST-to-HS voltage exceeds UVLOBST. In the two-switch
forward topology, the BST capacitor takes some time (a
few hundred microseconds) to charge and increase its
voltage above UVLOBST.
The typical hysteresis for both UVLO thresholds is 0.5V.
The bootstrap capacitor value should be selected care-
fully to avoid unintentional oscillations during turn-on
and turn-off at the DH output. Choose the capacitor
value about 20 times higher than the total gate capaci-
tance of the MOSFET. Use a low-ESR-type X7R dielec-
tric ceramic capacitor at BST (typically a 0.1µF ceramic
capacitor is adequate) and a parallel combination of
1µF and 0.1µF ceramic capacitors from VDD to GND.
The high-side MOSFET’s continuous on-time is limited
due to the charge loss from the high-side driver’s qui-
escent current. The maximum on-time is dependent on
the size of CBST, IBST (40µA max), and UVLOBST.
Output Driver
The MAX15012/MAX15013 have low 2.5ΩRDS_ON p-
channel and n-channel devices (totem pole) in the out-
put stage. This allows for a fast turn-on and turn-off of the
high gate-charge switching MOSFETs. The peak source
and sink current is typically 2A. Propagation delays from
the logic inputs to the driver outputs are matched to
within 8ns. The internal p- and n-channel MOSFETs have
a 1ns break-before-make logic to avoid any cross con-
duction between them. This internal break-before-make
logic eliminates shoot-through currents reducing the
operating supply current as well as the spikes at VDD.
See the Minimum Input Pulse Width section to under-
stand the effects of propagation delays on DH and DL.
The DL voltage is approximately equal to VDD, the DH-
to-HS voltage is approximately equal to VDD minus a
diode drop, when they are in a high state and to zero
when in a low state. The driver RDS_ON is lower at higher
VDD. Lower RDS_ON means higher source and sink cur-
rents and faster switching speeds.
Internal Bootstrap Diode
An internal diode connects from VDD to BST and is used
in conjunction with a bootstrap capacitor externally con-
nected between BST and HS. The diode charges the
capacitor from VDD when the DL low-side switch is on
and isolates VDD when HS is pulled high as the high-
side driver turns on (see the Typical Operating Circuit).
The internal bootstrap diode has a typical forward volt-
age drop of 0.9V and has a 10ns typical turn-off/turn-on
time. For lower voltage drops from VDD to BST, connect
an external Schottky diode between VDD and BST.
Driver Logic Inputs (IN_H, IN_L)
The MAX15012A/B/C/D are CMOS (VDD/2) logic-input
drivers while the MAX15013A/B/C/D have TTL-compati-
ble logic inputs. The logic-input signals are independent
of VDD. For example, the IC can be powered by a 10V
supply while the logic inputs are provided from a 12V
CMOS logic. Also, the logic inputs are protected against
voltage spikes up to 14V, regardless of the VDD voltage.
The TTL and CMOS logic inputs have 250mV and 1.6V
hysteresis, respectively, to avoid double pulsing during
transition. The logic inputs are high-impedance pins and
should not be left floating. The low 2.5pF input capaci-
tance reduces loading and increases switching speed.
The noninverting inputs are pulled down to GND and the
inverting inputs are pulled up to VDD internally using a
1MΩresistor. The PWM output from the controller must
assume a proper state while powering up the device.
With the logic inputs floating, the DH and DL outputs pull
low as VDD rises up above the UVLO threshold.
MAX15012/MAX15013
Minimum Input Pulse Width
The MAX15012/MAX15013 use a single-shot level-shifter
architecture to achieve low propagation delay. Typical
level shifter architecture causes a minimum (high or low)
pulse width (tDmin) at the output that may be higher than
the logic-input pulse width. For the MAX15012/
MAX15013 devices, the DH minimum high pulse-width
(tDmin-DH-H) is lower than the DL minimum low pulse
width (tDmin-DL-L) to avoid any shoot-through in the
absence of external BBM delay during the narrow pulse
at low duty cycle. See Figure 2.
At high duty cycle (close to 100%), the DH minimum low
pulse width (tDmin-DH-L) must be higher than the DL min-
imum low pulse width (tDmin-DL-L) to avoid the overlap
and shoot-through. See Figure 3. In case of the
MAX15012/MAX15013, there is a possibility of about
40ns overlap if an external BBM delay is not provided. It
is recommended to add external delay in the INH path
so that the minimum low pulse width seen at INH is
always longer than tPW-min. See the Electrical
Characteristics table for the typical values of tPW-min.
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
10 ______________________________________________________________________________________
Figure 2. Minimum Pulse-Width Behavior for Narrow Duty-Cycle Input (On-Time < tPW-min)
PW-MIN
DH
DL
tDMIN-DH-H
tDMIN-DL-L
INH
INL
DH
HS
N
DL N
VIN
VOUT
VDD
MAX15012B/
MAX15012D/
MAX15013B/
MAX15013D
PW-MIN
IN-BUILT
DEAD TIME
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
______________________________________________________________________________________ 11
Figure 3. Minimum Pulse-Width Behavior for High Duty-Cycle Input (Off-Time < tPW-min)
PW-MIN
DH
DL
INH
INL
DH
HS
N
DL N
VIN
VOUT
VDD
EXTERNAL
BBM DELAY
MAX15012B/
MAX15012D/
MAX15013B/
MAX15013D
PW-MIN
INH
INL
DH
HS
N
DL N
VIN
VOUT
VDD
EXTERNAL
BBM DELAY
MAX15012A/C
MAX15013A/C
PW-MIN
tDMIN-DH-L
tDMIN-DL-H
EXTERNAL
BBM DELAY
POTENTIAL
OVERLAP TIME
MAX15012/MAX15013
Applications Information
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX15012/MAX15013. Peak supply and output cur-
rents may exceed 4A when both drivers are driving
large external capacitive loads in-phase. Supply drops
and ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition
times. Ground shifts due to insufficient device ground-
ing may also disturb other circuits sharing the same AC
ground return path. Any series inductance in the VDD,
DH, DL, and/or GND paths can cause oscillations due
to the very high di/dt when switching the MAX15012/
MAX15013 with any capacitive load. Place one or more
0.1µF ceramic capacitors in parallel as close to the
device as possible to bypass VDD to GND. Use a
ground plane to minimize ground return resistance and
series inductance. Place the external MOSFET as close
as possible to the MAX15012/MAX15013 to further min-
imize board inductance and AC path resistance.
Power Dissipation
Power dissipation in the MAX15012/MAX15013 is pri-
marily due to power loss in the internal boost diode and
the nMOS and pMOS FETs.
For capacitive loads, the total power dissipation for the
device is:
where CLis the combined capacitive load at DH and
DL. VDD is the supply voltage and fSW is the switching
frequency of the converter. PDincludes the power dis-
sipated in the internal bootstrap diode. The internal
power dissipation reduces by PDIODE, if an external
bootstrap Schottky diode is used. The power dissipa-
tion in the internal boost diode (when driving a capaci-
tive load) is the charge through the diode per switching
period multiplied by the maximum diode forward volt-
age drop (Vf= 1V).
The total power dissipation when using the internal
boost diode is PDand, when using an external
Schottky diode, is PD- PDIODE. The total power dissi-
pated in the device must be kept below the maximum
of 0.471W for the 8-pin SO package at TA= +70°C
ambient.
Layout Information
The MAX15012/MAX15013 drivers source and sink
large currents to create very fast rise and fall edges at
the gates of the switching MOSFETs. The high di/dt can
cause unacceptable ringing if the trace lengths and
impedances are not well controlled. Use the following
PC board layout guidelines when designing with the
MAX15012/MAX15013:
• It is important that the VDD voltage (with respect to
ground) or BST voltage (with respect to HS) does
not exceed 13.2V. Voltage spikes higher than 13.2V
from VDD to GND or BST to HS can damage the
device. Place one or more low ESL 0.1µF decou-
pling ceramic capacitors from VDD to GND, and
from BST to HS as close as possible to the part. The
ceramic decoupling capacitors should be at least 20
times the gate capacitance being driven.
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from gate
to source when the gate is being pulled low. The
active current loop is from the MOSFET driver output
(DL or DH) to the MOSFET gate, to the MOSFET
source, and to the return terminal of the MOSFET dri-
ver (either GND or HS). When the gate of the MOSFET
is being pulled high, the active current loop is from
the MOSFET driver output, (DL or DH), to the
MOSFET gate, to the MOSFET source, to the return
terminal of the drivers decoupling capacitor, to the
positive terminal of the decoupling capacitor, and to
the supply connection of the MOSFET driver. The
decoupling capacitor is either the flying capacitor
connected between BST and HS or the decoupling
capacitor for VDD. Care must be taken to minimize the
physical length and the impedance of these AC cur-
rent paths.
PCV fV
DIODE DH DD SW f
≅×
()
××− 1
PCV f I I V
D L DD SW DDO BSTO DD
=× ×
⎛
⎝⎞
⎠++
()
×
2
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
12 ______________________________________________________________________________________
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
______________________________________________________________________________________ 13
Typical Application Circuits
Figure 4. MAX15012A/MAX15013A Half-Bridge Conversion
MAX15012A/C
MAX15013A/C
VOUT
N
N
VDD = 8V TO 12.6V VIN = 0 TO 175V*
VDD BST
IN_H
IN_L
GND
DL
DH
HS
PWM
CONTROLLER
PIN COMPATIBLE WITH THE HIP2100/HIP2101
*DERATE VDD IF VIN INCREASES ABOVE 125V. SEE NOTE 3 IN THE ELECTRICAL CHARACTERISTICS.
Figure 5. Two-Switch Forward Conversion
MAX15012A/C
MAX15013A/C
N
N
VDD = 8V TO 12.6V VIN = 0 TO 175V*
VOUT
VDD BST
IN_H
IN_L
GND
DL
DH
HS
PWM
CBST
*DERATE VDD IF VIN INCREASES ABOVE 125V. SEE NOTE 3 IN THE ELECTRICAL CHARACTERISTICS.
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
14 ______________________________________________________________________________________
MAX15012A/C
GND
VDD
IN_H DH
DL
HS
BST
IN_L
2
3
4
5
8
7
6
1
VDD/2 CMOS
SO
MAX15012B/D
GND
VDD
IN_H DH
DL
HS
BST
IN_L
2
3
4
5
8
7
6
1
VDD/2 CMOS
SO
MAX15013B/D
GND
VDD
IN_H DH
DL
HS
BST
IN_L
2
3
4
5
8
7
6
1
TTL
SO
MAX15013A/C
GND
VDD
IN_H DH
DL
HS
BST
IN_L
2
3
4
5
8
7
6
1
TTL
SO
Functional Diagrams
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
______________________________________________________________________________________ 15
MAX15012B/D
MAX15013B/D
N
N
VDD = 8V TO 12.6V VIN = 0 TO 175V*
VOUT
VDD BST
IN_H
IN_L
GND
DL
DH
HS
CBST
PWM
*DERATE VDD IF VIN INCREASES ABOVE 125V. SEE NOTE 3 IN THE ELECTRICAL CHARACTERISTICS.
Typical Operating Circuit
Chip Information
TRANSISTOR COUNT: 790
PROCESS: HV BiCMOS
IN_L
IN_HHS
1
2
8
7
DL
+
GNDBST
DH
VDD
SO
TOP VIEW
3
4
6
5
MAX15012A/B
MAX15013A/B
IN_L
IN_HHS
1
2
8
7
DL
+
GNDBST
DH
VDD
SO-EP
3
4
6
5
MAX15012C/D
MAX15013C/D
Pin Configurations
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX15013AASA+
-40°C to +125°C
8 SO
S8-5
MAX15013BASA+
-40°C to +125°C
8 SO
S8-5
MAX15013CASA+*
-40°C to +125°C 8 SO-EP**
S8E+14
MAX15013DASA+*
-40°C to +125°C 8 SO-EP**
S8E+14
Ordering Information (continued)
+Denotes lead-free package.
*Future product—contact factory for availability.
**EP = Exposed pad.
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
16 ______________________________________________________________________________________
SOICN .EPS
PACKAGE OUTLINE, .150" SOIC
1
1
21-0041 B
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
MAX
0.010
0.069
0.019
0.157
0.010
INCHES
0.150
0.007
E
C
DIM
0.014
0.004
B
A1
MIN
0.053A
0.19
3.80 4.00
0.25
MILLIMETERS
0.10
0.35
1.35
MIN
0.49
0.25
MAX
1.75
0.050
0.016L0.40 1.27
0.3940.386D
D
MINDIM
D
INCHES
MAX
9.80 10.00
MILLIMETERS
MIN MAX
16 AC
0.337 0.344 AB8.758.55 14
0.189 0.197 AA5.004.80 8
N MS012
N
SIDE VIEW
H 0.2440.228 5.80 6.20
e 0.050 BSC 1.27 BSC
C
HE
eBA1
A
D
0∞-8∞
L
1
VARIATIONS:
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
______________________________________________________________________________________ 17
8L, SOIC EXP. PAD.EPS
C
1
1
21-0111
PACKAGE OUTLINE
8L SOIC, .150" EXPOSED PAD
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX15012/MAX15013
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Heaney
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/06 Initial release —
1 12/07 Added exposed paddle versions of the MAX15012A/B and MAX15013A/B,
added Figures 2 and 3 and added SO-EP package outline 1–4, 8–11, 13–17