1.0 Functional Description
1.1 DAC ARCHITECTURE OVERVIEW
The DAC161S055 uses a resistor array to convert the input
code to an analog signal, which in turn is buffered by the rail-
to-rail output amplifier. The resistor array is factory trimmed
to achieve 16-bit accuracy.
An SPI interface shifts the input codes into the device. The
acquired input code is stored in the PREREG register. After
the input code is transferred to the DACREG register it affects
the state of the resistor array and the output level of the DAC.
The transfer can be initiated by the type of write command
used, by a software LDAC command or by the state of the
LDACB pin.
The user can control the power up state of the output using
the MZB pin and the power down state of the output using the
CONFIG register. Additionally, there are external pins and
CONFIG register bits that also control clearing the DAC.
NOTE: Although the DAC161S055 is a single channel de-
vice, the instruction set is for multichannel DACs. The
user must address channel 0 (A2,A1,A0={000}).
1.2 OUTPUT AMPLIFIER
The output buffer amplifier is a rail to rail type which buffers
the signal produced by the resistor array and drives the ex-
ternal load. All amplifiers, including rail to rail amplifiers, ex-
hibit a loss of linearity as the output nears the power rails (in
this case GND and VA). Thus the linearity of the part is spec-
ified over less than the full output range. The user can pro-
gram the CONFIG register to power down the amplifier and
either place it in the high impedance state (HiZ), or have the
output terminated by an internal 10 kΩ pull-down resistor.
1.3 REFERENCE
An external reference source is required to produce an output.
The reference input is not internally buffered and presents a
resistive load to the external source. Loading presented by
the VREF pin varies by about 12.5% depending on the input
code. Thus a low impedance reference should be used for
best results.
1.4 SERIAL INTERFACE
The 4-wire interface is compatible with SPI, QSPI and MI-
CROWIRE, as well as most DSPs. See the Timing Dia-
grams for timing information about the read and write
sequences. The serial interface is the four signals CSB,
SCLK, SDI and SDO.
A bus transaction is initiated by the falling edge of the CSB.
Once CSB is low, the input data is sampled at the SDI pin by
the rising edge of the SCLK. The output data is put out on the
SDO pin on the falling edge of SCLK. At least 24 SCLK cycles
are required for a valid transfer to occur. If CSB is raised be-
fore 24th rising edge of the SCLK, the transfer is aborted. If
the CSB is held low after the 24th falling edge of the SCLK,
the data will continue to flow through the FIFO and out the
SDO pin. Once CSB transitions high, the internal controller
will decode the most recent 24 bits that were received before
the rising edge of CSB. The DAC will then change state de-
pending on the instruction sent and the state of the LDACB
pin.
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The acquired data is shifted into an internal 24 bit shift register
(MSB first) which is configured as a 24 bit deep FIFO. As the
data is being shifted into the FIFO via the SDI pin, the prior
contents of the register are being shifted out through the SDO
output. While CSB is high, SDO is in a high-Z state. At the
falling edge of CSB, SDO presents the MSB of the data
present in the shift register. SDO is updated on every subse-
quent falling edge of SCLK (note — the first SDO transition
will happen on the first falling edge AFTER the first rising edge
of SCLK when CSB is low).
The 24 bits of data contained in the FIFO are interpreted as
an 8 bit COMMAND word followed by 16 bits of DATA. The
general format of the 24 bit data stream is shown below. The
full Instruction Set is tabulated in Section 1.12 INSTRUCTION
SET.
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1.4.1 SPI Write
SPI write operation is the simplest transaction available to the
user. There is no handshaking between master and the slave
(DAC161S055), and the master is the source of all signals
required for communication: SCLK, CSB, SDI. The format of
the data transfer is described in the section 1.4. The user in-
struction set is shown in Section 1.12 INSTRUCTION SET.
1.4.2 SPI Read
The read operation requires all 4 wires of the SPI interface:
SCLK, SCB, SDI, SDO. The simplest READ operation occurs
automatically during any valid transaction on the SPI bus
since SDO pin of DAC161S055 always shifts out the contents
of the internal FIFO. Therefore the user can verify the data
being shifted in to the FIFO by initiating another transaction
and acquiring data at SDO. This allows for verification of the
FIFO contents only.
The 3 internal registers (PREREG, DACREG, CONFIG) can
be accessed by the user through the Register Read com-
mands: RDDO, RDIN, RDCO respectively (see Section 1.12
INSTRUCTION SET). These operations require 2 SPI trans-
action to recover the register data. The first transaction shifts
in the Register Read command; an 8 bit command byte fol-
lowed by 16 bit “dummy” data. The Register Read command
will cause the transfer of contents of the internal register into
the FIFO. The second transaction will shift out the FIFO con-
tents; an 8 bit command byte (which is a copy of previous
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DAC161S055