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ADCS7476
ADCS7477
ADCS7478 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & WSON
Check for Samples: ADCS7476,ADCS7477,ADCS7478
1FEATURES DESCRIPTION
2 Variable Power Management The ADCS7476, ADCS7477, and ADCS7478 are low
Packaged in 6-Lead, SOT-23 and WSON power, monolithic CMOS 12-, 10- and 8-bit analog-to-
Power Supply used as Reference digital converters that operate at 1 MSPS. The
ADCS7476/77/78 are drop-in replacements for
Single +2.7V to +5.25V Supply Operation Analog Devices' AD7476/77/78. Each device is based
SPI™/QSPI™/MICROWIRE™/DSP Compatible on a successive approximation register architecture
with internal track-and-hold. The serial interface is
APPLICATIONS compatible with several standards, such as SPI™,
QSPI™, MICROWIRE™, and many common DSP
Automotive Navigation serial interfaces.
FA/ATM Equipment The ADCS7476/77/78 uses the supply voltage as a
Portable Systems reference, enabling the devices to operate with a full-
Medical Instruments scale input range of 0 to VDD. The conversion rate is
Mobile Communications determined from the serial clock (SCLK) speed.
These converters offer a shutdown mode, which can
Instrumentation and Control Systems be used to trade throughput for power consumption.
The ADCS7476/77/78 is operated with a single
KEY SPECIFICATIONS supply that can range from +2.7V to +5.25V. Normal
Resolution with no Missing Codes 12/10/8 bits power consumption during continuous conversion,
using a +3V or +5V supply, is 2 mW or 10 mW
Conversion Rate 1 MSPS respectively. The power down feature, which is
DNL +0.5, -0.3 LSB (typ) enabled by a chip select (CS) pin, reduces the power
INL ± 0.4 LSB (typ) consumption to under 5 µW using a +5V supply. All
Power Consumption three converters are available in a 6-lead, SOT-23
package and in a 6-lead WSON, both of which
3V Supply 2 mW (typ) provide an extremely small footprint for applications
5V Supply 10 mW (typ) where space is a critical consideration. These
products are designed for operation over the
automotive/extended industrial temperature range of
40°C to +125°C.
Connection Diagram
Figure 1. 6-Lead SOT-23 or WSON
See DBV or NGF Package
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADCS7476, ADCS7477, ADCS7478
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PIN DESCRIPTIONS
Pin No. Symbol Description
ANALOG I/O
3 VIN Analog input. This signal can range from 0V to VDD.
DIGITAL I/O
Digital clock input. The range of frequencies for this input is 10 kHz to 20 MHz, with ensured
4 SCLK performance at 20 MHz. This clock directly controls the conversion and readout processes.
5 SDATA Digital data output. The output words are clocked out of this pin by the SCLK pin.
6 CS Chip select. A conversion process begins on the falling edge of CS.
POWER SUPPLY
Positive supply pin. These pins should be connected to a quiet +2.7V to +5.25V source and bypassed
1 VDD to GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the power pin. The
ADCS7476/77/78 uses this power supply as a reference, so it should be thoroughly bypassed.
2 GND The ground return for the supply.
Block Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
Supply Voltage VDD 0.3V to +6.5V
Voltage on Any Analog Pin to GND 0.3V to VDD +0.3V
Voltage on Any Digital Pin to GND -0.3V to 6.5V
Input Current at Any Pin (3) ±10 mA
ESD Susceptibility
Human Body Model 3500V
Machine Model 200V
Soldering Temperature, Infrared,
10 seconds 215°C
Junction Temperature +150°C
Storage Temperature 65°C to +150°C
(1) Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions is not implied. Exposure to maximum ratings for extended periods may
affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Except power supply pins.
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Operating Ratings
Operating Temperature Range TMIN =40°C TATMAX = +125°C
VDD Supply Voltage +2.7V to +5.25V
Digital Input Pins Voltage Range (1) +2.7V to +5.25V
(1) Independent of supply voltage.
Package Thermal Resistance
Package θJA
6-Lead SOT-23 265°C / W
6-Lead WSON 78°C / W
ADCS7476/ADCS7477/ADCS7478 Specifications(1)
ADCS7476 Converter Electrical Characteristics
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted.
Boldface limits apply for TA=40°C to +85°C: all other limits TA= 25°C, unless otherwise noted.
Symbol Parameter Conditions Typical Limits Units
STATIC CONVERTER CHARACTERISTICS
VDD = 2.7V to 3.6V,
Resolution with No Missing Codes 12 Bits
40°C TA125°C
VDD = 2.7V to 3.6V, ±0.4 ±1 LSB (max)
40°C TA85°C
INL Integral Non-Linearity VDD = 2.7V to 3.6V, +1 LSB (max)
TA= 125°C -1.1 LSB (min)
VDD = 2.7V to 3.6V, +0.5 +1 LSB (max)
40°C TA85°C -0.3 -0.9 LSB (min)
DNL Differential Non-Linearity VDD = 2.7V to 3.6V, ±1 LSB (max)
TA= 125°C
VDD = 2.7V to 3.6V,
VOFF Offset Error ±0.1 ±1.2 LSB (max)
40°C TA125°C
VDD = 2.7V to 3.6V,
GE Gain Error ±0.2 ±1.2 LSB (max)
40°C TA125°C
DYNAMIC CONVERTER CHARACTERISTICS
SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 kHz, 40°C TA125°C 72 70 dB (min)
fIN = 100 kHz, 40°C TA85°C 72.5 70.8 dB (min)
SNR Signal-to-Noise Ratio fIN = 100 kHz, TA= 125°C 70.6 dB (min)
THD Total Harmonic Distortion fIN = 100 kHz -80 dB
SFDR Spurious-Free Dynamic Range fIN = 100 kHz 82 dB
Intermodulation Distortion, Second Order fa= 103.5 kHz, fb= 113.5 kHz -78 dB
Terms
IMD Intermodulation Distortion, Third Order fa= 103.5 kHz, fb= 113.5 kHz -78 dB
Terms +5V Supply 11 MHz
FPBW -3 dB Full Power Bandwidth +3V Supply 8 MHz
POWER SUPPLY CHARACTERISTICS
2.7 V (min)
VDD Supply Voltage 40°C TA125°C 5.25 V (max)
(1) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
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ADCS7476/ADCS7477/ADCS7478 Specifications(1)
ADCS7476 Converter Electrical Characteristics (continued)
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted.
Boldface limits apply for TA=40°C to +85°C: all other limits TA= 25°C, unless otherwise noted.
Symbol Parameter Conditions Typical Limits Units
VDD = +4.75V to +5.25V, 2 mA
SCLK On or Off
Normal Mode (Static) VDD = +2.7V to +3.6V, 1 mA
SCLK On or Off
VDD = +4.75V to +5.25V, 2.0 3.5 mA (max)
IDD fSAMPLE = 1 MSPS
Normal Mode (Operational) VDD = +2.7V to +3.6V, 0.6 1.6 mA (max)
fSAMPLE = 1 MSPS
VDD = +5V, SCLK Off 0.5 µA
Shutdown Mode VDD = +5V, SCLK On 60 µA
VDD = +5V, fSAMPLE = 1 MSPS 10 17.5 mW (max)
Power Consumption, Normal Mode
(Operational) VDD = +3V, fSAMPLE = 1 MSPS 2 4.8 mW (max)
PDVDD = +5V, SCLK Off 2.5 µW
Power Consumption, Shutdown Mode VDD = +3V, SCLK Off 1.5 µW
ANALOG INPUT CHARACTERISTICS
VIN Input Range 0 to VDD V
IDCL DC Leakage Current ±1 µA (max)
CINA Analog Input Capacitance 30 pF
DIGITAL INPUT CHARACTERISTICS
VIH Input High Voltage 2.4 V (min)
VDD = +5V 0.8 V (max)
VIL Input Low Voltage VDD = +3V 0.4 V (max)
IIN Input Current VIN = 0V or VDD ±10 nA ±1 µA (max)
CIND Digital Input Capacitance 2 4pF (max)
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA,
VOH Output High Voltage VDD 0.2 V (min)
VDD = +2.7V to +5.25V
VOL Output Low Voltage ISINK = 200 µA 0.4 V (max)
IOL TRI-STATE Leakage Current ±10 µA (max)
COUT TRI-STATE Output Capacitance 2 4pF (max)
Output Coding Straight (Natural) Binary
AC ELECTRICAL CHARACTERISTICS
fSCLK Clock Frequency 40°C TA125°C 20 MHz (max)
40 % (min)
DC SCLK Duty Cycle 60 % (max)
tTH Track/Hold Acquisition Time 400 ns (max)
fRATE Throughput Rate See USING THE ADCS7476/77/78 1MSPS (max)
tAD Aperture Delay 3 ns
tAJ Aperture Jitter 30 ps
ADCS7476/ADCS7477/ADCS7478 Specifications(1) ADCS7477 Converter Electrical
Characteristics
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted.
Boldface limits apply for TA=40°C to +85°C: all other limits TA= 25°C, unless otherwise noted.
Symbol Parameter Conditions Typical Limits Units
STATIC CONVERTER CHARACTERISTICS
(1) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
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ADCS7476/ADCS7477/ADCS7478 Specifications(1) ADCS7477 Converter Electrical
Characteristics (continued)
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted.
Boldface limits apply for TA=40°C to +85°C: all other limits TA= 25°C, unless otherwise noted.
Symbol Parameter Conditions Typical Limits Units
Resolution with No Missing Codes 10 Bits
INL Integral Non-Linearity ±0.2 ±0.7 LSB (max)
+0.3 LSB (max)
DNL Differential Non-Linearity ±0.7
-0.2 LSB (min)
VOFF Offset Error ±0.1 ±0.7 LSB (max)
GE Gain Error ±0.2 ±1 LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 kHz 61.7 61 dBFS (min)
SNR Signal-to-Noise Ratio fIN = 100 kHz 62 dB
THD Total Harmonic Distortion fIN = 100 kHz -77 -73 dB (max)
SFDR Spurious-Free Dynamic Range fIN = 100 kHz 78 74 dB (min)
Intermodulation Distortion, Second Order fa= 103.5 kHz, fb= 113.5 kHz -78 dB
Terms
IMD Intermodulation Distortion, Third Order fa= 103.5 kHz, fb= 113.5 kHz -78 dB
Terms +5V Supply 11 MHz
FPBW -3 dB Full Power Bandwidth +3V Supply 8 MHz
POWER SUPPLY CHARACTERISTICS
2.7 V (min)
VDD Supply Voltage 5.25 V (max)
VDD = +4.75V to +5.25V, 2 mA
SCLK On or Off
Normal Mode (Static) VDD = +2.7V to +3.6V, 1 mA
SCLK On or Off
VDD = +4.75V to +5.25V, 2.0 3.5 mA (max)
IDD fSAMPLE = 1 MSPS
Normal Mode (Operational) VDD = +2.7V to +3.6V, 0.6 1.6 mA (max)
fSAMPLE = 1 MSPS
VDD = +5V, SCLK Off 0.5 µA (max)
Shutdown Mode VDD = +5V, SCLK On 60 µA (max)
VDD = +5V, fSAMPLE = 1 MSPS 10 17.5 mW (max)
Power Consumption, Normal Mode
(Operational) VDD = +3V, fSAMPLE = 1 MSPS 2 4.8 mW (max)
PDVDD = +5V, SCLK Off 2.5 µW (max)
Power Consumption, Shutdown Mode VDD = +3V, SCLK Off 1.5 µW (max)
ANALOG INPUT CHARACTERISTICS
VIN Input Range 0 to VDD V
IDCL DC Leakage Current ±1 µA (max)
CINA Analog Input Capacitance 30 pF
DIGITAL INPUT CHARACTERISTICS
VIH Input High Voltage 2.4 V (min)
VDD = +5V 0.8 V (max)
VIL Input Low Voltage VDD = +3V 0.4 V (max)
IIN Input Current VIN = 0V or VDD ±10 nA ±1 µA (max)
CIND Digital Input Capacitance 2 4pF (max)
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA,
VOH Output High Voltage VDD 0.2 V (min)
VDD = +2.7V to +5.25V
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ADCS7476/ADCS7477/ADCS7478 Specifications(1) ADCS7477 Converter Electrical
Characteristics (continued)
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted.
Boldface limits apply for TA=40°C to +85°C: all other limits TA= 25°C, unless otherwise noted.
Symbol Parameter Conditions Typical Limits Units
VOL Output Low Voltage ISINK = 200 µA 0.4 V (max)
IOL TRI-STATE Leakage Current ±10 µA (max)
COUT TRI-STATE Output Capacitance 2 4pF (max)
Output Coding Straight (Natural) Binary
AC ELECTRICAL CHARACTERISTICS
fSCLK Clock Frequency 20 MHz (max)
40 % (min)
DC SCLK Duty Cycle 60 % (max)
tTH Track/Hold Acquisition Time 400 ns (max)
fRATE Throughput Rate See USING THE ADCS7476/77/78 1MSPS (max)
tAD Aperture Delay 3 ns
tAJ Aperture Jitter 30 ps
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ADCS7476/ADCS7477/ADCS7478 Specifications(1)
ADCS7478 Converter Electrical Characteristics
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted.
Boldface limits apply for TA=40°C to +85°C: all other limits TA= 25°C, unless otherwise noted.
Symbol Parameter Conditions Typical Limits Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 8Bits
INL Integral Non-Linearity ±0.05 ±0.3 LSB (max)
DNL Differential Non-Linearity ±0.07 ±0.3 LSB (max)
VOFF Offset Error ±0.03 ±0.3 LSB (max)
GE Gain Error ±0.08 ±0.4 LSB (max)
Total Unadjusted Error ±0.07 ±0.3 LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
SINAD Signal-to-Noise Plus Distortion Ratio fIN = 100 kHz 49.7 49 dB (min)
SNR Signal-to-Noise Ratio fIN = 100 kHz 49.7 dB
THD Total Harmonic Distortion fIN = 100 kHz -77 -65 dB (max)
SFDR Spurious-Free Dynamic Range fIN = 100 kHz 69 65 dB (min)
Intermodulation Distortion, Second Order fa= 103.5 kHz, fb= 113.5 kHz -68 dB
Terms
IMD Intermodulation Distortion, Third Order fa= 103.5 kHz, fb= 113.5 kHz -68 dB
Terms +5V Supply 11 MHz
FPBW -3 dB Full Power Bandwidth +3V Supply 8 MHz
POWER SUPPLY CHARACTERISTICS
2.7 V (min)
VDD Supply Voltage 5.25 V (max)
VDD = +4.75V to +5.25V, 2 mA
SCLK On or Off
Normal Mode (Static) VDD = +2.7V to +3.6V, 1 mA
SCLK On or Off
VDD = +4.75V to +5.25V, 2.0 3.5 mA (max)
IDD fSAMPLE = 1 MSPS
Normal Mode (Operational) VDD = +2.7V to +3.6V, 0.6 1.6 mA (max)
fSAMPLE = 1 MSPS
VDD = +5V, SCLK Off 0.5 µA (max)
Shutdown Mode VDD = +5V, SCLK On 60 µA (max)
VDD = +5V, fSAMPLE = 1 MSPS 10 17.5 mW (max)
Power Consumption, Normal Mode
(Operational) VDD = +3V, fSAMPLE = 1 MSPS 2 4.8 mW (max)
PDVDD = +5V, SCLK Off 2.5 µW (max)
Power Consumption= Shutdown Mode VDD = +3V, SCLK Off 1.5 µW (max)
ANALOG INPUT CHARACTERISTICS
VIN Input Range 0 to VDD V
IDCL DC Leakage Current ±1 µA (max)
CINA Analog Input Capacitance 30 pF
DIGITAL INPUT CHARACTERISTICS
VIH Input High Voltage 2.4 V (min)
VDD = +5V 0.8 V (max)
VIL Input Low Voltage VDD = +3V 0.4 V (max)
IIN Digital Input Current VIN = 0V or VDD ±10 nA ±1 µA (max)
CIND Input Capacitance 2 4pF(max)
DIGITAL OUTPUT CHARACTERISTICS
(1) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
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ADCS7476/ADCS7477/ADCS7478 Specifications(1)
ADCS7478 Converter Electrical Characteristics (continued)
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted.
Boldface limits apply for TA=40°C to +85°C: all other limits TA= 25°C, unless otherwise noted.
Symbol Parameter Conditions Typical Limits Units
ISOURCE = 200 µA,
VOH Output High Voltage VDD 0.2 V (min)
VDD = +2.7V to +5.25V
VOL Output Low Voltage ISINK = 200 µA 0.4 V (max)
IOL TRI-STATE Leakage Current ±10 µA (max)
COUT TRI-STATE Output Capacitance 2 4pF (max)
Output Coding Straight (Natural) Binary
AC ELECTRICAL CHARACTERISTICS
fSCLK Clock Frequency 20 MHz (max)
40 % (min)
DC SCLK Duty Cycle 60 % (max)
tTH Track/Hold Acquisition Time 400 ns (max)
fRATE Throughput Rate See Applications Information 1MSPS (min)
tAD Aperture Delay 3 ns
tAJ Aperture Jitter 30 ps
Figure 2. Timing Test Circuit
Timing Test Circuit ADCS7476/ADCS7477/ADCS7478 Timing Specifications
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, Boldface limits apply for TA=40°C to +85°C:
all other limits TA= 25°C, unless otherwise noted. (1)
Symbol Parameter Conditions Typical Limits Units
tCONVERT 16 x tSCLK
tQUIET (2) 50 ns (min)
t1Minimum CS Pulse Width 10 ns (min)
t2CS to SCLK Setup Time 10 ns (min)
Delay from CS Until SDATA TRI-STATE
t320 ns (max)
Disabled (3)
VDD = +2.7 to +3.6 40 ns (max)
Data Access Time after SCLK Falling
t4Edge(4) VDD = +4.75 to +5.25 20 ns (max)
0.4 x
t5SCLK Low Pulse Width ns (min)
tSCLK
0.4 x
t6SCLK High Pulse Width ns (min)
tSCLK
VDD = +2.7 to +3.6 7ns (min)
t7SCLK to Data Valid Hold Time VDD = +4.75 to +5.25 5ns (min)
(1) All input signals are specified as tr= tf= 5 ns (10% to 90% VDD) and timed from 1.6V.
(2) Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion
(3) Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V.
(4) Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V.
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Timing Test Circuit ADCS7476/ADCS7477/ADCS7478 Timing Specifications (continued)
The following specifications apply for VDD = +2.7V to 5.25V, fSCLK = 20 MHz, Boldface limits apply for TA=40°C to +85°C:
all other limits TA= 25°C, unless otherwise noted. (1)
Symbol Parameter Conditions Typical Limits Units
25 ns (max)
VDD = +2.7 to +3.6 6ns (min)
SCLK Falling Edge to SDATA High
t8Impedance (5) 25 ns (max)
VDD = +4.75 to +5.25 5ns (min)
tPOWER- Power-Up Time from Full Power-Down 1 µs
UP
(5) t8is derived from the time taken by the outputs to change by 0.5V with the loading circuit shown above. The measured number is then
adjusted to remove the effects of charging or discharging the 25pF capacitor. This means t8is the true bus relinquish time, independent
of the bus loading.
Specification Definitions
APERTURE DELAY is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as
noise in the output.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5 LSB
for ADCS7476 and ADCS7477, VREF - 1 LSB for ADCS7478), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale LSB below the first code transition) through positive full scale LSB above the last
code transition). The deviation of any given code from this straight line is measured from the center of that
code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the
power in the either the two second order or all four third order intermodulation products to the sum of the
power in both of the original frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADCS7476/77/78 is
ensured not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB for the ADCS7476 and ADCS7477, and GND + 1 LSB for the ADCS7478).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or DC.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of
the input signal to the rms value of all of the other spectral components below half the clock frequency,
including harmonics but excluding DC.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal, where a spurious signal is any signal present in the output
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spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
where
f1is the RMS power of the fundamental (output) frequency
f2through f6are the RMS power in the first 5 harmonic frequencies (1)
TOTAL UNADJUSTED ERROR is the worst deviation found from the ideal transfer function. As such, it is a
comprehensive specification which includes full scale error, linearity error, and offset error.
Timing Diagrams
Figure 3. ADCS7476 Serial Interface Timing Diagram
Figure 4. ADCS7477 Serial Interface Timing Diagram
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Figure 5. ADCS7478 Serial Interface Timing Diagram
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Typical Performance Characteristics
TA= +25°C, VDD = 3V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, fIN = 100 kHz unless otherwise stated.
ADCS7476
ADCS7476 DNL ADCS7476 INL
Figure 6. Figure 7.
ADCS7476 THD
vs.
ADCS7476 Spectral Response @ 100kHz Input Source Impedance
Figure 8. Figure 9.
ADCS7476 THD ADCS7476 THD
vs. vs.
Input Frequency, 600 kSPS Input Frequency, 1 MSPS
Figure 10. Figure 11.
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Typical Performance Characteristics (continued)
TA= +25°C, VDD = 3V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, fIN = 100 kHz unless otherwise stated.
ADCS7476 ADCS7476 SINAD ADCS7476 SINAD
vs. vs.
Input Frequency, 600 kSPS Input Frequency, 1 MSPS
Figure 12. Figure 13.
ADCS7476 SNR ADCS7476 SINAD
vs. vs.
fSCLK fSCLK
Figure 14. Figure 15.
ADCS7477 DNL ADCS7477 INL
Figure 16. Figure 17.
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Typical Performance Characteristics (continued)
TA= +25°C, VDD = 3V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, fIN = 100 kHz unless otherwise stated.
ADCS7476 ADCS7477 SNR
vs.
ADCS7477 Spectral Response @ 100kHz Input fSCLK
Figure 18. Figure 19.
ADCS7477 SINAD
vs.
fSCLK ADCS7478 DNL
Figure 20. Figure 21.
ADCS7478 INL ADCS7478 Spectral Response @ 100kHz Input
Figure 22. Figure 23.
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SNAS192F APRIL 2003REVISED MARCH 2013
Typical Performance Characteristics (continued)
TA= +25°C, VDD = 3V, fSAMPLE = 1 MSPS, fSCLK = 20 MHz, fIN = 100 kHz unless otherwise stated.
ADCS7476 ADCS7478 SNR ADCS7478 SINAD
vs. vs.
fSCLK fSCLK
Figure 24. Figure 25.
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GND
SAMPLING
CAPACITOR
SW1
-
+CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
V /2
DD
SW2
VIN
GND
SAMPLING
CAPACITOR
SW1
-
+CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
V /2
DD
VIN
ADCS7476, ADCS7477, ADCS7478
SNAS192F APRIL 2003REVISED MARCH 2013
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APPLICATIONS INFORMATION
ADCS7476/77/78 OPERATION
The ADCS7476/77/78 are successive-approximation analog-to-digital converters designed around a charge-
redistribution digital-to-analog converter. Simplified schematics of the ADCS7476/77/78 in both track and hold
operation are shown in Figure 26 and Figure 27, respectively. In Figure 26 the device is in track mode: switch
SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in
this state until CS is brought low, at which point the device moves to hold mode.
Figure 27 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining
the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-
redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is
balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of
the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK.
Figure 26. ADCS7476/77/78 in Track Mode
Figure 27. ADCS7476/77/78 in Hold Mode
USING THE ADCS7476/77/78
Serial interface timing diagrams for the ADCS7476/77/78 are shown in Figure 3,Figure 4, and Figure 5. CS is
chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the
conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is
found.
Basic operation of the ADCS7476/77/78 begins with CS going low, which initiates a conversion process and data
transfer. Subsequent rising and falling edges of SCLK will be labeled with reference to the falling edge of CS; for
example, "the third falling edge of SCLK" shall refer to the third falling edge of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold
mode. The input signal is sampled and held for conversion at the falling edge of CS. The converter moves from
hold mode to track mode on the 13th rising edge of SCLK (see Figure 3,Figure 4,orFigure 5). The SDATA pin
will be placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever
occurs first. After a conversion is completed, the quiet time tQUIET must be satisfied before bringing CS low again
to begin another conversion.
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