R5S72030W200FP - Renesas Technology / Hitachi Semiconductor

Revision Date: Sep. 28, 2009

32 SH7203 Group

Hardware Manual

Renesas 32-Bit RISC Microcompute

SuperHTM RISC engine Family / SH7200 Series

SH7203 R5S72030W200FP

Rev.3.00

REJ09B0313-0300

The revision list can be viewed directly by clicking the title page.

The revision list summarizes the locations of revisions and

additions. Details should always be checked by referring to the

relevant text.

Rev. 3.00 Sep. 28, 2009 Page ii of xxx

REJ09B0313-0300

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate

Renesas products for their use. Renesas neither makes warranties or representations with respect to the

accuracy or completeness of the information contained in this document nor grants any license to any

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out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,

programs, algorithms, and application circuit examples.

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4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and

application circuit examples, is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas products listed in this

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(3) healthcare intervention (e.g., excision, administration of medication, etc.)

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damages arising out of the use of Renesas products beyond such specified ranges.

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appropriate treatment for aging degradation or any other applicable measures. Among others, since the

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Notes regarding these materials

Rev. 3.00 Sep. 28, 2009 Page iii of xxx

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General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in

the manual.

⎯ The input pins of CMOS products are generally in the high-impedance state. In

operation with an unused pin in the open-circuit state, extra electromagnetic noise is

induced in the vicinity of LSI, an associated shoot-through current flows internally, and

malfunctions may occur due to the false recognition of the pin state as an input signal.

Unused pins should be handled as described under Handling of Unused Pins in the

manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

⎯ The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the

states of pins are not guaranteed from the moment when power is supplied until the

reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on

reset function are not guaranteed from the moment when power is supplied until the

power reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

⎯ The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has

become stable. When switching the clock signal during program execution, wait until the

target clock signal has stabilized.

⎯ When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization

of the clock signal. Moreover, when switching to a clock signal produced with an

external resonator (or by an external oscillator) while program execution is in progress,

wait until the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different type number,

confirm that the change will not lead to problems.

⎯ The characteristics of MPU/MCU in the same group but having different type numbers

may differ because of the differences in internal memory capacity and layout pattern.

When changing to products of different type numbers, implement a system-evaluation

test for each of the products.

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Configuration of This Manual

This manual comprises the following items:

1. General Precautions in the Handling of MPU/MCU Products

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs according to the

module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section

includes notes in relation to the descriptions given, and usage notes are given, as required, as the

final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

• Product Type, Package Dimensions, etc.

10. Main Revisions for This Edition (only for revised versions)

The list of revisions is a summary of points that have been revised or added to earlier versions.

This does not include all of the revised contents. For details, see the actual locations in this

manual.

11. Index

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Preface

This LSI is an RISC (Reduced Instruction Set Computer) microcomputer which includes a

Renesas Technology-original RISC CPU as its core, and the peripheral functions required to

configure a system.

Target Users: This manual was written for users who will be using this LSI in the design of

application systems. Target users are expected to understand the fundamentals of

electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of this LSI to the target users.

Refer to the SH-2A, SH2A-FPU Software Manual for a detailed description of the

instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the SH-2A, SH2A-FPU Software Manual.

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the

List of Registers.

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• Description of Numbers and Symbols

Aspects of the notations for register names, bit names, numbers, and symbolic names in this

manual are explained below.

CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter

input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.

14.3 Operation

The style "register name"_"instance number" is used in cases where there is more than one

instance of the same function or similar functions.

[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.

In descriptions involving the names of bits and bit fields within this manual, the modules and

registers to which the bits belong may be clarified by giving the names in the forms

"module name"."register name"."bit name" or "register name"."bit name".

(1) Overall notation

(2) Register notation

Rev. 0.50, 10/04, page 416 of 914

14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)

14.3.1 Interval Count Operation

(4)

(3)

(2)

Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),

hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.

[Examples] Binary: B'11 or 11

Hexadecimal: H'EFA0 or 0xEFA0

Decimal: 1234

(3) Number notation

An overbar on the name indicates that a signal or pin is active-low.

[Example] WDTOVF

Note: The bit names and sentences in the above figure are examples and do not refer to

specific data in this manual.

(4) Notation for active-low

When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in

CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in

CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000

and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,

a f/4 clock is selected.

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• Description of Registers

Each register description includes a bit chart, illustrating the arrangement of bits, and a table of

bits, describing the meanings of the bit settings. The standard format and notation for bit charts

and tables are described below.

Indicates the bit number or numbers.

In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case

of a 16-bit register, the bits are arranged in order from 15 to 0.

Indicates the name of the bit or bit field.

When the number of bits has to be clearly indicated in the field, appropriate notation is

included (e.g., ASID[3:0]).

A reserved bit is indicated by "−".

Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such

cases, the entry under Bit Name is blank.

(1) Bit

(2) Bit name

Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.

0: The initial value is 0

1: The initial value is 1

−: The initial value is undefined

(3) Initial value

For each bit and bit field, this entry indicates whether the bit or field is readable or writable,

or both writing to and reading from the bit or field are impossible.

The notation is as follows:

R/W:

R/(W):

The bit or field is readable and writable.

However, writing is only performed to flag clearing.

The bit or field is readable.

"R" is indicated for all reserved bits. When writing to the register, write

the value under Initial Value in the bit chart to reserved bits or fields.

The bit or field is writable.

Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this

manual.

(4) R/W

Describes the function of the bit or field and specifies the values for writing.

(5) Description

Bit

13 to 11

All 0

R/W

Address Identifier

These bits enable or disable the pin function.

Reserved

This bit is always read as 0.

Reserved

This bit is always read as 1.

−

ASID2 to

ASID0

−

Bit Name Initial Value R/W Description

[Bit Chart]

[Table of Bits]

1514131211109876543210

Bit:

Initial value:

R/W:

0000001000000000

R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W

⎯ASID2 ⎯⎯⎯⎯⎯⎯ ACMP2QIFE

⎯ASID1 ASID0 ACMP1 ACMP0

−0R

(1) (2) (3) (4) (5)

Reserved

These bits are always read as 0.

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All trademarks and registered trademarks are the property of their respective owners.

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Contents

Section 1 Overview................................................................................................1

1.1 SH7203 Features.................................................................................................................... 1

1.2 Product Lineup....................................................................................................................... 9

1.3 Block Diagram..................................................................................................................... 10

1.4 Pin Arrangement .................................................................................................................. 11

1.5 Pin Functions ....................................................................................................................... 12

1.6 Pin Assignments................................................................................................................... 22

Section 2 CPU......................................................................................................47

2.1 Register Configuration......................................................................................................... 47

2.1.1 General Registers.................................................................................................... 47

2.1.2 Control Registers .................................................................................................... 48

2.1.3 System Registers..................................................................................................... 50

2.1.4 Register Banks ........................................................................................................ 51

2.1.5 Initial Values of Registers....................................................................................... 51

2.2 Data Formats........................................................................................................................ 52

2.2.1 Data Format in Registers ........................................................................................ 52

2.2.2 Data Formats in Memory........................................................................................ 52

2.2.3 Immediate Data Format .......................................................................................... 53

2.3 Instruction Features.............................................................................................................. 54

2.3.1 RISC-Type Instruction Set...................................................................................... 54

2.3.2 Addressing Modes .................................................................................................. 58

2.3.3 Instruction Format................................................................................................... 63

2.4 Instruction Set...................................................................................................................... 67

2.4.1 Instruction Set by Classification ............................................................................. 67

2.4.2 Data Transfer Instructions....................................................................................... 73

2.4.3 Arithmetic Operation Instructions .......................................................................... 77

2.4.4 Logic Operation Instructions .................................................................................. 80

2.4.5 Shift Instructions..................................................................................................... 81

2.4.6 Branch Instructions ................................................................................................. 82

2.4.7 System Control Instructions.................................................................................... 83

2.4.8 Floating-Point Operation Instructions..................................................................... 85

2.4.9 FPU-Related CPU Instructions ............................................................................... 87

2.4.10 Bit Manipulation Instructions ................................................................................. 88

2.5 Processing States.................................................................................................................. 90

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Section 3 Floating-Point Unit (FPU)...................................................................93

3.1 Features................................................................................................................................ 93

3.2 Data Formats........................................................................................................................ 94

3.2.1 Floating-Point Format............................................................................................. 94

3.2.2 Non-Numbers (NaN) .............................................................................................. 97

3.2.3 Denormalized Numbers .......................................................................................... 98

3.3 Register Descriptions...........................................................................................................99

3.3.1 Floating-Point Registers ......................................................................................... 99

3.3.2 Floating-Point Status/Control Register (FPSCR).................................................. 100

3.3.3 Floating-Point Communication Register (FPUL) ................................................. 101

3.4 Rounding............................................................................................................................ 102

3.5 FPU Exceptions ................................................................................................................. 103

3.5.1 FPU Exception Sources ........................................................................................ 103

3.5.2 FPU Exception Handling...................................................................................... 103

Section 4 Clock Pulse Generator (CPG) ...........................................................105

4.1 Features.............................................................................................................................. 105

4.2 Input/Output Pins............................................................................................................... 108

4.3 Clock Operating Modes ..................................................................................................... 109

4.4 Register Descriptions......................................................................................................... 113

4.4.1 Frequency Control Register (FRQCR) ................................................................. 113

4.5 Changing the Frequency .................................................................................................... 116

4.5.1 Changing the Multiplication Rate......................................................................... 116

4.5.2 Changing the Division Ratio................................................................................. 117

4.6 Usage of the Clock Pins..................................................................................................... 118

4.6.1 In the Case of Inputting an External Clock........................................................... 118

4.6.2 In the Case of Using a Crystal Resonator ............................................................. 119

4.6.3 In the Case of Not Using the Clock Pin................................................................ 119

4.7 Oscillation Stabilizing Time .............................................................................................. 120

4.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator............................ 120

4.7.2 Oscillation Stabilizing Time of the PLL circuit.................................................... 120

4.8 Notes on Board Design ...................................................................................................... 121

4.8.1 Note on Using a PLL Oscillation Circuit.............................................................. 121

4.9 Usage Note......................................................................................................................... 122

Section 5 Exception Handling ...........................................................................123

5.1 Overview............................................................................................................................ 123

5.1.1 Types of Exception Handling and Priority ........................................................... 123

5.1.2 Exception Handling Operations............................................................................ 125

5.1.3 Exception Handling Vector Table ........................................................................ 127

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5.2 Resets ................................................................................................................................. 129

5.2.1 Input/Output Pins.................................................................................................. 129

5.2.2 Types of Reset ...................................................................................................... 129

5.2.3 Power-On Reset .................................................................................................... 130

5.2.4 Manual Reset ........................................................................................................ 132

5.3 Address Errors ................................................................................................................... 133

5.3.1 Address Error Sources .......................................................................................... 133

5.3.2 Address Error Exception Handling....................................................................... 134

5.4 Register Bank Errors.......................................................................................................... 135

5.4.1 Register Bank Error Sources................................................................................. 135

5.4.2 Register Bank Error Exception Handling ............................................................. 135

5.5 Interrupts............................................................................................................................ 136

5.5.1 Interrupt Sources................................................................................................... 136

5.5.2 Interrupt Priority Level ......................................................................................... 137

5.5.3 Interrupt Exception Handling................................................................................ 138

5.6 Exceptions Triggered by Instructions ................................................................................ 139

5.6.1 Types of Exceptions Triggered by Instructions .................................................... 139

5.6.2 Trap Instructions................................................................................................... 140

5.6.3 Slot Illegal Instructions......................................................................................... 140

5.6.4 General Illegal Instructions................................................................................... 141

5.6.5 Integer Division Exceptions.................................................................................. 141

5.6.6 FPU Exceptions .................................................................................................... 142

5.7 When Exception Sources Are Not Accepted ..................................................................... 143

5.8 Stack Status after Exception Handling Ends...................................................................... 144

5.9 Usage Notes ....................................................................................................................... 146

5.9.1 Value of Stack Pointer (SP) .................................................................................. 146

5.9.2 Value of Vector Base Register (VBR) .................................................................. 146

5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ......... 146

5.9.4 Note before Exception Handling Begins Running................................................ 147

Section 6 Interrupt Controller (INTC) ...............................................................149

6.1 Features.............................................................................................................................. 149

6.2 Input/Output Pins............................................................................................................... 151

6.3 Register Descriptions ......................................................................................................... 152

6.3.1 Interrupt Priority Registers 01, 02, 05 to 17 (IPR01, IPR02, IPR05 to IPR17) .... 153

6.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 155

6.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 156

6.3.4 Interrupt Control Register 2 (ICR2)...................................................................... 157

6.3.5 IRQ Interrupt Request Register (IRQRR)............................................................. 158

6.3.6 PINT Interrupt Enable Register (PINTER)........................................................... 160

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6.3.7 PINT Interrupt Request Register (PIRR) .............................................................. 161

6.3.8 Bank Control Register (IBCR).............................................................................. 162

6.3.9 Bank Number Register (IBNR) ............................................................................ 163

6.4 Interrupt Sources................................................................................................................ 165

6.4.1 NMI Interrupt........................................................................................................ 165

6.4.2 User Break Interrupt ............................................................................................. 165

6.4.3 H-UDI Interrupt.................................................................................................... 165

6.4.4 IRQ Interrupts....................................................................................................... 165

6.4.5 PINT Interrupts..................................................................................................... 166

6.4.6 On-Chip Peripheral Module Interrupts ................................................................. 167

6.5 Interrupt Exception Handling Vector Table and Priority................................................... 168

6.6 Operation ........................................................................................................................... 178

6.6.1 Interrupt Operation Sequence ............................................................................... 178

6.6.2 Stack after Interrupt Exception Handling ............................................................. 181

6.7 Interrupt Response Time.................................................................................................... 182

6.8 Register Banks ................................................................................................................... 188

6.8.1 Banked Register and Input/Output of Banks ........................................................ 189

6.8.2 Bank Save and Restore Operations....................................................................... 189

6.8.3 Save and Restore Operations after Saving to All Banks....................................... 191

6.8.4 Register Bank Exception ...................................................................................... 192

6.8.5 Register Bank Error Exception Handling ............................................................. 192

6.9 Data Transfer with Interrupt Request Signals.................................................................... 193

6.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but

Not DMAC Activating.......................................................................................... 194

6.9.2 Handling Interrupt Request Signals as Sources for Activating DMAC but

Not CPU Interrupt................................................................................................. 194

6.10 Usage Note......................................................................................................................... 195

6.10.1 Timing to Clear an Interrupt Source ..................................................................... 195

6.10.2 Timing of IRQOUT Negation............................................................................... 195

Section 7 User Break Controller (UBC)............................................................197

7.1 Features.............................................................................................................................. 197

7.2 Input/Output Pin ................................................................................................................ 199

7.3 Register Descriptions......................................................................................................... 200

7.3.1 Break Address Register (BAR)............................................................................. 201

7.3.2 Break Address Mask Register (BAMR) ............................................................... 202

7.3.3 Break Data Register (BDR) .................................................................................. 203

7.3.4 Break Data Mask Register (BDMR)..................................................................... 204

7.3.5 Break Bus Cycle Register (BBR) ......................................................................... 205

7.3.6 Break Control Register (BRCR) ........................................................................... 207

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7.4 Operation ........................................................................................................................... 210

7.4.1 Flow of the User Break Operation ........................................................................ 210

7.4.2 Break on Instruction Fetch Cycle.......................................................................... 211

7.4.3 Break on Data Access Cycle................................................................................. 212

7.4.4 Value of Saved Program Counter ......................................................................... 213

7.4.5 Usage Examples.................................................................................................... 214

7.5 Usage Notes ....................................................................................................................... 217

Section 8 Cache..................................................................................................219

8.1 Features.............................................................................................................................. 219

8.1.1 Cache Structure..................................................................................................... 219

8.2 Register Descriptions ......................................................................................................... 222

8.2.1 Cache Control Register 1 (CCR1) ........................................................................ 222

8.2.2 Cache Control Register 2 (CCR2) ........................................................................ 224

8.3 Operation ........................................................................................................................... 228

8.3.1 Searching Cache ................................................................................................... 228

8.3.2 Read Access.......................................................................................................... 230

8.3.3 Prefetch Operation (Only for Operand Cache) ..................................................... 230

8.3.4 Write Operation (Only for Operand Cache).......................................................... 231

8.3.5 Write-Back Buffer (Only for Operand Cache)...................................................... 231

8.3.6 Coherency of Cache and External Memory .......................................................... 233

8.4 Memory-Mapped Cache .................................................................................................... 234

8.4.1 Address Array....................................................................................................... 234

8.4.2 Data Array ............................................................................................................ 235

8.4.3 Usage Examples.................................................................................................... 237

8.4.4 Notes ..................................................................................................................... 238

Section 9 Bus State Controller (BSC)................................................................239

9.1 Features.............................................................................................................................. 239

9.2 Input/Output Pins............................................................................................................... 242

9.3 Area Overview................................................................................................................... 244

9.3.1 Address Map......................................................................................................... 244

9.3.2 Data Bus Width and Pin Function Setting in Each Area....................................... 245

9.4 Register Descriptions ......................................................................................................... 246

9.4.1 Common Control Register (CMNCR) .................................................................. 247

9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 7) ..................................... 250

9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 7) .................................. 255

9.4.4 SDRAM Control Register (SDCR)....................................................................... 289

9.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 293

9.4.6 Refresh Timer Counter (RTCNT)......................................................................... 295

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9.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 296

9.5 Operation ........................................................................................................................... 297

9.5.1 Endian/Access Size and Data Alignment.............................................................. 297

9.5.2 Normal Space Interface ........................................................................................ 304

9.5.3 Access Wait Control ............................................................................................. 309

9.5.4 CSn Assert Period Expansion ............................................................................... 311

9.5.5 MPX-I/O Interface................................................................................................ 312

9.5.6 SDRAM Interface................................................................................................. 316

9.5.7 Burst ROM (Clocked Asynchronous) Interface.................................................... 360

9.5.8 SRAM Interface with Byte Selection ................................................................... 362

9.5.9 PCMCIA Interface................................................................................................ 367

9.5.10 Burst MPX-I/O Interface ...................................................................................... 374

9.5.11 Burst ROM (Clocked Synchronous) Interface...................................................... 379

9.5.12 Wait between Access Cycles ................................................................................ 380

9.5.13 Bus Arbitration ..................................................................................................... 387

9.5.14 Others.................................................................................................................... 389

9.6 Usage Notes ....................................................................................................................... 391

9.6.1 Note when using both the bus arbitration function and

the software standby mode ................................................................................... 391

Section 10 Direct Memory Access Controller (DMAC)...................................393

10.1 Features.............................................................................................................................. 393

10.2 Input/Output Pins............................................................................................................... 396

10.3 Register Descriptions......................................................................................................... 397

10.3.1 DMA Source Address Registers (SAR)................................................................ 401

10.3.2 DMA Destination Address Registers (DAR)........................................................ 402

10.3.3 DMA Transfer Count Registers (DMATCR) ....................................................... 402

10.3.4 DMA Channel Control Registers (CHCR) ........................................................... 403

10.3.5 DMA Reload Source Address Registers (RSAR)................................................. 411

10.3.6 DMA Reload Destination Address Registers (RDAR)......................................... 412

10.3.7 DMA Reload Transfer Count Registers (RDMATCR) ........................................ 413

10.3.8 DMA Operation Register (DMAOR) ................................................................... 414

10.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).................. 418

10.4 Operation ........................................................................................................................... 421

10.4.1 Transfer Flow........................................................................................................ 421

10.4.2 DMA Transfer Requests ....................................................................................... 423

10.4.3 Channel Priority.................................................................................................... 428

10.4.4 DMA Transfer Types............................................................................................ 431

10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing .................................... 440

10.5 Usage Notes ....................................................................................................................... 444

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10.5.1 Setting of the Half-End Flag and Generation of the Half-End Interrupt............. 444

10.5.2 Timing of DACK and TEND Outputs ................................................................ 444

10.5.3 Notice about using external request mode .......................................................... 445

10.5.4 Notice about using on-chip peripheral module request mode or

auto-request mode............................................................................................... 446

10.5.5 Notes on Using Flag Bits .................................................................................... 447

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)...................................449

11.1 Features ............................................................................................................................ 449

11.2 Input/Output Pins............................................................................................................... 454

11.3 Register Descriptions ......................................................................................................... 455

11.3.1 Timer Control Register (TCR)............................................................................ 459

11.3.2 Timer Mode Register (TMDR)........................................................................... 463

11.3.3 Timer I/O Control Register (TIOR) .................................................................... 466

11.3.4 Timer Interrupt Enable Register (TIER)............................................................. 484

11.3.5 Timer Status Register (TSR)............................................................................... 487

11.3.6 Timer Buffer Operation Transfer Mode Register (TBTM)................................. 492

11.3.7 Timer Input Capture Control Register (TICCR)................................................. 493

11.3.8 Timer A/D Converter Start Request Control Register (TADCR) ....................... 494

11.3.9 Timer A/D Converter Start Request Cycle Set Registers

(TADCORA_4 and TADCORB_4).................................................................... 497

11.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers

(TADCOBRA_4 and TADCOBRB_4)............................................................... 497

11.3.11 Timer Counter (TCNT)....................................................................................... 498

11.3.12 Timer General Register (TGR) ........................................................................... 498

11.3.13 Timer Start Register (TSTR) .............................................................................. 499

11.3.14 Timer Synchronous Register (TSYR)................................................................. 500

11.3.15 Timer Read/Write Enable Register (TRWER) ................................................... 502

11.3.16 Timer Output Master Enable Register (TOER) .................................................. 503

11.3.17 Timer Output Control Register 1 (TOCR1)........................................................ 504

11.3.18 Timer Output Control Register 2 (TOCR2)........................................................ 507

11.3.19 Timer Output Level Buffer Register (TOLBR) .................................................. 510

11.3.20 Timer Gate Control Register (TGCR) ................................................................ 511

11.3.21 Timer Subcounter (TCNTS) ............................................................................... 513

11.3.22 Timer Dead Time Data Register (TDDR)........................................................... 514

11.3.23 Timer Cycle Data Register (TCDR) ................................................................... 514

11.3.24 Timer Cycle Buffer Register (TCBR)................................................................. 515

11.3.25 Timer Interrupt Skipping Set Register (TITCR) ................................................. 515

11.3.26 Timer Interrupt Skipping Counter (TITCNT)..................................................... 517

11.3.27 Timer Buffer Transfer Set Register (TBTER) .................................................... 518

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11.3.28 Timer Dead Time Enable Register (TDER)........................................................ 520

11.3.29 Timer Waveform Control Register (TWCR) ...................................................... 521

11.3.30 Bus Master Interface........................................................................................... 522

11.4 Operation ........................................................................................................................... 523

11.4.1 Basic Functions................................................................................................... 523

11.4.2 Synchronous Operation....................................................................................... 529

11.4.3 Buffer Operation................................................................................................. 531

11.4.4 Cascaded Operation ............................................................................................ 535

11.4.5 PWM Modes....................................................................................................... 540

11.4.6 Phase Counting Mode......................................................................................... 545

11.4.7 Reset-Synchronized PWM Mode ....................................................................... 552

11.4.8 Complementary PWM Mode.............................................................................. 555

11.4.9 A/D Converter Start Request Delaying Function................................................ 594

11.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ..... 598

11.5 Interrupt Sources................................................................................................................ 599

11.5.1 Interrupt Sources and Priorities .......................................................................... 599

11.5.2 DMAC Activation .............................................................................................. 601

11.5.3 A/D Converter Activation................................................................................... 601

11.6 Operation Timing............................................................................................................... 603

11.6.1 Input/Output Timing........................................................................................... 603

11.6.2 Interrupt Signal Timing ...................................................................................... 610

11.7 Usage Notes ....................................................................................................................... 614

11.7.1 Module Standby Mode Setting ........................................................................... 614

11.7.2 Input Clock Restrictions ..................................................................................... 614

11.7.3 Caution on Period Setting................................................................................... 615

11.7.4 Contention between TCNT Write and Clear Operations.................................... 615

11.7.5 Contention between TCNT Write and Increment Operations............................. 616

11.7.6 Contention between TGR Write and Compare Match........................................ 617

11.7.7 Contention between Buffer Register Write and Compare Match ....................... 618

11.7.8 Contention between Buffer Register Write and TCNT Clear ............................. 619

11.7.9 Contention between TGR Read and Input Capture............................................. 620

11.7.10 Contention between TGR Write and Input Capture............................................ 621

11.7.11 Contention between Buffer Register Write and Input Capture........................... 622

11.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection .... 622

11.7.13 Counter Value during Complementary PWM Mode Stop.................................. 624

11.7.14 Buffer Operation Setting in Complementary PWM Mode ................................. 624

11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag ................ 625

11.7.16 Overflow Flags in Reset Synchronous PWM Mode........................................... 626

11.7.17 Contention between Overflow/Underflow and Counter Clearing....................... 627

11.7.18 Contention between TCNT Write and Overflow/Underflow.............................. 628

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11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to

Reset-Synchronized PWM Mode........................................................................ 628

11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized

PWM Mode......................................................................................................... 629

11.7.21 Interrupts in Module Standby Mode ................................................................... 629

11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection.......... 629

11.8 MTU2 Output Pin Initialization......................................................................................... 630

11.8.1 Operating Modes................................................................................................. 630

11.8.2 Reset Start Operation .......................................................................................... 630

11.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc................. 631

11.8.4 Overview of Initialization Procedures and Mode Transitions

in Case of Error during Operation, etc................................................................ 632

Section 12 Compare Match Timer (CMT).........................................................663

12.1 Features ............................................................................................................................ 663

12.2 Register Descriptions ......................................................................................................... 664

12.2.1 Compare Match Timer Start Register (CMSTR) ................................................ 665

12.2.2 Compare Match Timer Control/Status Register (CMCSR) ................................ 666

12.2.3 Compare Match Counter (CMCNT)................................................................... 668

12.2.4 Compare Match Constant Register (CMCOR) ................................................... 668

12.3 Operation ........................................................................................................................... 669

12.3.1 Interval Count Operation .................................................................................... 669

12.3.2 CMCNT Count Timing....................................................................................... 669

12.4 Interrupts............................................................................................................................ 670

12.4.1 Interrupt Sources and DMA Transfer Requests .................................................. 670

12.4.2 Timing of Compare Match Flag Setting ............................................................. 670

12.4.3 Timing of Compare Match Flag Clearing........................................................... 671

12.5 Usage Notes ....................................................................................................................... 672

12.5.1 Conflict between Write and Compare-Match Processes of CMCNT ................. 672

12.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ................. 673

12.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT................... 674

12.5.4 Compare Match between CMCNT and CMCOR ............................................... 674

Section 13 Watchdog Timer (WDT)..................................................................675

13.1 Features ............................................................................................................................ 675

13.2 Input/Output Pin................................................................................................................. 677

13.3 Register Descriptions ......................................................................................................... 678

13.3.1 Watchdog Timer Counter (WTCNT).................................................................. 678

13.3.2 Watchdog Timer Control/Status Register (WTCSR).......................................... 679

13.3.3 Watchdog Reset Control/Status Register (WRCSR) .......................................... 681

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13.3.4 Notes on Register Access ................................................................................... 682

13.4 WDT Usage ....................................................................................................................... 684

13.4.1 Canceling Software Standby Mode..................................................................... 684

13.4.2 Changing the Frequency ..................................................................................... 684

13.4.3 Using Watchdog Timer Mode ............................................................................ 685

13.4.4 Using Interval Timer Mode ................................................................................ 687

13.5 Usage Notes ....................................................................................................................... 688

13.5.1 Timer Variation .................................................................................................. 688

13.5.2 Prohibition against Setting H'FF to WTCNT...................................................... 688

13.5.3 Interval Timer Overflow Flag............................................................................. 688

13.5.4 System Reset by WDTOVF Signal..................................................................... 689

13.5.5 Manual Reset in Watchdog Timer Mode............................................................ 689

Section 14 Realtime Clock (RTC)..................................................................... 691

14.1 Features ............................................................................................................................ 691

14.2 Input/Output Pin ................................................................................................................ 693

14.3 Register Descriptions......................................................................................................... 694

14.3.1 64-Hz Counter (R64CNT) .................................................................................. 695

14.3.2 Second Counter (RSECCNT) ............................................................................. 696

14.3.3 Minute Counter (RMINCNT)............................................................................. 697

14.3.4 Hour Counter (RHRCNT) .................................................................................. 698

14.3.5 Day of Week Counter (RWKCNT) .................................................................... 699

14.3.6 Date Counter (RDAYCNT) ................................................................................ 700

14.3.7 Month Counter (RMONCNT) ............................................................................ 701

14.3.8 Year Counter (RYRCNT)................................................................................... 702

14.3.9 Second Alarm Register (RSECAR) .................................................................... 703

14.3.10 Minute Alarm Register (RMINAR).................................................................... 704

14.3.11 Hour Alarm Register (RHRAR) ......................................................................... 705

14.3.12 Day of Week Alarm Register (RWKAR) ........................................................... 706

14.3.13 Date Alarm Register (RDAYAR)....................................................................... 707

14.3.14 Month Alarm Register (RMONAR) ................................................................... 708

14.3.15 Year Alarm Register (RYRAR).......................................................................... 709

14.3.16 RTC Control Register 1 (RCR1)......................................................................... 710

14.3.17 RTC Control Register 2 (RCR2)......................................................................... 712

14.3.18 RTC Control Register 3 (RCR3)......................................................................... 714

14.4 Operation ........................................................................................................................... 715

14.4.1 Initial Settings of Registers after Power-On ....................................................... 715

14.4.2 Setting Time........................................................................................................ 715

14.4.3 Reading Time...................................................................................................... 716

14.4.4 Alarm Function................................................................................................... 717

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14.5 Usage Notes ....................................................................................................................... 718

14.5.1 Register Writing during RTC Count................................................................... 718

14.5.2 Use of Real-time Clock (RTC) Periodic Interrupts............................................. 718

14.5.3 Transition to Standby Mode after Setting Register............................................. 718

14.5.4 Notes on Register Read and Write Operations.................................................... 719

Section 15 Serial Communication Interface with FIFO (SCIF) ........................721

15.1 Features ............................................................................................................................ 721

15.2 Input/Output Pins............................................................................................................... 724

15.3 Register Descriptions ......................................................................................................... 725

15.3.1 Receive Shift Register (SCRSR)......................................................................... 727

15.3.2 Receive FIFO Data Register (SCFRDR) ............................................................ 727

15.3.3 Transmit Shift Register (SCTSR) ....................................................................... 728

15.3.4 Transmit FIFO Data Register (SCFTDR)........................................................... 728

15.3.5 Serial Mode Register (SCSMR).......................................................................... 729

15.3.6 Serial Control Register (SCSCR)........................................................................ 732

15.3.7 Serial Status Register (SCFSR)........................................................................... 736

15.3.8 Bit Rate Register (SCBRR) ................................................................................ 744

15.3.9 FIFO Control Register (SCFCR) ........................................................................ 754

15.3.10 FIFO Data Count Set Register (SCFDR) ............................................................ 757

15.3.11 Serial Port Register (SCSPTR) ........................................................................... 758

15.3.12 Line Status Register (SCLSR) ............................................................................ 761

15.3.13 Serial Extension Mode Register (SCEMR)......................................................... 762

15.4 Operation ........................................................................................................................... 763

15.4.1 Overview............................................................................................................. 763

15.4.2 Operation in Asynchronous Mode ...................................................................... 766

15.4.3 Operation in Clock Synchronous Mode.............................................................. 777

15.5 SCIF Interrupts................................................................................................................... 785

15.6 Usage Notes ....................................................................................................................... 786

15.6.1 SCFTDR Writing and TDFE Flag ...................................................................... 786

15.6.2 SCFRDR Reading and RDF Flag ....................................................................... 786

15.6.3 Restriction on DMAC Usage .............................................................................. 787

15.6.4 Break Detection and Processing ......................................................................... 787

15.6.5 Sending a Break Signal....................................................................................... 787

15.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode).... 787

15.6.7 Selection of Base Clock in Asynchronous Mode................................................ 789

Section 16 Synchronous Serial Communication Unit (SSU) ............................791

16.1 Features ............................................................................................................................ 791

16.2 Input/Output Pins............................................................................................................... 793

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16.3 Register Descriptions......................................................................................................... 794

16.3.1 SS Control Register H (SSCRH) .......................................................................... 795

16.3.2 SS Control Register L (SSCRL) ........................................................................... 797

16.3.3 SS Mode Register (SSMR) ................................................................................... 798

16.3.4 SS Enable Register (SSER) .................................................................................. 799

16.3.5 SS Status Register (SSSR).................................................................................... 801

16.3.6 SS Control Register 2 (SSCR2) ............................................................................ 804

16.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)................................... 805

16.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3).................................... 806

16.3.9 SS Shift Register (SSTRSR)................................................................................. 807

16.4 Operation ........................................................................................................................... 808

16.4.1 Transfer Clock ...................................................................................................... 808

16.4.2 Relationship of Clock Phase, Polarity, and Data .................................................. 808

16.4.3 Relationship between Data Input/Output Pins and Shift Register ........................ 809

16.4.4 Communication Modes and Pin Functions ........................................................... 811

16.4.5 SSU Mode............................................................................................................. 813

16.4.6 SCS Pin Control and Conflict Error...................................................................... 822

16.4.7 Clock Synchronous Communication Mode .......................................................... 823

16.5 SSU Interrupt Sources and DMAC.................................................................................... 830

16.6 Usage Note......................................................................................................................... 831

16.6.1 Module Standby Mode Setting ............................................................................. 831

16.6.2 Note on Continuous Transmission/Reception in SSU Slave Mode ...................... 831

16.6.3 Note in the Master Transmission Operation or the Master Transmission/

Reception Operation of SSU Mode ...................................................................... 831

Section 17 I2C Bus Interface 3 (IIC3)................................................................833

17.1 Features.............................................................................................................................. 833

17.2 Input/Output Pins............................................................................................................... 835

17.3 Register Descriptions......................................................................................................... 836

17.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 837

17.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 840

17.3.3 I2C Bus Mode Register (ICMR)............................................................................ 842

17.3.4 I2C Bus Interrupt Enable Register (ICIER)........................................................... 844

17.3.5 I2C Bus Status Register (ICSR)............................................................................. 846

17.3.6 Slave Address Register (SAR).............................................................................. 849

17.3.7 I2C Bus Transmit Data Register (ICDRT) ............................................................ 849

17.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 850

17.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 850

17.3.10 NF2CYC Register (NF2CYC).............................................................................. 851

17.4 Operation ........................................................................................................................... 852

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17.4.1 I2C Bus Format...................................................................................................... 852

17.4.2 Master Transmit Operation................................................................................... 853

17.4.3 Master Receive Operation..................................................................................... 855

17.4.4 Slave Transmit Operation ..................................................................................... 857

17.4.5 Slave Receive Operation....................................................................................... 860

17.4.6 Clocked Synchronous Serial Format..................................................................... 861

17.4.7 Noise Filter ........................................................................................................... 865

17.4.8 Example of Use..................................................................................................... 866

17.5 Interrupt Requests .............................................................................................................. 870

17.6 Bit Synchronous Circuit..................................................................................................... 871

17.7 Usage Notes ....................................................................................................................... 873

17.7.1 Note on the Setting of ICCR1.CKS[3:0]............................................................... 873

17.7.2 Settings for Multi-Master Operation..................................................................... 873

17.7.3 Note on Master Receive Mode.............................................................................. 873

17.7.4 Note on Setting ACKBT in Master Receive Mode............................................... 874

17.7.5 Note on the States of Bits MST and TRN when Arbitration Is Lost..................... 874

Section 18 Serial Sound Interface (SSI) ............................................................875

18.1 Features.............................................................................................................................. 875

18.2 Input/Output Pins............................................................................................................... 878

18.3 Register Description........................................................................................................... 879

18.3.1 Control Register (SSICR) ..................................................................................... 880

18.3.2 Status Register (SSISR) ........................................................................................ 886

18.3.3 Transmit Data Register (SSITDR)........................................................................ 891

18.3.4 Receive Data Register (SSIRDR) ......................................................................... 891

18.4 Operation Description........................................................................................................ 892

18.4.1 Bus Format............................................................................................................ 892

18.4.2 Non-Compressed Modes....................................................................................... 893

18.4.3 Operation Modes................................................................................................... 903

18.4.4 Transmit Operation ............................................................................................... 904

18.4.5 Receive Operation................................................................................................. 907

18.4.6 Temporary Stop and Restart Procedures in Transmit Mode ................................. 910

18.4.7 Serial Bit Clock Control........................................................................................ 911

18.5 Usage Notes ....................................................................................................................... 912

18.5.1 Limitations from Underflow or Overflow during DMA Operation ...................... 912

Section 19 Controller Area Network (RCAN-TL1) ..........................................913

19.1 Summary............................................................................................................................ 913

19.1.1 Overview............................................................................................................... 913

19.1.2 Scope..................................................................................................................... 913

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19.1.3 Audience............................................................................................................... 913

19.1.4 References............................................................................................................. 913

19.1.5 Features................................................................................................................. 914

19.2 Architecture ....................................................................................................................... 915

19.3 Programming Model - Overview ....................................................................................... 919

19.3.1 Memory Map ........................................................................................................ 919

19.3.2 Mailbox Structure ................................................................................................. 921

19.3.3 RCAN-TL1 Control Registers .............................................................................. 938

19.3.4 RCAN-TL1 Mailbox Registers............................................................................. 959

19.3.5 Timer Registers..................................................................................................... 974

19.4 Application Note................................................................................................................ 988

19.4.1 Test Mode Settings ............................................................................................... 988

19.4.2 Configuration of RCAN-TL1 ............................................................................... 990

19.4.3 Message Transmission Sequence.......................................................................... 995

19.4.4 Message Receive Sequence ................................................................................ 1009

19.4.5 Reconfiguration of Mailbox................................................................................ 1011

19.5 Interrupt Sources.............................................................................................................. 1013

19.6 DMAC Interface .............................................................................................................. 1014

19.7 CAN Bus Interface........................................................................................................... 1015

19.8 Setting I/O Ports for RCAN-TL1..................................................................................... 1016

19.9 Usage Notes ..................................................................................................................... 1018

19.9.1 Notes on Port Setting for Multiple Channels Used as Single Channel ............... 1018

Section 20 A/D Converter (ADC) ...................................................................1019

20.1 Features............................................................................................................................ 1019

20.2 Input/Output Pins............................................................................................................. 1021

20.3 Register Descriptions....................................................................................................... 1022

20.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ............................................ 1023

20.3.2 A/D Control/Status Register (ADCSR) .............................................................. 1024

20.4 Operation ......................................................................................................................... 1028

20.4.1 Single Mode........................................................................................................ 1028

20.4.2 Multi Mode ......................................................................................................... 1031

20.4.3 Scan Mode .......................................................................................................... 1033

20.4.4 A/D Converter Activation by External Trigger or MTU2 .................................. 1036

20.4.5 Input Sampling and A/D Conversion Time ........................................................ 1036

20.4.6 External Trigger Input Timing............................................................................ 1038

20.5 Interrupt Sources and DMAC Transfer Request.............................................................. 1039

20.6 Definitions of A/D Conversion Accuracy........................................................................ 1040

20.7 Usage Notes ..................................................................................................................... 1041

20.7.1 Module Standby Mode Setting ........................................................................... 1041

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20.7.2 Setting Analog Input Voltage ........................................................................... 1041

20.7.3 Notes on Board Design ..................................................................................... 1041

20.7.4 Processing of Analog Input Pins....................................................................... 1042

20.7.5 Permissible Signal Source Impedance .............................................................. 1043

20.7.6 Influences on Absolute Precision...................................................................... 1044

20.7.7 A/D Conversion in Deep Standby Mode .......................................................... 1044

20.7.8 Note on Usage in Scan Mode and Multi Mode................................................. 1044

Section 21 D/A Converter (DAC)....................................................................1045

21.1 Features .......................................................................................................................... 1045

21.2 Input/Output Pins............................................................................................................. 1046

21.3 Register Descriptions ....................................................................................................... 1047

21.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)......................................... 1047

21.3.2 D/A Control Register (DACR) ......................................................................... 1048

21.4 Operation ......................................................................................................................... 1050

21.5 Usage Notes ..................................................................................................................... 1051

21.5.1 Module Standby Mode Setting ......................................................................... 1051

21.5.2 D/A Output Hold Function in Software Standby Mode.................................... 1051

21.5.3 Setting Analog Input Voltage ........................................................................... 1051

21.5.4 D/A Conversion in Deep Standby Mode .......................................................... 1051

Section 22 AND/NAND Flash Memory Controller (FLCTL) ........................1053

22.1 Features .......................................................................................................................... 1053

22.2 Input/Output Pins............................................................................................................. 1057

22.3 Register Descriptions ....................................................................................................... 1058

22.3.1 Common Control Register (FLCMNCR).......................................................... 1059

22.3.2 Command Control Register (FLCMDCR)........................................................ 1062

22.3.3 Command Code Register (FLCMCDR)............................................................ 1065

22.3.4 Address Register (FLADR) .............................................................................. 1066

22.3.5 Address Register 2 (FLADR2) ......................................................................... 1068

22.3.6 Data Counter Register (FLDTCNTR)............................................................... 1069

22.3.7 Data Register (FLDATAR)............................................................................... 1070

22.3.8 Interrupt DMA Control Register (FLINTDMACR) ......................................... 1071

22.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) ..................................... 1077

22.3.10 Ready Busy Timeout Counter (FLBSYCNT)................................................... 1078

22.3.11 Data FIFO Register (FLDTFIFO)..................................................................... 1079

22.3.12 Control Code FIFO Register (FLECFIFO) ....................................................... 1080

22.3.13 Transfer Control Register (FLTRCR)............................................................... 1081

22.4 Operation ......................................................................................................................... 1082

22.4.1 Access Sequence............................................................................................... 1082

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22.4.2 Operating Modes ................................................................................................ 1083

22.4.3 Register Setting Procedure.................................................................................. 1084

22.4.4 Command Access Mode ..................................................................................... 1085

22.4.5 Sector Access Mode............................................................................................ 1090

22.4.6 ECC Error Correction ......................................................................................... 1092

22.4.7 Status Read ......................................................................................................... 1093

22.5 Interrupt Sources.............................................................................................................. 1095

22.6 DMA Transfer Specifications .......................................................................................... 1096

22.7 Usage Notes ..................................................................................................................... 1096

Section 23 USB 2.0 Host/Function Module (USB).........................................1097

23.1 Features............................................................................................................................ 1097

23.2 Input/Output Pins............................................................................................................. 1099

23.3 Register Description......................................................................................................... 1101

23.3.1 System Configuration Control Register (SYSCFG) ......................................... 1103

23.3.2 System Configuration Status Register (SYSSTS)............................................. 1105

23.3.3 Device State Control Register (DVSTCTR)..................................................... 1107

23.3.4 Test Mode Register (TESTMODE) .................................................................. 1111

23.3.5 FIFO Port Configuration Registers (CFBCFG, D0FBCFG, D1FBCFG) ......... 1113

23.3.6 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO) ............................................ 1116

23.3.7 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)............. 1117

23.3.8 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) ........ 1121

23.3.9 FIFO Port SIE Register (CFIFOSIE)................................................................ 1123

23.3.10 Transaction Counter Registers (D0FIFOTRN, D1FIFOTRN) ......................... 1124

23.3.11 Interrupts Enable Register 0 (INTENB0) ......................................................... 1125

23.3.12 Interrupt Enabled Register 1 (INTENB1)......................................................... 1128

23.3.13 BRDY Interrupts Enable Register (BRDYENB).............................................. 1130

23.3.14 NRDY Interrupt Enable Register (NRDYENB) ............................................... 1131

23.3.15 BEMP Interrupt Enabled Register (BEMPENB).............................................. 1133

23.3.16 Interrupt Status Register 0 (INTSTS0) ............................................................. 1135

23.3.17 Interrupt Status Register 1 (INTSTS1) ............................................................. 1137

23.3.18 BRDY Interrupt Status Register (BRDYSTS).................................................. 1140

23.3.19 NRDY Interrupt Status Register (NRDYSTS) ................................................. 1142

23.3.20 BEMP Interrupt Status Register (BEMPSTS) .................................................. 1144

23.3.21 Frame Number Register (FRMNUM)............................................................... 1146

23.3.22 μFrame Number Register (UFRMNUM) ......................................................... 1148

23.3.23 USB Address Register (USBADDR)................................................................ 1149

23.3.24 USB Request Type Register (USBREQ).......................................................... 1150

23.3.25 USB Request Value Register (USBVAL) ........................................................ 1151

23.3.26 USB Request Index Register (USBINDX) ....................................................... 1151

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23.3.27 USB Request Length Register (USBLENG) .................................................... 1152

23.3.28 DCP Configuration Register (DCPCFG) .......................................................... 1153

23.3.29 DCP Maximum Packet Size Register (DCPMAXP)......................................... 1155

23.3.30 DCP Control Register (DCPCTR) .................................................................... 1156

23.3.31 Pipe Window Select Register (PIPESEL)......................................................... 1158

23.3.32 Pipe Configuration Register (PIPECFG) .......................................................... 1159

23.3.33 Pipe Buffer Setting Register (PIPEBUF).......................................................... 1162

23.3.34 Pipe Maximum Packet Size Register (PIPEMAXP)......................................... 1164

23.3.35 Pipe Timing Control Register (PIPEPERI)....................................................... 1165

23.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 7)........................................... 1167

23.3.37 USB AC Characteristics Switching Register (USBACSWR)........................... 1169

23.4 Operation ......................................................................................................................... 1170

23.4.1 System Control ................................................................................................. 1170

23.4.2 Interrupt Functions............................................................................................ 1172

23.4.3 Pipe Control ...................................................................................................... 1190

23.4.4 Buffer Memory ................................................................................................. 1197

23.4.5 Control Transfers (DCP)................................................................................... 1213

23.4.6 Bulk Transfers (PIPE1 to PIPE5)...................................................................... 1216

23.4.7 Interrupt Transfers (PIPE6 and PIPE7)............................................................. 1218

23.4.8 Isochronous Transfers (PIPE1 and PIPE2) ....................................................... 1219

23.4.9 SOF Interpolation Function .............................................................................. 1226

23.4.10 Pipe Schedule.................................................................................................... 1228

23.5 Usage Notes ..................................................................................................................... 1230

23.5.1 Note on Using Isochronous OUT Transfer ....................................................... 1230

23.5.2 Procedure for Setting the USB Transceiver...................................................... 1231

23.5.3 Timing for the Clearing of Interrupt Sources.................................................... 1232

Section 24 LCD Controller (LCDC)................................................................1233

24.1 Features............................................................................................................................ 1233

24.2 Input/Output Pins............................................................................................................. 1235

24.3 Register Configuration..................................................................................................... 1236

24.3.1 LCDC Input Clock Register (LDICKR) ........................................................... 1237

24.3.2 LCDC Module Type Register (LDMTR) ......................................................... 1239

24.3.3 LCDC Data Format Register (LDDFR)............................................................ 1242

24.3.4 LCDC Scan Mode Register (LDSMR) ............................................................. 1244

24.3.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ....... 1246

24.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ....... 1247

24.3.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ....... 1248

24.3.8 LCDC Palette Control Register (LDPALCR)................................................... 1249

24.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ................................... 1250

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24.3.10 LCDC Horizontal Character Number Register (LDHCNR) ............................. 1251

24.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR)..................................... 1252

24.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ......................... 1253

24.3.13 LCDC Vertical Total Line Number Register (LDVTLNR).............................. 1254

24.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ......................................... 1255

24.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ... 1256

24.3.16 LCDC Interrupt Control Register (LDINTR) ................................................... 1257

24.3.17 LCDC Power Management Mode Register (LDPMMR) ................................. 1260

24.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR)............................ 1262

24.3.19 LCDC Control Register (LDCNTR)................................................................. 1264

24.3.20 LCDC User Specified Interrupt Control Register (LDUINTR)........................ 1265

24.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ......... 1267

24.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) ...................... 1268

24.4 Operation ......................................................................................................................... 1269

24.4.1 LCD Module Sizes which Can Be Displayed in this LCDC............................. 1269

24.4.2 Limits on the Resolution of Rotated Displays, Burst Length, and

Connected Memory (SDRAM)......................................................................... 1270

24.4.3 Color Palette Specification ............................................................................... 1277

24.4.4 Data Format ...................................................................................................... 1278

24.4.5 Setting the Display Resolution.......................................................................... 1281

24.4.6 Power Management Registers........................................................................... 1281

24.4.7 Operation for Hardware Rotation ..................................................................... 1286

24.5 Clock and LCD Data Signal Examples............................................................................ 1289

24.6 Usage Notes ..................................................................................................................... 1299

24.6.1 Procedure for Halting Access to Display Data Storage VRAM

(Synchronous DRAM in Area 3) ...................................................................... 1299

Section 25 Pin Function Controller (PFC) ......................................................1301

25.1 Features............................................................................................................................ 1307

25.2 Register Descriptions....................................................................................................... 1308

25.2.1 Port B I/O Register L (PBIORL) ...................................................................... 1309

25.2.2 Port B Control Registers L1 to L4 (PBCRL1 to PBCRL4) .............................. 1310

25.2.3 Port C I/O Register L (PCIORL) ...................................................................... 1315

25.2.4 Port C Control Register L1 to L4 (PCCRL1 to PCCRL4)................................ 1315

25.2.5 Port D I/O Register L (PDIORL)...................................................................... 1321

25.2.6 Port D Control Registers L1 to L4 (PDCRL1 to PDCRL4).............................. 1321

25.2.7 Port E I/O Register L (PEIORL)....................................................................... 1338

25.2.8 Port E Control Registers L1 to L4 (PECRL1 to PECRL4)............................... 1338

25.2.9 Port F I/O Registers H, L (PFIORH, PFIORL)................................................. 1345

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25.2.10 Port F Control Registers H1 to H4, L1 to L4

(PFCRH1 to PFCRH4, PFCRL1 to PFCRL4) .................................................. 1346

25.2.11 IRQOUT Function Control Register (IFCR) .................................................... 1360

25.2.12 SSI Oversampling Clock Selection Register (SCSR) ....................................... 1361

25.3 Switching Pin Function of Port A .................................................................................... 1363

25.4 Usage Notes ..................................................................................................................... 1364

Section 26 I/O Ports.........................................................................................1365

26.1 Features............................................................................................................................ 1365

26.2 Port A............................................................................................................................... 1366

26.2.1 Register Descriptions .......................................................................................... 1366

26.2.2 Port A Data Register L (PADRL) ....................................................................... 1366

26.3 Port B ............................................................................................................................... 1368

26.3.1 Register Descriptions .......................................................................................... 1368

26.3.2 Port B Data Register L (PBDRL) ....................................................................... 1369

26.3.3 Port B Port Register L (PBPRL)......................................................................... 1371

26.4 Port C ............................................................................................................................... 1372

26.4.1 Register Descriptions .......................................................................................... 1372

26.4.2 Port C Data Register L (PCDRL) ....................................................................... 1373

26.4.3 Port C Port Register L (PCPRL)......................................................................... 1375

26.5 Port D............................................................................................................................... 1376

26.5.1 Register Descriptions .......................................................................................... 1376

26.5.2 Port D Data Registers L (PDDRL) ..................................................................... 1377

26.5.3 Port D Port Registers L (PDPRL)....................................................................... 1379

26.6 Port E ............................................................................................................................... 1380

26.6.1 Register Descriptions .......................................................................................... 1380

26.6.2 Port E Data Registers L (PEDRL) ...................................................................... 1381

26.6.3 Port E Port Registers L (PEPRL)........................................................................ 1383

26.7 Port F................................................................................................................................ 1384

26.7.1 Register Descriptions .......................................................................................... 1385

26.7.2 Port F Data Registers H and L (PFDRH, PFDRL) ............................................. 1385

26.7.3 Port F Port Registers H and L (PFPRH, PFPRL)................................................ 1389

26.8 Usage Notes ..................................................................................................................... 1391

Section 27 On-Chip RAM ...............................................................................1393

27.1 Features............................................................................................................................ 1393

27.2 Usage Notes ..................................................................................................................... 1395

27.2.1 Page Conflict....................................................................................................... 1395

27.2.2 RAME and RAMWE Bits .................................................................................. 1395

27.2.3 Areas where Placing Instructions Is Prohibited .................................................. 1396

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Section 28 Power-Down Modes......................................................................1397

28.1 Features............................................................................................................................ 1397

28.1.1 Power-Down Modes ......................................................................................... 1397

28.2 Register Descriptions....................................................................................................... 1400

28.2.1 Standby Control Register (STBCR).................................................................. 1401

28.2.2 Standby Control Register 2 (STBCR2)............................................................. 1402

28.2.3 Standby Control Register 3 (STBCR3)............................................................. 1403

28.2.4 Standby Control Register 4 (STBCR4)............................................................. 1405

28.2.5 Standby Control Register 5 (STBCR5)............................................................. 1407

28.2.6 Standby Control Register 6 (STBCR6)............................................................. 1409

28.2.7 System Control Register 1 (SYSCR1).............................................................. 1410

28.2.8 System Control Register 2 (SYSCR2).............................................................. 1412

28.2.9 System Control Register 3 (SYSCR3).............................................................. 1413

28.2.10 Deep Standby Control Register (DSCTR) ........................................................ 1415

28.2.11 Deep Standby Control Register 2 (DSCTR2) ................................................... 1417

28.2.12 Deep Standby Cancel Source Select Register (DSSSR) ................................... 1418

28.2.13 Deep Standby Cancel Source Flag Register (DSFR)........................................ 1420

28.2.14 Retention On-Chip RAM Trimming Register (DSRTR) .................................. 1422

28.3 Operation ......................................................................................................................... 1423

28.3.1 Sleep Mode ....................................................................................................... 1423

28.3.2 Software Standby Mode.................................................................................... 1424

28.3.3 Software Standby Mode Application Example................................................. 1427

28.3.4 Deep Standby Mode.......................................................................................... 1428

28.3.5 Module Standby Function................................................................................. 1434

28.4 Usage Notes ..................................................................................................................... 1434

28.4.1 Notes on Writing to Registers........................................................................... 1434

28.4.2 Notice about Deep Standby Control Register 2 (DSCTR2).............................. 1434

28.4.3 Notice about Power-On Reset Exception Handling.......................................... 1435

Section 29 User Debugging Interface (H-UDI)...............................................1437

29.1 Features............................................................................................................................ 1437

29.2 Input/Output Pins............................................................................................................. 1438

29.3 Register Descriptions....................................................................................................... 1439

29.3.1 Bypass Register (SDBPR) ................................................................................ 1439

29.3.2 Instruction Register (SDIR) .............................................................................. 1439

29.4 Operation ......................................................................................................................... 1441

29.4.1 TAP Controller ................................................................................................. 1441

29.4.2 Reset Configuration .......................................................................................... 1442

29.4.3 TDO Output Timing ......................................................................................... 1442

29.4.4 H-UDI Reset ..................................................................................................... 1443

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29.4.5 H-UDI Interrupt ................................................................................................ 1443

29.5 Usage Notes ..................................................................................................................... 1444

Section 30 List of Registers .............................................................................1445

30.1 Register Addresses

(by functional module, in order of the corresponding section numbers).......................... 1446

30.2 Register Bits..................................................................................................................... 1469

30.3 Register States in Each Operating Mode.......................................................................... 1517

Section 31 Electrical Characteristics ...............................................................1521

31.1 Absolute Maximum Ratings ............................................................................................ 1521

31.2 Power-on/Power-off Sequence......................................................................................... 1522

31.3 DC Characteristics ........................................................................................................... 1523

31.4 AC Characteristics ........................................................................................................... 1531

31.4.1 Clock Timing .................................................................................................... 1532

31.4.2 Control Signal Timing ...................................................................................... 1536

31.4.3 Bus Timing ....................................................................................................... 1539

31.4.4 UBC Timing ..................................................................................................... 1574

31.4.5 DMAC Timing.................................................................................................. 1575

31.4.6 MTU2 Timing................................................................................................... 1576

31.4.7 WDT Timing..................................................................................................... 1577

31.4.8 SCIF Timing ..................................................................................................... 1578

31.4.9 SSU Timing ...................................................................................................... 1579

31.4.10 IIC3 Timing ...................................................................................................... 1582

31.4.11 SSI Timing........................................................................................................ 1584

31.4.12 RCAN-TL1 Timing .......................................................................................... 1586

31.4.13 ADC Timing ..................................................................................................... 1587

31.4.14 FLCTL Timing ................................................................................................. 1588

31.4.15 USB Timing...................................................................................................... 1596

31.4.16 LCDC Timing................................................................................................... 1598

31.4.17 I/O Port Timing................................................................................................. 1600

31.4.18 H-UDI Timing .................................................................................................. 1601

31.4.19 AC Characteristics Measurement Conditions ................................................... 1603

31.5 A/D Converter Characteristics ......................................................................................... 1604

31.6 D/A Converter Characteristics ......................................................................................... 1605

31.7 Usage Note....................................................................................................................... 1606

Appendix ..........................................................................................................607

A. Pin States.......................................................................................................................... 1607

B. Treatment of Unused Pins................................................................................................ 1613

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C. Package Dimensions ........................................................................................................ 1615

Main Revisions for this Edition.........................................................................1617

Index .......................................................................................................1641

Section 1 Overview

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Section 1 Overview

1.1 SH7203 Features

This LSI is a single-chip RISC (reduced instruction set computer) microcontroller that includes a

Renesas Technology-original RISC CPU as its core, and the peripheral functions required to

configure a system.

The CPU in this LSI is the SH-2A CPU that provides upward compatibility for SH-1, SH-2, and

SH-2E CPUs at object code level. It has a RISC-type instruction set and uses a superscalar

architecture and a Harvard architecture, which greatly improves instruction execution speed. In

addition, the 32-bit internal-bus architecture that is independent from the direct memory access

controller (DMAC) enhances data processing power. This CPU brings the user the ability to set up

high-performance systems with strong functionality at less expense than was achievable with

previous microcontrollers, and is even able to handle realtime control applications requiring high-

speed characteristics.

This LSI has a floating-point unit (FPU) and cache. In addition, this LSI includes on-chip

peripheral functions necessary for system configuration, such as 64-Kbyte RAM for high-speed

operation, 16-Kbyte RAM for data retention, a multi-function timer pulse unit 2 (MTU2), a

compare match timer (CMT), a realtime clock (RTC), a serial communication interface with FIFO

(SCIF), a synchronous serial communication unit (SSU), an I2C bus interface 3 (IIC3), a serial

sound interface (SSI), a controller area network (RCAN-TL1), an A/D converter, a D/A converter,

an AND/NAND flash memory controller (FLCTL), a USB2.0 host/function module (USB), an

interrupt controller (INTC), and I/O ports.

This LSI also provides an external memory access support function to enable direct connection to

various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of

designing and manufacturing application systems. Furthermore, I/O pins in this LSI have weak

keeper circuits that prevent the pin voltage from entering an intermediate potential range.

Therefore, no external circuits to fix the input level are required, which reduces the parts number

considerably.

The features of this LSI are listed in table 1.1.

Section 1 Overview

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Table 1.1 SH7203 Features

Items Specification

CPU • Renesas Technology original SuperH architecture

• Compatible with SH-1, SH-2, and SH-2E at object code level

• 32-bit internal data bus

• Support of an abundant register-set

⎯ Sixteen 32-bit general registers

⎯ Four 32-bit control registers

⎯ Four 32-bit system registers

⎯ Register bank for high-speed response to interrupts

• RISC-type instruction set (upward compatible with SH series)

⎯ Instruction length: 16-bit fixed-length basic instructions for improved

code efficiency and 32-bit instructions for high performance and

usability

⎯ Load/store architecture

⎯ Delayed branch instructions

⎯ Instruction set based on C language

• Superscalar architecture to execute two instructions at one time

including FPU

• Instruction execution time: Up to two instructions/cycle

• Address space: 4 Gbytes

• Internal multiplier

• Five-stage pipeline

• Harvard architecture

Section 1 Overview

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Items Specification

Floating-point unit

(FPU)

• Floating-point co-processor included

• Supports single-precision (32-bit) and double-precision (64-bit)

• Supports data type and exceptions that conforms to IEEE754 standard

• Two rounding modes: Round to nearest and round to zero

• Two denormalization modes: Flush to zero

• Floating-point registers

⎯ Sixteen 32-bit floating-point registers (single-precision × 16 words

or double-precision × 8 words)

⎯ Two 32-bit floating-point system registers

• Supports FMAC (multiplication and accumulation) instructions

• Supports FDIV (division) and FSQRT (square root) instructions

• Supports FLDI0/FLDI1 (load constant 0/1) instructions

• Instruction execution time

⎯ Latency (FAMC/FADD/FSUB/FMUL): Three cycles (single-

precision), eight cycles (double-precision)

⎯ Pitch (FAMC/FADD/FSUB/FMUL): One cycle (single-precision), six

cycles (double-precision)

Note: FMAC only supports single-precision

• Five-stage pipeline

Cache memory • Instruction cache: 8 Kbytes

• Operand cache: 8 Kbytes

• 128-entry/way, 4-way set associative, 16-byte block length

configuration each for the instruction cache and operand cache

• Write-back, write-through, LRU replacement algorithm

• Way-lock function available (only for operand cache); ways 2 and 3

can be locked

Interrupt controller

(INTC)

• Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to

PINT0)

• On-chip peripheral interrupts: Priority level set for each module

• 16 priority levels available

• Register bank enabling fast register saving and restoring in interrupt

processing

Section 1 Overview

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Items Specification

Bus state controller

(BSC)

• Address space divided into eight areas (0 to 7), each a maximum of 64

Mbytes

• The following features settable for each area independently

⎯ Bus size (8, 16, or 32 bits): Available sizes depend on the area.

⎯ Number of access wait cycles (different wait cycles can be

specified for read and write access cycles in some areas)

⎯ Idle wait cycle insertion (between same area access cycles or

different area access cycles)

⎯ Specifying the memory to be connected to each area enables

direct connection to SRAM, SRAM with byte selection, SDRAM,

and burst ROM (clocked synchronous or asynchronous). The

address/data multiplexed I/O (MPX) interface and burst MPX-I/O

interface are also available.

⎯ PCMCIA interface

⎯ Outputs a chip select signal (CS0 to CS7) according to the target

area (CS assert or negate timing can be selected by software)

• SDRAM refresh

Auto refresh or self refresh mode selectable

• SDRAM burst access

Direct memory access

controller (DMAC)

• Eight channels; external request available for four of them

• Can be activated by on-chip peripheral modules

• Burst mode and cycle steal mode

• Intermittent mode available (16 and 64 cycles supported)

• Transfer information can be automatically reloaded

Clock pulse generator

(CPG)

• Clock mode: Input clock can be selected from external input (EXTAL,

CKIO, or USB_X1) or crystal resonator

• Input clock can be multiplied by 16 (max.) by the internal PLL circuit

• Three types of clocks generated:

⎯ CPU clock: Maximum 200 MHz

⎯ Bus clock: Maximum 66 MHz

⎯ Peripheral clock: Maximum 33 MHz

Watchdog timer

(WDT)

• On-chip one-channel watchdog timer

• A counter overflow can reset the LSI