1 Mb (64K x 16) Static RAM
PRELIMINARY
CY62127DV18
MoBL2
®
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05226 Rev . *A Revised May 5, 2005
Features
• Very high speed: 55 ns
• Voltage range: 1.65V to 2.2V
• Ultra-low active power
—Typical active current: 0.5 mA @ f = 1 MHz
—Typical active current: 3.75 mA @ f = fMAX
• Ultra-lo w standby powe r
• Easy memory expansion with CE</> and OE</> fea-
tures
• Automatic power-down wh en deselected
• Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
Functional Description[1]
The CY62127DV18 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features ad-
vanced circuit design to p rovide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The device can be put into standby mode reducing power con-
sumption by more than 99% when deselected Chip Enable
(CE) HIGH or both BHE and BLE are HIGH. The input/output
pins (I/O0 through I/O15) are placed in a high-impedance state
when: deselected Chip Enable (CE) HIGH, outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH) or during a write operation
(Chip Enable (CE) LOW and Write Enable (WE) LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) LOW and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/Os pins (A0 through A15). If Byte High Enable (BHE) is LOW ,
then data from I/O pins (I/O8 through I/O15) is written into the
location specified on the ad
Reading from the device is accomplished by taking Ch ip En-
able (CE) LOW and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low En able (BLE) is LOW,
then O7. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O8 to I/O15. See the truth table at the
back of this data sheet for a complete description of re
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array I/O0–I/O7
COLUMN DECODER
A11
A12
A13
A14
A15
2048 X 512
SENSE AMPS
DATA IN DRIVERS
OE
I/O8–I/O15
CE
WE
BLE
BHE
ROW DECODER
A7
A6
A3
A0
A2
A1
A5
A4
A8
Power - Down
Circuit BHE
BLE
CE
A9
A10
CY62127DV18
MoBL2®
PRELIMINARY
Document #:38-05226 Rev.*A Page 2 of 11
Pin Configuration[2]
Note:
2. E3 (DNU) can be left as NC or V ss to ensure prop er op eration. or l ef t open (Exp ansion Pins E4 - 2M, D3 - 4M, H1 - 8M, G 2 - 16M, H6 - 32 M)., NC Pin s ar e not
connected to the die.
WE
VCC
A11
A10
DNU
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
VSS
A7
I/O0
BHE
DNU
DNU
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
DNU
DNU DNU
3
26
5
4
1
D
E
B
A
C
F
G
H
FBGA
DNU
Top View
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15 29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
NC
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21 23
24 NC
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
CY62127DV18
MoBL2®
PRELIMINARY
Document #:38-05226 Rev.*A Page 3 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential.−0.2V to VCCMAX + 0.2V
DC Voltage Applied to Outputs
in High-Z State[3]....................................−0.2V to VCC + 0.2V
DC Input Voltage[3]................................−0.2V to VCC + 0.2V
Output Current into Outputs (LOW).......... ... ................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ............. .. ............................. .. ... ...> 200 mA
Operating Range
Notes:
3. VIL(min.) = −1.0V for pulse durations less than 20 ns., VIH(max.) = Vcc+0.5V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
5. Tested initially and after any design or proces changes that may af fect these parameters.
Range Ambient
Temperature (TA)V
CC
Industrial −40°C to +85°C 1.65V to 2.2V
Product Portfolio
Product VCC Range(V) Speed
(ns)
Power Dissipation
Operating, Icc (mA) Standby, ISB2 (µA)f = 1 MHz f = fMAX
Min. Typ. Max. Typ.[4] Max. Typ.[4] Max. Typ.[4] Max.
CY62127DV18L 1.65 1.8 2.2 55 0.5 1.5 3.75 7.5 0.5 5
CY62127DV18LL 55 0.5 1.5 3.75 7.5 0.5 4
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions CY62127DV18-55 UnitMin. Typ.[4] Max.
VOH Output HIGH Voltage IOH = −0.1 mA 1.4 V
VOL Output LOW Voltage IOL = 0.1 mA 0.2 V
VIH Input HIGH Voltage 1.4 VCC + 0.2 V
VIL Input LOW Voltage −0.2 0.4 V
IIX Input Leakage Current GND < VI < VCC −1+1µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled −1+1µA
ICC VCC Operating Supply Cur-
rent f = fMAX = 1/tRC Vcc = 2.2V, IOUT =
0mA, CMOS level 3.75 7.5 mA
f = 1 MHz 0.5 1.5
ISB1 Automatic CE Power-down
Current − CMOS Inputs CE > VCC − 0.2V,
VIN > VCC − 0.2V, VIN < 0.2V,
f = fMAX (Address and Data Only),
f = 0 (OE, WE, BHE and BLE)
L0.55µA
LL 0.5 4
ISB2 Automatic CE Power-down
Current − CMOS Inputs CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V,
f = 0, VCC=2.2V
L0.55µA
LL 0.5 4
Capacitance[5]
Parameter Description Test Con ditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz
VCC = VCC(typ) 8pF
COUT Output Capacitance 8 pF
Thermal Resistance
Parameter Description Test Conditions FBGA TSOP II Unit
θJA Thermal Resistance (Junction to Ambient)[5] Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board 55 76 °C/W
θJC Thermal Resistance (Junction to Case)[5] 12 11 °C/W
CY62127DV18
MoBL2®
PRELIMINARY
Document #:38-05226 Rev.*A Page 4 of 11
AC Test Loads and Waveforms
Data Retention Characteristics
Data Retention Waveform[7]
Notes:</>
6. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Ch ip Enable signals or by disabling both
V
CC
Typ
V
CC
OUTPUT
R2
C = 50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT V
TH
Equivalent to: TH
ÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise Time:
1 V/ns Fall Time:
1 V/ns
L
Parameters 1.8V UNIT
R1 13500 Ω
R2 10800 Ω
R
TH
6000 Ω
V
TH
0.80 V
Parameter Description Conditions Min. Typ.[4] Max. Unit
VDR VCC for Data Retention 1 2.2 V
ICCDR Data Retention Current VCC=1.5V, CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V L4µA
LL 3
tCDR[5] Chip Deselect to Data
Retention Time 0ns
tR[6] Operation Recovery Time 100 µs
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
t
R
CE
V
CC
VCC(min.) VCC(min.)
CY62127DV18
MoBL2®
PRELIMINARY
Document #:38-05226 Rev.*A Page 5 of 11
Switching Characteristics (Over the Operating Range)[8]
Parameter Description CY62127DV18-55 UnitMin. Max.
Read Cycle
tRC Read Cycle Time 55 ns
tAA Address to Data Valid 55 ns
tOHA Data Hold from Address Change 10 ns
tACE CE LOW to Data Valid 55 ns
tDOE OE LOW to Data Valid 25 ns
tLZOE OE LOW to Low Z[9] 5ns
tHZOE OE HIGH to High Z[9,11] 20 ns
tLZCE CE LOW to Low Z[9] 10 ns
tHZCE CE HIGH to High Z[9,11] 20 ns
tPU CE LOW to Power-up 0 ns
tPD CE HIGH to Power-down 55 ns
tDBE BLE/BHE LOW to Data Va lid 55 ns
tLZBE[10] BLE/BHE LOW to Low Z[9] 5ns
tHZBE BLE/BHE HIGH to High-Z[9,11] 20 ns
Write Cycle[12]
tWC Write Cycle Time 55 ns
tSCE CE LOW to Write End 40 ns
tAW Address Set-up to Write End 40 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-up to Write Start 0 ns
tPWE WE Pulse Width 40 ns
tBW BLE/BHE LOW to Write End 40 ns
tSD Data Set-up to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High Z[9,11] 20 ns
tLZWE WE HIGH to Low Z[9] 10 ns
Notes:
8. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading
of the specified IOL/IOH and 50 pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t
10. If both byte enables are toggled together, this value is 10 ns.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signal
CY62127DV18
MoBL2®
PRELIMINARY
Document #:38-05226 Rev.*A Page 6 of 11
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13,14]
Read Cycle No. 2 (OE Controlled)[14,15]
Notes:
13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
OE
DATA OUT
SUPPLY
CURRENT
BHE, BLE
ICC
ISB
HIGH
IMPEDANCE
ADDRESS
tLZBEtDBE tHZBE
CE
VCC
CY62127DV18
MoBL2®
PRELIMINARY
Document #:38-05226 Rev.*A Page 7 of 11
Write Cycle No. 1 (WE Controlled) [11,12, 16, 17, 18]
Write Cycle No. 2 (CE Controlled) [11,12, 16, 17, 18]
Notes:
16. Data I/O is high-impedance if OE = VIH.
17. If CE goes HIGH simultaneously with WE HIGH, the out put remains in a high-impedance state .
18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
A
DDRESS
WE
DATA I/O
OE
BHE/BLE t
BW
DON'T CARE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
A
DDRESS
WE
DATA I/O
OE
BHE/BLE t
BW
t
SA
DON'T CARE
CY62127DV18
MoBL2®
PRELIMINARY
Document #:38-05226 Rev.*A Page 8 of 11
Write Cycle No. 3 (WE Controlled, OE LOW )[17, 18]
Write Cycle No. 4 (BHE</>/ BLE</> Controlled, OE</> LOW)</>[17, 18]</>
DATA
IN
VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
A
DDRESS
WE
DATA I/O
t
BW
BHE/BLE
DON'T CARE
DATA I/O
A
DDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
CE
WE
DATA
IN
VALID
t
BW
BHE/BLE
t
SCE
t
PWE
DON'T CARE
CY62127DV18
MoBL2®
PRELIMINARY
Document #:38-05226 Rev.*A Page 9 of 11
Package Diagrams
Truth Table
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
55 CY62127DV18L-55BVI BV48A 48-ball Fine Pitch BGA (6mm x 8mm x 1mm) Industrial
CY62127DV18LL-55BVI BV48A 48-ball Fine Pitch BGA (6mm x 8mm x 1mm)
CY62127DV18L-55ZI Z44 44-Lead TSOP Type II
CY62127DV18LL-55ZI Z44 44-Lead TSOP Type II
X X X H H High Z Deselect/Power-down Standby(I
SB
)
L H L L L Read All bits Active (I
CC
)
L H L H L Read Lower Byte Only Active (I
CC
)
L H L L H Read Upper Byte Only Active (I
CC
)
L H H L L Output Disabled Active (I
CC
)
L H H H L Output Disabled Active (I
CC
)
L H H L H Output Disabled Active (I
CC
)
High Z
High Z
High Z
Data Out
Data Out
High Z
Data Out
High Z
High Z
High Z
Data Out
High Z
High Z
LLXLLData In Data In Write Active (I
CC
)
L
LL
LX
XH
LL
HData In
High Z High Z
Data In Write Lower Byte Only
Write Upper Byte Only Active (I
CC
)
Active (I
CC
)
51-85150-*B
48-Ball (6 mm x 8 mm x 1 mm) Fine Pitch BGA BV48A
PRELIMINARY CY62127DV18
MoBL2
®
Document #: 38-05226 Rev. *A Page 10 of 11
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or othe r ri gh ts. Cypr es s S em icon du ct or do es n ot aut ho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemn ifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
MoBL is a registered trademark, and MoBL2 an d More Battery Li fe are tra demarks, of C ypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
51-85087-A
44-Pin TSOP II Z44
CY62127DV18
MoBL2®
PRELIMINARY
Document #:38-05226 Rev.*A Page 11 of 11
Document History Page
Document Title: CY62127DV18 MoBL2® 1 Mb (64K x 16) Static RAM
Document Number: 38-05226
REV. ECN NO. Issue Date Orig. of
Change Description of Ch ange
** 118006 10/01/02 CDY New Data Sheet
*A 127312 06/17/03 MPR Changed status from Advance Information to Preliminary
Changed Isb2 to 5 uA(L), 4 uA(LL)
Changed Iccdr to 4 uA(L), 3 uA(LL)
Changed Cin from 6 pF to 8 pF
