CY62127DV18 MoBL2(R) PRELIMINARY 1 Mb (64K x 16) Static RAM Features * Very high speed: 55 ns * Voltage range: 1.65V to 2.2V * Ultra-low active power -- Typical active current: 0.5 mA @ f = 1 MHz -- Typical active current: 3.75 mA @ f = fMAX * Ultra-low standby power * Easy memory expansion with CE</> and OE</> features * Automatic power-down when deselected * Packages offered in a 48-ball FBGA and a 44-lead TSOP Type II Functional Description[1] The CY62127DV18 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable (CE) HIGH or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable (CE) HIGH, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable (CE) LOW and Write Enable (WE) LOW). Writing to the device is accomplished by taking Chip Enable (CE) LOW and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/Os pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the ad Reading from the device is accomplished by taking Chip Enable (CE) LOW and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of re Logic Block Diagram A6 A5 A4 A3 A2 A1 A0 64K x 16 RAM Array 2048 X 512 SENSE AMPS A10 A9 A8 A7 ROW DECODER DATA IN DRIVERS I/O0-I/O7 I/O8-I/O15 BHE WE CE OE BLE A14 A15 A13 A12 A11 COLUMN DECODER Power - Down Circuit CE BHE BLE Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05226 Rev. *A * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised May 5, 2005 CY62127DV18 MoBL2(R) PRELIMINARY Pin Configuration[2] TSOP II (Forward) Top View FBGA Top View 1 2 OE BLE 3 A0 4 A1 5 A2 6 DNU A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C I/O3 VCC D A7 VSS I/O11 DNU VCC I/O12 DNU DNU I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 DNU A12 A13 WE I/O7 G A9 A10 A11 DNU H DNU A8 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Note: 2. E3 (DNU) can be left as NC or Vss to ensure proper operation. or left open(Expansion Pins E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M)., NC Pins are not connected to the die. Document #:38-05226 Rev.*A Page 2 of 11 CY62127DV18 MoBL2(R) PRELIMINARY DC Input Voltage[3] ................................ -0.2V to VCC + 0.2V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. -65C to +150C Latch-up Current .................................................... > 200 mA Ambient Temperature with Power Applied............................................. -55C to +125C Operating Range Supply Voltage to Ground Potential .-0.2V to VCCMAX + 0.2V Range Ambient Temperature (TA) VCC Industrial -40C to +85C 1.65V to 2.2V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.2V to VCC + 0.2V Product Portfolio Power Dissipation Operating, Icc (mA) VCC Range(V) Product CY62127DV18L f = 1 MHz Standby, ISB2 (A) f = fMAX Min. Typ. Max. Speed (ns) Typ.[4] Max. Typ.[4] Max. Typ.[4] Max. 1.65 1.8 2.2 55 0.5 1.5 3.75 7.5 0.5 5 55 0.5 1.5 3.75 7.5 0.5 4 CY62127DV18LL DC Electrical Characteristics Over the Operating Range CY62127DV18-55 Parameter Description Test Conditions VOH Output HIGH Voltage IOH = -0.1 mA VOL Output LOW Voltage IOL = 0.1 mA Min. Typ.[4] Max. Unit 0.2 V 1.4 V VIH Input HIGH Voltage 1.4 VCC + 0.2 V VIL Input LOW Voltage -0.2 0.4 V IIX Input Leakage Current GND < VI < VCC -1 +1 A IOZ Output Leakage Current GND < VO < VCC, Output Disabled -1 +1 A ICC VCC Operating Supply Cur- f = fMAX = 1/tRC rent f = 1 MHz 3.75 7.5 mA 0.5 1.5 ISB1 ISB2 Vcc = 2.2V, IOUT = 0mA, CMOS level Automatic CE Power-down Current - CMOS Inputs CE > VCC - 0.2V, VIN > VCC - 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) L 0.5 5 LL 0.5 4 Automatic CE Power-down Current - CMOS Inputs CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC=2.2V L 0.5 5 LL 0.5 4 A A Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz VCC = VCC(typ) Max. Unit 8 pF 8 pF Thermal Resistance Parameter FBGA TSOP II Unit 55 76 C/W JC 12 11 Notes: 3. VIL(min.) = -1.0V for pulse durations less than 20 ns., VIH(max.) = Vcc+0.5V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. 5. Tested initially and after any design or proces changes that may affect these parameters. C/W JA Description Test Conditions Thermal Resistance (Junction to Ambient)[5] Still Air, soldered on a 3 x 4.5 inch, Thermal Resistance (Junction to Case)[5] two-layer printed circuit board Document #:38-05226 Rev.*A Page 3 of 11 CY62127DV18 MoBL2(R) PRELIMINARY AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC Typ 10% GND R2 CL = 50 pF 90% 10% 90% Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: Fall Time: 1 V/ns THEVENIN EQUIVALENT RTH OUTPUT VTH Parameters 1.8V UNIT R1 13500 R2 10800 R TH 6000 V TH 0.80 V Data Retention Characteristics Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[5] Chip Deselect to Data Retention Time tR[6] Operation Recovery Time Conditions Min. Typ.[4] Max. Unit 2.2 V L 4 A LL 3 1 VCC=1.5V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 ns 100 s Data Retention Waveform[7] VCC V CC(min.) tCDR DATA RETENTION MODE VDR > 1.5V V CC(min.) tR CE Notes:</> 6. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 s. . 7. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both Document #:38-05226 Rev.*A Page 4 of 11 CY62127DV18 MoBL2(R) PRELIMINARY Switching Characteristics (Over the Operating Range)[8] CY62127DV18-55 Parameter Description Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 ns tDOE OE LOW to Data Valid 25 ns 20 ns 55 [9] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[9,11] tLZCE CE LOW to Low Z[9] tHZCE CE HIGH to High Z[9,11] tPU CE LOW to Power-up tPD CE HIGH to Power-down tDBE BLE/BHE LOW to Data Valid tLZBE[10] BLE/BHE LOW to Low Z[9] tHZBE BLE/BHE HIGH to ns 55 10 5 ns 10 ns 20 ns 55 ns 55 ns 0 ns 5 High-Z[9,11] ns ns ns 20 ns Write Cycle[12] tWC Write Cycle Time 55 ns tSCE CE LOW to Write End 40 ns tAW Address Set-up to Write End 40 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 40 ns tBW BLE/BHE LOW to Write End 40 ns tSD Data Set-up to Write End 25 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[9,11] tLZWE [9] WE HIGH to Low Z ns 20 10 ns ns Notes: 8. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 50 pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t 10. If both byte enables are toggled together, this value is 10 ns. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signal Document #:38-05226 Rev.*A Page 5 of 11 CY62127DV18 MoBL2(R) PRELIMINARY Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13,14] tRC ADDRESS tAA tOHA DATA OUT DATA VALID PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled)[14,15] ADDRESS tRC CE tACE OE BHE, BLE tDBE tHZBE tLZBE tHZOE tDOE tLZOE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes: 13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #:38-05226 Rev.*A Page 6 of 11 CY62127DV18 MoBL2(R) PRELIMINARY Write Cycle No. 1 (WE Controlled) [11,12, 16, 17, 18] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID DON'T CARE tHZOE Write Cycle No. 2 (CE Controlled) [11,12, 16, 17, 18] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE / BLE OE tSD DATA I/O tHD DATA IN VALID DON'T CARE tHZOE Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #:38-05226 Rev.*A Page 7 of 11 CY62127DV18 MoBL2(R) PRELIMINARY Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tHD tSD DATA I/O DATAIN VALID DON'T CARE tLZWE tHZWE Write Cycle No. 4 (BHE</>/BLE</> Controlled, OE</> LOW)</>[17, 18]</> tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O DON'T CARE Document #:38-05226 Rev.*A tHD DATAIN VALID Page 8 of 11 CY62127DV18 MoBL2(R) PRELIMINARY Truth Table X X X H H High Z High Z Deselect/Power-down L H L H L Standby (I SB ) L L L Data Out Data Out Read All bits Active (I CC ) L H L Data Out High Z Read Lower Byte Only Active (I CC ) H L L H High Z Data Out Read Upper Byte Only Active (I CC ) L H H L L High Z High Z Output Disabled Active (I CC ) L H H H L High Z High Z Output Disabled Active (I CC ) L H H L H High Z High Z Output Disabled Active (I CC ) L L X L L Data In Data In Write Active (I CC ) L L X H L Data In High Z Write Lower Byte Only Active (I CC ) L L X L H High Z Data In Write Upper Byte Only Active (I CC ) Ordering Information Speed (ns) 55 Ordering Code Package Name Package Type CY62127DV18L-55BVI BV48A 48-ball Fine Pitch BGA (6mm x 8mm x 1mm) CY62127DV18LL-55BVI BV48A 48-ball Fine Pitch BGA (6mm x 8mm x 1mm) CY62127DV18L-55ZI Z44 44-Lead TSOP Type II CY62127DV18LL-55ZI Z44 44-Lead TSOP Type II Operating Range Industrial Package Diagrams 48-Ball (6 mm x 8 mm x 1 mm) Fine Pitch BGA BV48A 51-85150-*B Document #:38-05226 Rev.*A Page 9 of 11 PRELIMINARY CY62127DV18 MoBL2(R) Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05226 Rev. *A Page 10 of 11 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY62127DV18 MoBL2(R) Document History Page Document Title: CY62127DV18 MoBL2(R) 1 Mb (64K x 16) Static RAM Document Number: 38-05226 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 118006 10/01/02 CDY New Data Sheet *A 127312 06/17/03 MPR Changed status from Advance Information to Preliminary Changed Isb2 to 5 uA(L), 4 uA(LL) Changed Iccdr to 4 uA(L), 3 uA(LL) Changed Cin from 6 pF to 8 pF Document #:38-05226 Rev.*A Page 11 of 11