Product Specification PE613050 UltraCMOS(R) SP4T Tuning Control Switch, 5-3000 MHz Product Description The PE613050 is an SP4T tuning control switch based on Peregrine's UltraCMOS(R) technology. This highly versatile switch supports a wide variety of tuning circuit topologies with emphasis on impedance matching and aperture tuning applications. PE613050 features low onresistance and insertion loss across key cellular frequency bands from 5 to 3000 MHz. PE613050 offers high RF power handling and ruggedness, while meeting challenging harmonic and linearity requirements enabled by Peregrine's HaRPTM technology. With two-pin low voltage CMOS control, all decoding and biasing is integrated on-chip and no external bypassing or filtering components are required. UltraCMOS tuning devices feature ease of use while delivering superior RF performance. With built-in bias voltage generation and ESD protection, tuning control switches provide a monolithically integrated tuning solution for demanding RF applications. Features Open reflective architecture Low on-resistance of 1.6 Low insertion loss 0.25 dB @ 900 MHz 0.40 dB @ 2200 MHz High power handling 35.1 dBm @ 900 MHz 35.1 dBm @ 2200 MHz Wide power supply range (2.3V to 5.5V) High ESD tolerance of 2 kV HBM on all pins Applications include Tunable antennas Tunable matching networks Bypassing applications RFID readers Figure 1. Functional Diagram Figure 2. Package Type 12-lead 2 2 0.5 mm QFN ANT ESD RF1 RF3 ESD ESD RF2 RF4 ESD CMOS Control / Driver and ESD V1 V2 VDD GND DOC-32614-6 www.psemi.com ESD DOC-62867 (c)2013-2018 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 8 Product Specification PE613050 Table 1. Electrical Specifications @ 25C, VDD = 2.75V Parameter Condition Min Operating Frequency Typ 5 Max Unit 3000 MHz RON RF-ANT, ON state, DC measurement 1.6 COFF RF-ANT, any OFF state 0.14 pF RF-ANT 5-100 MHz 0.17 RF-ANT 100-698 MHz 0.20 0.30 dB RF-ANT 698-960 MHz 0.25 0.35 dB RF-ANT 960-1710 MHz 0.35 0.45 dB RF-ANT 1710-2170 MHz 0.40 0.50 dB RF-ANT 2170-2500 MHz 0.45 0.55 dB RF-ANT 2500-2690 MHz 0.50 0.60 dB Insertion Loss 1 RF-ANT 5-100 MHz Isolation2 Harmonics3 dB 46 dB RF-ANT 100-698 MHz 26 28 dB RF-ANT 698-960 MHz 25 27 dB RF-ANT 960-1710 MHz 21 23 dB RF-ANT 1710-2170 MHz 19 21 dB RF-ANT 2170-2500 MHz 18 20 dB RF-ANT 2500-2690 MHz 17 19 dB RF-ANT 2690-3000 MHz 15 17 dB RF-ANT (2fo: 5 to 100 MHz; +26 dBm @ TX) -58 dBm RF-ANT (3fo: 5 to 100 MHz; +26 dBm @ TX) -87 dBm RF-ANT (2fo: 698 to 915 MHz; +35 dBm @ TX) -62 -36 dBm RF-ANT (3fo: 698 to 915 MHz; +35 dBm @ TX) -55 -36 dBm RF-ANT (2fo: 1710 to 1910 MHz; +33 dBm @ TX) -58 -36 dBm RF-ANT (3fo: 1710 to 1910 MHz; +33 dBm @ TX) -55 -36 dBm RF-ANT (2fo: 698 to 798 MHz; +26 dBm @ TX) -80 -36 dBm RF-ANT (3fo: 698 to 798 MHz; +26 dBm @ TX) -82 -36 dBm RF-ANT (2fo: 2500 to 2570 MHz; +26 dBm @ TX) -70 -36 dBm RF-ANT (3fo: 2500 to 2570 MHz; +26 dBm @ TX) -70 -36 dBm 5-100 MHz 80 dBm 100-3000 MHz 72 dBm Input IP3 Bands I,II,V,VIII, +20 dBm CW @ TX freq, -15 dBm CW @ 2TX-RX freq, 50, SWON IMD3 Switching Time Start-up Time 3 50% VCTRL to 90% RF ON or 10% RF OFF Time from VDD within specification to all performances within specification -120 -105 dBm 2 5 s 70 s Notes: 1. Tapered transmission lines on evaluation board provide optimal matching; no additional components on evaluation board required to meet specified performance. See Figure 5 for evaluation board layout. 2. Open reflective architecture for flexible configuration of switch in tuning application. 3. Pulsed RF input with 4620 s period, 50% duty cycle, measured per 3GPP TS 45.005. (c)2013-2018 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 8 DOC-32614-6 UltraCMOS(R) RFIC Solutions PE613050 Product Specification Table 4. Operating Ranges DGND 2 9 RF1 8 ANT RF2 GND 11 10 V1 5 RF4 Description VDD DGND 3 V2 Switch control input, CMOS logic level 4 V1 Switch control input, CMOS logic level Digital Ground RF I/O GND Ground1 7 RF3 RF I/O 8 ANT RF Common - Antenna 9 RF1 RF I/O 10 GND Ground1 PAD 5.50 V 140 200 A 1.5 3.1 V VIL Control Voltage Low 0 0 0.5 V 1 10 A 105 183 184 VPK VPK VPK +85 C 1,2 -40 +25 Table 5. Absolute Maximum Ratings Symbol Min Max Unit Supply Voltage -0.3 5.5 V Digital Input Voltage (V1, V2) -0.3 3.6 V TST Storage Temperature Range -65 +150 C 2000 V VESD,HBM HBM ESD Voltage, All Pins* Note: * Human Body Model (MIL_STD 883 Method 3015.7). RF I/O Digital Ground1 Exposed Paddle2 Notes: 1. All ground pins must be tied together (pins 6, 10, 12). 2. Recommend grounding but can be left floating. Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE613050 in the 12-lead 2 2 mm QFN package is MSL1. Table 3. Truth Table Path V2 V1 RF1-ANT 0 0 RF2-ANT 1 0 RF3-ANT 0 1 RF4-ANT 1 1 DOC-32614-6 www.psemi.com Parameter/Conditions VCTRL VDD RF4 6 13 2.75 Supply 5 RF2 2.30 Notes: 1. Between all RF ports, and from RF ports to GND. 2. Pulsed RF input duty cycle of 50% and 4620 s, measured per 3GPP TS 45.005. 3. RF input power of 35.1 dBm, 50. 4. RF input power of 35.1 dBm, 50. 5. RF input power of 30.0 dBm, 50. 2 DGND Unit 1.2 TOP Operating Temperature Range RF3 1 12 Max VIH Control Voltage High Peak Operating RF Voltage 5-100 MHz 100 MHz-1 GHz 1 GHz-3 GHz Pin Name 11 Typ Control Input Current Table 2. Pin Descriptions Pin No. Min IDD Power Supply Current (VDD = 2.75V, +25 C) 7 3 4 V2 13 PAD Exposed Paddle VDD Supply Voltage 6 1 Parameter GND VDD DGND Pin 1 12 Figure 3. Pin Configuration (Top View) Exceeding absolute maximum ratings may cause permanent damage. Operating should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. (c)2013-2018 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 8 Product Specification Equivalent Circuit Model Description PE613050 Table 6. Equivalent Circuit Model Parameters The Equivalent Circuit Model shown in Figure 4 can be used to accurately model the impedance, insertion loss, and isolation of the SP4T Tuning Switch. It provides a very close correlation to measured data and can easily be used in circuit simulation programs. Table 7 provides the mapping between the desired switch RF state (RF1 thru RF4) and the state variables (SW1 thru SW4). The equivalent circuit model parameter values can be calculated using equations shown in Table 6. Variable Equation (SW=0 for OFF and SW=1 for ON) Unit CP 0.25 pF COFF 0.14 pF RSW1 If SW1 == 1then 1.6 else 400e3 RSW2 If SW2 == 1then 1.6 else 400e3 RSW3 If SW3 == 1then 1.6 else 400e3 RSW4 If SW4 == 1then 1.6 else 400e3 LS 0.4 nH Table 7. Equivalent Circuit Model Variables RF State Variable Path V2 V1 SW1 SW2 SW3 SW4 RF1-ANT 0 0 1 0 0 0 RF2-ANT 1 0 0 1 0 0 RF3-ANT 0 1 0 0 1 0 RF4-ANT 1 1 0 0 0 1 Figure 4. Equivalent Circuit Model Schematic RSW1 LS COFF RF1 RSW2 CP LS COFF RF2 LS RSW3 CP ANT CP LS COFF RF3 RSW4 CP LS COFF RF4 CP (c)2013-2018 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 8 DOC-32614-6 UltraCMOS(R) RFIC Solutions PE613050 Product Specification Evaluation Board The SP4T switch Evaluation Board was designed to ease customer evaluation of Peregrine's PE613050. The RF common port is connected through a 50 transmission line via the top SMA connector, J1. RF1, RF2, RF3 and RF4 are connected through 50 transmission lines via SMA connectors J3, J5, J2 and J4, respectively. A through 50 transmission is available via SMA connectors J6 and J7. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board consists of a 4 layer stack with 2 outer layers made of Rogers 4350B (r = 3.48) and 2 inner layers of FR4 (r = 4.80). The total thickness of this board is 62 mils (1.57 mm). The inner layers provide a ground plane for the transmission lines. Each transmission line is designed using a coplanar waveguide with ground plane (CPWG) model using a trace width of 32 mils (0.813 mm), gap of 15 mils (0.381 mm), and a metal thickness of 1.4 mils (0.051 mm). DOC-32614-6 www.psemi.com Figure 5. Evaluation Board Layout PRT-28405 (c)2013-2018 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 8 Product Specification PE613050 Figure 6. Evaluation Board Schematic J1 SMASM ANT 1 2 U2 PE613050-QFN_12L_2X2 J5 SMASM 3 V2 2 4 V1 RF2 RF4 RFGND 1 VDD 1 RF3 RF2 RFGND PADDLE 7 5 10 14 12 10 8 6 4 2 J4 SMASM 13 RF4 1 R2 DNI J8 HEADER 14 14 12 10 8 6 4 2 2 2 6 RF1 1 2 9 11 J2 SMASM RF3 2 DGND RF1 12 TEST 1 ANT 8 J3 SMASM 13 11 9 7 5 3 1 13 11 9 TEST 7 VDD 5 3 V2 1 V1_DUT C5 DNI C4 DNI R3 DNI C3 DNI R1 DNI C2 DNI C1 DNI J7 SMASM 1 2 1 Through Line 2 J6 SMASM DOC-32627 (c)2013-2018 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 8 DOC-32614-6 UltraCMOS(R) RFIC Solutions PE613050 Product Specification Figure 7. Package Drawing 12-lead 2 2 0.50 mm 0.25 (X12) 0.10 C 2.00 A (X2) 0.475 (X12) 0.800.05 0.290.05 (x12) 9 7 B 0.50 (x8) 6 0.50 (x8) 10 0.800.05 2.00 0.85 2.40 12 0.200.05 (X12) 0.10 C 4 1 3 (X2) 1.00 Chamfer 0.25x45 PIN #1 Identifier TOP VIEW BOTTOM VIEW 0.85 2.40 RECOMMENDED LAND PATTERN DOC-50486 0.10 C 0.10 0.05 0.500.05 0.05 C SEATING PLANE C A B C ALL FEATURES 0.152 REF. SIDE VIEW 0.05 MAX C Notes: 1. Dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M, 1994. Figure 8. Top Marking Specifications PPZZ YWW DOC-51207 DOC-32614-6 www.psemi.com Marking Spec Symbol Package Marking PP DS ZZ 00-ZZ Y 0-9 WW 01-53 Note: Definition Part number code for PE613050 Last two characters of lot code Last digit of year, starting from 2009 (0 for 2010, 1 for 2011, etc.) Work week (PP), the package marking specific to the PE613050, is shown in the figure instead of the standard Peregrine package marking symbol (P). (c)2013-2018 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 8 Product Specification PE613050 Figure 9. Tape and Reel Specifications Tape Feed Direction Pin 1 Top of Device Device Orientation in Tape Table 8. Ordering Information Order Code Package Description Shipping Method PE613050A-Z 12-lead QFN 2 2 0.50 mm Package Part in Tape and Reel 3,000 units / T&R EK613050-01 Evaluation Kit Evaluation Kit 1 set / box Sales and Contact Information For sales and contact information please visit www.psemi.com. (c)2013-2018 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 8 DOC-32614-6 UltraCMOS(R) RFIC Solutions PE613050 Product Specification Document Categories Advance Information The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The datasheet contains preliminary data. Additional data may be added at a later date. pSemi reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The datasheet contains final data. In the event pSemi decides to change the specifications, pSemi will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Sales Contact For additional information, contact Sales at sales@psemi.com. Disclaimers The information in this document is believed to be reliable. However, pSemi assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. pSemi's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the pSemi product could create a situation in which personal injury or death might occur. pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Patent Statement pSemi products are protected under one or more of the following U.S. patents: patents.psemi.com Copyright and Trademark (c)2018, pSemi Corporation, a Murata company. All rights reserved. The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. DOC-32614-6 www.psemi.com (c)2013-2018 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 8