PE613050A-Z - PEREGRINE SEMICONDUCTOR

Page 1 of 8

CMOS Control /

Driver and ESD

V1 V2 VDD GND

RF1

ESD

RF3

ESD

ANT

ESD

RF2

ESD

RF4

ESD

Product Specification

UltraCMOS® SP4T Tuning Control

Switch, 5–3000 MHz

PE613050

Features

 Open reflective architecture

 Low on-resistance of 1.6Ω

 Low insertion loss

 0.25 dB @ 900 MHz

 0.40 dB @ 2200 MHz

 High power handling

 35.1 dBm @ 900 MHz

 35.1 dBm @ 2200 MHz

 Wide power supply range (2.3V to 5.5V)

 High ESD tolerance of 2 kV HBM

on all pins

 Applications include

 Tunable antennas

 Tunable matching networks

 Bypassing applications

 RFID readers

Figure 2. Package Type

12-lead 2  2  0.5 mm QFN

Figure 1. Functional Diagram

Product Description

The PE613050 is an SP4T tuning control switch based

on Peregrine’s UltraCMOS® technology. This highly

versatile switch supports a wide variety of tuning circuit

topologies with emphasis on impedance matching and

aperture tuning applications. PE613050 features low on-

resistance and insertion loss across key cellular

frequency bands from 5 to 3000 MHz.

PE613050 offers high RF power handling and

ruggedness, while meeting challenging harmonic and

linearity requirements enabled by Peregrine’s HaRP™

technology. With two-pin low voltage CMOS control, all

decoding and biasing is integrated on-chip and no

external bypassing or filtering components are required.

UltraCMOS tuning devices feature ease of use while

delivering superior RF performance. With built-in bias

voltage generation and ESD protection, tuning control

switches provide a monolithically integrated tuning

solution for demanding RF applications.

DOC–62867

Page 2 of 8

Product Specification PE613050

Table 1. Electrical Specifications @ 25°C, VDD = 2.75V

Notes: 1. Tapered transmission lines on evaluation board provide optimal matching; no additional components on evaluation board required to meet specified performance.

See Figure 5 for evaluation board layout.

2. Open reflective architecture for flexible configuration of switch in tuning application.

3. Pulsed RF input with 4620 µs period, 50% duty cycle, measured per 3GPP TS 45.005.

Parameter Condition Min Typ Max Unit

Operating Frequency 5 3000 MHz

RON RF–ANT, ON state, DC measurement 1.6 Ω

COFF RF–ANT, any OFF state 0.14 pF

Insertion Loss1

RF–ANT 5–100 MHz 0.17 dB

RF–ANT 100–698 MHz 0.20 0.30 dB

RF–ANT 698–960 MHz 0.25 0.35 dB

RF–ANT 960–1710 MHz 0.35 0.45 dB

RF–ANT 1710–2170 MHz 0.40 0.50 dB

RF–ANT 2170–2500 MHz 0.45 0.55 dB

RF–ANT 2500–2690 MHz 0.50 0.60 dB

Isolation2

RF–ANT 5–100 MHz 46 dB

RF–ANT 100–698 MHz 26 28 dB

RF–ANT 698–960 MHz 25 27 dB

RF–ANT 960–1710 MHz 21 23 dB

RF–ANT 1710–2170 MHz 19 21 dB

RF–ANT 2170–2500 MHz 18 20 dB

RF–ANT 2500–2690 MHz 17 19 dB

RF–ANT 2690–3000 MHz 15 17 dB

Harmonics3

RF–ANT (2fo: 5 to 100 MHz; +26 dBm @ TX) –58 dBm

RF–ANT (3fo: 5 to 100 MHz; +26 dBm @ TX) –87 dBm

RF–ANT (2fo: 698 to 915 MHz; +35 dBm @ TX) –62 –36 dBm

RF–ANT (3fo: 698 to 915 MHz; +35 dBm @ TX) –55 –36 dBm

RF–ANT (2fo: 1710 to 1910 MHz; +33 dBm @ TX) –58 –36 dBm

RF–ANT (3fo: 1710 to 1910 MHz; +33 dBm @ TX) –55 –36 dBm

RF–ANT (2fo: 698 to 798 MHz; +26 dBm @ TX) –80 –36 dBm

RF–ANT (3fo: 698 to 798 MHz; +26 dBm @ TX) –82 –36 dBm

RF–ANT (2fo: 2500 to 2570 MHz; +26 dBm @ TX) –70 –36 dBm

RF–ANT (3fo: 2500 to 2570 MHz; +26 dBm @ TX) –70 –36 dBm

5–100 MHz 80 dBm

Input IP3 100–3000 MHz 72 dBm

IMD3 Bands I,II,V,VIII, +20 dBm CW @ TX freq, –15 dBm CW @ 2TX–RX freq, 50Ω, SWON –120 –105 dBm

Switching Time 50% VCTRL to 90% RF ON or 10% RF OFF 2 5 µs

Start-up Time3 Time from VDD within specification to all performances within specification 70 µs

Page 3 of 8

Product Specification PE613050

Moisture Sensitivity Level

The Moisture Sensitivity Level rating for the

PE613050 in the 12-lead 2  2 mm QFN package

is MSL1.

VDD

V2

GND

DGNDV1

GND

RF3

RF1

Pin 1

DGND 2

1

3

4

6

7

9

10

12

RF4 5

ANT

8

RF2

11

13 PAD

Exposed

Paddle

Figure 3. Pin Configuration (Top View)

Table 2. Pin Descriptions

Pin No. Pin Name Description

1 VDD Supply

2 DGND Digital Ground

3 V2 Switch control input, CMOS logic level

4 V1 Switch control input, CMOS logic level

5 RF4 RF I/O

6 GND Ground1

7 RF3 RF I/O

8 ANT RF Common - Antenna

9 RF1 RF I/O

10 GND Ground1

11 RF2 RF I/O

12 DGND Digital Ground1

13 PAD Exposed Paddle2

Table 5. Absolute Maximum Ratings

Table 4. Operating Ranges

Parameter Min Typ Max Unit

VDD Supply Voltage 2.30 2.75 5.50 V

IDD Power Supply Current

(VDD = 2.75V, +25 °C) 140 200 µA

VIH Control Voltage High 1.2 1.5 3.1 V

VIL Control Voltage Low 0 0 0.5 V

Control Input Current 1 10 µA

Peak Operating RF Voltage1,2

5–100 MHz

100 MHz–1 GHz

1 GHz–3 GHz

105

183

184

VPK

TOP Operating Temperature

Range –40 +25 +85 °C

Symbol Parameter/Conditions Max Unit Min

VDD Supply Voltage 5.5 V –0.3

VCTRL Digital Input Voltage (V1, V2) 3.6 V –0.3

TST Storage Temperature Range +150 °C –65

VESD,HBM HBM ESD Voltage, All Pins* 2000 V

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating.

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS

devices are immune to latch-up.

Notes: 1. Between all RF ports, and from RF ports to GND.

2. Pulsed RF input duty cycle of 50% and 4620 µs, measured per 3GPP

TS 45.005.

3. RF input power of 35.1 dBm, 50Ω.

4. RF input power of 35.1 dBm, 50Ω.

5. RF input power of 30.0 dBm, 50Ω.

Exceeding absolute maximum ratings may cause

permanent damage. Operating should be

restricted to the limits in the Operating Ranges

table. Operation between operating range

maximum and absolute maximum for extended

periods may reduce reliability.

Note: * Human Body Model (MIL_STD 883 Method 3015.7).

Path V2 V1

RF1–ANT 0 0

RF2–ANT 1 0

RF3–ANT 0 1

RF4–ANT 1 1

Table 3. Truth Table

Notes: 1. All ground pins must be tied together (pins 6, 10, 12).

2. Recommend grounding but can be left floating.

Page 4 of 8

Product Specification PE613050

Figure 4. Equivalent Circuit Model Schematic

Equivalent Circuit Model Description

The Equivalent Circuit Model shown in Figure 4

can be used to accurately model the impedance,

insertion loss, and isolation of the SP4T Tuning

Switch. It provides a very close correlation to

measured data and can easily be used in circuit

simulation programs.

Table 7 provides the mapping between the desired

switch RF state (RF1 thru RF4) and the state

variables (SW1 thru SW4).

The equivalent circuit model parameter values can

be calculated using equations shown in Table 6.

Table 6. Equivalent Circuit Model Parameters

Variable Equation (SW=0 for OFF and SW=1 for ON) Unit

CP 0.25 pF

COFF 0.14 pF

RSW1 If SW1 == 1then 1.6 else 400e3 Ω

RSW2 If SW2 == 1then 1.6 else 400e3 Ω

RSW3 If SW3 == 1then 1.6 else 400e3 Ω

RSW4 If SW4 == 1then 1.6 else 400e3 Ω

LS 0.4 nH

COFF

RSW4

LS

RF4

CP

COFF

RSW3

LS

RF3

CP

COFF

RSW2

LS

RF2

CP

COFF

RSW1

LS

RF1

CP

ANT

LS

Table 7. Equivalent Circuit Model Variables

RF State Variable

Path V2 V1 SW1 SW2 SW3 SW4

RF1–ANT 0 0 1 0 0 0

RF2–ANT 1 0 0 1 0 0

RF3–ANT 0 1 0 0 1 0

RF4–ANT 1 1 0 0 0 1

Page 5 of 8

Product Specification PE613050

Evaluation Board

The SP4T switch Evaluation Board was designed

to ease customer evaluation of Peregrine’s

PE613050. The RF common port is connected

through a 50Ω transmission line via the top SMA

connector, J1. RF1, RF2, RF3 and RF4 are

connected through 50Ω transmission lines via SMA

connectors J3, J5, J2 and J4, respectively. A

through 50Ω transmission is available via SMA

connectors J6 and J7. This transmission line can

be used to estimate the loss of the PCB over the

environmental conditions being evaluated.

The board consists of a 4 layer stack with 2 outer

layers made of Rogers 4350B (εr = 3.48) and 2

inner layers of FR4 (εr = 4.80). The total thickness

of this board is 62 mils (1.57 mm). The inner layers

provide a ground plane for the transmission lines.

Each transmission line is designed using a

coplanar waveguide with ground plane (CPWG)

model using a trace width of 32 mils (0.813 mm),

gap of 15 mils (0.381 mm), and a metal thickness

of 1.4 mils (0.051 mm).

Figure 5. Evaluation Board Layout

PRT-28405

Page 6 of 8

Product Specification PE613050

Figure 6. Evaluation Board Schematic

Through Line

C3

DNI

1

13

35

57

7

22

44

66

88

10 10

12 12

14 14 13

13

9

911

11

J8

HEADER 14

1

2

J6

SMASM

1

2

J1

SMASM

1

2

J4

SMASM

1

2

J5

SMASM

C4

DNI C2

DNI

1

2

J3

SMASM

1

2

J7

SMASM

1

2

J2

SMASM

C1

DNI

6RFGND

1VDD

4V1

11 RF2

7

RF3 5

RF4 10

RFGND 13

PADDLE

9RF1

3V2

2DGND

12 TEST

8

ANT

U2

PE613050-QFN_12L_2X2

C5

DNI

R2

DNI

R1

DNI

R3

DNI

RF1

V2

RF2

VDD

RF4

RF3

ANT

TEST

V1_DUT

DOC-32627

Page 7 of 8

Product Specification PE613050

2.00

A0.10 C

C

0.10 C

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.05 C

SEATING PLANE

PIN #1 Identifier

B

(X2)

0.10 C A B

0.05 C

ALL FEATURES

RECOMMENDED LAND PATTERN

0.10 C

(X2) 0.80±0.05

0.80±0.05

0.20±0.05

(X12)

1.00 1

3

4

6

79

10

12

2.40

0.475

(X12)

0.25

(X12)

0.50

0.85

2.40

0.85

0.152 REF. 0.05 MAX

0.50±0.05

0.29±0.05

(x12)

0.50

(x8)

Chamfer

0.25x45°

Figure 7. Package Drawing

12-lead 2  2  0.50 mm

Figure 8. Top Marking Specifications

Marking Spec

Symbol Package

Marking Definition

PP DS Part number code for PE613050

ZZ 00–ZZ Last two characters of lot code

Y 0–9 Last digit of year, starting from 2009

(0 for 2010, 1 for 2011, etc.)

WW 01–53 Work week

DOC-50486

Notes: 1. Dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M, 1994.

Note: (PP), the package marking specific to the PE613050, is shown in the figure instead of

the standard Peregrine package marking symbol (P).

PPZZ

YWW

DOC-51207

Page 8 of 8

Product Specification PE613050

Sales and Contact Information

For sales and contact information please visit www.psemi.com.

Table 8. Ordering Information

Order Code Package Description Shipping Method

PE613050A-Z 12-lead QFN 2  2  0.50 mm Package Part in Tape and Reel 3,000 units / T&R

EK613050-01 Evaluation Kit Evaluation Kit 1 set / box

Figure 9. Tape and Reel Specifications

Tape Feed Direction

Device Orientation in Tape

Top of

Device

Pin 1

Page 9 of 8

Product Specification PE613050

Document Categories

Advance Information

The product is in a formative or design stage. The datasheet contains design target specifications for prod-

uct development. Specifications and features may change in any manner without notice.

Preliminary Specification

The datasheet contains preliminary data. Additional data may be added at a later date. pSemi reserves the

right to change specifications at any time without notice in order to supply the best possible product.

Product Specification

The datasheet contains final data. In the event pSemi decides to change the specifications, pSemi will notify

customers of the intended changes by issuing a CNF (Customer Notification Form).

Sales Contact

For additional information, contact Sales at sales@psemi.com.

Disclaimers

The information in this document is believed to be reliable. However, pSemi assumes no liability for the use

of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits

described in this document are implied or granted to any third party. pSemi’s products are not designed or

intended for use in devices or systems intended for surgical implant, or in other applications intended to

support or sustain life, or in any application in which the failure of the pSemi product could create a situation

in which personal injury or death might occur. pSemi assumes no liability for damages, including conse-

quential or incidental damages, arising out of the use of its products in such applications.

Patent Statement

pSemi products are protected under one or more of the following U.S. patents: patents.psemi.com

Copyright and Trademark

Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi

logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries.