Power Matters. Spaceflight FPGAs RTAXTM-S/SL RTAX-DSP RT-ProASIC(R)3 RTSX-SU The leader in programmable digital logic integration for spaceflight applications. Taking Designs from Earth to Outer Space Whether you're designing for low earth orbit, deep space, or anything in between, Microsemi's high reliability, low power spaceflight FPGAs are your best choice. With a history of providing the most reliable, robust, low power flash and antifuse-based FPGAs in the industry, Microsemi offers the best combination of features, performance and radiation tolerance. Design high speed communications payloads, high resolution sensors and instruments, and flight-critical systems that enable tomorrow's space missions. Only Microsemi can meet the power, size, cost and reliability targets that reduce time-to-launch and minimize cost and schedule risks. Table of Contents RTAXTM-S/SL * Industry-Standard QML Class V Qualified Spaceflight FPGA * High Performance and Low Power Consumption * Unprecedented 33 M+ Device-Hours of Reliability Data from flight and commercially equivalent units 4 RTAX-DSP * High-Speed Arithmetic Functions for Spaceflight Applications * Embedded Hardwired Radiation-Tolerant Multipliers * Based on Flight-Tested Architecture and Process 5 RT ProASIC 3 * Very Low Power Consumption Spaceflight FPGA * Reprogrammability Without Radiation-Induced Configuration Upsets * Single-Chip Form-Factor 6 RTSX-SU * Industry's Highest-Volume Spaceflight FPGA * Long-Established Flight Heritage and Reliability * Industry-Standard CQFP Packaging 7 FPGA Packages * Package Dimensions 8 Design Environment for Microsemi System Critical Devices * Microsemi's Libero(R) Integrated Design Environment (IDE) Tools and Editions 10 Intellectual Property Cores for System Critical FPGAs * MIL-STD-1553B IP Cores * Digital Signal Processing IP Cores 11 Prototyping Flows * Prototyping with Axcelerator(R) Units * Prototyping with RTAX-S/SL/DSP or RTSX-SU PROTO Units * RTAX-S/SL Prototyping with Flash Devices 12 Package Prototyping Solutions * Adapter Sockets 13 Daisy-Chained Packages * Facilitating Package Qualification 13 Device Programming * Silicon Sculptor 3 * FlashPro4 14 (R) Please refer to www.microsemi.com/soc and appropriate product datasheets for the latest device information and valid ordering codes. 3 RTAX-S/SL Radiation-tolerant FPGA alternative to radiation-hardened ASICs RTAX-S/SL radiation-tolerant FPGAs offer industry-leading advantages for designers of spaceflight systems. High performance and low power consumption, true single-chip form factor and live-at-power-up operation all combine to make RTAX-S/SL devices the FPGAs of choice for space designers. * Single event latch-up (SEL) immune to LETTH in excess of 117 MeV-cm2/mg * Single event upset (SEU) less than 1E-10 errors per bit-day (worst-case geosynchronous orbit) * Total ionizing dose (TID): 300 Krad functional, 200 Krad parametric * Ceramic package offerings (CQFP, CCGA, CLGA) * Pin-compatible commercial devices for easy and inexpensive prototyping * Prototype units with same footprint and timing as flight units * Screening: B Flow: MIL-STD-883B E Flow: Microsemi Extended Flow V Flow: MIL-PRF-38535 QML Class V * Up to 840 user-programmable I/Os RTAX-S/SL Devices RTAX-S/SL Devices RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL 250,000 1,000,000 2,000,000 4,000,000 Register (R-cells) 1,408 6,048 10,752 20,160 Combinatorial (C-cells) 2,816 12,096 21,504 40,320 12 36 64 120 54 k 162 k 288 k 540 k Hardwired 4 4 4 4 Routed 4 4 4 4 8 8 8 8 Capacity Equivalent System Gates Modules Embedded RAM/FIFO (without EDAC) RAM Blocks RAM (k = 1,024 bits) Clocks (segmentable) I/Os I/O Banks User I/Os (maximum) 248 418 684 840 I/O Registers 744 1,548 2,052 2,520 624 208, 352 624 352 624, 1152 256, 352 1272 352 R TAX-S/ SL Package Pins CG/LG CQ I/Os Per Package RTAX-S/SL Devices I/O Type RTAX250S/SL NonSingle- Differential Adjacent Ended I/Os I/O Pairs I/O Pairs RTAX1000S/SL Total I/Os NonSingle- Differential Adjacent Ended I/Os I/O Pairs I/O Pairs RTAX2000S/SL Total I/Os NonSingle- Differential Adjacent Ended I/Os I/O Pairs I/O Pairs RTAX4000S/SL Total I/Os NonSingle- Differential Adjacent Ended I/Os I/O Pairs I/O Pairs CQ208 7 41 13 115 -- -- -- -- -- -- -- -- -- -- -- -- CQ256 -- -- -- -- -- -- -- -- 4 66 0 136 -- -- -- -- CQ352 2 98 0 198 2 98 0 198 2 98 0 198 4 81 0 166 CG624 0 124 0 248 68 170 5 418 52 178 5 418 -- -- -- -- CG1152 -- -- -- -- -- -- -- -- 0 342 0 684 -- -- -- -- CG1272 -- -- -- -- -- -- -- -- -- -- -- -- 0 420 0 840 Note: An em dash (--) indicates that the device/package combination is not available. 4 Total I/Os An up-to-date cross reference list showing DSCC part numbers is posted at www.microsemi.com/soc/documents/DSCC_CrossRef.pdf. RTAX-DSP Industry's most reliable spaceflight FPGAs with DSP capabilities RTAX-DSP spaceflight FPGAs add embedded radiation-tolerant multiply-accumulate blocks to the tried-and-trusted industry-standard RTAX-S/SL product family. The result is a dramatic increase in device performance and utilization when implementing arithmetic functions, such as those encountered in DSP algorithms, without sacrificing reliability or radiation tolerance. RTAX-DSP integrates complex DSP functions into a single device without any external components for code storage and without multiple-chip implementations for radiation mitigation. * Highly reliable, nonvolatile antifuse technology * 2,000,000 to 4,000,000 system gates * Up to 120 DSP Mathblocks with 125 MHz 18x18 bit multiply-accumulate * Up to 540 Kbits of embedded memory with optional EDAC protection * Up to 840 user-programmable I/Os * SEU less than 1E-10 errors per bit-day (worst-case GEO) * Advanced CCGA and LGA packaging for space applications * SEL immune to LETTH in excess of 117 MeV-cm2/mg * Screening: E-Flow (Microsemi Extended Flow), B-Flow (MIL-STD-883B) and EV-Flow (Class V Flow processing as per MIL-PRF-38535) * Enhanced SET for R-cells: 0.12 events / RTAX2000D device / 100 years at 120 MHz * RTAX-DL version with low static power * Total dose: 300 Krad (functional) and 200 Krad (parametric) RTAX-DSP Devices RTAX-DSP Devices RTAX2000D/DL RTAX4000D/DL 2,000,000 4,000,000 9,856 18,480 19,712 36,960 64 120 Capacity Equivalent System Gates Modules Register (R-cells) Combinatorial (C-cells) Embedded Multiply-Accumulate Blocks DSP Mathblocks Embedded RAM/FIFO (without EDAC) RAM Blocks RAM (k=1,024 bits) 64 120 288 k 540 k Clocks (segmentable) Hardwired 4 4 Routed 4 4 R TAX-DSP I/Os 8 8 684 840 I/O Registers 2,052 2,520 Package Pins CG/LG (DSP)* CQ 1272 352 1272 352 I/O Banks User I/Os (maximum) Note: * The body size of the 1272-pin CCGA and LGA packages used on the RTAX-DSP devices is slightly larger than the body size of the 1272-pin CCGA and LGA used on the RTAX4000S/SL devices. I/Os Per Package RTAX-DSP Devices RTAX2000D RTAX4000D CQ352 166 166 CG1272/LG1272 684 840 Note: The user I/Os include clock buffers. 5 RT ProASIC3 Low power, reprogrammable FPGAs for space Radiation-tolerant (RT) ProASIC3 FPGAs are the first to offer designers of spaceflight hardware a radiation-tolerant, reprogrammable, nonvolatile logic integration vehicle. They are intended for low power space applications requiring up to 350 MHz operation and up to 3,000,000 system gates. * Ceramic column grid array with Six Sigma copper-wrapped lead-tin columns * Total ionizing dose: 25 Krad to 30 Krad with less than 10% propagation delay change at standard test dose rate; up to 40 Krad at low dose rate * Supports single-voltage system operation * Up to 504 Kbits of true dual-port SRAM * ISP protected with industry standard on-chip 128-bit advanced encryption * Live-at-power-up (LAPU) level 0 support * Standard (AES) decryption via JTAG (IEEE 1532-compliant) RT ProASIC3 Devices RT ProASIC3 Devices RT3PE600L RT3PE3000L System Gates 600,000 3,000,000 VersaTiles (D-flip-flops) 13,824 75,264 RAM (k = 1,024 bits) 108 k 504 k RAM Blocks (4,608 bits) 24 112 FlashROM (Kbits) 1 1 Secure (AES) ISP Yes Yes Integrated PLL in CCCs 6 6 VersaNet Globals 18 18 I/O Banks 8 8 Maximum User I/Os 270 620 Package Pins CG/LG CQ 484 256 484, 896 256 I/Os Per Package R T P roASIC3 RT ProASIC3 Devices I/O Type RT3PE3000L Differential I/O Pairs Single-Ended I/Os Differential I/O Pairs CG/LG484 270 135 341 168 CG/LG896 -- -- 620 310 166 82 166 82 CQ256 6 RT3PE600L Single-Ended I/Os RTSX-SU Flight-proven in space--time after time RTSX-SU radiation-tolerant FPGAs are enhanced versions of Microsemi's commercial SX-A family of devices, specifically designed for enhanced radiation performance. Featuring SEU-hardened D-type flip-flops that offer the benefits of triple module redundancy (TMR) without requiring cumbersome user intervention, the RTSX-SU family is a unique product offering for space applications. * 230 MHz system performance (310 MHz internal) * Very low power consumption (up to 68 W at standby) * 3.3 V and 5.0 V mixed voltage * Configurable I/O support for 3.3 V / 5 V PCI, LVTTL, TTL and CMOS * Secure programming technology protects against reverse engineering and design theft * Low cost prototyping option * Deterministic, user-controllable timing * 100% circuit resource utilization with 100% pin locking * JTAG boundary scan testing in compliance with IEEE Standard 1149.1--dedicated JTAG reset (TRST) pin * Unique in-system diagnostic and verification capability with Silicon Explorer II * Highly reliable, nonvolatile antifuse technology * 32,000 to 72,000 ASIC gates (48,000 to 108,000 system gates) * Up to 360 user-programmable I/Os * Hermetically-sealed packages for space applications (CQFP, CCGA/CLGA, CCLG) RTSX-SU Devices RTSX-SU Devices RTSX32SU RTSX72SU Typical Gates 32,000 72,000 System Gates 48,000 108,000 1,800 4,024 Capacity Logic Modules Combinatorial Cells 1,080 2,012 Maximum Flip-Flops 1,980 4,024 Maximum User I/Os 227 360 SEU-Hardened Register Cells (D-flip-flops) Clocks 3 3 Quadrant Clocks 0 4 Speed Grades Std., -1 Std., -1 Package Pins CQ CG CC 84, 208, 256 208, 256 624 256 R TSX -SU I/Os Per Package RTSX-SU Devices RTSX32SU RTSX72SU CQ84 62 -- CQ208 173 170 CQ256 227 212 CC256 202 -- CG624 -- 360 Note: The user I/Os include clock buffers. An up-to-date cross reference list showing DSCC part numbers is posted at www.microsemi.com/soc/documents/DSCC_CrossRef.pdf. 7 FPGA Packages Key: bs - package body size excluding leads h - package thickness p - pin pitch / ball pitch Chips shown at actual size. CQ352 CQ256 b.s. 1.417x1.417" (36.00x36.00 mm) h. 105 mils (2.67 mm) p. 20 mils (0.50 mm) FP GA Pa c k a ge s b.s. 1.890x1.890" (48.00x48.00 mm) h. 105 mils (2.67 mm) p. 20 mils (0.50 mm) CQ84 b.s. 0.65x0.65" (16.51x16.51 mm) h. 90 mils (2.29 mm) p. 25 mils (0.64 mm) CQ172 b.s. 1.18x1.18" (29.972x29.972 mm) h. 105 mils (2.67 mm) p. 25 mils (0.64 mm) CQ132 b.s. 0.95x0.95" (24.13x24.13 mm) h. 105 mils (2.67 mm) p. 25 mils (0.64 mm) CG1152/LG1152 CG896/LG896 RTAX2000S and RTAX2000SL only b.s. 1.220x1.220" b.s.1.378x1.378" (35.00x35.00 mm) h. CCGA - 218 mils (5.535 mm) h. LGA - 129 mils (3.28 mm) p. 39 mils (1.00 mm) 8 (31.00x31.00 mm) h. CCGA - 218 mils (5.535 mm) h. LGA - 129 mils (3.28 mm) p. 39 mils (1.00 mm) The b.s. dimension is the nominal package body dimension, exclusive of leads. For more information concerning package dimensions, refer to the Microsemi Package Mechanical Drawings document located at www.microsemi.com/soc/documents/PckgMechDrwngs.pdf. CQ196 b.s. 1.35x1.35" (34.29x34.29 mm) h. 105 mils (2.67 mm) p. 25 mils (0.64 mm) CQ208 b.s. 1.15x1.15" (29.21x29.21 mm) h. 105 mils (2.67 mm) p. 20 mils (0.50 mm) CGD1272/LGD1272 CG1272/LG1272 RTAX2000D and RTAX4000D only RTAX4000S and RTAX4000SL only b.s. h. h. p. b.s. 1.457x1.457" TBD TBD TBD TBD (37.00x37.00 mm) FPGA Pa c k a ge s h. CCGA - 218 mils (5.535 mm) h. CLGA - 129 mils (3.28 mm) p. 39 mils (1.00 mm) CC256 CG624/LG624 b.s. 1.27x1.27" (32.50x32.50 mm) h. CCGA - 194 mils (4.94 mm) h. LGA - 90 mils (2.30 mm) p. 50 mils (1.27 mm) CG484/LG484 b.s. 0.91x0.91" (23.00x23.00 mm) h. CCGA - 225 mils (5.72 mm) h. LGA - 138 mils (3.51 mm) p. 7.5 mils (0.19 mm) b.s.0.67x0.67" (17.00x17.00 mm) h. 72 mils (1.847 mm) p. 7.5 mils (0.19 mm) 9 Design Environment for Microsemi System Critical Devices Microsemi system critical FPGAs are fully supported by Microsemi's Libero(R) Integrated Design Environment (IDE) software. Libero IDE is an integrated design manager that integrates design tools while guiding the user through the design flow, managing all design and log files and passing necessary design data among tools. Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify Pro(R) AE from Synopsys ,(R) ModelSim(R) HDL Simulator from Mentor Graphics and Designer design implementation software from Microsemi. Libero(R) Integrated Design Environment (IDE) Design Creation IP Block Creation IP Cores and Templates Schematic Editor SmartDesign Designer Layout Option Catalog ViewDraw(R) AE Verification Design Implementation Designer software includes sophisticated place-and-route features plus a comprehensive suite of backend support tools for timing constraints, timing and power analysis, I/O attribute and pin assignment, and much more. DSP Optimization Design Synthesis Testbench Generation Synplify(R) DSP AE Synthesis Synplify / Synplify Pro AE User Testbench In-Silicon Verification Setup Microsemi's SmartDesign tool simplifies the use of Microsemi's IP in user designs as well as offering a simple way to build on-chip processors with custom peripherals. Most Microsemi IP cores are now included by default in Libero IDE as either obfuscated or RTL versions, depending on the license selected. Design Simulation Functional and Timing Debug Instrumentation Identify(R) AE Pre-/Post-Synthesis Post-Layout ModelSim(R) AE For embedded designers, Microsemi offers FREE SoftConsole Eclipse-based IDE for use with ARM(R) CortexTM-M1 and Cortex-M3, and Core8051s as well as evaluation versions from KeilTM and IAR Systems (R). Full versions are available from the respective suppliers. Des ign En vi r on me n t fo r Mic rose mi Sy ste m Critic a l De vic e s SoC System Design Design Analysis Physical Design SmartTime Compile Smart Power Place-and-Route Back-Annotate Design Planning ChipPlanner Bitstream Generation Global Planner Processor Code Development and Debug I/O Planner SoftConsole FPGA Debug Programming FlashPro SoC Products Group Design Debug (flash products) Silicon Sculptor Identify(R) AE (flash products) Silicon Explorer (antifuse products) FPGA Design Support Libero IDE Licenses Device Support All families Gold (FREE) Platinum Up to 1,500,000 gates Obfuscated x Microsemi IP Platinum Evaluation Standalone All devices All devices All devices RTL Obfuscated RTL x x Synthesis Synplify Pro AE Simulation ModelSim AE x x x Identify(R) AE x x x Microsemi Debug x x x x x (R) (R) Debug Program File x Operating System Support* Tool Libero IDE SoftConsole Keil IAR FlashPro FlashPro USB Driver Windows XP Professional Now Now Now Now Now Now (32-bit and 64-bit) Windows Vista Business Now Now Now Now Now Now (32-bit and 64-bit) Windows 7 Professional Now Now Now Now Now Now (32-bit and 64-bit) (R) RedHat Linux WS 4.0 Now N/A N/A N/A N/A N/A RedHat Linux WS 5.0 Now N/A N/A N/A N/A N/A RedHat Linux WS 5.2 Now N/A N/A N/A N/A N/A (R) Note: * FPGA programming is only supported in Windows XP Pro, Windows Vista, and Windows 7. 10 Intellectual Property Cores for System Critical FPGAs Microsemi has more than 180 intellectual property (IP) products designed and optimized to support communications, consumer, military, industrial, automotive and aerospace markets. Microsemi IP solutions streamline your designs, enable faster time-to-market and minimize design costs and risk. You can access Microsemi IP cores through the Microsemi Libero IDE suite of development tools via the SmartDesign IP design interface. Many Microsemi cores feature firmware drivers accessible through the Firmware Catalog tool. Integrated solutions are also available, featuring Microsemi IP and highlighting the advantages of Microsemi's intrinsically low power FPGAs. A few key IP cores for system critical applications are shown below, and you can view the entire library of cores at www.microsemi.com/soc. MIL-STD-1553B IP Cores MIL-STD-1553 is a command/response, dual-redundant, time-multiplexed serial data bus used in severe environments. Microsemi Core1553 IP cores provide robust, fully tested MIL-STD-1553A and B implementations that are compatible with legacy 1553 solutions. Microsemi provides everything needed to incorporate one or more 1553B cores into a system design. Core1553BRM, Core1553BRT, Core1553BRT-EBR and Core1553BBC are available. Core1553BRM * Compliant to MIL-STD-1553A and B Encoder BusA * 12, 16, 20 or 24 MHz clock operation Protocol Controller Decoder * Simultaneous RT/MT operation BusB Backend Interface * Bus Controller (BC), Remote Terminal (RT) and Monitor Terminal (MT) Memory Decoder * Built-in test capability * Advanced RT functions Command Legalization * Sophisticated BC reduces host overhead CPU Interface and Registers * Interfaces to standard transceivers * Redundancy for severe environments * Low power operation Inte lle c tua l P rope rty Core s for Sy s tem C r iti cal F PG A s Digital Signal Processing IP Cores Microsemi digital signal processing (DSP) cores deliver digital filtering and signal processing capabilities. Cores taking advantage of on-chip multiplier blocks in Microsemi's new RTAX-DSP devices offer outstanding performance in spaceflight applications. CoreFFT * Highly parameterizable DirectCore RTL generator optimized for the RTAX-DSP family supports forward and inverse complex FFT Complex Input Data Mem1 Data Buffer Twiddle LUT * Bit-reversed or natural output order Mem0 Mem1 Complex FFT Output * Two's complement I/O data Mem0 Radix-2 Butterfly Write Switch * 8 to 32 bits I/O real and imaginary data and twiddle coefficients Ping Buffer Read Switch Pong Buffer * Transforms sizes from 32 to 8,192 points Bit-Reversed Write Addr * Selection of unconditional or conditional block floating point scaling * Embedded RAM-block-based twiddle LUT Buffered FFT Block Diagram * Built-in memory buffers with optional extensive or minimal memory buffering configurations * Handshake signals to facilitate easy interface to user circuitry CoreFIR * Highly parameterizable DirectCore RTL generator optimized for the RTAX-DSP family implements a range of filter types, including single rate fully enumerated (parallel), single rate folded (semi-parallel) filter and multi-rate polyphase interpolation FIR filter * Run-time reloadable coefficients, multiple coefficient sets, or fixed coefficients * Performance up to 124 MHz * Full precision output * Supports up to 1,024 FIR filter taps * Coefficient symmetry optimization (on the fully enumerated filters) * 2-bit to 18-bit input data and coefficient precision * Signed or unsigned data and coefficients 11 Prototyping Flows With the introduction of Microsemi's RTAX-S/SL devices, designers now have access to the most powerful FPGAs available for aerospace and radiation-intensive applications. Prototype verification is an important step in system integration where accurate behavioral simulation and static timing analysis are crucial. Since the enhanced radiation characteristics of radiation-tolerant devices are not required during the prototyping phase of the design, Microsemi has developed various prototyping options for RTAX-S/SL for early design development and functional verification. Prototyping with Axcelerator Units Design Capture Start Synchronous Design Methodologies Avoid Forbidden Macros The prototyping solution using the commercial Axcelerator devices consists of two parts: Pre-Synthesis Simulation * A well-documented design flow that allows the customer to target an RTAX-S/SL design to the equivalent commercial Axcelerator device Synthesis Post-Synthesis Simulation * A set of Microsemi Extender circuit boards that map the commercial device package to the appropriate RTAX-S/SL package footprint Designer Place-and-Route Select RTAX-S Device Set I/O and Timing Constraints Perform Static Timing Analysis This methodology provides the user with a cost-effective solution while maintaining the short time-to-market associated with Microsemi FPGAs. Post-Layout Simulation RTAX-S/SL Step Generate Axcelerator AFM Generate RTAX-S AFM Board-Level Verification Final Verification and Flight Axcelerator Step End P rototy ping Flow s Prototyping with RTAX-S/SL/DSP or RTSX-SU PROTO Units The RTAX-S/SL/DSP or RTSX-SU PROTO units offer a prototyping solution that can be used for final timing verification of the flight design. The RTAX-S/SL/DSP or RTSX-SU PROTO prototype units have the same timing attributes as the RTAX-S/SL/DSP or RTSX-SU flight units. Prototype units are offered in non-hermetic ceramic packages. The prototype units include "PROTO" in their part number, and "PROTO" is marked on devices to indicate that they are not intended for space flight. They also are not intended for applications that require the quality of spaceflight units, such as qualification of spaceflight hardware. RT-PROTO units offer no guarantee of hermeticity, and no MIL-STD-883B processing. At a minimum, users should plan on using class B level devices for all qualification activities. The RT-PROTO units are electrically tested in a manner to guarantee their performance over the full military temperature range. The RT-PROTO units will also be offered in -1 or standard speed grades, so as to enable customers to validate the timing attributes of their space designs using actual flight silicon. RTAX-S/SL Prototyping with Flash Devices Aldec's RTAX-S/SL prototyping solution allows customers to take advantage of Microsemi's flash-based reprogrammable ProASIC3 devices. Aldec provides software that remaps antifuse primitives to flash, which reduces design time and cost. In addition, the hardware adapter is footprint compatible with RTAX-S/SL; therefore, a customer does not need to redesign a new board for prototyping. 12 Package Prototyping Solutions Microsemi has developed multiple low-cost prototyping solutions for RTAX-S/SL devices that ultimately are packaged in CQFP or CCGA for the production system. These solutions utilize Axcelerator family Fine Pitch Ball Grid Array (FBGA) or Ceramic Land Grid Array (CLGA) packages as prototyping vehicles: * CQFP to FBGA adapter socket * CQFP to CLGA adapter socket * CCGA to FBGA adapter socket * CCGA to CLGA adapter socket The CQFP to FBGA adapter sockets have an FBGA configuration on the top and a CQFP configuration on the bottom. The adapter sockets enable customers to use a commercial Axcelerator FG package during prototyping, and then switch to an equivalent CQ256 or CQ352 package for production. Adapter Socket Prototyped and Prototype Device SK-AX250-CQ352RTFG484S For prototyping RTAX250S/L-CQ352 or AX250-CQ352 using AX250-FG484 package CQ352 to FG896 SK-AX1-AX2-KITTOP and SK-AX1-CQ352-KITBTM For prototyping RTAX1000S/L-CQ352 or AX1000-CQ352 using AX1000-FG896 package CQ352 to FG896 SK-AX1-AX2-KITTOP and SK-AX2-CQ352-KITBTM For prototyping RTAX2000S/L-CQ352 or AX2000-CQ352 using AX2000-FG896 package CQ256 to FG896 SH-AX2-CQ256-KITTOP and SK-AX2-CQ256-KITBTM For prototyping RTAX2000S/L-CQ352 or AX2000-CQ256 using AX2000-FG896 package CG624 to FG484 SK-SX72-CG624RTFG484 For prototyping RTSX72SU-CG624 or A54SX72A-CG624 using A54SX72A-FG484 package CG624 to FG896 SK-AX1-AX2-KITTOP and SK-AX1-CG624-KITBTM For prototyping RTAX1000S-CG624, RTAX1000SL-CG624, or AX1000-CG624 using AX1000-FG896 package CG624 to FG896 SK-AX1-AX2-KITTOP and SK-AX2-CG624-KITBTM For prototyping RTAX2000S-CG624, RTAX2000SL-CG624, or AX2000-CG624 using AX2000-FG896 package RTAX2000S CQ256 to FG896 Ceramic Adapter, Top and Bottom Pa c k a ge Prototy ping Solutions / Da is y -Ch ai ne d P ac kages Ordering Part Number CQ352 to FG484 Daisy-Chained Packages To facilitate the qualification of target FPGA device socket and board assembly practices without using costly flight-quality parts, Microsemi offers certain Ceramic Column Grid Array (CCGA) and Ceramic Land Grid Array (CLGA) packages with adjacent pairs of pins tied together. By assembling these packages onto a qualification PC board that is laid out with adjacent pairs of solder pads tied together but offset by one pin as compared to the package, a single signal can be fed into one pin of the package and routed into and out of the entire package in a serial daisy chain fashion so all pins of the package are used. This is useful for performing continuity and impedance tests to validate board assembly techniques with surface-mount grid array packages. Microsemi's daisy chain packages feature metal routing tracks between adjacent pairs of package pins, internal to the package. For package qualification, an unbonded silicon die is included in the package. Microsemi Part Number Description LG624 DAISY CHAIN-1 624-pin CLGA mechanical package LG1152 DAISY CHAIN 1152-pin CLGA mechanical package LG1272 DAISY CHAIN 1272-pin CLGA mechanical package CG484 DAISY CHAIN 484-pin CCGA mechanical package CG624 DAISY CHAIN SIX 624-pin CCGA mechanical package CG896 DAISY CHAIN 896-pin CCGA mechanical package CG1152 DAISY CHAIN 1152-pin CCGA mechanical package CG1272 DAISY CHAIN 1272-pin CCGA mechanical package Partial View of 624 CGA with Adjacent Pin Pairs Tied Together Package Printed Circuit Board Daisy Chain Start All Pins are Connected Serially 13 Device Programming Silicon Sculptor 3 The Silicon Sculptor 3 programmer, which supports both antifuse and flash FPGAs, delivers high data throughput and promotes ease of use, while lowering the overall cost of ownership. The Silicon Sculptor 3 programmer includes a high-speed USB 2.0 interface that enables customers to connect as many as 12 programmers to a single PC. This enables an easily expandable, low to medium volume production programming system to be dynamically assembled. Through the use of universal Microsemi socket adapters, the Silicon Sculptor 3 device programs all Microsemi packages, including PLCC, PQFP, VQFP, TQFP, QFN, PBGA, FBGA, CSP, CPGA, CQFP, CCGA, and CLGA. FlashPro4 The FlashPro4 programmer for flash FPGAs utilizes a JTAG interface, where a single JTAG chain can be used for multiple Microsemi flash devices on a JTAG chain. In-system programming using the JTAG port adds the flexibility of field upgrades or post-assembly production-line characterization. Production costs are significantly reduced as a result of elimination of expensive sockets on the board. De vic e Progra mming All FlashPro programmers use JEDEC-standard STAPL files, meaning there are no algorithms built into the software. The FlashPro software and user interface support FlashPro4 and FlashPro Lite programmers, so you do not have to learn new software to switch from one hardware programmer to another. 14 www.microsemi.com/soc You may be interested in: Terrestrial FPGA and SoC Product Catalog: www.microsemi.com/soc/documents/ProdCat_PIB.pdf Solutions and IP Catalog: www.microsemi.com/soc/documents/IPPIB.pdf Microsemi SoC Products Group 3870 North First Street, San Jose, CA 95134 Phone: 408.643.6000 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise Drive, Aliso Viejo, CA 92656 Within the USA: (800) 713-4113 Outside the USA: (949) 380-6100 Fax: (949) 215-4996 * www.microsemi.com (c)2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 55700043-6/4.12 MS2-003-12