2Gb DDR3 SDRAM B-Die

NT5CB512M4BN / NT5CB256M8BN / NT5CB128M16BP

NT5CC512M4BN / NT5CC256M8BN / NT5CC128M16BP

1

REV 1.1

08 / 2010

Feature

 Programmable Sequential / Interleave Burst Type

 Programmable Burst Length: 4, 8

 8 bit prefetch architecture

 Output Driver Impedance Control

 OCD Calibration

 Dynamic ODT (Rtt_Nom & Rtt_WR)

 Auto Self-Refresh

 Self-Refresh Temperature

 RoHS compliance and Halogen free

 Packages:

The 2Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing

2,147,483,648 bits. It is internally configured as an octal-bank DRAM.

The 2Gb chip is organized as 64Mbit x 4 I/O x 8 bank, 32Mbit x 8 I/O x 8 bank or 16Mbit x 16 I/O x 8 bank device. These

synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.

The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are

synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks

(CK rising and  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source

synchronous fashion.

These devices operate with a single 1.5V ± 0.075V and 1.35V -0.0675V/+0.1V power supply and are available in BGA

packages.

2

REV 1.1

08 / 2010

See the balls through the package

3

REV 1.1

08 / 2010

See the balls through the package

4

REV 1.1

08 / 2010

5

REV 1.1

08 / 2010

6

REV 1.1

08 / 2010

7

REV 1.1

08 / 2010

8

REV 1.1

08 / 2010

9

REV 1.1

08 / 2010

REV 1.1

08 / 2010

as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length,

burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4,

fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write

REV 1.1

08 / 2010

CAS Latency

The CAS Latency is defined by MR0 (bit A9~A11) as shown in the MR0 Definition figure. CAS Latency is the delay, in clock

cycles, between the internal Read command and the availability of the first bit of output data. DDR3 SDRAM does not

support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL);

RL = AL + CL.

Test Mode

The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0

up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be equal or larger

than tWR(min).

Precharge PD DLL

MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or „slow-exit‟, the

DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be met

prior to the next valid command. When MR0 (A12=1), or „fast-exit‟, the DLL is maintained after entering precharge

power-down and upon exiting power-down requires tXP to be met prior to the next valid command.

REV 1.1

08 / 2010

Mode Register MR1

The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance, additive

latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on , , ,  high on

REV 1.1

08 / 2010

REV 1.1

08 / 2010

Write leveling

For better signal integrity, DDR3 memory module adopted fly by topology for the commands, addresses, control signals,

and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes

REV 1.1

08 / 2010

REV 1.1

08 / 2010

The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock cycles,

between the internal Write command and the availability of the first bit of input data. DDR3 DRAM does not support any half

clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL);

WL=AL+CWL.

Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)

DDR3 SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh

operation in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately.

Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if

DDR3 SDRAM devices support the following options or requirements referred to in this material. For more details refer to

“Extended Temperature Usage” on page48. DDR3 SDRAMs must support Self-Refresh operation at all supported

ASR function or program the SRT bit appropriately.

REV 1.1

08 / 2010

Mode Register MR3

The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on , , ,

REV 1.1

08 / 2010

The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To

enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the

MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any

subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or

RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power

The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. The

To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1, as shown in

command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode.

REV 1.1

08 / 2010

MPR Functional Description

•One bit wide logical interface via all DQ pins during READ operation.

•Register Read on x16:

•DQL[0] and DQU[0] drive information from MPR.

•DQL[7:1] and DQU[7:1] either drive the same information as DQL[0], or they drive 0b.

•Addressing during for Multi Purpose Register reads for all MPR agents:

•BA[2:0]: don‟t care

•A[1:0]: A[1:0] must be equal to „00‟b. Data read burst order in nibble is fixed

•A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst

Chop 4 cases, the burst order is switched on nibble base A[2]=0b, Burst order: 0,1,2,3 *)

A[2]=1b, Burst order: 4,5,6,7 *)

•A[9:3]: don‟t care

DDR3 SDRAM.

•Regular read latencies and AC timings apply.

NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.