This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 1
H5GQ1H24AFR
1Gb (32Mx32) GDDR5 SGRAM
H5GQ1H24AFR
Rev. 1.0/Nov. 2009 2
H5GQ1H24AFR
Revision History
Revision No. History Draft Date Remark
0.1 Defined target spec. Dec. 2008 Preliminary
0.2 Updated tRTPS / tRTW / tFAW / t32AW / Thermal Characteristics Mar. 2009 Preliminary
0.3 Updated tCKE / Pin Cap / CRCWL / CRCRL/ IDD / PLL Value April. 2009 Preliminary
0.4 Updated tRRDL / Revision ID/ Density ID
Removed tFLK / tSTDBYLK May. 2009 Preliminary
0.5 Updated tCKE / tCKSRE / tCKSRX (@ 6Gbps only) May. 2009 Preliminary
0.6 Updated CRCWL / VREFD Selection Coding
Updated Auto VREFD Training
Updated tCKE & tPD
Updated Leakage Current
Updated x16 Mode ID D Value & 1.35V Timing Parameters
Updated Ordering Information
July. 2009 Preliminary
0.7 VREFD Options Figure31 change Sep. 2009 Preliminary
1.0 Revision 1.0 Release Nov. 2009
Rev. 1.0/Nov. 2009 3
H5GQ1H24AFR
TABLE OF CONTENTS
FEATURES........................................................................................................................................................5
FEATURES..............................................................................................................................................5
FUNCTIONAL DESCRIPTION....................................................................................................................5
DEFINITION OF SINGLE STATE TERMINOLOGY............................ ........................................................................7
CLOCKING..........................................................................................................................................................8
INITIALIZATION................................................................................................................................................10
POWER UP SEQUENCE...........................................................................................................................10
INITIALIZATION WITH STABLE POWER..................................................................................................11
VENDOR ID...........................................................................................................................................13
ADDRESS.........................................................................................................................................................15
ADDRESSING.........................................................................................................................................15
ADDRESS BUS INVERSIO N(A BI)....................... ........................ ........................ ......................... ..............16
BAND GROUP........................................................................................................................................18
TRAINING....... .. .................................................................... ...........................................................................21
INTERFACE TRAINING SEQUENCE..........................................................................................................21
ADDRESS TRAINING..............................................................................................................................22
WCK2CK TRAINING...............................................................................................................................25
READ TRAINING...................................................................................................................................32
WRITE TRAINING.................................................................................................................................38
MODE REGISTER..............................................................................................................................................41
Mode REGISTER 0(MR0)..................................................................................................... ..................42
Mode REGISTER 1(MR1)..................................................................................................... ..................45
Mode REGISTER 2(MR2)..................................................................................................... ..................48
Mode REGISTER 3(MR3)..................................................................................................... ..................50
Mode REGISTER 4(MR4)..................................................................................................... ..................52
Mode REGISTER 5(MR5)..................................................................................................... ..................55
Mode REGISTER 6(MR6)..................................................................................................... ..................57
Mode REGISTER 7(MR7)..................................................................................................... ..................60
Mode REGISTER 15(MR15)....................................................................................................................62
OPERATION......................................................................................................................................................63
COMMAND.............................................................................................................................................63
DESELECT.............................................................................................................................................65
NO OPERATION.....................................................................................................................................65
MODE REGISTER SET.............................................................................................................................65
ACTIVATION..........................................................................................................................................66
BANK RESTRITIONS...............................................................................................................................68
WRITE (WOM).......................................................................................................................................70
WRITE DATA MAS(DM)...........................................................................................................................89
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 4
H5GQ1H24AFR
READ....................................................................................................................................................86
DQ PREAMBLE .....................................................................................................................................95
READ AND WRITE DATA BUS INVERSION (DBI).......................................................................................97
ERROR DETECTION CODE.....................................................................................................................99
PRECHARGE........................................................................................................................................103
AUTO PRECHARGE...............................................................................................................................104
REFRESH.............................................................................................................................................104
SELF REFRESH....................................................................................................................................106
POWER -DOWN.. ........ ....... ..... ....... ....... ..... ....... ........ ....... ..... ....... ....... ..... ........ ....... ..............................109
COMMAND TRUTH TABLE...................................................................... .. .............................................110
RDQS MODE.... .......... ....... .......... ......... .......... ....... .......... .......... ....... .......... ......... .. ...............................114
CLOCK FREQUENCY CHANGE SEQUENCE..............................................................................................116
DYNAMIC VOLT AGE SWITCHING(DVS)........... ... .............................................. .....................................117
TEMPERATURE SENSOR......... .. ... .............................................. ........................ ........................ ...........119
DUTY CYCLE CORRECTOR....................................................................................................................120
OPERATING CONDITIONS............................ ........................ ........................ .. ......................... .........................122
Absolute Maximum Ratings.. ......................... ........................ ........................ ... ........................ .............122
AC & DC Characteristics........................................................................................................................124
CLOCK TO DATA TIMING SENSITIVITY..................................................................................................148
PA CKA GE SPE CI FICAT ION. ...............................................................................................................................151
BALL-OUT...............................................................................................................................................151
SIGNALS.................................................................................................................................................153
ON DIE TERMINATION(ODT)....................................................................................................................156
PACKAGE DIMENSIONS...........................................................................................................................157
MIRROR FUNCTION(MF) E NA BLE A ND X1 6 MODE ENA BLE.. ... ..... .... ..... ... ..... .... ..... ..... ... .... ..... ..... ... .... ..... ..... .. ....158
BOUNDARY SCAN............................................................................................................................................163
Rev. 1.0/Nov. 2009 5
H5GQ1H24AFR
FEATURES
•Singleendedinterfacefordata,addressandcommand
•Quarterdata‐ratedifferentialclockinputsCK/CK#for
ADR/CMD
•Twohalfdata‐ratedifferentialclockinputsWCK/
WCK#,eachassociatedwithtwodatabytes(DQ,DBI#,
EDC)
•DoubleDataRate(DDR)data(WCK)
•SingleDataRate(SDR)command(CK)
•DoubleDataRate(DDR)addressing(CK)
•16internalbanks
•4bankgroupsfortCCDL=3tCK
•8nprefetcharchitecture:256bitperarrayreadorwrite
access
•Burstlength:8only
• ProgrammableCASlatency:5to20tCK
• ProgrammableWRITElatency:1to7tCK
•WRITEDatamaskfunctionviaaddressbus(single/
doublebytemask)
• Databusinversion(DBI)&addressbusinversion
(ABI)
• Input/outputPLLon/offmode
• Addresstraining:addressinputmonitoringbyDQ
pins
• WCK2CKclocktrainingwithphaseinformationby
EDCpins
• DatareadandwritetrainingviaREADFIFO
•READFIFOpatternpreloadbyLDFFcommand
•DirectwritedataloadtoREADFIFObyWRTR
command
•ConsecutivereadofREADFIFObyRDTRcommand
• Read/Writedatatransmissionintegritysecuredby
cyclicredundancycheck(CRC‐8)
• READ/WRITEEDCon/offmode
• ProgrammableEDCholdpatternforCDR
• ProgrammableCRCREADlatency=0to3tCK
• ProgrammableCRCWRITElatency=7to14tCK
•LowPowermodes
•RDQSmodeonEDCpin
•Optionalon‐chiptemperaturesensorwithread‐out
•Auto&selfrefreshmodes
•Autoprechargeoptionforeachburstaccess
• 32ms,autorefresh(8kcycles)
• Temperaturesensorcontrolledselfrefreshrate
•On‐dietermination(ODT);nominalvaluesof60ohm
and120ohm
•Pseudoopendrain(POD‐15)compatibleoutputs(40
ohmpulldown,60ohmpullup)
•ODTandoutputdrivestrengthauto‐calibrationwith
externalresistorZQpin(120ohm)
• Programmableterminationanddriverstrengthoffsets
• SelectableexternalorinternalVREFfordatainputs;
programmableoffsetsforinternalVREF
• SeparateexternalVREFforaddress/commandinputs
•VendorID,FIFOdepthandDensityinfofieldsfor
identification
• x32/x16modeconfigurationsetatpower‐upwithEDC
pin
•MirrorfunctionwithMFpin
• BoundaryscanfunctionwithSENpin
•1.6V/1.5V+/‐0.045Vsupplyfordeviceoperation
(VDD)
•1.6V/1.5V+/‐0.045VsupplyforI/Ointerface(VDDQ)
• 170ballBGApackage
FUNCTIONAL DESCRIPTION
TheGDDR5SGRAMisahighspeeddynamic
random‐accessmemorydesignedforapplications
requiringhighbandwidth.GDDR5devicescontain
thefollowingnumberofbits:
1Gbhas1,073,741,824bitsandsixteenbanks
TheGDDR5SGRAMusesa8nprefetch
architectureandDDRinterfacetoachievehigh‐
speedoperation.Thedevicecanbeconfiguredto
operateinx32modeorx16(clamshell)mode.The
modeisdetectedduringdeviceinitialization.The
GDDR5interfacetransferstwo32bitwidedata
wordsperWCKclockcycleto/fromtheI/Opins.
Correspondingtothe8n‐prefetchasinglewriteor
readaccessconsistsofa256bitwide,twoCKclock
cycledatatransferattheinternalmemorycoreand
eightcorresponding32bitwideone‐halfWCKclock
cycledatatransfersattheI/Opins.
TheGDDR5SGRAMoperatesfromadifferential
clockCKandCK#.Commandsareregisteredat
everyrisingedgeofCK.Addressesareregisteredat
everyrisingedgeofCKandeveryrisingedgeof
CK#.
GDDR5replacesthepulsedstrobes(WDQS&
RDQS)usedinpreviousDRAMssuchasGDDR4
withafreerunningdifferentialforwardedclock
(WCK/WCK#)withbothinputandoutputdata
registeredanddrivenrespectivelyatbothedgesof
theforwardedWCK.
ReadandwriteaccessestotheGDDR5SGRAMare
burstoriented;anaccessstartsataselectedlocation
andconsistsofatotalofeightdatawords.Accesses
beginwiththeregistrationofanACTIVEcommand,
whichisthenfollowedbyaREADorWRITE
command.Theaddressbitsregisteredcoincident
withtheACTIVEcommandandthenextrisingCK#
edgeareusedtoselectthebankandtherowtobe
accessed.Theaddressbitsregisteredcoincident
withtheREADorWRITEcommandandthenext
risingCK#edgeareusedtoselectthebankandthe
columnlocationfortheburstaccess.
Rev. 1.0 /Nov. 2009 6
H5GQ1H24AFR
ORDERING INFORMATION
Above Hynix P/N’s are Leead-free, RoHS Compliant and Halogen-free.
Note.1)It supports not only 5Gbps @ 1.5V, but also 3.2Gbps @ 1.35V.
PartNo PowerSupply CKFrequency WCKFrequency MaxDataRate Interface
H5GQ1H24AFR-R0C VDD/VDDQ=1.6V 1.50GHz 3.00GHz 6.0Gbps/pin
POD_15
H5GQ1H24AFR-T3C
VDD/VDDQ=1.5V
1.375GHz 2.75GHz 5.5Gbps/pin
H5GQ1H24AFR-T2L (Note1) 1.25GHz 2.50GHz 5.0Gbps/pin
H5GQ1H24AFR-T2C 1.25GHz 2.50GHz 5.0Gbps/pin
H5GQ1H24AFR-T1C 1.125GHz 2.25GHz 4.5Gbps/pin
H5GQ1H24AFR-T0C 1.00GHz 2.00GHz 4.0Gbps/pin
Rev. 1.0/Nov. 2009 7
H5GQ1H24AFR
0.1.DEFINITIONOFSIGNALSTATETERMINOLOGY
GDDR5SGRAMwillbeoperatedinbothODTEnable(terminated)andODTDisable(unterminated)
modes.ForhighestdataratesitisrecommendedtooperateintheODTEnablemode.ODTDisablemode
isdesignedtoreducepowerandmayoperateatreduceddatarates.ThereexistsituationswhereODT
Enablemodecannotbeguaranteedforashortperiodoftime,i.e.duringpowerup.
Followingarefourterminologiesdefinedforthestateofadevice(GDDR5SGRAMorcontroller)pindur‐
ingoperation.Thestateofthebuswillbedeterminedbythecombinationofthedevicepinsconnectedto
thebusinthesystem.ForexampleinGDDR5itispossiblefortheSGRAMpintobetristatedwhilethe
controllerpinisHighorODT.InbothcasesthebuswouldbeHighiftheODTisenabled.Fordetailson
theGDDR5SGRAMpinsandtheirfunctionsee“PACKAGESPECIFICATION”onpage 156and“SIG‐
NALS”onpage 158inthesectionentitled“PACKAGESPECIFICATION”onpage 156.
Devicepinsignallevel:
•High:AdevicepinisdrivingtheLogic“1”state.
•Low:AdevicepinisdrivingtheLogic“0”state.
•Hi‐Z:Adevicepinistristate.
•ODT:AdevicepinterminateswithODTsetting,whichcouldbeterminatingortristatedependingonMode
Registersetting.
Bussignallevel:
•High:OnedeviceonbusisHighandallotherdevicesonbusareeitherODTorHi‐Z.Thevoltagelevelonthebus
wouldbenominallyVDDQ
•Low:OnedeviceonbusisLowandallotherdevicesonbusareeitherODTorHi‐Z.Thevoltagelevelonthebus
wouldbenominallyVOL(DC)ifODTwasenabled,orVSSQifHi‐Z.
•Hi‐Z:AlldevicesonbusareHi‐Z.Thevoltagelevelonbusisundefinedasthebusisfloating.
•ODT:AtleastonedeviceonbusisODTandallothersareHi‐Z.Thevoltagelevelonthebuswouldbenominally
VDDQ.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 8
H5GQ1H24AFR
0.2.CLOCKING
TheGDDR5SGRAMoperatesfromadifferentialclockCKandCK#.Commandsareregisteredatevery
risingedgeofCK.AddressesareregisteredateveryrisingedgeofCKandeveryrisingedgeofCK#.
GDDR5usesaDDRdatainterfaceandan8n‐prefetcharchitecture.Thedatainterfaceusestwodifferen‐
tialforwardedclocks(WCK/WCK#).DDRmeansthatthedataisregisteredateveryrisingedgeofWCK
andrisingedgeofWCK#.WCKandWCK#arecontinuouslyrunningandoperateattwicethefrequency
ofthecommand/addressclock(CK/CK#).
Figure 1:GDDR5ClockingandInterfaceRelationship
CK
CK#
COMMAND
ADDRESS
DQ
*1
WCK
WCK#
Note:Figure.1showstherelationshipbetweenthedatarateofthebusesandtheclocksandisnotatimingdiagram.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 9
H5GQ1H24AFR
.
Figure 2:BlockDiagramofanexampleclocksystem
ClockPhase
Oscillator
QD
CMD/ADD
CMD/ADD DRAM
QD
QB
DQ[0]‐[7]
DQ
early/late
Receiver
DQ
WCK
int
DQ
DRAM
PLL
QD
DQ
Phasedetector/
corelogic early/latefrom
For8databits
Controller GDDR5SGRAM
PLL
clock
DataTx/Rx
WCK/WCK#
(2GHz)
CK/CK#
(1GHz)
CMDsampledbyCK/CK#asSDR
ADDsampledbyCK/CK#asDDR
ADD/CMDcenteredwithCK/CK#
calibrationdata
Phaseaccumulator
Controller
ClockPhase
Controller
(4Gbps)
core
core
(1GHz)
DQ
WCK2CK
Alignment
ToEDCpin
/2
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 10
H5GQ1H24AFR
1.INITIALIZATION
1.1.POWER‐UPSEQUENCE
GDDR5 SGRAMs must be powered up and initialized in a predefined manner as shown in <Link>Figure . Operational
procedures other than those specified may result in undefined operation. The Mode Registers do not have RESET
default values, except fo r ABI#, ADR/CMD termina tion, and the EDC hold p attern. I f the mode regis ters are not set dur-
ing the initialization sequence, it may lead to unspecified operation.
Step
1ApplypowertoVDD
2ApplypowertoVDDQatsametimeorafterpowerisappliedtoVDD
3ApplyVREFCandVREFDatsametimeorafterpowerisappliedtoVDDQ
4Afterpowerisstable,providestableclocksignalsCK/CK#
5 AssertandholdRESET#lowtoensurealldriversareinHi‐Zandallactiveterminationsareoff.AssertandholdNOPcommand.
6 Waitaminimumof200μs.
7Ifboundaryscanmodeisnecessary,SENcanbeassertedHIGHtoenterboundaryscanmode.Boundaryscanmodemustbe
entereddirectlyafterpower‐upwhileRESET#islow.Onceboundaryscanisexecuted,power‐upsequenceshouldbefollowed.
8
SetCKE#forthedesiredADR/CMDODTsettings,thenbringRESET#HightolatchinthelogicstateofCKE#,tATSandtATHmust
bemetduringthisprocedure.See<Link>Table1forthevaluesandlogicstatesforCKE#.TherisingedgeofRESET#willdetermine
x32modeorx16modedependingonthestateofEDC1(EDC2whenMF=1).Innormalx32mode,EDC1hastobesustainedHIGH
untilRESET#isHIGH.See<Link>TableforthevaluesandlogicstatesforEDC1(EDC2whenMF=1).
9BringCKE#LowaftertATHissatisfied
10 Waitatleast200μsreferencedfromthebeginningoftATS
11 Issueatleast2NOPcommands
12 IssueaPRECHARGEALLcommandfollowedbyNOPcommandsuntiltRPissatisfied
13 IssueMRScommandtoMR15.SetGDDR5SGRAMintoaddresstrainingmode(optional)
14 Completeaddresstraining(optional)
15 IssueMRScommandtoreadtheVendorID
16 IssueMRScommandtosetWCK01/WCK01#andWCK23/WCK23#terminationvalues
17 ProvidestableclocksignalsWCK01/WCK01#andWCK23/WCK23#
18
IssueMRScommandstousePLLornotandselectthepositionofaWCK/CKphasedetector.TheuseofPLLandthepositionofa
phasedetectorshouldbeissuedbeforeWCK2CKtraining.IssueMRScommandsincludingPLLresettothemoderegistersinany
order.tMRDmustbemetduringthisprocedure.WLmrs,CLmrs,CRCWLandCRCRLmustbeprogrammedbeforeWCK2CK
training.
19 IssuetwoREFRESHcommandsfollowedbyNOPuntiltRFCissatisfied
20 AfteranynecessaryGDDR5trainingsequencessuchasWCK2CKtraining,READtraining(LDFF,RDTR)andWRITEtraining
(WRTR,RDTR),thedeviceisreadyforoperation.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 11
H5GQ1H24AFR
Figure 3:GDDR5SGRAMPower‐upInitialization
1.2.Initialization with Stable Power
Thefollowingsequenceisrequiredforresetsubsequenttopower‐upinitialization.Thisrequiresthatthe
powerhasbeenstablewithinthespecifiedVDDandVDDQrangessincepower‐upinitialization(See
Figure 4)
Table 1AddressandCommandTermination
VA L U E (OHMS) CKE#atRESET#hightransition
ZQ/2 Low
ZQ High
TRAIN/MRS
TRAIN/MRS
ADR
CKE#
min.200μs
CMD
V
DD
V
DDQ
V
REFD/C
RESET#
t
ATS
t
ATH
Voltagesand
CKstable
DQ<31:0>,
DBI#<3:0>
ADR
EDC<3,0>
AllBanks
Precharge
WCK
NOP
NOP
CK#
CK
WCK#
PRE NOP
t
RP
Executionofsteps
13‐21inPower‐up
sequence
TRAIN/MRS
TRAIN/MRS
ADR
A.C.
ADR ADR
min.200μs
NOP
NOP
EDC<2,1> x32
x16
TRAIN/MRS
A.C.
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Note:A.C.=AnyCommand
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 12
H5GQ1H24AFR
1)AssertRESET#Lowanytimewhenresetisneeded.
2)HoldRESET#Lowforminimum100ns.AssertandholdNOPcommand.
3)SetCKE#forthedesiredADR/CMDODTsettings,thenbringRESET#Hightolatchinthelogicstateof
CKE#;tATSandtATHmustbemetduringthisprocedure.KeepEDC1(MF=0)/EDC2(MF=1)atthesame
logiclevelasduringpower‐upinitializationasdevicefunctionalityisnotguaranteediftheI/Owidthhas
changed.
4)Continuewithstep9ofthepower‐upinitializationsequence.
Figure 4:InitializationwithStablePower
TRAIN/MRS
ADR
CKE#
min.100ns
CMD
V
DD
,V
DDQ
V
REFD/C
RESET#
t
ATS
t
ATH
DQ<31:0>,
DBI#<3:0>
ADR
EDC<3:0>
AllBanks
Precharge
WCK
NOP
NOP
CK#
CK
WCK#
PRE NOP
t
RP
Executionofsteps
13‐21inPower‐up
sequence
TRAIN/MRS
TRAIN/MRS
ADR
A.C.
ADR ADR
min.200μs
NOP
NOP
TRAIN/MRS
A.C.
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Notes:1.A.C.=AnyCommand
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 13
H5GQ1H24AFR
1.2.VENDORID
GDDR5SGRAMsarerequiredtoincludeaVendorIDfeaturethatallowsthecontrollertoreceiveinforma‐
tionfromtheGDDR5SGRAMtodifferentiatebetweendifferentvendorsanddifferentdevicesusinga
softwarealgorithm.
WhentheVendorIDfunctionisenabledtheGDDR5SGRAMwillprovideitsManufacturersVendorCode
onbits[3:0]asshowninTable2;RevisionIdentificationonbits[7:4];Densityonbits[9:8];FIFODepthon
bits[11:10]asshowninTable3&Table4.Bits[15:12]areRFU.
VendorIDispartoftheINFOfieldofModeRegister3(MR3)andisselectedbyissuingaMODEREGIS‐
TERSETcommandwithMR3bitA6setto1,andbitA7setto0.MR3bitsA0‐A5andA8‐A11aresettothe
desiredvalues.
TheVendorIDwillbedrivenontotheDQbusaftertheMRScommandthatsetsbitsA6to1andA7to0.
TheDQbuswillbecontinuouslydrivenuntilanMRScommandsetsMR3A6andA7backto0todisable
theINFOfieldortoanothervalidstatefortheINFOfieldiftheINFOfieldincludessupportforadditional
vendorspecificinformation.TheDQbuswillbeinODTstateaftertWRIDOFF(max).Thecodecanbesam‐
pledbythecontrollerafterwaitingtWRIDON(max)andbeforetWRIDOFF(min).DBIisnotenabledor
ignoredduringallVendorIDoperations.Table4showsthemappingoftheVendorIDinfotothephysical
DQs.The16bitsofVendorIDaresentonByte0and2whenMF=0.WhenMF=1the16bitsaresenton
Byte1and3.Optionallythevendormayreplicatethedataontheother2byteswheninx32mode.Byte0
wouldbereplicatedonByte1andByte2wouldbereplicatedonByte3whenMF=0.WhenMF=1,Byte1
wouldbereplicatedonByte0andByte3wouldbereplicatedonByte2.
TAB LE2.ManufacturersVen d or Code
ManufacturersID Bit3Bit2Bit1Bit0NameofCompany
0 0000 Reserved
1 0001 Samsung
2 0010 Qimonda
3 0011 Elpida
4 0100 Etron
5 0101 Nanya
6 0110 Hynix
7 0111 ProMOS
8 1000 Winbond
9 1001 ESMT
A 1010 Reserved
B 1011 Reserved
C 1100 Reserved
D 1101 Reserved
E 1110 Reserved
F 1111 Micron
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 14
H5GQ1H24AFR
Figure 5:VendorIDTimingDiagram
Table 3RevisionID&Density&FIFODepth
RevisionID Density FIFO
Bit7Bit6Bit6Bit4Bit9Bit8Bit11 Bit10
00010110
Table 4VendorIDtoDQmapping
Bit 76543210
MF=0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
MF=1 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24
Feature RevisionIdentification ManufacturersVendorCode
Bit 15 14 13 12 11 10 9 8
MF=0 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16
MF=1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
Feature RFU FIFODepth Density
CK#
CK
CMD
BA0‐BA3
A2‐A5
A9,A10
A0,A1
A8
A7
A11
A6
MRA MRA
Code
Code
Code Code
Code
Code
CodeCode
t
WRIDON
(max)
DQ
t
WRIDOFF
(min)
VendorID+RevCode
MRA=ModeRegisterAddress;Code=Opcodetobeloaded
NOP MRS NOP NOP NOP NOP MRS NOP NOP NOP NOP
DonʹtCare
Code
Code
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 15
H5GQ1H24AFR
2.ADDRESS
2.1.ADDRESSING
GDDR5SGRAMsuseadoubledatarateaddressschemetoreducepinsrequiredontheGDDR5SGRAM
asshowninTable5.TheaddressesshouldbeprovidedtotheGDDR5SGRAMintwoparts;thefirsthalfis
latchedontherisingedgeofCKalongwiththecommandpinssuchasRAS#,CAS#andWE#;thesecond
halfislatchedonthenextrisingedgeofCK#.
TheuseofDDRaddressingallowsalladdressvaluestobelatchedinatthesamerateastheSDRcom‐
mands.Alladdressesrelatedtocommandaccesshavebeenpositionedforlatchingontheinitialrising
edgeforfasterdecoding.
Note:AddresspinA12isrequiredonlyfor2Gdensity.
GDDR5addressingincludessupportfor1Gdensity.Foralldensitiestwomodesaresupported(x32mode
orx16mode).x32andx16modesdifferonlyinthenumberofvalidcolumnaddresses,asshowninTable6.
Table 5AddressPairs
Clock
RisingCK BA3 BA2 BA1 BA0 (A12) A11 A10 A9 A8
RisingCK# A3 A4 A5 A2 (RFU) A6 A0 A1 A7
Table 6AddressingScheme
1G
x32mode x16mode
Rowaddress A0~A11 A0~A11
Columnaddress A0~A5 A0~A6
Bankaddress BA0~BA3 BA0~BA3
Autoprecharge A8 A8
PageSize 2K 2K
Refresh8K/32ms 8K/32ms
Refreshperiod 3.9us 3.9us
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 16
H5GQ1H24AFR
2.2.ADDRESSBUSINVERSION(ABI)
AddressBusInversion(ABI)reducesthepowerrequirementsonaddresspins,astheno.ofaddresslines
drivingalowlevelcanbelimitedto4(incaseA12/RFUisnotwired)or5(incaseA12/RFUiswired).
TheAddressBusInversionfunctionisassociatedwiththeelectricalsignallingontheaddresslines
betweenacontrollerandtheGDDR5SGRAM,regardlessofwhethertheinformationconveyedonthe
addresslinesisaroworcolumnaddress,amoderegisterop‐code,adatamask,oranyotherpattern.
TheABI#inputisanactiveLowdoubledatarate(DDR)signalandsampledbytheGDDR5SGRAMatthe
risingedgeofCKandtherisingedgeofCK#alongwiththeaddressinputs.
OnceenabledbythecorrespondingABIModeRegisterbit,theGDDR5SGRAMwillinvertthepattern
receivedontheaddressinputsincaseABI#wassampledLow,orleavethepatternnon‐invertedincase
ABI#wassampledHigh,asshowninFigure6.
Figure 6:ExampleofAddressBusInversionLogic
8(9) 8(9) to
DRAM
core
ABI#
Address
Pins
fromModeRegister:
0=enabled
1=disabled
Note:buswidthis8whenA12/RFUpinisnotpresent,and9whenA12/RFUpinispresent
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 17
H5GQ1H24AFR
TheflowdiagraminFigure7illustratestheABIoperation.Thecontrollerdecideswhethertoinvertornot
invertthedataconveyedontheaddresslines.TheGDDR5SGRAMhastoperformthereverseoperation
basedontheleveloftheABI#pin.AddressinputtimingparametersareonlyvalidwithABIbeingenabled
andamaximumof4addressinputsdrivenLow.
Figure 7:AddressBusInversion(ABI)FlowDiagram
Datatobesent
onaddresslines
’0’count
>4?
ABI#=’L’
Invert
Yes
ABI#=’H’
Don’tinvert
No
Determine’0’
count
Datareceived
onaddresslines
ABI#=’H’
Don’tinvert
ABI#=’L’
Invert
Controller
GDDR5
SGRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 18
H5GQ1H24AFR
2.3.BANKGROUPS
ForGDDR5SGRAMdevicesoperatingatfrequenciesaboveacertainthreshold,theactivitywithinabank
groupmustberestrictedtoensureproperoperationofthedevice.The8or16banksinGDDR5SGRAMs
aredividedintofourbankgroups.ThebankgroupsfeatureiscontrolledbybitsA10andA11inMode
Register3(MR3).TheassignmentofthebankstothebankgroupsisshowninTable7.
Thesebankgroupsallowthespecificationofdifferentcommanddelayparametersdependingonwhether
back‐to‐backaccessesaretobankswithinonebankgrouporacrossbankgroupsasshowninTable8.
Table 7BankGroups
Bank Addressing 1G
BA3 BA2 BA1 BA0 16banks
00000
GroupA
10001
20010
30011
40100
GroupB
50101
60110
70111
81000
GroupC
91001
101010
111011
121100
GroupD
131101
141110
151111
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 19
H5GQ1H24AFR
Note.1:ParameterstRTPSandtRTPLapplyonlywhenREADandPRECHARGEgotothesamebank;usetRTPSwhenBGare
disabled,andtRTPLwhenBGareenabled.
Table 8CommandSequencesAffectedbyBankGroups
CommandSequence
CorrespondingACTimingParameter
Notes
BankGroups
Disabled
BankGroupsEnabled
Accessestodifferentbank
groups
Accesseswithinthesame
bankgroup
ACTIVEtoACTIVE tRRDS tRRDS tRRDL
WRITEtoWRITE tCCDS tCCDS tCCDL
READtoREAD tCCDS tCCDS tCCDL
InternalWRITEtoREAD tWTRS tWTRS tWTRL
READtoPRECHARGE tRTPS 1tck tRTPL 1
Rev. 1.0 /Nov. 2009 20
H5GQ1H24AFR
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CLK
CAS
DQ
A0 A1 B0 B1 C0 C1
A0 A1 B0 B1 C1
Example1(BankGroupsdisabled):tCCDS=2*tCK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CLK
CAS
DQ
A0 A1 A2 A3
A0 A1 A2
Example2:(BankGroupsenabled):tCCDL=4*tCK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CLK
CAS
DQ
A0 B0 A1 B1 C0 D0
A0 B0 A1 B1 C0
Example3:(BankGroupsenabled):tCCDS=2*tCK
T12
T12
T12
D0
A3
C1
T13
T13
T13
C0 D0
D0 C1
Back-to-back column accesses based on tCCDL and tCCDS parameters.
Notes:
1)Columnaccessesaretoopenbanks,andtRCDhasbeenmet.
2)CL=0assumed
3)Ax,Bx,Cx,Dx:accessestobankgroupsA,B,CorD,respectively
4)Withbankgroupsenabled,tCCDLis3tCK,asprogrammedinMR3.
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 21
H5GQ1H24AFR
3.TRAINING
3.1.INTERFACETRAININGSEQUENCE
DuetothehighdataratesofGDDR5,itisrecommendedthattheinterfacesbetrainedtooperatewiththe
optimaltimings.GDDR5SGRAMhasfeaturesdefinedwhichallowforcompleteandefficienttrainingof
theI/OinterfacewithouttheuseoftheGDDR5SGRAMarray.Theinterfacetrainingsarerequiredfornor‐
malDRAMfunctionalityunlessrunninginlowerfrequencymodesasdescribedinthelowfrequencysec‐
tion.Interfacetimingswillonlybeguaranteedafterallrequiredtrainingshavebeenexecuted.
Arecommendedorderoftrainingsequenceshasbeenchosenbasedonthefollowingcriteria:
TheaddresstrainingmustbedonefirsttoallowfullaccesstotheModeRegisters.(MRSforaddresstrain‐
ingisaspecialsingledataratemoderegistersetguaranteedtoworkwithouttraining).Addressinputtim‐
ingshallfunctionwithouttrainingaslongastAS/HaremetattheGDDR5SGRAM.
WCK2CKtrainingshouldbedonebeforereadtrainingbecauseashiftinWCKrelativeCKwillcausea
shiftinallREADtimingsrelativetoCK.
READtrainingshouldbedonebeforeWRITEtrainingbecauseoptimalWRITEtrainingdependsoncor‐
rectREADdata.
Figure 8:InterfaceTrainingSequence
Initialization
AddressTraining(optional)
WCK2CKAlignmentTraining
READTraining
WRITETraining
StartNormalOperation
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 22
H5GQ1H24AFR
3.2.ADDRESSTRAINING
TheGDDR5SGRAMprovidesmeansforaddressbusinterfacetraining.Thecontrollermayusethe
addresstrainingmodetoimprovethetimingmarginsontheaddressbus.
AddresstrainingmodeisenteredandexitedviatheADTbitinModeRegister15(MR15).ModeRegister
15supportsthesamesetupandholdtimesontheaddresspinsasforcommandstoallowasafeentryinto
addresstrainingmode.
AddresstrainingmodeusesaninternalbridgebetweentheGDDR5SGRAM’saddressinputsandDQ/
DBI#outputs.ItalsousesaspecialREADcommandforaddresscapturethatisencodedusingtheSDR
commandpinsonly(CS#,RAS#,CAS#,WE#=L,H,L,H).Theaddressvaluesnormallyusedtoencodethe
commandswillnotbeinterpreted.Oncetheaddresstrainingmodehasbeenentered,theaddressvalues
registeredcoincidentwiththisspecialREADcommandwillbetransmittedtothecontrollerontheDQ/
DBI#pins.Thecontrolleristhenexpectedtocomparetheaddresspatternreceivedtotheexpectedvalue
andtoadjusttheaddresstransmittimingaccordingly.Theproceduremayberepeatedusingdifferent
addresspatternandinterfacetimings.
NoWCKclockisrequiredforthisspecialREADcommandoperationduringaddresstrainingmode.The
latchedaddressesaredrivenoutasynchronously.
TheonlycommandsallowedduringaddresstrainingmodearethisspecialREAD,MRS(e.g.toexit
addresstrainingmode)andNOP/DESELECT.
WhenenabledbytheABIbitinModeRegister1,addressbusinversion(ABI)iseffectiveduringaddress
trainingmode.ItissuggestedtotraintheABI#pin’sinterfacetimingtogetherwiththeotheraddresslines.
ThetimingdiagraminFigure9illustratesthetypicalcommandsequenceinaddresstrainingmode.The
DQ/DBI#outputdriversareenabledaslongastheADTbitisset.Theminimumspacingbetweenconsec‐
utivespecialREADcommandsis2tCK.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 23
H5GQ1H24AFR
Figure 9:AddressTrainingTiming
Table10definesthecorrespondencebetweenaddressbitsandDQ/DBI#.Devicesconfiguredtox16mode
reflecttheaddressonthetwobytesbeingenabledinthatmode,whicharebytes0and2forMF=0and
bytes1and3forMF=1configurations.Devicesconfiguredtox32modereflecttheaddressonthesameDQ
asinx16mode;inadditiontheyareallowedbutnotrequiredtoreflecttheaddressonthosebytesthatare
disabledinx16mode,thusreflectingeachaddresstwice.
DevicesnotsupportinganA12/RFUpinshalldrivealogicHighontheDBI#pins.
Table 9ACtimingsinAddressTrainingMode
Parameter Symbol Min Max Unit
READcommandtodataoutdelaytADR 0.5*tCK+0 0.5*tCK+10 ns
ADTofftoDQ/DBI#inODTstatedelay tADZ ‐‐ 0.5*tCK+10 ns
CK#
CK
t
ADR
Even
DQ
Notes:
1)READcommandencoding:CS#=L,RAS#=H,CAS#=L,WE#=H
2)ADRxR=1sthalfofaddressx,sampledonrisingedgeofCK;
ADRxR#=2ndhalfofaddressx,sampledonrisingedgeofCK#
3)AddressessampledonrisingedgeofCKarereturnedonevenDQaftertADR;
addressessampledonrisingedgeofCK#arereturnedonoddDQsimultaneouslywithevenDQ
4)DQsareenabledwhenADTbitinModeRegister15setto1(EnterAddressTrainingMode)
DQsaredisabledaftert
ADZ
whenADTbitinModeRegister15setto0(ExitAddressTrainingMode)
ADRx
R#
CMD
ADDR
ADRy
R
ADRy
R#
Odd
DQ
t
ADR
t
MRD
MR15
A10=1
ADRx
R
DonʹtCare
ADRx
RADRy
R
ADRx
R# ADRy
R#
ADRz
R
ADRz
R
ADRz
R#
t
ADR
MR15
A10=0
t
ADZ
ADRz
R#
MRS NOP READ(*) NOP READ(*) NOP READ(*) NOP MRS NOP NOP NOP NOP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 24
H5GQ1H24AFR
Table 10AddresstoDQMappinginAddressTrainingMode
Output AddressbitsregisteredatrisingedgeofCK
A12 A8 A11 BA1 BA2 BA3 BA0 A9 A10
DQ DBI0# DQ22 DQ20 DQ18 DQ16 DQ6 DQ4 DQ2 DQ0
DBI1# DQ30 DQ28 DQ26 DQ24 DQ14 DQ12 DQ10 DQ8
Output AddressbitsregisteredatrisingedgeofCK#
RFU A7 A6 A5 A4 A3 A2 A1 A0
DQ DBI2# DQ23 DQ21 DQ19 DQ17 DQ7 DQ5 DQ3 DQ1
DBI3# DQ31 DQ29 DQ27 DQ25 DQ15 DQ13 DQ11 DQ9
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 25
H5GQ1H24AFR
3.3.WCK2CKTRAINING
ThepurposeofWCK2CKtrainingistoalignthedataWCKclockwiththecommandCKclocktoaidinthe
GDDR5SGRAM’sinternaldatasynchronizationbetweenthelogicclockedbyCK/CK#andWCK/WCK#.
ThiswillhelptodefinebothReadandWritelatenciesbetweentheGDDR5SGRAMandmemorycontrol‐
ler.WCK2CKtrainingmodeiscontrolledviaMRS.
BeforestartingWCK2CKtraining,thefollowingconditionsmustbemet:
•CK/CK#clockisstableandtoggling
•Thetimingofalladdressandcommandpinsmustbeguaranteed
•PLLon/off(MR1bitA7)andPLLdelaycompensationenable(MR7bitA2)aresettodesiredmodebeforeWCKto
CKtrainingisstarted
•ThedesiredWCK2CKalignmentpoint(MR6,bitA0)isselected
•TheEDCholdpattern(MR4,bitsA0‐A3)mustbeprogrammedto‘1111’
•2ModeRegisterbitsforinternalWCK01andWCK23inversion(MR3,bitsA2‐A3)mustbesettoaknownstate
•Allbanksareidleandnoothercommandexecutionisinprogress
WCK2CKtrainingmustbedoneafteranyofthefollowingconditions:
•Deviceinitialization
•AnyCLmrs,WLmrs,CRCRLorCRCWLlatencychange
•CKandWCKfrequencychanges
•PLLon/off(MR1bitA7)andPLLdelaycompensationmode(MR7bitA2)changes
• ChangeoftheWCK2CKalignmentpoint(MR6,bitA0)
•WCKstatechangefromofftotoggling,includingselfrefreshexitorexitfrompower‐downwhenbitA1(LP2)in
MR5isset
Figure10andFigure11showexampleWCK2CKtrainingsequences.WCK2CKtrainingisenteredvia
MRSbysettingbitA4inMR3.ThiswillinitiatetheWCKdivide‐by‐2circuitsassociatedwithWCK01and
WCK23clocksintheGDDR5SGRAM.Incasethedivide‐by‐2circuitsareatoppositeoutputphases,
whichisindicatedbyopposite“early/late”phasesontheEDCpinsassociatedwithWCK01andWCK23
(seebelow),theymaybeputinphasebyusingtheWCK01andWCK23inversionbits.Alternatively,the
WCKclocksmaybeputintoastableinactivestateforthisinitializationeventtoaidinresettingalldivid‐
erstothesameoutputphaseasshownin<Link>Figure11.Thechallengeofthismethodistorestartthe
WCKclocksinawaythateventheirfirstclockedgesmeettheWCKclockinputspecification.Otherwise,
divide‐by‐2circuitsforbothWCK01andWCK23mightagainhaveoppositephasealignment.
Figure12illustrateshowtheWCKphaseinformationisderived.Thephasedetectors(PD)samplethe
internallydivided‐by‐2WCKclocks.Onlyonesamplepointisshowninthefigureforclarity.Inreality,
whenWCK2CKtrainingmodeisenabled,asamplewilloccureverytCKandwillbetranslatedtotheEDC
pinsaccordingly.Ifthedivided‐by‐2WCKclockarrivesearly,thentheEDCpinoutputstheEDChold
patternduringthetimeintervalspecifiedinFigure12.Ifthedivided‐by‐2WCKclockarriveslate,thenthe
EDCpinoutputstheinvertedEDCholdpatternduringthetimeintervalspecifiedinFigure12.Thisis
showninTable11.
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 26
H5GQ1H24AFR
Figure 10:ExampleWCK2CKTrainingSequence
Figure 11:ExampleWCK2CKTrainingSequencewithWCKStopping
CK
CK#
NOP NOP MRS NOP NOP NOP NOP MRS MRS
CMD A.C.
t
LK
t
MRD
EnterWCK2CKTraining StartWCK2CK
PhaseSearch
PLLResetExitWCK2CKTraining
(setsdatasynchronizers,
restsFIFOpointers)
WCK
WCK#
(PLLononly)
NOPMRSNOP NOPNOPNOP MRSNOPNOP ValidMRS
CK#
CK
CMD
tWCK2MRS
WCK
W
CK#
tMRSTWCK tWCK2TR
EnterWCK2CK
TrainingbyMRS
WCK
Restart
StartWCK2CK
PhaseSearch
tLK tMRD
ExitWCK2CK
(resetsWCKdivide‐
by‐2circuits) resetsFIFOpointers)
(Setdatasynchronizers,
TrainingbyMRS
PLLReset
(PLLononly)
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 27
H5GQ1H24AFR
Figure 12:EDCpinBehaviourforWCK2CKTraining(assumes‘1111’asEDCHoldPattern)
Theidealalignmentisindicatedbythephasedetectoroutputtransitioningfrom“early”to“late”when
thedelayoftheWCKphaseiscontinuouslyincreased.TheWCKphaserangeforidealalignmentisspeci‐
fiedbytheparametertWCK2CKPIN;thevalue(s)varywiththePLLmode(onoroff)andtheselectedalign‐
mentpoint.
Ifenabled,thePLLshallnotinterfereinthebehavioroftheWCK2CKtraining.Significantlymovingthe
phaseand/orstoppingtheWCKduringtrainingmaydisturbthePLL.ItisrequiredtoperformaPLLreset
aftertheWCK2CKtraininghasdeterminedandselectedtheproperalignmentbetweenWCKandCK
clocks.ThePLLlocktimetLKmustbemetbeforeexitingWCK2CKtrainingtoguaranteethatthePLLisin
locksuchthattheGDDR5SGRAMdatasynchronizersaresetuponWCK2CKtrainingexit.
WCK2CKtrainingisexitedviaMRSbyresettingbitA4inMR3.Forproperresetofthedatasynchronizers
itisrequiredthattheWCKandCKclocksarealignedwithintWCK2CKSYNCatthetimeoftheWCK2CK
trainingexit.
Table 11PhaseDetectorandEDCPinbehavior
WCK/2valuesampledbyCK WCK2CKPhase DataonEDCPin Action
‘1’ ‘Early’ EDChold(‘1111’) IncreaseDelayonWCK
‘0’ ‘Late’ InvertedEDCHold(‘0000’) DecreaseDelayonWCK
x
EDC0
CK
WCK01/2
WCK23/2
(internal)
x x x x x x x x x x x x x x
EDC2
1
‐tWCK2CK
tWCKTPH
WCKEarly
EDC0
WCK01/2
WCK23/2
(internal)
xxxxxxxx xxxxxxx
EDC2
0
+tWCK2CK
tWCKTPH
WCKLate
1
2
1111
0000
EDC0
WCK01/2
WCK23/2
(internal)
x x x x x x x x x x x x x x x
EDC2
tWCKTPH
3x x x x
Aligned
Late
Early
~
~
~
~~
~
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 28
H5GQ1H24AFR
AfterexitingWCK2CKtrainingmode,theWCKphaseisallowedtofurtherdriftfromtheidealalignment
pointbyamaximumoftWCK2CK(e.g.duetovoltageandtemperaturevariation).OncethisWCKphase
driftexceedstWCK2CK(min)ortWCK2CK(max),itisrequiredtorepeattheWCK2CKtrainingandrealign
theclocks.
WCK2CKalignmentatPINMode
TheWCKandCKphasealignmentpointcanbechangedviaMRSbysettingbitA0inMR6.Innormal
mode,whenMR6A0issetto‘0’,thephasesofCKandWCKarealignedatCKpinsandtheendofWCK
treeasshowninFigure13.Ontheotherhand,whenMR6A0issetto‘1’,thephasesofCKandWCKare
alignedatthepinasshowninFigure14.PINmodeissupporteduptothemaxCKclockfrequencyof
fCKPIN,andisanoptiontoreducethetimeofWCK2CKtrainingatlowfrequency.
Figure 13:NormalMode
Figure 14:PinMode
WCK2CKAutoSynchronization
GDDR5SGRAMssupportaWCK2CKautomaticsynchronizationmodethateliminatestheneedfor
WCK2CKtraininguponpower‐downexit.Thismodeiscontrolledbytheautosyncbit(MR7,bitA4),and
iseffectivewhentheLP2bit(MR5,bitA1)issetandtheWCKclocksarestoppedduringpower‐down.
CK
CK#
WCK
WCK#
DQ
CK
EDC
InternalWCK/2
InternalCK
Phase
Detector
CK
CK#
WCK
WCK#
DQ
CK
EDC
InternalWCK/2
InternalCK
Phase
Detector
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
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Rev. 1.0 /Nov. 2009 29
H5GQ1H24AFR
Also,thismodeworksforbothnormalandPINmode.WhenWCK2CKautomaticsynchronizationmode
isenabled,afullWCK2CKtrainingincludingPhasesearchisnotrequiredafterpower‐downexit,
althoughWCK2CKMRSmustbeissuedmomentarilyforsettingthedatasynchronizers.However,WCK
andCKclocksmustmeetthetWCK2CKSYNCspecificationuponpower‐downexit.Anyallowedcommand
maybeissuedaftertXPNoraftertLKincasethePLLhadbeenenableduponpower‐downentry.ThePLL
sequenceisnotaffectedbythismode.TheuseofWCK2CKautomaticsynchronizationmodeisrestricted
toloweroperatingfrequenciesuptofCKAUTOSYNCasdescribedinthedatasheets.
Table12describesWCK2CKtrainingmethodsfordifferentfrequencyranges.EachFrequencyrangeis
vendorspecific.NormalandPINmodeofWCK2CKtrainingaredescribedinTable12.Eachfrequency
rangeisDRAMvendorspecific.DividerinitializationcanbedonebytrainingwithWCK2CKinversion,
WCK2CKstopping,orWCK2CKauto‐sync.IftheuserwantstouseWCK2CKstopfordividerinitializa‐
tioninsteadofWCK2CKauto‐sync,theusermustnotsettheWCK2CKauto‐sync.Lowfrequency,the
combineduseofPINandWCK2CKauto‐syncmodescanminimizeWCK2CKtrainingtime.
*Note:ThedividedWCK/WCK#shouldbealignedCK/CK#byWCK2CKAutoSynchronizationorWCKstopmode
ThefollowingexamplesdescribetheWCK2CKtraininginmoredetail.
Example1:outlineofabasicWCK2CKtrainingsequencewithoutWCKclockstop:
1)EnabletrainingmodeviaMRSandwaittMRD
2)SweepandobservethephaseindependentlyforWCK01onEDC0andWCK23onEDC2;incase
theinternaldivide‐by‐2circuitsareatoppositephaseuseeithertheWCK01orWCK23inversion
bit
tofliponeoftheWCKdivide‐by‐2circuits
3)AdjusttheWCKphaseindependentlyforWCK01andWCK23totheoptimalpoint(“ideal
alignment”)
4)IssueaPLLresetandwaitfortLK(PLLonmodeonly)
5)WhileallWCKandCKarealigned,exitWCK2CKtrainingmodeviaMRS
6)WaittMRDfortheresetofdatasynchronizers
Table 12WCK2CKtrainingsimplifiedforNormalmodeandPINmode
HighFrequencyLowFrequency
Frequency ≥ 2Gbps ＜ 2Gbps
WCK2CKalignmentmode Normal PIN Normal PIN
PhaseSearch Required Required No* No*
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 30
H5GQ1H24AFR
Example2:outlineofabasicWCK2CKtrainingsequencewithoptionalWCKclockstop:
1)StopWCKclockswithWCK01/WCK23LOWandWCK01#/WCK23#HIGH
2)WaittWCK2MRSforinternalWCKclockstosettle
3)EnabletrainingmodeviaMRSandwaittMRDfordivide‐by‐2circuitstoreset
4)StartWCKclockswithoutglitches(bothdivide‐by‐2circuitsremaininsync)
5)WaittWCK2TRforinternalWCKclockstostabilize
6)SweepandobservethephaseindependentlyforWCK01onEDC0andWCK23onEDC2;adjust
the
WCKphasetotheoptimalpoint(“idealalignment”)
7)IssueaPLLresetandwaittLK(PLLonmodeonly)
8)WhileallWCKandCKarealigned,exitWCK2CKtrainingmodeviaMRS
9)WaittMRDfortheresetofdatasynchronizers
READandWRITElatencytimingsaredefinedrelativetoCK.AnyoffsetinWCKandCKatthepinsand/
orthephasedetectorwillbereflectedinthelatencytimings.Theparametersusedtodefinetherelation‐
shipbetweenWCKandCKareshowninFigure6.FormoredetailsontheimpactonREADandWRITE
timingsseetheOPERATIONSsection.
Figure 15:WCK2CKTimings
CK
CK#
t
CH
t
CL
t
CK
WCK
WCK# t
WCK2CKPIN
Case1:Negativet
WCK2CKPIN
;t
WCK2CK
=0(idealWCK2CKalignment)
t
WCK
WCK
WCK#
Case2:Negativet
WCK2CKPIN
;negativet
WCK2CK
WCK
WCK# t
WCK2CKPIN
Case3:Positivet
WCK2CKPIN
;t
WCK2CK
=0(idealWCK2CKalignment)
t
WCK2CKPIN
+t
WCK2CK
WCK#
WCK
Case4:Positivet
WCK2CKPIN
;positivet
WCK2CK
t
WCK2CKPIN
+t
WCK2CK
Note: t
WCK2CKPIN
andt
WCK2CK
parametervaluescouldbenegativeorpositivenumbers,dependingontheselected
WCK2CKalignmentpoint,PLL‐on‐orPLL‐offmodeoperationanddesignimplementation.Theyalsovaryacross
PVT.WCK2CKtrainingisrequiredtodeterminethecorrectWCK‐to‐CKphaseforstabledeviceoperation.
t
WCKH
t
WCKL
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Rev. 1.0 /Nov. 2009 31
H5GQ1H24AFR
GDDR5WCK2CKTraininginx16mode
ForconfigurationswithWCKclocksnotsharedbetweentwoGDDR5SGRAMsitissuggestedtosetthe
WCKphasetotheidealalignmentpoint.However,forconfigurationswheretwoGDDR5SGRAMs(x16)
sharetheirWCKclocksasinax16clamshell,anoffsetgivenbythemidpointofbothDRAM’sidealWCK
positionsmayberequired.Themaximumallowedoffsetinthiscaseisspecifiedbyparameter
tWCK2CKSYNC:itdefinestheWCKoffsetrangefromtheidealalignmentwhichstillguaranteesaGDDR5
SGRAMdevicetointernallysynchronizeitsWCKandCKclocksupontrainingexit.
Example:outlineoftrainingsequenceforx32andx16configurationswith2GDDR5SGRAMssharing
theirWCKclocks(e.g.clamshell):
1)EnabletrainingmodeforbothDRAMsviaMRSandwaittMRD
2)ForbothDRAMssweepandobservethephaseindependentlyforWCK01onEDC0andWCK23
on
EDC2;incasetheinternaldivide‐by‐2circuitsareatoppositephasesuseeithertheWCK01or
WCK23inversionbittofliponeoftheWCKdivide‐by‐2circuits;incaseofsharedCS#signalsuse
MREMF0andMREMF1bitsinMR15toexplicitlydirecttheMRScommandforthisphaseflipping
toeitherDRAM1orDRAM2(“softchipselect”);
3)SweepandobservethephaseonDRAM1independentlyforWCK01onEDC0andWCK23on
EDC2;storethesettingfortheoptimalWCKphase
4)SweepandobservethephaseonDRAM2independentlyforWCK01onEDC0andWCK23on
EDC2;storethesettingfortheoptimalWCKphase
5)SweepWCK01andWCK23phasetomidpointofDRAM1andDRAM2optimalsettings
6)IssueaPLLresetandwaitfortLK(PLLonmodeonly)
7)WhileallWCKandCKarealigned,exitWCK2CKtrainingmodeviaMRS
8)WaittMRDfortheresetofdatasynchronizers
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 32
H5GQ1H24AFR
3.4.READTRAINING
Readtrainingallowsthememorycontrollertofindthedata‐eyecenter(symboltraining)andburstframe
location(frametraining)foreachhigh‐speedoutputoftheGDDR5SGRAM.Eachpin(DQ0‐DQ31,DBI0#‐
DBI3#,EDC0‐EDC3)canbeindividuallytrainedduringthissequence.
ForReadTrainingthefollowingconditionsmustbetrue:
•atleastonebankisactive,oranautorefreshmustbeinprogressandbitA2inModeRegister5(MR5)issetto0to
allowtrainingduringautorefresh(todisablethisspecialREFenablingoftheWCKclocktreeanACTcommand
mustbeissued,orthedevicemustbesetintopower‐downorselfrefreshmode)
•WCK2CKtrainingmustbecomplete
•thePLLmustbelocked,ifenabled
•RDBIandWDBImustbeenabledpriortoandduringReadTrainingifthetrainingshallincludetheDBI#pins.
RDCRCandWRCRCmustbeenabledpriortoandduringReadTrainingifthetrainingshallincludetheEDC
pins.
ThefollowingcommandsareassociatedwithReadTraining:
•LDFFtopreloadtheReadFIFO;
•RDTRtoreadaburstofdatadirectlyoutoftheReadFIFO.
NeitherLDFFnorRDTRaccessthememorycore.NoMRSisrequiredtoenterReadTraining.
Figure16showsanexampleoftheinternaldatapathsusedwithLDFFandRDTR.Table13listsACtiming
parametersassociatedwithReadTraining.
Table 13LDFFandRDTRTIMINGS
PARAMETER SYMBOL
VALUES
UNIT NOTES
MIN MAX
ACTIVEtoLDFFcommanddelay tRCDLTR 10 – ns
ACTIVEtoRDTRcommanddelay tRCDRTR 10 – ns
REFRESHtoRDTRorWRTRcommanddelay tREFTR 10 – ns
RDTRtoRDTRcommanddelay tCCDS 2–t
CK
LDFFtoLDFFcommandcycletime tLTLTR 4–t
CK
LDFF(111)toLDFFcommandcycletime tLTL7TR 4–t
CK a
a. Themin.valuedoesnotexceed8tCK.
LDFF(111)toRDTRcommanddelay tLTRTR 4–t
CK
READorRDTRtoLDFFcommanddelay tRDTLT 4–t
CK
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 33
H5GQ1H24AFR
Figure 16:DataPathsusedforReadandWriteTraining
LDFFCommand
TheLDFFcommand(Figure17)isusedtosecurelyloaddatatotheGDDR5SGRAMReadFIFOsviathe
addressbus.DependingontheGDDR5SGRAMREADFIFOdepthnFIFO6,anybitpatternoflength32‐
48canbeloadeduniquelytoeveryDQ,DBI#andEDCpinwithinabyte.TheFIFOdepthisfixedby
designandcanbereadviatheVendorIDfunction.
EightLDFFcommandsarerequiredtofilloneFIFOstage;eachLDFFcommandloadsoneburstposition,
andthebankaddressesBA0‐BA2selecttheburstpositionfrom0to7.
ThedatapatternisconveyedonaddresspinsA0‐A7forDQ0‐DQ7,A9forDBI0#,andBA3forEDC0;the
dataareinternallyreplicatedtoall4bytes,asshowninFigure18.
72
WRTRstrobe
(CKdomain)
WRTR
FIFO6×72=432 bitsperbyte
RDTRstrobe
(WCK)
Reverse
DBI
DRAM
Core
64
64
WRTR
output
pointer
input
pointer
DQ0‐DQ7
DBI0#
EDC0
e.g.500Mbps
DBI
e.g.4Gbps
e.g.
500Mbps
RDTRstrobe
(WCK)
72
LDFF
ADDR
72
8
DEMUX
LDFF
8
10
BA0‐BA2
Notes:
1)FIFOdepthof5shown;supportedFIFOdepths:4,5or6
2)datapathsshownfor1of4bytes(byte0)
Address
Path
4321
043210
output
pointer
input
pointer
4321
043210
9
0
8
16
24
32
40
48
56
64
1
9
17
25
33
41
49
57
65
2
10
18
26
34
42
50
58
66
3
11
19
27
35
43
51
59
67
4
12
20
28
36
44
52
60
68
5
13
21
29
37
45
53
61
69
6
14
22
30
38
46
54
62
70
7
15
23
31
39
47
55
63
71
8
8:1TX
9
ParalleltoSerial
Converter
SerialtoParallel
Converter
72
8:1RX
8:1
ParalleltoSerial
Converter
CRCstrobe
LDFFstrobe(burst7)
WRTRstrobe
LDFFstrobe(burst7)
M
U
X
M
U
X
72
M
U
X
DQ
72
M
U
X
8
CRC8
RX
DatapathusedwithRDTR
DatapathusedwithWRTR
8
M
U
X
0 1 2 3 4 5 67
CRCFIFO6×8=48 bitsper byte
DatapathusedwithLDFF
DatapathusedwithLDFF/WRTR
TX
5
5
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Rev. 1.0 /Nov. 2009 34
H5GQ1H24AFR
LDFFloadstheDBIFIFOregardlessoftheWDBIandRDBIModeRegisterbits.ItalsoloadstheEDCFIFO
regardlessoftheWRCRCandRDCRCModeRegisterbits,andnoCRCiscalculated;however,RDBIand
RDCRCmustbeenabledtoreadtheDBIandEDCbits,respectively,withtheRDTRcommand.
Figure 17:LDFFCommand
CS#
WE#
CAS#
RAS#
CKE# LOW
LDFF
CK
CK#
A9,BA3
A1,A3
A8,A10,A11
BA0‐BA2
A2,A4,A5
0,0,1
A0,A7,A6
DATA DATA
DATA
DATA
DATA=FIFOdata
BP
BP=BurstPosition
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 35
H5GQ1H24AFR
Figure 18:LDFFCommandAddresstoDQ/DBI#/EDCMapping
Allburstaddresses0to7mustbeloaded;LDFFcommandstoburstaddress0to6maybeissuedinran‐
domorder;theLDFFcommandtoburstaddress7(LDFF7)mustbethelastof8consecutiveLDFFcom‐
mands,asiteffectivelyloadsthedataintotheFIFOandresultsinaFIFOpointerincrement.Consecutive
LDFFcommandshavetobespacedbyatleasttLTLTR,andatleasttLTL7TRcyclesarerequiredaftereach
LDFFcommandtoburstaddress7.
LDFFpatternmayefficientlybereplicatedtothenextFIFOstagesbyissuingconsecutiveLDFFcommands
toburstaddress7(withidenticaldatapattern).ThedatapatterninthescratchmemoryforLDFFwillbe
availableuntilthefirstRDTRcommand.
TheDQ/DBI#outputbuffersremaininODTstateduringLDFF.
AnamountofLDFFcommandstoburstaddress7greaterthantheFIFOdepthisallowedandshallresult
inaloopingoftheFIFO’sdatainput.
ThetotalnumberofLDFFcommandstoburstaddress7moduloFIFOdepthmustequalthetotalnumber
ofRDTRcommandsmoduloFIFOdepthwhenusedinconjunctionwithRDTR.NoREADorWRITEcom‐
mandsareallowedbetweenLDFFandRDTR.
TheEDCholdpatternisdrivenontheEDCpinsduringLDFF(providedRDQSmodeisnotenabled).
A0
A1
A6
A3
A4
A5
A7
A10
A9
A11
BA1
A8
A0
A1
A2
A3
A9
A4
A5
A6
A7
1FIFOSTAGE=1BURST
012 3 456
7
76543210
11110000
11001100
10101010
H
L
BurstPosition
BA2
BA1
BA0
CK
LDFFFIFOLoadPulse
L
LDFFCommand
CK#
Address‐to‐DQMapping
BA3
BA3
DBI0# DBI1# DBI2# DBI3#
EDC0 EDC1 EDC2 EDC3
DQ7 DQ15 DQ23 DQ31
DQ6 DQ14 DQ22 DQ30
DQ5 DQ13 DQ21 DQ29
DQ4 DQ12 DQ20 DQ28
DQ3 DQ11 DQ19 DQ27
DQ2 DQ10 DQ18 DQ26
DQ1 DQ9 DQ17 DQ25
DQ0 DQ8 DQ16 DQ24
Byte0Byte1Byte2Byte3
A2BA0
BA2
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 36
H5GQ1H24AFR
RDTRCommand
ARDTRburstisinitiatedwithaRDTRcommandasshowninFigure19.Nobankorcolumnaddressesare
usedasthedataisreadfromtheinternalREADFIFO,notthearray.Thelengthoftheburstinitiatedwith
aRDTRcommandiseight.ThereisnointerruptionnortruncationofRDTRbursts.
Figure 19:RDTRCommand
ARDTRcommandmayonlybeissuedwhenabankisopenorarefreshisinprogressandbitA2inMR5
issetto0toallowtrainingduringrefresh.
RDBIandRDCRCmustbeenabledtoreadtheDBIandEDCbits,respectively,withtheRDTRcommand.
Ifnotset,theDBI#pinswillremaininODTstate,andtheEDCpinswilldrivetheEDCholdpattern.
IncaseoftheRDQSmode,theEDCpinfunctionslikewithanormalREADinthismode.TheDBI#pin
behaveslikeaDQ,andnoencodingwithDBIisperformed.
AnamountofRDTRcommandsgreaterthantheFIFOdepthisallowedandshallresultinaloopingofthe
FIFO’sdataoutput.TheFIFOdepthfromwhichtheRDTRdataisreadmustbeanumberbetween4‐6and
mustbespecifiedbytheDRAMvendor.TheFIFOdepthisreadviatheVendorIDfunction.
DuringRDTRbursts,thefirstvaliddata‐outelementwillbeavailableaftertheCASlatency(CL).The
latencyisthesameasforREAD.ThedataontheEDCpinscomeswithadditionalCRClatency(tCRCRD)
aftertheCL.
Uponcompletionofaburst,assumingnootherRDTRcommandhasbeeninitiated,allDQandDBI#pins
willdriveavalueofʹ1ʹandtheODTwillbeenabledatamaximumof1tCKlater.Thedrivevalueandter‐
minationvaluemaybedifferentduetoseparatelydefinedcalibrationoffsets.IftheODTisdisabled,the
pinswilldriveHi‐Z.
CS#
WE#
CAS#
RAS#
CKE#
A9(A12)
A1
A8,A10,A11
BA0‐BA3
A2‐A5
LOW
RDTR
CK
CK#
0,1,1
A7,A0,A6
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 37
H5GQ1H24AFR
DatafromanyRDTRburstmaybeconcatenatedwithdatafromasubsequentRDTRcommand.Acontin‐
uousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelementof
acompletedburst.ThenewRDTRcommandshouldbeissuedafterthefirstRDTRcommandaccordingto
thetCCDStiming.
AWRTRcanbeissuedanytimeafteraRDTRcommandaslongasthebusturnaroundtimetRTWismet.
ThetotalnumberofRDTRcommandsmoduloFIFOdepthmustbeequaltototalnumberofWRTRcom‐
mandsmoduloFIFOdepthwhenusedinconjunctionwithWRTR.NoREADorWRITEcommandsare
allowedbetweenWRTRandRDTR.
ThetotalnumberofRDTRcommandsmoduloFIFOdepthmustbeequaltothetotalnumberofLDFF
commandstoburstposition7moduloFIFOdepthwhenusedinconjunctionwithLDFF.NoREADor
WRITEcommandsareallowedbetweenLDFFandRDTR.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 38
H5GQ1H24AFR
3.5.WRITETRAINING
Writetrainingallowsthememorycontrollertofindthedata‐eyecenter(symboltraining)andburstframe
location(frametraining)foreachhigh‐speedinputoftheGDDR5SGRAM.Eachpin(DQ0‐DQ31,DBI0#‐
DBI3#)canbeindividuallytrainedduringthissequence.
ForWriteTrainingthefollowingconditionsmustbetrue:
•atleastonebankisactive,oranautorefreshmustbeinprogressandbitA2inModeRegister5(MR5)issetto0to
allowtrainingduringautorefresh(todisablethisspecialREFenablingoftheWCKclocktreeanACTcommand
mustbeissued,orthedevicemustbesetintopower‐downorselfrefreshmode)
•thePLLmustbelocked,ifenabled.
•WCK2CKtrainingshouldbecomplete
• Readtrainingshouldbecomplete
•RDBIandWDBImustbeenabledpriortoandduringWriteTrainingifthetrainingshallincludetheDBI#pins.
RDCRCandWRCRCmustbeenabledpriortoandduringWriteTrainingifthetrainingshallincludetheEDC
pins.
ThefollowingcommandsareassociatedwithWriteTraining:
•WRTRtowriteaburstofdatadirectlyintotheReadFIFO;
•RDTRtoreadaburstofdatadirectlyoutoftheReadFIFO.
NeitherWRTRnorRDTRaccessthememorycore.NoMRSisrequiredtoenterWriteTraining.
Figure16showsanexampleoftheinternaldatapathsusedwithWRTRandRDTR.Figure21showsatyp‐
icalWritetrainingcommandsequenceusingWRTRandRDTR.Table14listsACtimingparametersasso‐
ciatedwithWRITETraining.
Table 14WRTRandRDTRTimings
PARAMETER SYMBOL
VALUES
UNIT NOTES
MIN MAX
ACTIVEtoWRTRcommanddelay tRCDWTR 10 – ns
ACTIVEtoRDTRcommanddelay tRCDRTR 10 – ns
REFRESHtoRDTRorWRTRcommanddelay tREFTR 10 – ns
RD/WRbankAtoRD/WRbankBcommanddelay
differentbankgroups tCCDS 2–t
CK a
a. tCCDSiseitherforgaplessconsecutiveREADorRDTR(anycombination),gaplessconsecutiveWRITE,orgaplessconsecutive
WRTRcommands.
WRTRtoRDTRcommanddelay tWTRTR WL‐tWLmin – tCK
WRITEtoWRTRcommanddelay tWRWTR WL+CRCWL+2 – tCK
READorRDTRtoWRITEorWRTRcommanddelay tRTW 1–ns
b
b. tRTWisnotadevicelimitbutdeterminedbythesystembusturnaroundtime.ThedifferencebetweentWCK2DQOandtWCK2DQI
shallbeconsideredinthecalculationofthebusturnaroundtime.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 39
H5GQ1H24AFR
WRTRCommand
AWRTRburstisinitiatedwithaWRTRcommandasshowninFigure20.Nobankorcolumnaddresses
areusedasthedataiswrittentotheinternalREADFIFO,notthearray.Thelengthoftheburstinitiated
withaWRTRcommandiseight.ThereisnointerruptionnortruncationofWRTRbursts.
Figure 20:WRTRCommand
AWRTRcommandmayonlybeissuedwhenabankisopenorarefreshisinprogressandbitA2inMR5
issetto0toallowtrainingduringrefresh.
WDBIandWRCRCmustbeenabledtowritetheDBIandEDCbits,respectively,withtheWRTRcom‐
mand.IfWDBIisnotset,a‘1’willbewrittentotheDBIFIFO,anda‘1’willbeassumedfortheDBI#input
intheCRCcalculation.IncontrasttoanormalWRITE,noCRCisreturnedbytheWRTRcommandand
theEDCpinswilldrivetheEDCholdpattern.
IncaseoftheRDQSmode,theEDCpinfunctionslikewithanormalREADinthismode.Pleasenotethat
RDCRCmustbeenabledtoreadthecalculatedCRCdatawiththeRDTRcommand.
AnamountofWRTRcommandsequaltotheFIFOdepthisrequiredtofullyloadtheFIFO;anynumberof
WRTRcommandsgreaterthantheFIFOdepthisallowedandshallresultinaloopingoftheFIFO’sdata
input.TheFIFOdepthtowhichtheWRTRdataiswrittenmustbe6.TheFIFOdepthisreadviatheVen‐
dorIDfunction.
DuringWRTRbursts,thefirstvaliddata‐inelementmustbeavailableattheinputlatchaftertheWrite
Latency(WL).TheWriteLatencyisthesameasforWRITE.
Uponcompletionofaburst,assumingnootherWRTRdataisexpectedonthebustheGDDR5SGRAM
DQandDBI#pinswillbedrivenaccordingtotheODTstate.Anyadditionalinputdatawillbeignored.
WRTR
CS#
WE#
CAS#
RAS#
CKE# LOW
CK
CK#
A9(A12)
A1
A8,A10,A11
BA0‐BA3
A2‐A5
0,1,1
A7,A0,A6
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Rev. 1.0 /Nov. 2009 40
H5GQ1H24AFR
DatafromanyWRTRburstmaybeconcatenatedwithdatafromasubsequentWRTRcommand.Acontin‐
uousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelementof
acompletedburst.ThenewWRTRcommandshouldbeissuedafterthepreviousWRTRcommand
accordingtothetCCDStiming.
ARDTRcanbeissuedanytimeafteraWRTRcommandaslongastheinternalbusturnaroundtime
tRTWTRismet.
ThetotalnumberofWRTRcommandsmoduloFIFOdepthmustequalthetotalnumberofRDTRcom‐
mandsmoduloFIFOdepthwhenusedinconjunctionwithRDTR.NoREADorWRITEcommandsare
allowedbetweenWRTRandRDTR.
Figure 21:WriteTrainingusingWRTRandRDTRCommands
CK#
CK
CMD
WLmrs
DQ
NOPWRTR
1.WLmrs,CLmrsandCRCRLsetto1foreaseofillustration;checkModeRegisterdefinitionforsupportedsettings
WRTR
ADDR
T0 T1 T2 T3 T4 T5 Ta Ta+1 Ta+2 Ta+3 Ta+4
NOP NOP NOP RDTR NOP RDTR NOP NOP
WCK
WCK#
D0
D1
D2
D3
D4
D5
D6
D7
EDC
D0
D1
D2
D3
D4
D5
D6
D7
EDCHoldEDCHoldEDCHoldEDCHold EDCHoldEDCHoldEDCHold EDCHold
DonʹtCare
WLmrs
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D0
D1
CLmrs CRCRL CLmrs CRCRL
tWTRTR
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 41
H5GQ1H24AFR
4.MODEREGISTERS
GDDR5 specifies 10 Mode Registers to define the specific mode of operation. MR0 to MR7 and MR15 are defined as shown in
the overview in Figure 22. MR8 to MR13 are not def ined an d may be use d by DRAM vendor s for ve ndor sp ecif ic fe atur es. Repr o-
gramming the Mode Registers will not alter the contents of the memory array.
All Mode Register s are progr ammed vi a the MODE REGIS TER SET (MRS) command and will ret ain t he st ored inform atio n unti l
they are reprogrammed or the device loses power. Mode Registers must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these
requirements will result in unspecified operation.
No default states are defined for Mode Registers except when otherwise noted. Users therefore must fully initialize all Mode Reg-
isters to the desired values e.g. upon power-up.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are
reserved for fut ure use and must be pro grammed to 0. Bit A12 i s not used for any mode re gist er pro gramming as this ad dress input
is not defined for 1G density.
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
MR0 00000WriteRecovery(WR) TM CASLatency(CLmrs) WriteLatency
(WLmrs)
MR1 00010
PLL
Reset ABI WDBI RDBI PLL Cal
Upd ADR/CMD
Termination Data
Termination Driver
Strength
MR2 00100 ADR/CMD
TerminationOffset
DataandWCK
TerminationOffset
OCDPullup
DriverOffset
OCDPulldown
DriverOffset
MR3 00110 Bank
Groups WCK
Termination Info RDQS
Mode WCK
2CK WCK
23Inv WCK
01Inv SelfRefresh
MR4 01000
EDC
13Inv WR
CRC RD
CRC
CRCRead
Latency
(CRCRL)
CRCWriteLatency
(CRCWL) EDCHoldPattern
MR5 01010 RFU PLLBandwidth
(PLLBW) LP3 LP2 RFU
MR6 01100 VREFDOffset
Upper2bytes
VREFDOffset
Lower2bytes
VREFD Auto
VREFD
VREFD
Merge
WCK
PIN
MR7 01110 DCC RFU
Half
VREFD
Temp
Sense DQ
PreA Auto
Sync LF
Mode RFU
MR14 RFU
MR15 11110RFUADT
MRE
MF1 MRE
MF0 XXXXXXXX
Figure 22. Mode Registers Overview
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 42
H5GQ1H24AFR
4.1.MODEREGISTER0(MR0)
ModeRegister0controlsoperatingmodessuchasWriteLatency,CASlatency,WriteRecoveryandTest
ModeasshowninFigure23.
TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=0,BA1=0,BA2=0
andBA3=0.
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00000 WriteRecovery(WR) TM CASLatency(CLmrs) WriteLatency
(WLmrs)
A11 A10 A9 A8 WriteRecovery
(WR)
0000 4
0001 5
0010 6
0011 7
0100 8
0101 9
0110 10
0111 11
1000 12
1001 13
1010 14
1011 15
1100 16
1101 17
1110 18
1111 19
A7 TestMode
0Normal
1TestMode
A2 A1 A0 WriteLatency
(WLmrs)
000 RFU
001 1
010 2
011 3
100 4
101 5
110 6
111 7
A6 A5 A4 A3 CASLatency(CLmrs)
0000 5
0001 6
0010 7
0011 8
0100 9
0101 10
0110 11
0111 12
1000 13
1001 14
1010 15
1011 16
1100 17
1101 18
1110 19
1111 20
Figure 23. Mode Register 0 (MR0) Definition
Rev. 1.0 /Nov. 2009 43
H5GQ1H24AFR
WRITELatency(WLmrs)
TheWRITElatency(WLmrs)isthedelayinclockcyclesusedinthecalculationofthetotalWRITElatency
(WL)betweentheregistrationofaWRITEcommandandtheavailabilityofthefirstpieceofinputdata.
DRAMvendorspecificationsshouldbecheckedforvalue(s)ofWLmrssupported.ThefullWRITElatency
definitioncanbefoundinthesectionentitledOPERATION.
WhentheWRITElatenciesaresettosmallvalues(i.e.1,2,...clocks),theinputreceiversneverturnoff,in
turn,raisingtheoperatingpower.WhentheWRITElatencyissettohighervalues(i.e...6,7clocks)theinput
receiversturnonwhentheWRITEcommandisregistered.Refertovendordatasheetsforvalue(s)of
WLmrswheretheinputreceiversarealwaysonoronlyturnonwhentheWRITEcommandisregistered
Speed AllowableOperatingFrequency(Gbps)
WL7 WL6 WL5 WL4 WL3 WL2 WL1
6.0Gbps
5.5Gbps
5.0Gbps
4.5Gbps
4.0Gbps
CASLatency(CLmrs)
TheCASlatency(CLmrs)isthedelayinclockcyclesusedinthecalculationofthetotalREADlatency
(CL)betweentheregistrationofaREADcommandandtheavailabilityofthefirstpieceofoutputdata.
BydefaultCLmrsisspecifiedbybitsA3‐A6,definingaCLmrsrangeof5to20tCK.
DRAMvendorspecificationsshouldbecheckedforvalue(s)ofCLmrssupported.ThefullREADlatency
definitioncanbefoundinthesectionentitledOPERATION
Speed RDBI
ON/OFF
AllowableOperatingFrequency(Gbps)
CL20 CL19 CL18 CL17 CL16 CL15 CL14 CL13 CL12
6.0Gbps OFF
ON
5.5Gbps OFF
ON
5.0Gbps OFF
ON
4.5Gbps OFF
ON
4.0Gbps OFF
ON
Rev. 1.0 /Nov. 2009 44
H5GQ1H24AFR
WRITERecovery(WR)
TheprogrammedWRvalueisusedfortheautoprechargefeaturealongwithtRPtodeterminetDAL.The
WRregisterbitsarenotarequiredfunctionandmaybeimplementedatthediscretionoftheDRAM
manufacturer.
WRmustbeprogrammedwithavaluegreaterthanorequaltoRU{tWR/tCK},whereRUstandsforround
up,tWRistheanalogvaluefromthevendordatasheetandtCKistheoperatingclockcycletime.
BydefaultWRisspecifiedbybitsA8‐A11,definingaWRrangeof4to19tCK.
TestMode
ThenormaloperatingmodeisselectedbyissuingaMODEREGISTERSETcommandwithbitA7setto
’0’,andbitsA0‐A6andA8‐A11settothedesiredvalues.ProgrammingbitA7to‘1’placesthedeviceintoa
testmodethatisonlytobeusedbytheDRAMmanufacturer.Nofunctionaloperationisspecifiedwithtest
modeenabled.
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 45
H5GQ1H24AFR
4.2.MODEREGISTER1(MR1)
ModeRegister1controlsfunctionslikedrivestrength,datatermination,address/commandtermination,
ReadDBI,WriteDBI,ABI,controlofcalibrationupdatesandPLLasshowninFigure24.
TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=1,BA1=0,BA2=0
andBA3=0.BitsA0‐A1,A4‐A6andA10ofthisregisterareinitializedwith’0’s.
Figure 24. Mode Register 1 (MR1) Definition
ImpedanceAutocalibrationofOutputBufferandActiveTerminator
GDDR5SGRAMsofferautocalibratingimpedanceoutputbuffersandon‐dieterminations.Thisenablesa
usertomatchthedriverimpedanceandterminationstothesystemwithinagivenrange.Toadjustthe
impedance,anexternalprecisionresistorisconnectedbetweentheZQpinandVSSQ.Anominalresistor
A1 A0 DriverStrength
00
AutoCalibrationOn
01 RFU
10Nominal(60/40)
11 RFU
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00010
PLL
Reset ABI WDBI RDBI PLL Cal
Upd ADR/CMD
Termination Data
Termination Driver
Strength
A3 A2 DataTermination
00 Disabled
01 ZQ/2
10 ZQ
11 RFU
A5 A4 ADD/CMDTermination
00CKE#valueatReset
01 ZQ/2
10 ZQ
11 Disabled
A7 PLL
0Off
1On
A11 PLLReset
0No
1Yes
A9 WriteDBI
0On
1Off
A10 ABI
0On
1Off
A8 ReadDBI
0On
1Off
A6 CalibrationUpdate
0On
1Off
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Rev. 1.0 /Nov. 2009 46
H5GQ1H24AFR
valueof120Ohmsisequivalenttothe40OhmsPulldownand60OhmsPullupnominalimpedancesof
GDDR5SGRAMs.RESET#,CKandCK#arenotinternallyterminated.CKandCK#shallbeterminatedon
thesystemusingexternal1%resistorstoVDDQ.
Theoutputdriverandon‐dieterminationimpedancesareupdatedduringallREFRESHcommandsto
compensateforvariationsinsupplyvoltageandtemperature.Theimpedanceupdatesaretransparentto
thesystem.
DriverStrength
BitsA0andA1definethedriverstrength.TheAutoCalibrationsettingenablestheAuto‐Calibration
functionalityforthePulldown,PullupandTerminationoverprocess,temperatureandvoltagechanges.
Thedesigntargetforthefactorysettingis40OhmPulldown,60OhmPullupdriverstrengthwithnominal
process,voltageandtemperatureconditions.
ThenominaloptionenablesthefactorysettingforthePulldown,Pullupdriverstrengthandtermination.
Withthisoptionenabled,driverstrengthandterminationareexpectedtochangewithprocess,voltage
andtemperature.ACtimingsareonlyguaranteedwithAutoCalibration.
DataTermination
BitsA2andA3definethedataterminationvaluefortheon‐dietermination(ODT)fortheDQandDBI#
pinsincombinationwiththedriverstrengthsetting.
TheterminationcanbesettoavalueofZQ/2whichisintendedforasingleloadedsystem,orZQwhich
isintendedforaweakerterminationusedinalowerpowerorfrequencyapplications.Thedata
terminationmayalsobeturnedoff.
ADR/CMDTermination
BitsA4andA5definetheaddress/commandtermination.Thedefaultsetting(’00’)providesthatthe
address/commandterminationisdeterminedbylatchingCKE#ontherisingedgeofRESET#.
Theaddress/commandterminationcanalsobesettoavalueofZQ/2whichisintendedforasingle
loadedsystem,orZQwhichisintendedfordoubleloadedconfigurationswithtwodevicessharinga
commonaddress/commandbus.Theaddress/commandterminationmayalsobeturnedoff.
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 47
H5GQ1H24AFR
CalibrationUpdate
TheCalibrationUpdatesettingenablesthecalibrationvaluetobeupdatedautomaticallybytheauto
calibrationengine.Thefunctionisenableduponpower‐uptoreduceupdateinducedjitter.Theusermay
decidetosuppressupdatesfromtheautocalibrationenginebydisablingCalibrationUpdate(A6=1).
ThecalibrationupdatescanoccurwithanyREFRESHcommand.Theupdateisnotcompleteforatime
tKOafterthelatchingoftheREFRESHcommand.DuringthistKOtime,onlyNOPorDESELECT
commandsmaybeissued
PLLandPLLReset
IfaPLListobeused,itmustbeenabledfornormaloperationbysettingbitA7to’1’.
APLLresetisdonebyturningthePLLoffthenon,orbyuseofthePLLResetbitA11.ThePLLResetbit
isselfclearingmeaningthatitreturnsbacktothevalue‘0’afterthePLLresetfunctionhasbeenissued.
RDBIandWDBI
BitA8controlsDataBusInversion(DBI)forREADs(RDBI),andbitA9controlsDataBusInversionfor
WRITEs(WDBI).FormoredetailsonDBIseeREADandWRITEDataBusInversion(DBI)inthesection
entitledOPERATION.
ABI
AddressBusInversion(ABI)isselectedindependentlyfromDBIusingbitA10.Whenenabledanydata
sentovertheaddressbus(whetheropcode,addresses,LDFFdataorDM)isinvertedornotinvertedbased
onthestateofABI#signal.FormoredetailsonABIseeAddressBusInversion(ABI)inthesectionentitled
OPERATION.
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Rev. 1.0 /Nov. 2009 48
H5GQ1H24AFR
4.3.MODEREGISTER2(MR2)
ModeRegister2definestheoutputdriver(OCD)andterminationoffsetsasshowninFigure25.
ModeRegister2isprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=0,BA1=1,
BA2=0andBA3=0.
Figure 25. Mode Register 2 (MR2) Definition
ImpedanceOffsets
ThedriverandterminationimpedancesmaybeoffsetindividuallyforPDdriver,PUdriver,DQ/DBI#/
WCKterminationandaddress/commandtermination.Theoffsetimpedancestepvaluesmaybenon‐
linearandwillvaryacrossPVT.WithnegativeoffsetstepsthedrivestrengthswillbedecreasedandRon
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00100 ADR/CMD
TerminationOffset DataandWCK
TerminationOffset OCDPullup
DriverOffset OCDPulldown
DriverOffset
A2 A1 A0 OCDPulldown
DriverOffset
000 0
001 +1
010 +2
011 +3
100 ‐4
101 ‐3
110 ‐2
111 ‐1
A5 A4 A3 OCDPullup
DriverOffset
000 0
001 +1
010 +2
011 +3
100 ‐4
101 ‐3
110 ‐2
111 ‐1
A8 A7 A6 DataandWCK
TerminationOffset
000 0
001 +1
010 +2
011 +3
100 ‐4
101 ‐3
110 ‐2
111 ‐1
A11 A10 A9 ADR/CMD
TerminationOffset
000 0
001 +1
010 +2
011 +3
100 ‐4
101 ‐3
110 ‐2
111 ‐1
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Rev. 1.0 /Nov. 2009 49
H5GQ1H24AFR
willbeincreased.WithpositiveoffsetstepsthedrivestrengthswillbeincreasedandRonwillbe
decreased.Withnegativeoffsetstepsthetermin‐ationvaluewillbeincreased.Withpositiveoffsetsteps
theterminationvaluewillbedecreased.
IVcurvesandACtimingsareonlyguaranteedwithzerooffset.
Figure 26. Impedance Offsets
Calibration
Engine
120
Ohms
VSSQ
ZQ
Pullup
Impedance
Pulldown
Impedance
Offset
PUDriver
Offset
PDDriver
ADD/CMD
Termination
Impedance
Offset
ADD/CMDTermination
DQ/DBI#/WCK
Termination
Impedance
Offset
DQ/DBI#/WCKTermination
Autocalibrated
Impedance
Note:sumofoffset+auto‐
calibratedimpedancecannot
exceedmaximum/minimum
availableimpedancesteps
FixedImpedance
nominal(60/40)
Auto/Fixed
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Rev. 1.0 /Nov. 2009 50
H5GQ1H24AFR
4.4.MODEREGISTER3(MR3)
ModeRegister3controlsfunctionsincludingBankGroups,WCKtermination,selfrefresh,RDQSmode,
DRAMInfoandWCK2CKtrainingasshowninFigure27.
ModeRegister3isprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=1,BA1=1,
BA2=0andBA3=0.
Figure 27. Mode Register 3 (MR3) Definition
SelfRefresh
Therefreshintervalinselfrefreshmodemaybesetto32ms,16msand8ms.
WCK2CK
BitA4(WCK2CK)enablesanddisablestheWCK2CKalignmenttraining.Fordetailsonthistraining
sequence,seethesectiononTRAINING.
A1 A0 SelfRefresh
00 32ms
0 1 16ms
10 8ms
11 RFU
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00110 Bank
Groups WCK
Termination Info RDQS
ModeWCK
2CK WCK
23Inv WCK
01Inv SelfRefresh
A9 A8 WCKTermination
00 Disabled
01 ZQ/2
10 ZQ
11 RFU
A4 WCK2CKTraining
0Off
1On
A3 WCK23Invert
0Off
1On
A2 WCK01Invert
0Off
1On
A7 A6 DRAMInfo
00 off
01 VendorID
1 0 TemperatureReadout
11 RFU
A5 RDQS
Mode
0Off
1On
A11 A10 BankGroups
0X
off/tCCDL=2tCK
1X
on/tCCDL=3tCK
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Rev. 1.0 /Nov. 2009 51
H5GQ1H24AFR
WCK01/WCK23Inversion
BitsA2andA3controlwhethertheinternalphaseoftheWCK01andWCK23clockinputsafterinternal
divide‐by‐2shallbeinverted,correspondingtoa2U.I.phaseshift.Thebitsareusedinconjunctionwith
WCK2CKtrainingmode.
RDQSMode
BitA5enablestheRDQSmodeoftheGDDR5SGRAM.InthismodetheEDCpinswillactasaREAD
strobe(RDQS).NoCRCissupportedinRDQSmode,andallrelatedbitsinMR4willbeignored.A
detaileddescriptionoftheRDQSmodecanbefoundinthesectionentitledOPERATION.
DRAMInfo
BitsA6andA7enabletheDRAMInfomodewhichisprovidedtooutputtheVendorID,orthecurrent
junctiontemperature.
TheVendorIDidentifiesthemanufactureroftheGDDR5SGRAM,andprovidesthedierevision,
memorydensityandFIFOdepth.
TheTemperatureReadoutprovidestheSGRAM’sjunctiontemperature.Theon‐chiptemperaturesensor
isenabledinadvancebybitA6inMR7.
WCKTermination
BitsA8andA9definetheterminationvaluefortheon‐dietermination(ODT)fortheWCK01,WCK01#,
WCK23andWCK23#pinsincombinationwiththedriverstrengthsetting.
TheterminationcanbesettoavalueofZQ/2whichisintendedforasingleloadedsystem,orZQwhich
isintendedfordoubleloadconfigurationswithtwodevicessharingtheWCKclocks.TheWCK
terminationmayalsobeturnedoff.
BankGroups
BitA11enablesthebankgroupsfeature.WithA11setto‘1’,thebankgroupsfeatureisenabledand
tCCDLis3tCK.
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Rev. 1.0 /Nov. 2009 52
H5GQ1H24AFR
4.5.MODEREGISTER4(MR4)
ModeRegister4definestheErrorDetectionCode(EDC)featuresofGDDR5SGRAMsasshownin
Figure28.
TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=0,BA1=0,BA2=1
andBA3=0.BitsA0‐A3(EDCHoldPattern)ofthisregisterareinitializedwith’1111’.
Figure 28. Mode Register 4 (MR4) Definition
EDCHoldpattern/EDC13Invert
The4‐bitEDCholdpatternisconsideredabackgroundpatterntransmittedontheEDCpins.Theregister
isinitializedwithall’1’s.Thepatternisshiftedfromrighttoleftandrepeatedwitheveryclockcycle.The
outputtimingisthesameasofaREADburst.
CRCburstscalculatedfromWRITEsorREADswillreplacetheEDCholdpatternforthedurationof
thosebursts,providedCRCisenabledforthosebursts.
WitheachMRScommandtoMR4thatchangesbitsA0‐A3orA9‐A11,theEDCholdpatternwillbe
undefinedfortMRD.
A3 A2 A1 A0 EDCHoldPattern
0000 Pattern
...
1111 Pattern
Burst
Pos3Burst
Pos2Burst
Pos1Burst
Pos0
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01000
EDC
13Inv WR
CRC RD
CRC
CRCRead
Latency
(CRCRL)
CRCWriteLatency
(CRCWL) EDCHoldPattern
A6 A5 A4 CRCWriteLatency(CRCWL)
000 N/A
001 8
010 9
011 10
100 11
101 12
110 13
111 14
A8 A7 CRCReadLatency(CRCRL)
00 0
01 1
10 2
11 3
A10 WRCRC
0On
1Off
A9 RDCRC
0On
1Off
A11 EDCHoldPatternInvert
forEDC1+EDC3
0EDCholdpatternnot
inverted
1EDCholdpatterninverted
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Rev. 1.0 /Nov. 2009 53
H5GQ1H24AFR
TheEDCholdpatternwillnotbetransmittedwhenthedeviceisinaddresstrainingmode,inWCK2CK
trainingmode,inRDQSmode,inselfrefreshmode,inresetstate,inpower‐downstatewiththeLP2bit
set,orinscanmode.
WithregisterbitA11setHigh,EDC1andEDC3willtransmittheinvertedEDCholdpattern,resultingin
apseudo‐differentialpattern.Pleasenotethatthisfunctionisnotavailableinx16configuration.BitA11is
ignoredforREAD,WRITEandRDTRCRCburstsandtheclockphaseinformationinWCK2CKtraining
mode.
CRCWriteLatency(CRCWL)
ThevalueoftheCRCwritelatencyisloadedintoregisterbitsA4‐A6.IftheDRAMvendordoesnot
supporttheModeRegisterdefinitionofCRCWL,theModeRegistersettingswillbeignored.Inthatcase
thevalidfixedlatencyisgivenwiththeDRAMvendor’sspecification.TheusermustsettheCRCWL
ModeRegisterbits.
Speed AllowableOperatingFrequency(Gbps)
CRCWL14 CRCWL13 CRCWL12 CRCWL11 CRCWL10 CRCWL9 CRCWL8
6.0Gbps
5.5Gbps
5.0Gbps
4.5Gbps
4.0Gbps
CRCReadLatency(CRCRL)
ThevalueoftheCRCreadlatencyisloadedintoregisterbitsA7‐A8.IftheDRAMvendordoesnotsupport
theModeRegisterdefinitionofCRCRL,theModeRegistersettingswillbeignored.Inthatcasethevalid
fixedlatencyisgivenwiththeDRAMvendor’sspecification.TheusermustsettheCRCRLModeRegister
bits.
Speed RDBI
ON/OFF
AllowableOperatingFrequency(Gbps)
CRCRL3 CRCRL2 CRCRL1 CRCRL0
6.0Gbps OFF
ON
5.5Gbps OFF
ON
5.0Gbps OFF
ON
4.5Gbps OFF
ON
4.0Gbps OFF
ON
Rev. 1.0 /Nov. 2009 54
H5GQ1H24AFR
ReadCRC
BitA9controlstheCRCcalculationforREADbursts.Whenenabled,thecalculatedCRCpatternwillbe
transmittedontheEDCpinswiththelatencyasprogrammedintheCRCRLfieldofthisregister.With
ReadCRCbeingoff,noCRCwillbecalculatedforREADbursts,andtheEDCholdpatternwillbe
transmittedinstead.
WriteCRC
BitA10controlstheCRCcalculationforWRITEbursts.Whenenabled,thecalculatedCRCpatternwillbe
transmittedontheEDCpinswiththelatencyasprogrammedintheCRCWLfieldofthisregister.With
WriteCRCbeingoff,noCRCwillbecalculatedforWRITEbursts,andtheEDCholdpatternwillbetrans‐
mittedinstead.
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Rev. 1.0 /Nov. 2009 55
H5GQ1H24AFR
4.6.MODEREGISTER5(MR5)
ModeRegister5definesdigitalRAS,PLLband‐widthandlowpowermodesasshowninFigure29.
TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=1,BA1=0,BA2=1
andBA3=0.
Figure 29. Mode Register 5 (MR5) Definition
A1 LP2
0Off
1On
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01010 RFU PLLBandwidth LP3 LP2 RFU
A5 A4 A3 ‐3dB[MHz]
BW3dBLL
Peak[MHz]
BWPKLL
Peak[dB]
PKLL
000 13 2 ＜1.2
001 18 4 ＜1.1
010 22 5 ＜1.1
011 28 7 ＜1.2
100 36 10 ＜1.2
101 44 13 ＜1.2
110 54 15 ＜1.7
111 69 20 ＜1.5
A2 LP3
0Off
1On
Note 1) PLL BW characteristics is extracted at 4Gbps
Note 2) PLL BW is linearly proportional to the data rate
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Rev. 1.0 /Nov. 2009 56
H5GQ1H24AFR
LowPowerModes(LP2,LP3)
BitsA1‐A2controlseverallowpowermodesoftheGDDR5SGRAM.Themodesareindependentofeach
other.
WhenbitA1(LP2)isset,theWCKreceiversmaybeturnedoffduringpower‐down.
WhenbitA2(LP3)isset,RDTR,WRTRandLDFFcommandsarenotallowedwhileaREFcommandis
beingexecuted.
PLL Bandwidth
ThePLLbandwidthmayoptionallybeconfiguredtomatchsystemcharacteristics.Eachsettingdefinesa
uniquecombinationof‐3dBcornerfrequency,peakingfrequencyandpeakingmagnitude.
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Rev. 1.0 /Nov. 2009 57
H5GQ1H24AFR
4.7.MODEREGISTER6(MR6)
ModeRegister6controlstheWCK2CKalignmentpointanddefinesVREFDrelatedfeaturessuchas
source,level,offsets,VREFDMergeandVREFDAutoCalibrationmode,asshowninFigure30.
TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=0,BA1=1,BA2=1
andBA3=0.
Figure 30. Mode Register 6 (MR6) Definition
WCK2CKAlignmentPoint(WCKPIN)
BitA0definesthepositionofthealignmentpointbetweenCKandWCK.Whensetto‘0‘,thealignment
pointwillbeatthephasedetectorinsidetheGDDR5SGRAM.Whensetto‘1‘,thealignmentpointwillbe
attheCKandWCKpins.
InputReferenceVoltageforDQandDBI#Pins
GDDR5SGRAMsoffermultipleoptionsfortheinputreferencevoltage(Vref)fortheDQandDBI#pins,
asshowninFigure31.
A11 A10 A9 A8 VREFD
Offset
0000 0/
default
0001 +1
0010 +2
0011 +3
0100 +4
0101 +5
0110 +6
0111 +7
1000
0/Auto
(opt.)
1001 ‐7
1010 ‐6
1011 ‐5
1100 ‐4
1101 ‐3
1110 ‐2
1111 ‐1
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01100 VREFDOffset
BytesinrowsA‐FVREFDOffset
BytesinrowsM‐U
VREFD Auto
VREFDVREFD
Merge WCK
PIN
A3 VREFD
0externalVREFDpins
1 internallygenerated
A1 VREFDMerge
0Off
1On
A7 A6 A5 A4 VREFD
Offset
0000 0/
default
0001 +1
0010 +2
0011 +3
0100 +4
0101 +5
0110 +6
0111 +7
1000
0/Auto
(opt.)
1001 ‐7
1010 ‐6
1011 ‐5
1100 ‐4
1101 ‐3
1110 ‐2
1111 ‐1
A0 WCK2CK
AlignmentPt.
0PDinside
DRAM
1PDatpins
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Rev. 1.0 /Nov. 2009 58
H5GQ1H24AFR
SeparateVrefcircuitsareassociatedwiththebytesinrowsAtoFandthebytesinrowsMtoU,with
separateVREFDpinsfortherequiredexternalVref.
TheonlymandatorymodeisthatVrefwillbesuppliedexternallyattheVREFDpins.Thismodeis
configuredwithbitsA1‐A3andbitA7inMR7allsetto’0’.
Figure 31. VREFD Options
VREFDMerge
TheVREFDMergemodeisenabledwhenbitA1issetto’1’.TheexternallysuppliedVFREDandthe
internallygeneratedVrefwillbemerged,resultingintheaveragevalueofboth.DRAMvendor
specificationsshouldbecheckedforvaluesofexternalresistorsthatmaybeconnectedtoVREFDpinsin
thisVREFMergemode.
AutoVREFDTraining
WhenAutoissetforVREFDoffsets,theinternalVrefgeneratormustbetrained.BitA2enablesthis
training;thebitisself‐clearing,meaningthatitreturnsbacktothevalue‘0’afterthetraininghas
completed.
Oncethetrainingmodeisenabled,theGDDR5SGRAMdrivestheEDCpinsLowtoindicatetothe
controllerthatthetraininghasstarted.ThecontrollerisnowexpectedtosendthespecifiedPRBSpattern
totheGDDR5SGRAM.Uponcompletionofthetraining,theGDDR5SGRAMstopsdrivingtheEDCpins
Low,andtheEDCpinswillresumetransmittingtheEDCholdpattern.
But,itisnotsupported.
VREFD
BitA3selectsbetweenexternalandinternalVref.Thebitis“Don’tCare”whenVREFMergemodeis
selected.
VREFDOffsetsandVREFDAutoMode
ItsupportsthecapabilitytooffsetVrefindependentlyfortheupper2bytesandthelower2bytes.The
offsetstepvaluesmaybenon‐linearandwillvaryacrossPVT.
VREFD
0.5*VDDQ(opt.)
0.7*VDDQ(opt.)
VREFD
Merge
(opt.)
+
+
‐
Receiver
DQ/DBI#
+
VREFDOffsets
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Rev. 1.0 /Nov. 2009 59
H5GQ1H24AFR
ThevendorsmayoptionallysupporttheoffsetcapabilitytobeappliedtotheexternalVref(notshownin
Figure31).
TheoptionalAutosettingforVREFDenablestheGDDR5SGRAMtosearchforitsownoptimalinternal
Vref.Thereisnooffsetfromthisinternallydeterminedvalue(seealsoAutoVREFDTraining).
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 60
H5GQ1H24AFR
4.8.MODEREGISTER7(MR7)
ModeRegister7controlsfeatureslikePLLStandby,PLLFast‐Lock,PLLDelayCompensation,Low
Frequencymode,AutoSynchronization,DataPreamble,TemperatureSensoroperation,HalfVREFD,
VDDRangeandDCCasshowninFigure32.
TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=1,BA1=1,BA2=1
andBA3=0.
Figure 32. Mode Register 7 (MR7) Definition
LowFrequencyMode
WhenLowFrequencyModeisenabledbybitA3,thepowerconsumptionofinputreceiversandclock
treesisreduced.Themaximumoperatingfrequencyforthislowfrequencymodeisgiveninthevendor‘s
datasheet.
WCK2CKAutoSynchronization
GDDR5SGRAMssupportaWCK2CKautomaticsynchronizationmodethateliminatestheneedfor
WCK2CKtraininguponpower‐downexitorforreducingWCK2CKtrainingtimeatlowfrequency.This
modeiscontrolledbybitA4.ForadetaileddescriptionseeWCK2CKAutoSynchronizationinthesection
entitledWCK2CKTraining.
A11 A10 DCC
00 noDCC/
DCCofforhold/opt.
01 DCCstart
10 DCCresetl
11 RFU
A3 LowFrequencyMode
0Off
1On
A4 WCK2CKAutoSync
0Off
1On
A5 DataPreamble
0Off
1On
A6 Tempe ratureSensor
0Off
1On
A7 HalfVFRED
00.7*VDDQ
10.5*VDDQ
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01110 DCC RFU
Half
VREFD
Temp
Sense DQ
PreA Auto
Sync LF
Mode RFU
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Rev. 1.0 /Nov. 2009 61
H5GQ1H24AFR
DataPreamble
WhenenabledbybitA5,non‐gaplessREADburstswillbeprecededbyafixeddatapreambleontheDQ
andDBI#pinsof4U.I.duration.TheprogrammedREADlatencydoesnotchangewhentheData
Preambleisenabled.ThepatternisnotencodedwithRDBI,however,ifRDBIisdisabled,theDBI#pins
willnottoggleanddriveaHIGH.
TemperatureSensor
Theon‐chiptemperaturesensorisenabledbybitA6.
AdetaileddescriptionoftheTemperatureSensorcanbefoundintheVENDORID,TEMPSENSORand
SCANsection.
HalfVREFD
ThismodeallowsuserstoadjusttheVreflevelincasetheGDDR5SGRAMisoperatedwithout
termination:whenbitA7issetto’1’,aVreflevelofnominally0.5*VDDQisexpectedattheVREFDpinor
beinggeneratedinternally(seeFigure31).
DutyCycleCorrection(DCC)
BitsA10andA11controltheoperationofthedutycyclecorrector(DCC).TheDCCcanbeusedtocancel
outastaticdutycycleerrorontheWCKclocks.FormoredetailsseeDutyCycleCorrection(DCC)inthe
sectionentitledOPERATION.
VREFDSelectionOptionsSummary
ThefollowingtablesummarizesthecompletesetofVREFDselectionoptions.
Table 15VREFDSelectionOptions
MR6 MR7
Description
A3
InternalVREFD
A7
HalfVREFD
00 External
01 External
10 Internal0.7*VDDQ
11 Internal0.5*VDDQ
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Rev. 1.0 /Nov. 2009 62
H5GQ1H24AFR
4.9.MODEREGISTER15(MR15)
ModeRegister15controlsaddresstrainingmode(ADT)andaccesstoModeRegisters0to14(MRE)as
showninFigure33.
TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=1,BA1=1,BA2=1
andBA3=1.
ModeRegister15isaspecialregisterthatoperatesinSDRaddressingmode.Increasedsetupandhold
timesasforcommandinputsareassumedtoensuretheMRScommandtothisregisterissuccessfulwhile
addresstraining(ADT)hasnottakenplaceandtheintegrityofDDRaddressesmaynotbeguaranteed.
ThisisindicatedbysettingbitsA0‐A7toDon’tCare(“X”)whicharepairedwiththeusablebits(A8‐A11)
andtheModeRegisteraddress(BA0‐BA3).
Figure 33. Mode Register 15 (MR15) Definition
AddressTraining(ADT)
AddresstrainingmodeisenabledanddisabledwithbitA10.
ModeRegister0‐14Enable
WhendisabledbybitA8(forSGRAMsconfiguredtoMF=0)orbitA9(forSGRAMsconfiguredtoMF=1),
theGDDR5SGRAMwillignoreanyMODEREGISTERSETcommandtoModeRegisters0to14.If
enabled,MODEREGISTERSETcommandsfunctionasnormal.MODEREGISTERSETcommandsto
ModeRegister15(thisregister)arenotaffectedandwillalwaysbeexecuted.
ThisfunctionalallowsforindividualconfigurationoftwoGDDR5SGRAMSonacommonaddressbus
withouttheuseofaCS#pin.
A9 MR0‐14EnableMF=1
0Enabled
1 Disabled
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
11110RFUADT
MRE
MF1
MRE
MF0 XXXXXXXX
A10 AddressTraining(ADT)
0Off
1On
A8 MR0‐14EnableMF=0
0Enabled
1 Disabled
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Rev. 1.0 /Nov. 2009 63
H5GQ1H24AFR
5.OPERATION
5.1.COMMANDS
Notes:
1)H=LogicHighLevel;L=LogicLowLevel;X=Don’tcare:signalmaybeHorL,butnotfloating
2)Addressesshownarelogicaladdresses;physicaladdressesareinvertedwhenaddressbusinversion(ABI)isactivatedandABI#=L
3)BA0‐BA3providetheModeRegisteraddress(MRA),A0‐A11theopcodetobeloaded
4)BA0‐BA3providethebankaddress(BA),A0‐A11(A12)providetherowaddress(RA).
5)BA0‐BA3providethebankaddress,A0‐A5(A6)providethecolumnaddress(CA);nosub‐wordaddressingwithinaburstof8.
6)ThecommandisRefreshwhenCKE#(n)=LandSelfRefreshEntrywhenCKE#(n)=H.
7)BA0‐BA3andCAareusedtoselectburstlocationanddatarespectively
8)DESELECTandNOParefunctionallyinterchangeable
9)InaddresstrainingmodeREADisdecodedfromthecommandspinsonlywithRAS#=H,CAS#=L,WE#=H
Table 16TruthTable‐Commands
Operation
Symbol
CKE#
CS# RAS# CAS# WE# BA A11 A10 A8
A6,
A7,
A9,
(A12)
A0‐
A5
(A6) Notes
Previous
cycle Current
cycle
DESELECT(NOP) DES L X HX X XXXXX X X1,2,8
NOOPERATION(NOP) NOP L X LHHHXXXX X X1,2,8
MODEREGISTERSET MRS L L L L L L MRA Opcode 1,2,3
ACTIVE(Selectbank&
activaterow)
ACT L L L L H H BA RA 1,2,4
READ(Selectbankand
column,&startburst)
RD L L LHLHBALLL XCA1,2,5,
9
READwithAutoprecharge RDA L L L H L H BA L L H X CA 1,2,5
LoadFIFO LDFF L L LHLHXHLL X X1,2,7
READTraining RDTR L L LH LHXHHL X X1,2
WRITEwithoutMask
(Selectbankandcolumn,&
startburst)
WOM L L LHLLBALLL XCA1,2,5
WRITEwithoutMaskwith
Autoprecharge
WOMAL L LHL LBALLHXCA1,2,5
WRITEwithsingle‐byte
mask
WSM L L L H L L BA L H L X CA 1,2,5
WRITEwithsingle‐byte
maskwithAutoprecharge
WSMA L L L H L L BA L H H X CA 1,2,5
WRITEwithdouble‐byte
mask(WDM)
WDM L L L H L L BA H L L X CA 1,2,5
WRITEwithdouble‐byte
maskwithAutoprecharge
WDMA L L L H L L BA H L H X CA 1,2,5
WRITETraining WRTR L L L H L L X H H L X X 1,2
PRECHARGE(Deactivate
rowinbankorbanks)
PRE L L L L H L BA X X L X X 1,2
PRECHARGEALL PREALL L L L L H L X X X H X X 1,2
REFRESH REF L L L L LHXXXX X X1,6
POWERDOWNENTRY PDE L H HX X XXXXX X X 1
LHHHXXXX X X 1
POWERDOWNEXIT PDX H L HX X XXXXX X X 1
LHHH
SELFREFRESHENTRY SRE L H L L LHXXXX X X1,6
SELFREFRESHEXIT SRX H L HX X XXXXX X X 1
LHHH
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Rev. 1.0 /Nov. 2009 64
H5GQ1H24AFR
Figure34andFigure35illustratethetimingsassociatedwiththeCommandandAddressinputaswellas
Datainput.
Figure 34. Command and Address Input Timings
Figure 35. Data Input Timings
CK#
CK
tCH tCL
tCK
COMMAND
tCMDS
tCMDPW
ADDRESS
tAH
tCMDH
tAPW
tAPW tAS tAH
tAS
DonʹtCare
tDIPW
tDIPW
tDIVW tDIVW
tWCK2DQI
tWCK2DQI
DQ/DBI#
WCK#
WCK
(1Pin)
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Rev. 1.0 /Nov. 2009 65
H5GQ1H24AFR
5.2.DESELECT(NOP)
TheDESELECTfunction(CS#HIGH)preventsnewcommandsfrombeingexecutedbytheGDDR5
SGRAM.TheGDDR5SGRAMiseffectivelydeselected.Operationsalreadyinprogressarenotaffected.
5.3.NOOPERATION(NOP)
TheNOOPERATION(NOP)commandisusedtoinstructtheselectedGDDR5SGRAMtoperformaNOP
(CS#LOW).Thispreventsunwantedcommandsfrombeingregisteredduringidleorwaitstates.Opera‐
tionsalreadyinprogressarenotaffected.
5.4.MODEREGISTERSET
TheMODEREGISTERSETcommandisusedtoloadtheModeRegistersoftheGDDR5SGRAM.Thebank
addressinputsBA0‐BA3selecttheModeRegister,andaddressputsA0‐A11(A12)determinetheop‐code
tobeloaded.SeeMODEREGISTERforaregisterdefinition.TheMODEREGISTERSETcommandcan
onlybeissuedwhenallbanksareidleandnoburstsareinprogress,andasubsequentexecutablecom‐
mandcannotbeissueduntiltMRDismet.
Figure 36. MRS Command
LOW
RA=RowAddress
CO=Op‐code
BA=BankAddress
ENAP=EnableAutoPrecharge
DISAP=DisableAutoPrecharge
ModeRegisterSet
CO CO
CS#
WE#
CAS#
RAS#
CKE#
CK
CK#
DONʹTCARE
BA CO
BA0‐BA3
A2‐A5
BA0,1,2,3 A2,3,4,5
A8,9,10,11,(12) A0,1,6,7
A8‐A11(A12)
A0,A1,A6,A7
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Rev. 1.0 /Nov. 2009 66
H5GQ1H24AFR
Figure 37. Mode Register Set Timings
5.5.ACTIVATION
BeforeanyREADorWRITEcommandscanbeissuedtoabankintheGDDR5SGRAM,arowinthatbank
mustbe“opened”.ThisisaccomplishedbytheACTIVEcommand(seeFigure38):BA0‐BA3selectthe
bank,andA0‐A11(A12)selecttherowtobeactivated.Oncearowisopen,aREADorWRITEcommand
couldbeissuedtothatrow,subjecttothetRCDspecification.
AsubsequentACTIVEcommandtoanotherrowinthesamebankcanonlybeissuedaftertheprevious
rowhasbeenclosed(precharged).TheminimumtimeintervalbetweentwosuccessiveACTIVEcom‐
mandsonthesamebankisdefinedbytRC.Aminimumtime,tRAS,musthaveelapsedbetweenopening
andclosingarow.
AsubsequentACTIVEcommandtoanotherbankcanbeissuedwhilethefirstbankisbeingaccessed,
whichresultsinareductionoftotalrow‐accessoverhead.Theminimumtimeintervalbetweentwosuc‐
cessiveACTIVEcommandsondifferentbankstodifferentbankgroupsisdefinedbytRRDS.Withbank
groupsenabled,theminimumtimeintervalbetweentwosuccessiveACTIVEcommandstodifferent
banksinthesamebankgroupisdefinedbytRRDL.InallothercasestheintervalisdefinedbytRRDS.
<Link>FigureshowsthetRCDandtRRDdefinition.
CK#
CK
CMD
A.C.=anycommandallowedinbankidlestate
tRP tMRD
UpdatingSetting NewSettingOldSetting
NOP PRE
ALL NOP MRS NOP A.C. NOP
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Rev. 1.0 /Nov. 2009 67
H5GQ1H24AFR
TherowremainsactiveuntilaPRECHARGEcommand(orREADorWRITEcommandwithAutoPre‐
charge)isissuedtothebank.
Figure 38. Active Command
Figure 39. Bank Activation Command Cycle
A8‐A11(A12)
A0,A1,A6,A7
LOW
RA=RowAddress
CA=ColumnAddress
BA=BankAddress
RowActivation
RA RA
CS#
WE#
CAS#
RAS#
CKE#
DONʹTCARE
BA RA
BA0‐BA3
A2‐A5
BA0,1,2,3 A2,3,4,5
A8,9,10,11,(12) A0,1,6,7
CK
CK#
CK#
CK
CMD
ADDR BA
RA RA BA CA BA BA
RA RA
t
RCD
t
RP
t
RAS
t
RC
BA=bankaddress;RA=rowaddress;CA=columnaddress
t
RCD
=t
RCDRD
,t
RCDWR
,t
RCDRTR
,t
RCDWTR
ort
RCDLTR
,dependingoncommand
(*)=couldalsobePREALL
NOP ACT NOP
RD/WR
NOP PRE* NOP ACT NOP
DonʹtCare
T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc1Tc0
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 68
H5GQ1H24AFR
5.6.BANKRESTRICTIONS
Theremaybeaneedtolimitthenumberofactivatesinarollingwindowtoensurethattheinstantaneous
currentsupplyingcapabilityofthedevicesisnotexceeded.Toreflecttheshorttermcapabilityofthe
GDDR5SGRAMcurrentsupply,theparametertFAW(fouractivatewindow)isdefined.Nomorethan4
banksmaybeactivatedinarollingtFAWwindow.ConvertingtoclocksisdonebydividingtFAW(ns)by
tCK(ns)androundinguptonextintegervalue.Asanexampleoftherollingwindow,if(tFAW/tCK)rounds
upto10clocks,andanactivatecommandisissuedatclockN,nomorethanthreefurtheractivatecom‐
mandsmaybeissuedatclocksN+1throughN+9asillustratedinFigure40.
ToreflectalongertermGDDR5SGRAMcurrentsupplycapability,theparametert32AW(thirty‐twoacti‐
vatewindow)isdefined.Nomorethan32banksmaybeactivatedinarollingt32AWwindow.Converting
toclocksisdonebydividingt32AW(ns)bytCK(ns)androundinguptonextintegervalue.Theuseofa
shorterandlongerrollingactivationwindowallowstheGDDR5SGRAMdesigntobeoptimizedtohandle
higherinstantaneouscurrentswithinashorterwindowwhilestilllimitingthecurrentstrainoveralonger
periodoftime.Thismeansthatingeneralt32AWwillbegreaterthanorequalto8*tFAWasshownin
Figure41.
ItispreferablethatGDDR5SGRAMshavenorollingactivationwindowrestrictions(tFAW=4*tRRD).
Figure 40. tRRD and tFAW
ACT
tRRD tRRD tRRD tRRD tRRD tRRD
tFAW
tFAW +3
*t
ACTACTACT ACT ACT ACT ACT
RRD
CK
CK#
CMD
t
RRD
=t
RRDL
ort
RRDS
dependingonBankGroupson/offsettingandaccessedbanks
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 69
H5GQ1H24AFR
Figure 41. t32AW
t
FAW
A.)t
32AW
>8*t
FAW
B.)t
32AW
=8*t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
32AW
t
32AW
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Rev. 1.0 /Nov. 2009 70
H5GQ1H24AFR
5.7.WRITE(WOM)
WRITEburstsareinitiatedwithaWRITEcommandasshowninFigure42.Thebankandcolumn
addressesareprovidedwiththeWRITEcommandandautoprechargeiseitherenabledordisabledfor
thataccesswiththeA8pin.Ifautoprechargeisenabled,therowbeingaccessedisprechargedatthecom‐
pletionoftheburstaftertRAS(min)hasbeenmet.ThelengthoftheburstinitiatedwithaWRITEcommand
iseightandthecolumnaddressisuniqueforthisburstofeight.Thereisnointerruptionnortruncationof
WRITEbursts.
Figure 42. WRITE Command
DuringWRITEbursts,thefirstvaliddata‐inelementmustbeavailableattheinputlatchaftertheWrite
Latency(WL).TheWriteLatencyisdefinedasWLmrs*tCK+tWCK2CKPIN+tWCK2CK+tWCK2DQI,where
WLmrsisthenumberofclockcyclesprogramedinMR0,tWCK2CKPINisthephaseoffsetbetweenWCK
andCKatthepinswhenphasealignedatphasedetector,tWCK2CKisthealignmenterrorbetweenWCK
andCKattheGDDR5SGRAMphasedetector,andtWCK2DQIistheWCKtoDQ/DBI#offsetasmeasured
attheDRAMpinstoensureconcurrentarrivalatthelatch.Thetotaldelayisrelativetothedataeyecenter
averagedoveronedouble‐byte.Themaximumskewwithinadouble‐byteisdefinedbytDQDQI.
Thedatainputvalidwindow,tDIVW,definesthetimeregionwheninputdatamustbevalidforreliable
datacaptureatthereceiverforanyoneworst‐casechannel.Itaccountsforjitterbetweendataandclockat
thelatchingpointintroducedinthepathbetweentheDRAMpadsandthelatchingpoint.Anyadditional
jitterintroducedintothesourcesignals(i.e.withinthesystembeforetheDRAMpad)mustbeaccounted
forinthefinaltimingbudgettogetherwiththechosenPLLmodeandbandwidth.tDIVWismeasuredat
thepins.tDIVWisdefinedforthePLLoffandonmodeseparately.InthecaseofPLLon,tDIVWmustbe
specifiedforeachsupportedbandwidth.IngeneraltDIVWissmallerthantDIPW.
A10,A11 0,0
CS#
WE#
CAS#
RAS#
CKE#
A9(A12)
A1
A8
LOW
WRITE
CK
CK#
CA
A0,A6
BA0‐BA3
A2‐A5 CA
BA
A7
ENAP
DISAP
BA=BankAddress;CA=ColumnAddress
ENAP=EnableAuto‐Precharge;DISAP=DisableAuto‐Precharge
0,0 CA
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 71
H5GQ1H24AFR
Thedatainputpulsewidth,tDIPW,definestheminimumpositiveornegativeinputpulsewidthforany
oneworst‐casechannelrequiredforproperpropagationofanexternalsignaltothereceiver.tDIPWismea‐
suredatthepins.tDIPWisindependentofthePLLmode.IngeneraltDIPWislargerthantDIVW.
Uponcompletionofaburst,assumingnootherWRITEdataisexpectedonthebustheGDDR5SGRAM
DQandDBI#pinswillbedrivenaccordingtotheODTstate.Anyadditionalinputdatawillbeignored.
DataforanyWRITEburstmaynotbetruncatedwithasubsequentWRITEcommand.
DatafromanyWRITEburstmaybeconcatenatedwithdatafromasubsequentWRITEcommand.Acon‐
tinuousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelement
ofacompletedburst.ThenewWRITEcommandshouldbeissuedafterthepreviousWRITEcommand
accordingtothetCCDtiming.IfthatWRITEcommandistoanotherbankthenanACTIVEcommandmust
precedetheWRITEcommandandtRCDWRalsomustbemet.
AREADcanbeissuedanytimeafteraWRITEcommandaslongastheinternalturnaroundtimetWTRis
met.IfthatREADcommandistoanotherbank,thenanACTIVEcommandmustprecedetheREADcom‐
mandandtRCDRDalsomustbemet.
APRECHARGEcanalsobeissuedtotheGDDR5SGRAMwiththesametimingrestrictionasthenew
WRITEcommandiftRASismet.AfterthePRECHARGEcommand,asubsequentcommandtothesame
bankcannotbeissueduntiltRPismet.
ThedatainversionflagisreceivedontheDBI#pintoidentifywhethertostorethetrueorinverteddata.If
DBI#isLOW,thedatawillbestoredafterinversioninsidetheGDDR5SGRAMandnotinvertedifDBI#is
HIGH.WRITEDataInversioncanbeenabled(A9=0)ordisabled(A9=1)usingWDBIinMR1.
WhenenabledbytheWRCRCflaginMR4,EDCdataarereturnedtothecontrollerwithalatencyof
(WLmrs+CRCWL)*tCK+tWCK2CKPIN+tWCK2CK+tWCK2DQO,whereCRCWListheCRCWritelatency
programmedinMR4andtWCK2DQOistheWCKtoDQ/DBI#/EDCphaseoffsetattheDRAMpins.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 72
H5GQ1H24AFR
Figure 43. WRITE Timings
CK
CK#
tCH tCL tCK
WLmrs
DQ/DBI#
(mean)
WCK#
WCK
tWCK2CKPIN+tWCK2CK
tWCK2DQI
DQ/DBI#
(firstbit)
DQ/DBI#
(lastbit)
tDQDQI(min)
tDQDQI(max)
1) WLmrsistheWRITElatencyprogrammedinModeRegisterMR0.
2) TimingsareshownwithpositivetWCK2CKPINandtWCK2CKvalues.SeeWCK2CKtimingsfor
tWCK2CKPINandtWCK2CKranges.
3) tWCK2DQIparametervaluescouldbenegativeorpositivenumbers,dependingonPLL‐onorPLL‐offmode
operationanddesignimplementation.TheyalsovaryacrossPVT.Datatrainingisrequiredtodetermine
theactualtWCK2DQIvalueforstableWRITEoperation.
4) tDQDQIdefinestheminimumtomaximumvariationoftWCK2DQIwithinadoublebyte(x32mode)or
asinglebyte(x16mode).
5) DataReadtimingsareusedforCRCreturntimingfromWRITEcommandswithCRCenabled.
D1 D2 D3 D4 D5 D6 D7D0
D1 D2 D3 D4 D5 D6 D7D0
D1 D2 D3 D4 D5 D6 D7D0
Case1:NegativetWCK2DQI
DQ/DBI#
(mean)
tWCK2DQI
DQ/DBI#
(firstbit)
DQ/DBI#
(lastbit)
tDQDQI(min)
tDQDQI(max)
D1 D2 D3 D4 D5 D6 D7D0
D1 D2 D3 D4 D5 D6 D7D0
D1 D2 D3 D4 D5 D6 D7D0
Case2:PositivetWCK2DQI
DonʹtCare
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 73
H5GQ1H24AFR
Figure 44. Single WRITE without EDC
CK
CK#
ADDRESS
DQ
DBI#
WCK#
WCK
DO DO
DBI DBI
n+7
n+7
n
n
Banka,
ColnColn
WL=WLmrs=3
T1 T2T0 T3 T4 T5 T6 T7 T8
T3n T4n
EDCHoldPattern
EDC
3.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
4.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet.
1.WLmrs=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
Notes:
5.tWCK2DQI=0isshownforillustrationpurposes.
DONʹTCARE TRANSITIONINGDATA
NOPWRITE
COMMAND NOP NOP NOP NOP NOP NOP NOP
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 74
H5GQ1H24AFR
Figure 45. Single WRITE with EDC
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
3.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
4.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet.
WL=WLmrs=3
T1 T2T0 T3 T4 T5 T11 T12 T13T3n T4n
Banka,
ColnColn
(
)()
(
)(
)
(
)(
)
(
)(
)
CRCWL=8
EDCHoldPattern EDCHold
Pattern
(
)(
)
(
)(
)
DO DO
DBI DBI
n+7
n+7
n
n
CK
CK#
DQ
DBI#
WCK#
WCK
EDC
(
)(
)
(
)(
)
EDC EDC
n+7
n
1.WLmrs=3andCRCWL=8isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
5.tWCK2DQI,tWCKDQO=0isshownforillustrationpurposes.
Notes:
DONʹTCARE TRANSITIONINGDATA
NOPWRITE NOP NOP NOP NOP NOP NOP NOP
ADDRESS
COMMAND
(
)()
(
)(
)
(
)(
)
(
)()
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 75
H5GQ1H24AFR
Figure 46. Non-Gapless WRITEs
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
4.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
5.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet.
DBI DBI
n+7n
DO DO
n+7
n
DO DO
m+7
m
DBI DBI
m+7
m
Banka,
ColmColm
WL=WLmrs=5
T7 T11 T12T0 T1 T2 T5 T5n T6 T6n T11nT10 T10n
Bankb,
ColnColn
WL=WLmrs=5
tRCDWR
Bankb,
Row Row
1.WLmrs=5andtRCDWR=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
Notes:
6.tWCK2DQI=0isshownforillustrationpurposes.
DONʹTCARE TRANSITIONINGDATA
NOPWRITE ACT WRITE NOP NOP NOP NOP NOP
CK
CK#
COMMAND
ADDRESS
DQ
DBI#
WCK#
WCK
(
)(
)
(
)()
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
(
)()
(
)()
(
)()
(
)()
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
(
)(
)
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 76
H5GQ1H24AFR
Figure 47. Gapless WRITEs
NOPWRITE WRITE NOP NOP NOP NOP NOP NOP
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
WL=WLmrs=2
Banka,
ColmColm
CK
CK#
COMMAND
DQ
DBI#
1.WLmrs=2isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
WCK#
WCK
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
T5 T7 T8T0 T1 T2 T3 T3n T4 T4n T5n T6
T2n
5.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
6.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet.
Banka,
ColnColn
DO DO
DBI DBI
m+7
m+7
m
m
tCCD
DO DO
n+7
n
DBI DBI
n+7n
WL=WLmrs=2
4.tCCD=tCCDSwhenbankgroupsisdisabledorthesecondWRITEistoadifferentbankgroup,otherwisetCCD=tCCDL.
Notes:
7.tWCK2DQI=0isshownforillustrationpurposes.
DONʹTCARE TRANSITIONINGDATA
ADDRESS
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 77
H5GQ1H24AFR
Figure 48. WRITE to READ
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
DO DO
m+7
m
CL=CLmrs=6
WL=WLmrs=3
DBI DBI
n+7n
Banka,
ColmColm
Ta0 Ta7 Ta8T0 T1 T3 T4 T4n T5 Ta6 Ta6n
DO DO
n+7
n
Bankb,
ColnColn
tWTR
respectivelymustbemet.
DBI DBI
m+7m
T3n
1.WLmrs=3andCLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
5.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
6.BeforetheREADandWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDortRCDWR
4.tWTR=tWTRLwhenbankgroupsisenabledandbothWRITEandREADaccessbanksinthesamebankgroup,otherwisetWTR=tWTRS.
Notes:
7.tWCK2DQI,tWCKDQO=0isshownforillustrationpurposes.
DONʹTCARE TRANSITIONINGDATA
NOPWRITE NOP NOP NOP READ NOP NOP NOP
CK
CK#
ADDRESS
DQ
DBI#
WCK#
WCK
COMMAND
(
)(
)
(
)()
(
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)
(
)()
(
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)
(
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)
(
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)
(
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)
(
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)
(
)()
(
)()
(
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)
(
)()
(
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)
(
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)
(
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)
(
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)
(
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(
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(
)()
(
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(
)()
(
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)
(
)()
(
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)
(
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)
(
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)
(
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)
(
)(
)
(
)()
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 78
H5GQ1H24AFR
Figure 49. WRITE to PRECHARGE
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
Banka,
ColnColn
CK
CK#
DQ
DBI#
WL=WLmrs=3
WCK#
WCK
T5 Ta0 Ta1T0 T1 T2 T3 T3n T4 T4n T6
tWR
Banka,
orall
tRP
DO DO
DBI DBI
n+7
n+7
n
n
1.WLmrs=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
4.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
5.BeforetheWRITEcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet.
Notes:
6.tWCK2DQI=0isshownforillustrationpurposes.
DONʹTCARE TRANSITIONINGDATA
NOPWRITE NOP NOP NOP NOP NOP PRE NOP
ADDRESS
COMMAND
(
)(
)
(
)()
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 79
H5GQ1H24AFR
5.8.WRITEDATAMASK(DM)
ThetraditionalmethodofusingaDMpinforWRITEdatamaskmustbeabandonedforanewmethod.
DuetothehighdatarateofGDDR5SGRAMs,biterrorsareexpectedontheinterfaceandarenotrecover‐
ablewhentheyoccuronthetraditionalDMpin.
InGDDR5theDMissenttotheSGRAMovertheaddressfollowingthebank/columnaddresscycleassoci‐
atedwiththecommand,duringtheNOP/DESELECTcommandsbetweentheWRITEcommandandthe
nextcommand.TheDMisusedtomaskthecorrespondingdataaccordingtothefollowingtable.
TwoadditionalWRITEcommandsthataugmentthetraditionalWRITEWithoutMask(WOM)are
requiredforproperDMsupport:
•WDM:WRITE‐With‐Doublebyte‐Mask:
2cyclecommandwherethe1stcyclecarriesaddressinformationandthe2ndcyclecarriesdatamask
information(2bytegranularity);
Table17:DMState
FUNCTION DM
Value DQ
WriteEnable 0 Valid
WriteInhibit 1 X
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 80
H5GQ1H24AFR
Figure 50. WRITE-With-Doublebyte-Mask Command
CS#
WE#
CAS#
RAS#
CKE#
A9(A12)
A1
A10,A11
A8
A7
LOW
WDM
CK
CK#
0,1
BA0‐BA3
A2‐A5
A0,A6
DM
DM
DM
DM DM
DM
DM
DM
ENAP
DISAP
CA
BA
CA
CA
BA=BankAddress;CA=ColumnAddress;DM=DataMask
ENAP=EnableAuto‐Precharge;DISAP=DisableAuto‐Precharge
Note:NOPshownasanexampleonly
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 81
H5GQ1H24AFR
Figure 51. WDM Timing
NOPWDM WDM NOP NOP NOP NOP NOP NOP
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
WL=WLmrs=2
Banka,
ColmColm
CK
CK#
COMMAND
DQ
DBI#
1.WLmrs=2isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
WCK#
WCK
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
T5 T7 T8T0 T1 T2 T3 T3n T4 T4n T5n T6
T2n
5.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
6.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet.
Banka,
ColnColn
DO DO
DBI DBI
m+7
m+7
m
m
tCCD
DO DO
n+7
n
DBI DBI
n+7n
WL=WLmrs=2
4.tCCD=tCCDSwhenbankgroupsisdisabledorthesecondWRITEistoadifferentbankgroup,otherwisetCCD=tCCDL.
Notes:
7.tWCK2DQI=0isshownforillustrationpurposes.
DONʹTCARE TRANSITIONINGDATA
ADDRESS DMmDMmDMnDMn
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 82
H5GQ1H24AFR
•WSM:WRITE‐With‐Singlebyte‐Mask:
3cyclecommandwherethe1stcyclecarriesaddressinformation,the2ndand3rdcyclecarrydatamask
information
Figure 52. WRITE-With-Singlebyte-Mask Command
CS#
WE#
CAS#
RAS#
CKE#
A9(A12)
A1
A10,A11
A8
A7
LOW
WSM
CK
CK#
0,1
BA0‐BA3
A2‐A5
A0,A6
DM
DM
DM
DM DM
DM
DM
DM
ENAP
DISAP
CA
BA
CA
CA
BA=BankAddress;CA=ColumnAddress;DM=DataMask
ENAP=EnableAuto‐Precharge;DISAP=DisableAuto‐Precharge
DM
DM
DM
DM DM
DM
DM
DM
Note:NOPshownasanexampleonly
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 83
H5GQ1H24AFR
Figure 53. WSM Timing
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
4.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
5.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDWRmustbemet.
DBI DBI
n+7n
DO DO
n+7
n
DO DO
m+7
m
DBI DBI
m+7
m
Banka,
ColmColm
WL=WLmrs=5
T7 T11 T12T0 T1 T2 T5 T5n T6 T6n T11nT10 T10n
Bankb,
ColnColn
WL=WLmrs=5
DMm
1.WLmrs=5andtRCDWR=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
Notes:
6.tWCK2DQI=0isshownforillustrationpurposes.
DONʹTCARE TRANSITIONINGDATA
NOPWSM NOP WSM NOP NOP NOP NOP NOP
CK
CK#
COMMAND
ADDRESS
DQ
DBI#
WCK#
WCK
(
)(
)
(
)()
(
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)
(
)()
(
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)
(
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)
(
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)
(
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)
(
)(
)
(
)()
(
)()
(
)()
(
)()
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
(
)(
)
DMmDMmDMmDMnDMnDMnDMn
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 84
H5GQ1H24AFR
Table 18WDMMappingformirrored&non‐mirroredx32Mode
ByteandBurstPositionMaskedduringWDM
ADR ADRCKRisingEdge ADR ADRCK#RisingEdge
Byte Burst Byte Burst
A10 DQ[15:0] 0A0 DQ[15:0] 4
A9 DQ[15:0] 1A1 DQ[15:0] 5
BA0 DQ[15:0] 2A2 DQ[15:0] 6
BA3 DQ[15:0] 3A3 DQ[15:0] 7
BA2 DQ[31:16] 0A4 DQ[31:16] 4
BA1 DQ[31:16] 1A5 DQ[31:16] 5
A11 DQ[31:16] 2A6 DQ[31:16] 6
A8 DQ[31:16] 3A7 DQ[31:16] 7
Table 19WDMMappingfornon‐mirroredx16Mode
ByteandBurstPositionMaskedduringWDM
ADRCKRisingEdge ADR ADRCK#RisingEdge
ADR Byte Burst Byte Burst
A10 DQ[7:0] 0A0 DQ[7:0] 4
A9 DQ[7:0] 1A1 DQ[7:0] 5
BA0 DQ[7:0] 2A2 DQ[7:0] 6
BA3 DQ[7:0] 3A3 DQ[7:0] 7
BA2 DQ[23:16] 0A4 DQ[23:16] 4
BA1 DQ[23:16] 1A5 DQ[23:16] 5
A11 DQ[23:16] 2A6 DQ[23:16] 6
A8 DQ[23:16] 3A7 DQ[23:16] 7
Table 20WDMMappingformirroredx16Mode
ByteandBurstPositionMaskedduringWDM
ADRCKRisingEdge ADR ADRCK#RisingEdge
ADR Byte Burst Byte Burst
A10 DQ[15:8] 0A0 DQ[15:8] 4
A9 DQ[15:8] 1A1 DQ[15:8] 5
BA0 DQ[15:8] 2A2 DQ[15:8] 6
BA3 DQ[15:8] 3A3 DQ[15:8] 7
BA2 DQ[31:24] 0A4 DQ[31:24] 4
BA1 DQ[31:24] 1A5 DQ[31:24] 5
A11 DQ[31:24] 2A6 DQ[31:24] 6
A8 DQ[31:24] 3A7 DQ[31:24] 7
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Table 21WSMMappingformirroredandnon‐mirroredx32Mode
ByteandBurstPositionMaskedDuringWSM
ADRCK1strisingEdge ADRCK#1strisingEdge ADRCK2ndrisingEdge ADRCK#2ndrisingEdge
ADR Byte Burst ADR Byte Burst ADR Byte Burst ADR Byte Burst
A10 DQ[7:0] 0A0 DQ[7:0] 4A10 DQ[15:8] 0A0 DQ[15:8] 4
A9 DQ[7:0] 1A1 DQ[7:0] 5A9 DQ[15:8] 1A1 DQ[15:8] 5
BA0 DQ[7:0] 2A2 DQ[7:0] 6BA0 DQ[15:8] 2A2 DQ[15:8] 6
BA3 DQ[7:0] 3A3 DQ[7:0] 7BA3 DQ[15:8] 3A3 DQ[15:8] 7
BA2 DQ[23:16] 0A4 DQ[23:16] 4BA2 DQ[31:24] 0A4 DQ[31:24] 4
BA1 DQ[23:16] 1A5 DQ[23:16] 5BA1 DQ[31:24] 1A5 DQ[31:24] 5
A11 DQ[23:16] 2A6 DQ[23:16] 6A11 DQ[31:24] 2A6 DQ[31:24] 6
A8 DQ[23:16] 3A7 DQ[23:16] 7A8 DQ[31:24] 3A7 DQ[31:24] 7
Table 22WSMMappingfornon‐mirroredx16Mode
ByteandBurstPositionMaskedDuringWSM
ADRCK1strisingEdge ADRCK#1strisingEdge ADRCK2ndrisingEdge ADRCK#2ndrisingEdge
ADR Byte Burst ADR Byte Burst Byte Burst Byte Burst
A10 DQ[7:0] 0A0 DQ[7:0] 4‐0‐4
A9 DQ[7:0] 1A1 DQ[7:0] 5‐1‐5
BA0 DQ[7:0] 2A2 DQ[7:0] 6‐2‐6
BA3 DQ[7:0] 3A3 DQ[7:0] 7‐3‐7
BA2 DQ[23:16] 0A4 DQ[23:16] 4‐0‐4
BA1 DQ[23:16] 1A5 DQ[23:16] 5‐1‐5
A11 DQ[23:16] 2A6 DQ[23:16] 6‐2‐6
A8 DQ[23:16] 3A7 DQ[23:16] 7‐3‐7
Table 23WSMMappingformirroredx16Mode
ByteandBurstPositionMaskedDuringWSM
ADRCK1strisingEdge ADRCK#1strisingEdge ADRCK2ndrisingEdge ADRCK#2ndrisingEdge
Byte Burst Byte Burst ADR Byte Burst ADR Byte Burst
‐0‐4A10 DQ[15:8] 0A0 DQ[15:8] 4
‐1‐5A9 DQ[15:8] 1A1 DQ[15:8] 5
‐2‐6BA0 DQ[15:8] 2A2 DQ[15:8] 6
‐3‐7BA3 DQ[15:8] 3A3 DQ[15:8] 7
‐0‐4BA2 DQ[31:24] 0A4 DQ[31:24] 4
‐1‐5BA1 DQ[31:24] 1A5 DQ[31:24] 5
‐2‐6A11 DQ[31:24] 2A6 DQ[31:24] 6
‐3‐7A8 DQ[31:24] 3A7 DQ[31:24] 7
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Rev. 1.0 /Nov. 2009 86
H5GQ1H24AFR
5.9.READ
AREADburstisinitiatedwithaREADcommandasshowninFigure54.Thebankandcolumnaddresses
areprovidedwiththeREADcommandandautoprechargeiseitherenabledordisabledforthataccess
withtheA8address.Ifautoprechargeisenabled,therowbeingaccessedisprechargedatthecompletion
oftheburstaftertRAS(min)hasbeenmet.ThelengthoftheburstinitiatedwithaREADcommandiseight
andthecolumnaddressisuniqueforthisburstofeight.ThereisnointerruptionnortruncationofREAD
bursts.
Figure 54. READ Command
DuringREADbursts,thefirstvaliddata‐outelementwillbeavailableaftertheCASlatency(CL).TheCAS
LatencyisdefinedasCLmrs*tCK+tWCK2CKPIN+tWCK2CK+tWCK2DQO,whereCLmrsisthenumberof
clockcyclesprogramedinMR0,tWCK2CKPINisthephaseoffsetbetweenWCKandCKatthepinswhen
phasealignedatphasedetector,tWCK2CKisthealignmenterrorbetweenWCKandCKattheGDDR5
SGRAMphasedetector,andtWCK2DQOistheWCKtoDQ/DBI#/EDCoffsetasmeasuredattheDRAM
pins.Thetotaldelayisrelativetothedataeyeinitialedgeaveragedoveronedouble‐byte.Themaximum
skewwithinadouble‐byteisdefinedbytDQDQO.
Uponcompletionofaburst,assumingnootherREADcommandhasbeeninitiated,allDQandDBI#pins
willdriveavalueofʹ1ʹandtheODTwillbeenabledatamaximumof1tCKlater.Thedrivevalueandter‐
minationvaluemaybedifferentduetoseparatelydefinedcalibrationoffsets.IftheODTisdisabled,the
pinswilldriveHi‐Z.
DatafromanyREADburstmaybeconcatenatedwithdatafromasubsequentREADcommand.Acontin‐
uousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelementof
acompletedburst.ThenewREADcommandshouldbeissuedafterthepreviousREADcommandaccord‐
ingtothetCCDtiming.IfthatREADcommandistoanotherbankthenanACTIVEcommandmustpre‐
cedetheREADcommandandtRCDRDalsomustbemet.
WE#
A10,A11 0,0
CS#
CAS#
RAS#
CKE#
A9(A12)
A1
A8
LOW
READ
CK
CK#
CA
A0,A6
BA0‐BA3
A2‐A5 CA
BA
A7
ENAP
DISAP
BA=BankAddress;CA=ColumnAddress
ENAP=EnableAuto‐Precharge;DISAP=DisableAuto‐Precharge
0,0 CA
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AWRITEcanbeissuedanytimeafteraREADcommandaslongasthebusturnaroundtimetRTWismet.
IfthatWRITEcommandistoanotherbank,thenanACTIVEcommandmustprecedethesecondWRITE
commandandtRCDWRalsomustbemet.
APRECHARGEcanalsobeissuedtotheGDDR5SGRAMwiththesametimingrestrictionasthenew
READcommandiftRASismet.AfterthePRECHARGEcommand,asubsequentcommandtothesame
bankcannotbeissueduntiltRPismet.
ThedatainversionflagisdrivenontheDBI#pintoidentifywhetherthedataistrueorinverteddata.If
DBI#isHIGH,thedataisnotinverted,andifLOWitisinverted.READDataInversioncanbeenabled
(A8=0)ordisabled(A8=1)usingRDBIinMR1.
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WhenenabledbytheRDCRCflaginMR4,EDCdataisreturnedtothecontrollerwithalatencyof(CLmrs
+CRCRL)*tCK+tWCK2CKPIN+tWCK2CK+tWCK2DQO,whereCRCRListheCRCReadlatencypro‐
grammedinMR4.
Figure 55. READ Word Lane Timing
CK
CK#
t
CH
t
CL
t
CK
CLmrs
DQ/DBI#/EDC
(mean)
WCK#
WCK
t
WCK2CKPIN
+t
WCK2CK
t
WCK2DQO
DQ/DBI#/EDC
(firstbit)
DQ/DBI#/EDC
(lastbit)
t
DQDQO
(min)
t
DQDQO
(max)
1) CLmrsistheCASlatencyprogrammedinModeRegisterMR0.
2) Timingsareshownwithpositivet
WCK2CKPIN
andt
WCK2CK
values.SeeWCK2CKtimingsfor
t
WCK2CKPIN
andt
WCK2CK
ranges.
3) t
WCK2DQO
parametervaluescouldbenegativeorpositivenumbers,dependingonPLL‐onorPLL‐offmode
operationanddesignimplementation.TheyalsovaryacrossPVT.Datatrainingisrequiredtodetermine
theactualt
WCK2DQO
valueforstableREADoperation.
4) t
DQDQO
definestheminimumtomaximumvariationoft
WCK2DQO
withinadoublebyte(x32mode)or
asinglebyte(x16mode).
5) t
DQDQO
alsoappliesforCRCdatafromWRITEandREADcommandswithCRCenabled,theEDChold
D1 D2 D3 D4 D5 D6 D7D0
D1 D2 D3 D4 D5 D6 D7D0
D1 D2 D3 D4 D5 D6 D7D0
Case1:Negativet
WCK2DQO
DQ/DBI#/EDC
(mean)
t
WCK2DQO
DQ/DBI#/EDC
(firstbit)
DQ/DBI#/EDC
(lastbit)
t
DQDQO
(min)
t
DQDQO
(max)
D1 D2 D3 D4 D5 D6 D7D0
D1 D2 D3 D4 D5 D6 D7D0
D1 D2 D3 D4 D5 D6 D7D0
Case2:Positivet
WCK2DQO
DonʹtCare
pattern,andthedatastrobeinRDQSmode.
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 89
H5GQ1H24AFR
Figure 56. Single READ without EDC
3.BeforetheREADcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet.
4.tWCK2DQO=0isshownforillustrationpurposes.
DBI
CL=CLmrs=6
Banka,
ColnColn
CK
CK#
DQ
DBI#
T0 T1 T2 T5 T6nT6 T7n T8 T9 T10T7
WCK#
DONʹTCARE TRANSITIONINGDATA
DO DO
DBI
n+7
n+7
n
n
(
)(
)
(
)(
)
(
)(
)
(
)(
)
ODTDisabled
ODTEnabled ODTEnabled
ODT (
)(
)
(
)(
)
1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
Notes:
EDCHoldPattern
EDC
WCK
ADDRESS
NOPREAD NOP NOP NOP NOP NOP NOP NOP
COMMAND
(
)()
(
)()
(
)(
)
(
)()
(
)(
)
(
)()
(
)(
)
(
)(
)
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 90
H5GQ1H24AFR
Figure 57. Single READ with EDC
EDCHoldPattern EDCHold
Pattern
EDC EDC
n+7
n
Banka,
ColnColn
CK
CK#
DQ
DBI#
CL=CLmrs=6
T0 T1 T6 T7 T7n
T6n T8 T10 T11 T12T9
EDC
WCK#
CRCRL=4
DONʹTCARE TRANSITIONINGDATA
DO DO
DBI DBI
n+7
n+7
n
n
WCK
3.BeforetheREADcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet.
4.tWCK2DQO=0isshownforillustrationpurposes.
1.CLmrs=6andCRCRL=4areshownasexamples.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
Notes:
ADDRESS
NOPREAD NOP NOP NOP NOP NOP NOP NOP
(
)()
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
(
)(
)
(
)(
)
COMMAND
T10n T11n
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Rev. 1.0 /Nov. 2009 91
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Figure 58. Non-Gapless READs
DBI DBI
n+7n
Banka,
ColmColm
CL=CLmrs=6
T8 T10 T11T0 T1 T3 T6 T6n T7 T7n T10n
T9 T9n
DONʹTCARE TRANSITIONINGDATA
DO DO
DBI DBI
m+7
m+7
m
m
DO DO
n+7
n
Bankb,
ColnColn
tCCD
CL=CLmrs=6
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
4.tCCD=tCCDLwhenbankgroupsareenabledandbothREADsaccessbanksinthesamebankgroup;otherwisetCCD=tCCDS.
5.BeforetheREADcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet.
1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
Notes:
6.tWCK2DQI=0isshownforillustrationpurposes.
NOP
READ READ NOP NOP NOP NOP NOP NOP
CK
CK#
COMMAND
DQ
DBI#
WCK#
WCK
ADDRESS
(
)(
)
(
)()
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)()
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
(
)()
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 92
H5GQ1H24AFR
Figure 59. Gapless READs
CL=CLmrs=6
Banka,
ColmColm
CK
CK#
DQ
DBI#
WCK#
WCK
T7 T9 T10T0 T1 T2 T3 T9nT6 T6n T7n T8 T8n
DONʹTCARE TRANSITIONINGDATA
Bankb,
ColnColn
DO DO
DBI DBI
m+7
m+7
m
m
tCCD
DO DO
n+7
n
DBI DBI
n+7n
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
4.tCCD=tCCDSwhenbankgroupsaredisabledorthesecondREADistoadifferentbankgroup;otherwisetCCD=tCCDL.
5.BeforetheREADcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet.
1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
Notes:
6.tWCK2DQI=0isshownforillustrationpurposes.
NOPREAD READ NOP NOP NOP NOP NOP NOP
COMMAND
ADDRESS
(
)()
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 93
H5GQ1H24AFR
Figure 60. READ to WRITE
DBI DBI
n+7n
DO DO
n+7
n
DO DO
DBI DBI
m+7
m+7
m
m
WL=WLmrs=3
CL=CLmrs=6
Banka,
ColmColm
T9 T11 T12T0 T1 T6 T7 T7n T8
T6n T10 T10n
DONʹTCARE TRANSITIONINGDATA
Bankb,
ColnColn
tRTW
T11n
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
respectivelymustbemet.
1.WLmrs=3andCLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
5.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
6.BeforetheREADandWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDortRCDWR
4.tWTR=tWTRLwhenbankgroupsisenabledandbothWRITEandREADaccessbanksinthesamebankgroup,otherwisetWTR=tWTRS.
Notes:
7.tWCK2DQI,tWCKDQO=0isshownforillustrationpurposes.
NOPREAD NOP WRITE NOP NOP NOP NOP NOP
CK
CK#
COMMAND
ADDRESS
DQ
DBI#
WCK#
WCK
(
)(
)
(
)()
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
(
)()
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responsability for use of circuits described. No patent licenses are implied.
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Figure 61. READ to PRECHARGE
DO DO
DBI DBI
n+7
n+7
n
n
Banka,
ColnColn
CK
CK#
DQ
DBI#
CL=CLmrs=6
WCK#
WCK
T5 T7 T8T0 T1 T2 T3 T4 T7nT6 T6n
tRTP
Banka,
orall
DONʹTCARE TRANSITIONINGDATA
tRP
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
4.tRTP=tRTPLwhenbankgroupsareenabledandthePRECHARGEcommandaccessesthesamebank;otherwisetRTP=tRTPS.
5.BeforetheREADcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet.
1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
Notes:
6.tWCK2DQO=0isshownforillustrationpurposes.
NOPREAD PRE NOP NOP NOP NOP NOP NOP
ADDRESS
COMMAND
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Rev. 1.0 /Nov. 2009 95
H5GQ1H24AFR
5.10.DQPREAMBLE
DQpreambleisafeatureforGDDR5SGRAMsthatisusedforREADdata.DQpreambleconditionsthe
DQsforbettersignalintegrityontheinitialdataofaburst.
Onceenabledbybit5inMR7,theDQpreamblewillprecedeallREADbursts,includingnon‐consecutive
READburstswithaminimumgapof1tCK,asshowninFigure58.Whenenabled,theDQpreamblepat‐
ternappliestoallDQandDBI#pinsinabyte,andthesamepatternisusedforallbytesasshownin
Figure62.DQpreambleisenabledordisabledforallbytes.TheEDCpinineachbyteisnotincludedinthe
DQpreamble.IfODTisenabled,theODTisdisabled1tCKbeforethestartofthepreamblepatternas
showninFigure63.
ThepreamblepatternontheDBI#pinisonlyenablediftheMRforRDBIisenabled(MR1A8bit).During
thepreambletheDBI#pinistreatedasanotherDQpinandthepreamblepatternontheDQsisnot
encodedwithRDBI.IfRDBIisdisabled,thentheDBI#pindrivesODT.
Notes:
1)ThenumberofMax0’sintheburstis4onlyifRDBIisenabled.Max0‘sisonaperbytebasisanddoesnotincludetheEDCpin.
2)x=ValidData
Figure 62. DQ Preamble Pattern
Byte0Byte1Byte2Byte3Idle Preamble Burst
DQ7 DQ15 DQ23 DQ31 1 1 1 1 0 1 0 1 x x x x x x x x
DQ6 DQ14 DQ22 DQ30 1 1 1 1 1 0 1 0 x x x x x x x x
DQ5 DQ13 DQ21 DQ29 1 1 1 1 0 1 0 1 x x x x x x x x
DQ4 DQ12 DQ20 DQ28 1 1 1 1 1 0 1 0 x x x x x x x x
DQ3 DQ11 DQ19 DQ27 1 1 1 1 0 1 0 1 x x x x x x x x
DQ2 DQ10 DQ18 DQ26 1 1 1 1 1 0 1 0 x x x x x x x x
DQ1 DQ9 DQ17 DQ25 1 1 1 1 0 1 0 1 x x x x x x x x
DQ0 DQ8 DQ16 DQ24 1 1 1 1 1 0 1 0 x x x x x x x x
DBI0# DBI1# DBI2# DBI3# 1 1 1 1 0 1 0 1 x x x x x x x x
Max0’s 0000545444444444
Time
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Rev. 1.0 /Nov. 2009 96
H5GQ1H24AFR
Figure 63. Preamble Timing Diagram
DBI
DO DO
DBI
n+7
n+7
n
n
DO DO
n+7
n
CL=CLmrs=6
Banka,
ColnColn
CK
CK#
DQ6
DBI#
T0 T1 T4 T5 T5n T6nT6 T7n T8 T9 T10T7
WCK#
DONʹTCARE TRANSITIONINGDATA
DQ7
WCK
ODTDisabled
ODTEnabled ODTEnabled
ODT
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
4.DQ6,DQ7andtheDBI#pinareshowntoillustratetheDQpreamblepattern.RDBIisEnabled(MR1A8=0).
5.BeforetheREADcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet.
1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
Notes:
6.tWCK2DQO=0isshownforillustrationpurposes.
NOPREAD NOP NOP NOP NOP NOP NOP NOP
ADDRESS
COMMAND
(
)(
)
(
)()
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)()
(
)(
)
(
)(
)
(
)(
)
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responsability for use of circuits described. No patent licenses are implied.
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5.11.READandWRITEDATABUSINVERSION(DBI)
TheGDDR5SGRAMDataBusInversion(DBIdc)reducestheDCpowerconsumptionondatapins,asthe
numberofDQlinesdrivingalowlevelcanbelimitedto4withinabyte.DBIdcisevaluatedperbyte.
ThereisoneDBI#pinperbyte:DBI0#isassociatedwithDQ0‐DQ7,DBI1#withDQ8‐DQ15,DBI2#with
DQ16‐DQ23andDBI3#withDQ24‐DQ31.
TheDBI#pinsarebidirectionalactiveLowdoubledatarate(DDR)signals.ForWrites,theyaresampled
bytheGDDR5SGRAMalongwiththeDQofthesamebyte.ForReads,theyaredrivenbytheGDDR5
SGRAMalongwiththeDQofthesamebyte.
OnceenabledbythecorrespondingRDBIModeRegisterbit,theGDDR5SGRAMinvertsreaddataand
setsDBI#Low,whenthenumberof’0’databitswithinabyteisgreaterthan4;otherwisetheGDDR5
SGRAMdoesnotinvertthereaddataandsetsDBI#High,asshowninFigure64.
OnceenabledbythecorrespondingWDBIModeRegisterbit,theGDDR5SGRAMinvertswritedata
receivedontheDQinputsincaseDBI#wassampledLow,orleavesthedatanon‐invertedincaseDBI#
wassampledHigh,asshowninFigure65.
Figure 64. Example of Data Bus Inversion Logic for READs
Figure 65. Example of Data Bus Inversion Logic for WRITEs
TheflowdiagraminFigure66illustratestheDBIdcoperation.Inanycase,thetransmitter(thecontroller
forWRITEs,theGDDR5SGRAMforREADs)decideswhethertoinvertornotinvertthedataconveyedon
theDQs.Thereceiver(theGDDR5SGRAMforWRITEs,thecontrollerforREADs)hastoperformthe
reverseoperationbasedonthelevelontheDBI#pin.Datainputandoutputtimingparametersareonly
validwithDBIbeingenabledandamaximumof4datalinesperbytedrivenLow.
88
from
DRAM
core DQ
fromModeRegister:
0=enabled
1=disabled
DBI#
’0’
count
>4
88to
DRAM
core
DBI#
DQ
fromModeRegister:
0=enabled
1=disabled
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 98
H5GQ1H24AFR
Figure 66. DBI Flow Diagram
DBI#PinSpecialFunctionOverview
TheDBI#pinhasspecialbehaviorcomparedtoDQpinsbecauseoftheabilitytoenableanddisableitvia
MRS.ForeitherWRITEorREADDBI#pintraining,bothDBIREADandDBIWRITEinMRSmustbe
enabled.ThebehavioroftheDBI#pininvariousmoderegistersettingsissummarizedbelow:
IfbothDBIREADandDBIWRITEareenabled:
•PindrivesDBIFIFOdatawithRDTRcommand
•DBI#pinFIFOacceptsWRTRdatawiththeWRTRcommand
IfonlyDBIREADisenabled:
•DBI#pindrivesODTwhennotREADorRDTR
IfonlyDBIWRITEisenabled:
•PinalwaysdrivesODT(unlessRESET)
IfbothDBIREADandDBIWRITEaredisabled:
•DBI#pindrivesODT(unlessRESET)
No Yes
Logical
outputdata
’0’count
>4?
DBI#=’L’
Invert
databyte
DBI#=’H’
Don’tinvert
databyte
Determine’0’count
indatabyte
Logical
inputdata
DBI#=’H’
Don’tinvert
databyte
DBI#=’L’
Invert
databyte
Transmitter
Receiver
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Rev. 1.0 /Nov. 2009 99
H5GQ1H24AFR
5.12.ERRORDETECTIONCODE(EDC)
TheGDDR5SGRAMprovideserrordetectiononthedatabustoimprovesystemreliability.Thedevice
generatesachecksumperbytelaneforbothREADandWRITEdataandreturnsthechecksumtothecon‐
troller.Basedonthechecksum,thecontrollercandecideifthedata(orthereturnedCRC)wastransmitted
inerrorandretrytheREADorWRITEcommand.TheGDDR5SGRAMitselfdoesnotperformanyerror
correction.ThefeaturesoftheEDCare:
•8bitchecksumon72bits(9channelsx8bitburst)
• dedicatedEDCtransferpinper9channels(4xperGDDR5SGRAM)
•asymmetricallatenciesonEDCtransferforReadsandWrites
TheCRCpolynomialusedbytheGDDR5SGRAMisanATM‐8HEC,X^8+X^2+X^1+1.Thestartingseed
valueissetinhardwareat“zero”.Table24showstheerrortypesthataredetectableandthedetectionrate.
ThebitorderingcalculationfortheCRCerrordetectionisoptimizedforerrorsinthetimeburstdirection.
Figure67showsthebitorientationonabytelanebasis.
Table 24ErrorCorrectionDetails
ErrorType DetectionRate
RandomSingleBit 100%
RandomDoubleBit 100%
RandomOddCount 100%
Burst<=8100%
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Figure 67. EDC Calculation matrix
TheCRCcalculationisembeddedintotheWRITEandREADdatastreamasshowninFigure16:
•forWRITEs,theCRCchecksumiscalculatedontheDQandDBI#inputdatabeforedecodingwithDBI
•forREADs,theCRCchecksumiscalculatedontheDQandDBI#outputdataafterencodingwithDBI
Thebitorderingisoptimizedforerrorsinthetimeburstdirection.Figure67showsthebitorientationona
bytelanebasis.Allʹ1sʹareassumedinthecalculationfortheDBI#inburstincaseDBIisdisabledfor
WRITEsorREADsintheModeRegister.
TheCRCcalculationisalsonotaffectedbyanydatamasksentalongwithWDM,WDMA,WSMorWSMA
commands.
TheEDClatencyisbasedontheCASlatencyforREADdataandtheWRITElatencyforWRITEdata.
Table25showsthe2timingparametersassociatedwiththeEDCscheme.
ModeRegister4isusedtodeterminethefunctionalityoftheEDCpin.RegisterbitsA9andA10controlthe
GDDR5SGRAM’sCRCcalculationindependentlyforREADsandWRITEs.WithEDCoff,thecalculated
CRCpatternwillbereplacedbytheEDCholdpatterndefinedinModeRegisterbitsA0‐A3.See“Mode
Registersonpage39”sectionformoredetails.
DQ0 0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DBI0#
Burst8Ordering(2tCK)
CRCDataInput
DQ/DBI#bitordering 0 1 2 3 4 5 67
CRCPolynomial
T0+8U.I.T0
CRCDataOutput
EDCbitordering
Burst8Ordering(2tCK)
X0 X1 X2 X3 X4 X5 X6 X7
T0+8U.I.
T0
X8+X2+X+1=0x83=(X+1)(X7+X6+X5+X4+X3+X2+1)
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Rev. 1.0 /Nov. 2009 101
H5GQ1H24AFR
Table 25EDCTiming
Description Parameter Value Units
EDCREADLatency tEDCRL CL+CRCRLtCK
EDCWRITELatency tEDCWL WL+CRCWL tCK
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EDCPinSpecialFunctionOverview
TheEDCpinisusedformanydifferentfunctions.ThebehavioroftheEDCpininvariousmodesissum‐
marizedinTable26.
Table 26EDCPinBehavior
DeviceStatus Condition EDC0‐EDC3PinStatus
DevicePower‐up
RESET#=LOW Hi‐Z
RESET#=HIGH;noWCKclocks High
RESET#=HIGH;stableWCKclocks EDCholdpattern(default=’1111’)
WCK2CKTraining WCKissampledHigh EDCholdpattern(’1111’)
WCKissampledLow InvertedEDCholdpattern(’0000’)
Idle
EDC13invMR4A11=0 EDCholdpattern
EDC13invMR4A11=1 EDC0,EDC2:EDCholdpattern
EDC1,EDC3:invertedEDCholdpattern
WRITEBurst WRCRCon CRCdata
WRCRCoff EDCholdpattern
READorRDTRburst RDCRCon CRCdata
RDCRCoff EDCholdpattern
LDFF WRCRC+RDCRCbothonorbothoff EDCholdpattern
WRTRburst ‐EDCholdpattern
Power‐Down
WCKenabled(MR5A1=0) EDCholdpattern
WCKdisabledduringPower‐Down
usingMR5A1=1 High
SelfRefresh ‐High
ReadBurstinRDQSMode MR3A5=1 Fixed’1010’strobepatternwith4U.I.
preamble
READburstinRDQSModewith
RDQSpseudo‐differential MR3A5=1;EDC13invMR4A11=1
EDC0,EDC2:Fixed’1010’strobepattern
with4U.I.preamble
EDC1,EDC3:Fixed’0101’strobepattern
with4U.I.preamble
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Rev. 1.0 /Nov. 2009 103
H5GQ1H24AFR
5.13.PRECHARGE
ThePRECHARGEcommand(seeFigure68)isusedtodeactivatetheopenrowinaparticularbank(PRE)
ortheopenrowinallbanks(PREALL).Thebank(s)willbeavailableforasubsequentrowaccessaspeci‐
fiedtime(tRP)afterthePRECHARGEcommandisissuedasillustratedinFigure39.
InputA8determineswhetheroneorallbanksaretobeprecharged.Incasewhereonlyonebankistobe
precharged,inputsBA0‐BA3selectthebank.OtherwiseBA0‐BA3aretreatedas“Don’tCare”.
Onceabankhasbeenprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITE
commandbeingissued.APRECHARGEcommandwillbetreatedasaNOPifthereisnoopenrowinthat
bank,orifthepreviouslyopenrowisalreadyintheprocessofprecharging.SequencesofPRECHARGE
commandsmustbespacedbyatleasttPPDasshowninFigure69.
Figure 68. PRECHARGE command
Figure 69. Precharge to Precharge Timings
BA=BankAddress(ifA8isLOW;
otherwiseDonʹtCare)
CS#
WE#
CAS#
RAS#
CKE#
A9‐A11(A12)
A0,A1,A6,A7
A8
BA0‐BA3
A2‐A5
LOW
PREALL
PRE
BA
Precharge
CK
CK#
A7
CK#
CK
CMD NOP
BAx,y=bankaddressx,y
ADDR
PRE NOP PRE NOP
BAy
t
PPD
BAx
t
RAS
t
RP
T0 T1 T2 T3 T4
DonʹtCare
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5.14.AUTOPRECHARGE
AutoPrechargeisafeaturewhichperformsthesameindividualbankprechargefunctionasdescribed
above,butwithoutrequiringanexplicitcommand.ThisisaccomplishedbyusingA8(A8=High),to
enableAutoPrechargeinconjunctionwithaspecificREADorWRITEcommand.Aprechargeofthebank
/rowthatisaddressedwiththeREADorWRITEcommandisautomaticallyperformeduponcompletion
ofthereadorwriteburst.AutoPrechargeisnonpersistentinthatitiseitherenabledordisabledforeach
individualREADorWRITEcommand.
AutoPrechargeensuresthataprechargeisinitiatedattheearliestvalidstagewithinaburst.Theuser
mustnotissueanothercommandtothesamebankuntiltheprechargetime(tRP)iscompleted.Thisis
determinedasifanexplicitPRECHARGEcommandwasissuedattheearliestpossibletime,asdescribed
foreachbursttypeintheOPERATIONsectionofthisspecification.
5.15.REFRESH
TheREFRESHcommandisusedduringnormaloperationoftheGDDR5SGRAM.Thecommandisnon
persistent,soitmustbeissuedeachtimearefreshisrequired.AminimumtimetRFCisrequiredbetween
twoREFRESHcommands.Thesameruleappliestoanyaccesscommandaftertherefreshoperation.All
banksmustbeprechargedpriortotheREFRESHcommand.
Therefreshaddressingisgeneratedbytheinternalrefreshcontroller.ThismakestheaddressbitsʺDonʹt
CareʺduringaREFRESHcommand.TheGDDR5SGRAMrequiresREFRESHcyclesatanaverageperi‐
odicintervaloftREFI(max).ThevaluesoftREFIfordifferentdensitiesarelistedinTable6.Toallowfor
improvedefficiencyinschedulingandswitchingbetweentasks,someflexibilityintheabsoluterefresh
intervalisprovided.AmaximumofeightREFRESHcommandscanbepostedtotheGDDR5SGRAM,and
themaximumabsoluteintervalbetweenanyREFRESHcommandandthenextREFRESHcommandis9*
tREFI.
DuringREFRESH,andwhenbitA2inMR5issetto0,WRTR,RDTR,andLDFFcommandsareallowedat
timetREFTRaftertheREFRESHcommand,whichenable(incremental)datatrainingtooccurinparallel
withtheinternalrefreshoperationandthuswithoutlossofperformanceontheinterface.SeeREADTrain‐
ingandWRITETrainingfordetails.
Asimpedanceupdatesfromtheauto‐calibrationenginemayoccurwithanyREFRESHcommand,itissafe
toonlyissueNOPcommandsduringtKOperiodtopreventfalsecommand,addressordatalatching
resultingfromimpedanceupdates.
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Rev. 1.0 /Nov. 2009 105
H5GQ1H24AFR
Figure 70. REFRESH command
Figure 71. Refresh Timings
CS#
WE#
CAS#
RAS#
CKE#
A9‐A11(A12)
A0,A1,A6
A8
BA0‐BA3
A2‐A5
LOW
Refresh
CK
CK#
A7
CK#
CK
CMD
t
KO
DQ
NOP
PRE
ALL
BA=bankaddress;RA=rowaddress
WRTRandRDTRcommandsareallowedduringrefreshunlessdisabledintheModeRegister
REF
ADDR
T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0
NOP
WRTR
NOP NOP NOP NOP NOP ACT
WCK
WCK#
D0
D1
D2
D3
D4
D5
D6
D7
WL=3
t
RP
t
RFC
t
REFTR
DonʹtCare
BA
RA
WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdetermines
theneededoffsetbetweenWCKandCK.
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Rev. 1.0 /Nov. 2009 106
H5GQ1H24AFR
5.16.SELF‐REFRESH
Self‐RefreshcanbeusedtoretaindataintheGDDR5SGRAM,eveniftherestofthesystemispowered
down.WhenintheSelf‐Refreshmode,theGDDR5SGRAMretainsdatawithoutexternalclocking.The
SELFREFRESHENTRYcommand(seeFigure72)isinitiatedlikeaREFRESHcommandexceptthatCKE#
ispulledHIGH.SELFREFRESHENTRYisonlyallowedwhenallbanksareprechargedwithtRPsatisfied,
andwhenthelastdataelementorCRCdataelementfromaprecedingREADorWRITEcommandhave
beenpushedout(tRDSRE).NOPcommandsarerequireduntiltCKSREismetaftertheenteringSelf‐Refresh.
ThePLLisautomaticallydisableduponenteringSelf‐Refreshandisautomaticallyenabledandresetupon
exitingSelf‐Refresh.IftheGDDR5SGRAMentersSelf‐RefreshwiththePLLdisabled,itwillexitSelf‐
RefreshwiththePLLdisabled.
OncetheSELFREFRESHENTRYcommandisregistered,CKE#mustbeheldHIGHtokeepthedevicein
Self‐Refreshmode.WhenthedevicehasenteredtheSelf‐Refreshmode,allexternalcontrolsignals,except
CKE#andRESET#are“Don’tcare”.ForproperSelf‐Refreshoperation,allpowersupplyandreference
pins(VDD,VDDQ,VSS,VSSQ,VREFC,VREFD)mustbeatvalidlevels.TheGDDR5SGRAMinitiatesa
minimumofoneinternalrefreshwithintCKEperiodonceitentersSelf‐Refreshmode.Theaddress,com‐
mand,dataandWCKpinsareinODTstate,andtheEDCpinsdriveaHIGH.
TheclockisinternallydisabledduringSelf‐Refreshoperationtosavepower.Theminimumtimethatthe
GDDR5SGRAMmustremaininSelf‐RefreshmodeistCKE.Theusermaychangetheexternalclockfre‐
quencyorhalttheexternalCKandWCKclockstCKSREafterSelf‐Refreshentryisregistered.However,the
clocksmustberestartedandstabletCKSRXbeforethedevicecanexitSelf‐Refreshoperation.
TheprocedureforexitingSelf‐Refreshrequiresasequenceofevents.First,theCKandWCKclocksmust
bestablepriortoCKE#goingbackLOW.AdelayofatleasttXSNRWmustbesatisfiedbeforeavalidcom‐
mandnotrequiringalockedPLLcanbeissuedtothedevicetoallowforcompletionofanyinternal
refreshinprogress.BeforeacommandrequiringalockedPLLcanbeapplied,adelayofatleasttXSRW
mustbesatisfied.
DuringSelf‐Refreshtheon‐dietermination(ODT)anddriverwillnotbeauto‐calibrated.Therefore,itis
recommendedthattheODTanddriverberecalibratedbythecontrolleruponexitingSelf‐Refresh.Alter‐
natively,ifchangesinvoltageandtemperaturearetrackedorknowntobeboundedthentheprovided
VoltageandTemperatureVariationtablesmaybeconsultedtodetermineifrecalibrationisnecessary.
UponexitfromSelf‐Refresh,theGDDR5SGRAMcanbeputbackintoSelf‐Refreshmodeafterwaitingat
leasttXSNRWperiodandissuingoneextraREFRESHcommand.
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Rev. 1.0 /Nov. 2009 107
H5GQ1H24AFR
Figure 72. SELF REFRESH Entry Command
Figure 73. Self Refresh Entry and Exit
Note:
1.Clock(CKandCK#)mustbestablebeforeexitingselfrefreshmode.
2.Devicemustbeintheallbanksidlestatepriortoenteringselfrefreshmode.
3.tXSNRWisrequiredbeforeanynon‐READorWRITEcommandcanbeapplied,andtXSRWisrequiredbeforeaREADorWRITEcommandcanbe
applied.
4.REF=REFRESHcommand.
CS#
WE#
CAS#
RAS#
CKE#
A9‐A11(A12)
A0,A1,A6
A8
BA0‐BA3
A2‐A5
HIGH
Self‐Refresh
CK
CK#
A7
CK#
CK
CMD
DQ
SRENOP
ADDR
T0 T1 T2 Ta0 Tb2Tb0 Tb1 Td0
SRX PREA Valid
NOP
t
CPDED
CKE#
NOP
t
CKSRE
t
CKSRX
t
RP
Tc0
EnterSelfRefreshModeExitSelfRefreshMode
t
XSNRW
t
XSRW
t
RDSRE
ort
WRSRE
SelfrefreshexitrequiresWCK2CKtrainingpriortoanyWRITEorREADoperation
AtleastoneREFRESHcommandshallbeissuedaftert
XSNRW
foroutputdriverandterminationimpedanceupdates.
NOP
DonʹtCare
t
CMDS
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Rev. 1.0 /Nov. 2009 108
H5GQ1H24AFR
Table 27PinStatesDuringSelfRefresh
Pin State
EDC High
DQ/DBI# ODT
ADR/CMD ODT
CKE# ODT(DrivenHighbyController)
WCK/WCK# ODT
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5.17.POWER‐DOWN
GDDR5SGRAMsrequiresCKE#tobeLOWatalltimesanaccessisinprogress:fromtheissuingofa
READorWRITEcommanduntilcompletionoftheburst.ForREADs,aburstcompletionisdefinedas
whenthelastdataelementincludingCRChasbeentransmittedontheDQoutputs,forWRITEs,aburst
completionisdefinedaswhenthelastdataelementhasbeenwrittentothememoryarrayandCRCdata
hasbeenreturnedtothecontroller.
POWER‐DOWNisenteredwhenCKE#isregisteredHIGH.IfPOWER‐DOWNoccurswhenallbanksare
idle,thismodeisreferredtoasprechargePOWER‐DOWN;ifPOWER‐DOWNoccurswhenthereisarow
activeinanybank,thismodeisreferredtoasactivePOWER‐DOWN.EnteringPOWER‐DOWNdeacti‐
vatestheinputandoutputbuffers,excludingCK,CK#,WCK,WCK#,EDCpinsandCKE#.
Formaximumpowersavings,theuserhastheoptionofdisablingthePLLpriortoenteringPOWER‐
DOWN.Inthatcase,onexitingPOWER‐DOWN,WCK2CKtrainingisrequiredtosettheinternalsynchro‐
nizerswhichwillincludetheenablingofthePLL,PLLreset,andtLKclockcyclesmustoccurbeforeany
READorWRITEcommandcanbeissued.
Whileinpower‐down,CKE#HIGHandstableCKandWCKsignalsmustbemaintainedatthedevice
inputs.TheEDCpinscontinuouslydrivetheEDCholdpattern;ifthecontrollerdoesnotrequireCDR,
usersmayprogramtheEDCholdpatternto’1111’priortoenteringpower‐downmode.POWER‐DOWN
durationislimitedbytherefreshrequirementsofthedevice.
ThePOWER‐DOWNstateissynchronouslyexitedwhenCKE#isregisteredLOW(inconjunctionwitha
NOPorDESELECTcommand).AvalidexecutablecommandmaybeappliedtXPNcycleslater.Themin.
power‐downdurationisspecifiedbytPD.
Figure 74. Power-Down Entry and Exit
Note:
1.MinimumCKE#pulsewidthmustsatisfytCKE.
2.AfterissuingPower‐Downcommand,twomoreNOPsshouldbeissued.
CK#
CK
CMD PDENOP
T0 T1 T2 T3 Tb0Ta1 Ta2
PDX ValidNOP
t
CPDED
CKE#
NOP
t
PD
EnterPower‐DownMode ExitPower‐DownMode
t
XPN
t
RDSRE
ort
WRSRE
WCK
WCK#
NOP
T4 Ta0
DonʹtCare
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Rev. 1.0 /Nov. 2009 110
H5GQ1H24AFR
5.18.COMMANDTRUTHTABLES
Notes:
1.CKE#nisthelogicstateofCKE#atclockedgen;CKE#n‐1wasthestateofCKE#atthepreviousclockedge.
2.CurrentstateisthestateoftheGDDR5SGRAMimmediatelypriortoclockedgen.
3.COMMANDnisthecommandregisteredatclockedgen,andACTIONnisaresultofCOMMANDn.
4.Allstatesandsequencesnotshownareillegalorreserved.
5.DESELECTorNOPcommandsshouldbeissuedonanyclockedgesoccurringduringthetXSRWperiod.AminimumoftLKis
neededforthePLLtolockbeforeapplyingaREADorWRITEcommandifthePLLwasdisabled.
Table 28PinStatesDuringPowerDown
Pin LP2 State
EDC WCK ‘Hold’
noWCK High
DQ/DBI# x ODT
ADR/CMD x ODT
CKE# x ODT(DrivenHighbyController)
WCK/WCK# x ODT
Table 29TruthTable–CKE#
CKE#n‐1CKE#nCURRENT
STATE COMMANDnACTIONnNOTES
HHPower‐Down X MaintainPower‐Down
HHSelfRefresh X MaintainSelfRefresh
HLPower‐Down DESELECTorNOP ExitPower‐Down
HLSelfRefresh DESELECTorNOP ExitSelfRefresh 5
LHAllBanksIdle DESELECTorNOP PrechargePower‐DownEntry
LHBank(s)Active DESELECTorNOP ActivePower‐DownEntry
LHAllBanksIdle REFRESH SelfRefreshEntry
LL See<Link>Table30and
<Link>Table31 1,2,3
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Rev. 1.0 /Nov. 2009 111
H5GQ1H24AFR
Notes
1.ThistableapplieswhenCKE#n‐1wasLOWandCKE#nisLOW(see<Link>Table29)andaftertXSNRhasbeenmet(iftheprevious
statewasselfrefresh).
2.Thistableisbank‐specific,exceptwherenoted(i.e.,thecurrentstateisforaspecificbankandthecommandsshownarethose
allowedtobeissuedtothatbankwheninthatstate).Exceptionsarecoveredinthenotesbelow.
3.Currentstatedefinitions:
Idle:Thebankhasbeenprecharged,andtRPhasbeenmet.
RowActive:Arowinthebankhasbeenactivated,andtRCDhasbeenmet.Nodatabursts/accessesandnoregisteraccessesare
inprogress.
Read:AREADbursthasbeeninitiated,withautoprechargedisabled.
Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled.
4.Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.DESELECTorNOPcommands,orallowable
commandstotheotherbankshouldbeissuedonanyclockedgeoccurringduringthesestates.Allowablecommandstotheother
bankaredeterminedbyitscurrentstateand<Link>Table30,andaccordingto<Link>Table31.
Precharging:StartswithregistrationofaPRECHARGEcommandandendswhentRPismet.OncetRPismet,thebankwillbein
theidlestate.
RowActivating:StartswithregistrationofanACTIVEcommandandendswhentRCDismet.OncetRCDismet,thebankwillbe
inthe“rowactive”state.
Readw/Auto‐PrechargeEnabled:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentRP
hasbeenmet.OncetRPismet,thebankwillbeintheidlestate.
Writew/Auto‐PrechargeEnabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentRP
hasbeenmet.OncetRPismet,thebankwillbeintheidlestate.
5.Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;DESELECTorNOPcommandsmustbeappliedoneach
positiveclockedgeduringthesestates.
Refreshing:StartswithregistrationofaREFRESHcommandandendswhentRCismet.OncetRCismet,theGDDR5SGRAMwill
beintheallbanksidlestate.
AccessingModeRegister:StartswithregistrationofaMODEREGISTERSETcommandandendswhentMRDhasbeenmet.Once
tMRDismet,theGDDR5SGRAMwillbeintheallbanksidlestate.
PrechargingAll:StartswithregistrationofaPRECHARGEALLcommandandendswhentRPismet.OncetRPismet,allbanks
willbeintheidlestate.
READorWRITE:StartswiththeregistrationoftheACTIVEcommandandendsthelastvaliddatanibble.
6.Allstatesandsequencesnotshownareillegalorreserved.
7.Notbank‐specific;requiresthatallbanksareidle,andburstsarenotinprogress.
8.Mayormaynotbebank‐specific;ifmultiplebanksaretobeprecharged,eachmustbeinavalidstateforprecharging.
Table 30TruthTable–CurrentStateBankn–CommandToBankn
CURRENT
STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES
Any H X X X DESELECT(NOP/continuepreviousoperation)
LHHHNOOPERATION(NOP/continuepreviousoperation)
Idle
LLHHACTIVE(selectandactivaterow)
LLLHREFRESH 4
LLLLMODEREGISTERSET 4
RowActive
LHLHREAD(selectcolumnandstartREADburst) 6
LHLL
WRITE(selectcolumnandstartWRITEburst)
(WOM,WSMorWDM) 6
L L H L PRECHARGE(deactivaterowinbankorbanks) 5
Read
(Auto
Precharge
Disabled)
LHLHREAD(selectcolumnandstartnewREADburst) 6
LHLL
WRITE(selectcolumnandstartWRITEburst)
(WOM,WSMorWDM) 6,8
L L H L PRECHARGE(onlyaftertheREADburstiscomplete 5
Write
(Auto
Precharge
Disabled)
(WOM,WSM
orWDM)
LHLHREAD(selectcolumnandstartREADburst) 6,7
LHLL
WRITE(selectcolumnandstartnewWRITEburst)
(WOM,WSMorWDM) 6
L L H L PRECHARGE(onlyaftertheWRITEburstiscomplete) 5,7
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 112
H5GQ1H24AFR
9.ReadsorWriteslistedintheCommand/ActioncolumnincludeReadsorWriteswithautoprechargeenabledandReadsorWrites
withautoprechargedisabled.
10.AWRITEcommandmaybeappliedafterthecompletionoftheREADburst
Notes
1.ThistableapplieswhenCKE#n‐1wasLOWandCKE#nisLOW(see<Link>Table30)andaftertXSNRhasbeenmet(iftheprevious
statewasselfrefresh).
2.WRITEinthistablereferstobothWOM/WOMA,WSM/WSMAandWDM/WDMAcommands
3.Thistabledescribesalternatebankoperation,exceptwherenoted(i.e.,thecurrentstateisforbanknandthecommandsshownare
thoseallowedtobeissuedtobankm,assumingthatbankmisinsuchastatethatthegivencommandisallowable).Exceptions
arecoveredinthenotesbelow.
4.Currentstatedefinitions:
Idle:Thebankhasbeenprecharged,andtRPhasbeenmet.
RowActive:Arowinthebankhasbeenactivated,andtRCDhasbeenmet.Nodatabursts/accessesandnoregisteraccessesare
inprogress.
Read:AREADbursthasbeeninitiated,withautoprechargedisabled.
Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled.
ReadwithAutoPrechargeEnabled:Seefollowingtext
WritewithAutoPrechargeEnabled:Seefollowingtext
4a.Thereadwithautoprechargeenabledorwritewithautoprechargeenabledstatescaneachbebrokenintotwoparts:theaccess
periodandtheprechargeperiod.Forreadwithautoprecharge,theprechargeperiodisdefinedasifthesameburstwas
Table 31TruthTable–CurrentStateBankn–CommandToBankm
CURRENT
STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES
Any H X X X DESELECT(NOP/continuepreviousoperation)
LHH H
NOOPERATION(NOP/continuepreviousoperation)
Idle X X X X AnyCommandOtherwiseAllowedtoBankm
RowActivating,
Active,or
Precharging
LLHH
ACTIVE(selectandactivaterow)
LHL H
READ(selectcolumnandstartREADburst) 6
LHL L
WRITE(selectcolumnandstartWRITEburst)
(WOM,WSMorWDM)
6
LLH L
PRECHARGE
Read
(AutoPrecharge
Disabled)
LLHH
ACTIVE(selectandactivaterow)
LHL H
READ(selectcolumnandstartnewREADburst) 6
LHL L
WRITE(selectcolumnandstartWRITEburst)
(WOM,WSMorWDM)
6
LLH L
PRECHARGE
Write
(AutoPrecharge
Disabled)
LLHH
ACTIVE(selectandactivaterow)
LHL H
READ(selectcolumnandstartREADburst) 6,7
LHL L
WRITE(selectcolumnandstartnewWRITEburst)
(WOM,WSMorWDM)
6
LLH L
PRECHARGE
Read
(WithAuto
Precharge)
LLHH
ACTIVE(selectandactivaterow)
LHL H
READ(selectcolumnandstartnewREADburst) 6
LHL L
WRITE(selectcolumnandstartWRITEburst)
(WOM,WSMorWDM)
6
LLH L
PRECHARGE
Write
(WithAuto
Precharge)
LLHH
ACTIVE(selectandactivaterow)
LHL H
READ(selectcolumnandstartREADburst) 6
LHL L
WRITE(selectcolumnandstartnewWRITEburst)
(WOM,WSMorWDM)
6
LLH L
PRECHARGE
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Rev. 1.0 /Nov. 2009 113
H5GQ1H24AFR
executedwithautoprechargedisabledandthenfollowedwiththeearliestpossiblePRECHARGEcommandthatstillaccesses
allofthedataintheburst.Forwritewithautoprecharge,theprechargeperiodbeginswhentWRends,withtWRmeasuredasif
autoprechargewasdisabled.Theaccessperiodstartswithregistrationofthecommandandendswheretheprechargeperiod
(ortRP)begins.Duringtheprechargeperiodofthereadwithautoprechargeenabledorwritewithautoprechargeenabled
states,ACTIVE,PRECHARGE,READandWRITEcommandstotheotherbankmaybeapplied.Ineithercase,allotherrelated
limitationsapply(e.g.,contentionbetweenreaddataandwritedatamustbeavoided).
4b.TheminimumdelayfromaREADorWRITEcommandwithautoprechargeenabled,toacommandtoadifferentbankis
summarizedbelow.
5.REFRESHandMODEREGISTERSETcommandsmayonlybeissuedwhenallbanksareidle.
6.Allstatesandsequencesnotshownareillegalorreserved.
7.READsorWRITEslistedintheCommand/ActioncolumnincludeREADsorWRITEswithautoprechargeenabledandREADsor
WRITEswithautoprechargedisabled.
*** CL=CASlatency(CL)
BL=Burstlength
WL=WRITElatency
tWTR=tWTRLifBankGroupsenabledandaccesstothesamebankotherwisetWTR=tWTRS
Table 32MinimumDelayBetweenCommandstoDifferentBankswithAutoPrechargeEnabled
FromCommand ToCommand Minimumdelay
(withconcurrentautoprecharge)
WRITE
withAUTO
PRECHARGE
(WOMA)
READorREADwithAUTOPRECHARGE [WLmrs+(BL/4)]tCK+tWTRL***
WRITEorWRITEwithAUTOPRECHARGE
(WOM/WOMA,WSM/WSMAorWDM/WDMA)
2*tCK
PRECHARGE 1tCK
ACTIVE 1tCK
WRITE
withAUTO
PRECHARGE
(WDMA)
READorREADwithAUTOPRECHARGE [WL+(BL/4)]tCK+tWTR***
WRITEorWRITEwithAUTOPRECHARGE
(WOM/WOMA,WSM/WSMAorWDM/WDMA)
2*tCK
PRECHARGE 2tCK
ACTIVE 2tCK
WRITE
withAUTO
PRECHARGE
(WSMA)
READorREADwithAUTOPRECHARGE [WL+(BL/4)]tCK+tWTR***
WRITEorWRITEwithAUTOPRECHARGE
(WOM/WOMA,WSM/WSMAorWDM/WDMA)
3*tCK
PRECHARGE 3tCK
ACTIVE 3tCK
READ
withAUTO
PRECHARGE
READorREADwithAUTOPRECHARGE 2*tCK
WRITEorWRITEwithAUTOPRECHARGE
(WOM/WOMA,WSM/WSMAorWDM/WDMA)
[CLmrs+(BL/4)+2‐WL]*tCK***
PRECHARGE 1tCK
ACTIVE 1tCK
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Rev. 1.0 /Nov. 2009 114
H5GQ1H24AFR
5.19.RDQSMODE
FordeviceoperationatlowerclockfrequenciestheGDDR5SGRAMmaybesetintoRDQSmodeinwhich
aREADDATASTROBE(RDQS)inthestyleofGDDR4willbesentontheEDCpinsalongwiththeREAD
data.ThecontrollerwillusetheRDQStolatchtheREADdata.
RDQSmodeisenteredbysettingtheRDQSModebitA5inModeRegister3(MR3).Whenthebitisset,the
GDDR5SGRAMwillasynchronouslyterminateanyEDCholdpatternanddrivealogicHIGHaftertMRD
atthelatest.AllfeaturescontrolledbyMR4areignoredbyRDQSmode.
READcommandsareexecutedasinnormalmoderegardingcommandtodataoutdelayandpro‐
grammedREADlatencies.Afixedclock‐likepatternasshowninFigure75isdrivenonEDCpinsinphase
(edgealigned)withtheDQ.Priortothefirstvaliddataelement,thisfixedclock‐likepatternorREADpre‐
ambleisdrivenfor2tWCK.
NoCRCiscalculatedinRDQSmode,neitherforREADsnorforWRITEs.TheCRCengineiseffectively
disabled,andthecorrespondingWRCRCandRDCRCModeRegisterbitsareignored.ThePLLmaybeon
oroffwithRDQSmode,dependingonsystemconsiderationsandthePLL’sminimumclockfrequency.
ThereisnoequivalentWDQSmode;WRITEcommandstotheGDDR5SGRAMarenotaffectedbyRDQS
mode.
RDQSmodeisexitedbyresettingtheRDQSModebit.InthiscasetheGDDR5SGRAMwillasynchro‐
nouslystartdrivingtheEDCholdpatternaftertMRD.
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H5GQ1H24AFR
TheWCK2CKtrainingshouldbeperformedpriortoenteringRDQSmode.NoWCK2CKtrainingcanbe
donewhentheRDQSmodeisactive.
Figure 75. RDQS Mode Timings
EDC1andEDC3canbetreatedaspseudo‐differentialtoEDC0andEDC2respectively,bysettingthe
EDC13Invfield,bitA11inMR4,asshowninTable34.
Table 33EDCpinbehaviorinRDQSmodeincludingpseudo‐differentialRDQS
MRSSet READ/RDTR
NOP
(except
RD/RDTR/
PDN/SRF)
POWER‐
DOWN/SELF
REFRESH
RDQSMode WCK2CK
Training EDC13Invert EDC02
Output
EDC13
Output
EDC0123
Output
EDC0123
Output
On Off
Off RDQS RDQS 1111 High
On RDQS Inverted
RDQS 1111 High
CK#
CK
CMD
DQ
NOPMRS
1.MRA=ModeRegisteraddressandopcode;BA=bankaddress;CA=columnaddress
READ
ADDR
MRAMRA
NOP NOP NOP NOP MRS NOP NOP
WCK
WCK#
D0
D1
D2
D3
D4
D5
D6
D7
EDC
CLmrs
BA CA
MRAMRA
t
MRD
EDC
Hold
NOP
t
MRD
EDC
Hold
EnterRDQSMode ExitRDQSMode
T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0
DonʹtCare
3.BeforetheREADcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandtRCDRDmustbemet.
4.tWCK2DQO=0isshownforillustrationpurposes.
2.WCKandCKareshownaligned(tWCK2CKPIN=0,tWCK2CK=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
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H5GQ1H24AFR
5.20.CLOCKFREQUENCYCHANGESEQUENCE
Step1)Waituntilallcommandshavefinished,allbanksareidle.
Step2)SendNOPorDESELECT(mustmeetsetup/holdrelativetoclockwhileclockischanging)to
GDDR5SGRAMfortheentiresequenceunlessstatedtodootherwise.Theusermusttakecareofrefresh
requirements.
Step3)IfthenewdesiredclockfrequencyisbelowtheminfrequencysupportedbyPLL‐onmode,turnthe
PLLoffviaanMRScommand.
Step4)Changetheclockfrequencyandwaituntilclockisstabilized.
Step5)IfthenewclockfrequencyiswithinthePLLonrangeandthePLLonstateisdesired,enablethe
PLLviaanMRSCommandifitisnotalreadyenabled.
Step6)Performaddresstrainingifrequired.
Step7)PerformWCK2CKtraining.AsdefinedintheWCK2CKtrainingprocess,ifthePLLisenabled,
thencompletesteps7aand7b:
7a)ResetthePLLbywritingtotheMRSregister.
7b)WaittLKclockcyclesbeforeissuinganycommandstotheGDDR5SGRAM.
Step8)ExitWCK2CKtraining.
Step9)PerformREADandWRITEtraining,ifrequired.
Step10)GDDR5SGRAMisreadyfornormaloperationafteranynecessaryinterfacetraining.
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H5GQ1H24AFR
5.21.DYNAMICVOLTAGESWITCHING(DVS)
GDDR5SGRAM’sallowthesupplyvoltagetobechangedduringthecourseofnormaloperationusingthe
GDDR5DynamicVoltageSwitching(DVS)feature.ByusingDVStheGDDR5SGRAM’spowerconsump‐
tioncanbereducedwheneveronlyafractionofthemaximumavailablebandwidthisrequiredbythecur‐
rentworkload.
DVSrequirestheGDDR5SGRAMtobeproperlyplacedintoselfrefreshbeforethevoltageischanged
fromtheexisingstablevoltage,VoriginaltothenewdesiredvoltageVnew.TheDVSproceduremayalso
requirechangestotheVDDRangemoderegisterusingMR7bitsA8andA9,dependingonwhetherthe
featureissupported.ThedatasheetshallbeconsultedregardingthesupportedsupplyvoltagesforDVS,
andanydependenciesofACtimingparametersontheselectedsupplyvoltage.
Clockfrequencychangescanalsotakeplacebeforeorafterenteringselfrefreshmodeusingthestandard
ClockFrequencyChangeprocedure.AclockfrequencychangeinconjunctionwithDVSisrequirediftCK
islessthantCKminsupportedbyVnew.Inthiscasenormaldeviceoperationincludingselfrefreshexitis
notguaranteedwithoutafrequencychange.Changingthefrequencywhileinselfrefreshisthemostsafe
procedure.
Onceselfrefreshisentered,tCKSREmustbemetbeforethesupplyvoltageisallowedtotransitionfrom
VoriginaltoVnew.AfterVDDandVDDQarestableatVnew,tVSmustbemettoallowforinternalvoltages
intheGDDR5SGRAMtostabilizebeforeselfrefreshmodemaybeexited.Duringthevoltagetransition
thevoltagemustnotgobelowVminofthelowervoltageofeitherVoriginalorVnewinordertopreventfalse
chipreset.VministheminimumvoltageallowedbyVDDorVDDQintheDCoperatingconditionstable.
VREFshallcontinuetotrackVDDQ.
DVSProcedure
Step1)Completealloperationsandprechargeallbanks.
Step2)IssueanMRScommandtosetVDDRangetopropervaluesforVnew.ThisstepisonlyrequiredwhentheVDD
RangemoderegisterfieldissupportedbytheGDDR5SGRAM.
Step3)Enterselfrefreshmode.Selfrefreshentryproceduremustbemet.
Step4)WaitrequiredtimetCKSREbeforechangingvoltagetoVnew.
Step5)ChangeVDDandVDDQtoVnew.
Step6)WaitrequiredtimetVSforvoltagestabilization.
Step7)Exitselfrefresh.Theselfrefreshexitproceduremustbemet.
Step8)IssueMRScommandstoadjustmoderegistersettingsasdesired(e.g.latencies,PLLon/off,CRCon/off,RDQS
modeon/off).
Step9)Performanyinterfacetrainingasrequired.
Step10)Continuenormaloperation.
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Rev. 1.0 /Nov. 2009 118
H5GQ1H24AFR
Figure 76. DVS Sequence
CK#
CK
CMD SRENOP
T0 T1 T2 Ta0 Tb2Tb0 Tb1 Td0
SRX PREA ValidNOP
t
CPDED
CKE#
NOP
t
CKSRE
t
CKSRX
t
RP
Tc0
EnterSelf‐RefreshModeExitSelf‐RefreshMode
t
XSNRW
t
XSRW
t
RDSRE
ort
WRSRE
SelfrefreshexitrequiresWCK2CKtrainingpriortoanyWRITEorREADoperation
AtleastoneREFRESHcommandshallbeissuedaftert
XSNRW
foroutputdriverandterminationimpedanceupdates
NOP
DonʹtCare
Voltageramp
t
VS
VDD,
VDDQ
V
original
V
new
VSS,VSSQ
V
original
>V
new
shownasanexampleofavoltagechange
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 119
H5GQ1H24AFR
5.22.TEMPERATURESENSOR
GDDR5SGRAMsincorporateatemperaturesensorwithdigitaltemperaturereadoutfunction.Thisfunc‐
tionallowsthecontrollertomonitortheGDDR5SGRAMdie’sjunctiontemperatureandusethisinforma‐
tiontomakesurethedeviceisoperatedwithinthespecifiedtemperaturerangeortoadjustinterface
timingsrelativetotemperaturechangesovertime.
ThetemperaturesensorisenabledbybitA6inModeRegister7(MR7).Inthiscasethetemperatureread‐
outisvalidaftertTSEN.Hynixapplies10ustotTSEN.
ThetemperaturereadoutusestheDRAMInfomodefeature.Thedigitalvalueisdrivenasynchronously
ontheDQbusfollowingtheMRScommandtoModeRegister3(MR3)thatsetsbitA7to1andbitA6to0.
ThetemperaturereadoutwillbecontinuouslydrivenuntilanMRScommandsetsbothbitsto0.
TheGDDR5SGRAM’sjunctiontemperatureislinearlyencodedasshowninTable35.Hynixhastheread‐
outtoasubsetofsixdigitalcodesoutofTable35,correspondingtosixtemperaturethresholds.
Table 34TemperatureSensorReadoutPattern
Temperature[°C]
BinaryTemperatureReadout
MF=0:
MF=1:
DQ[5:0]
DQ[31:26]
＜45 000000
55 000001
65 000011
75 000111
85 001111
95 011111
＞ 95 111111
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Rev. 1.0 /Nov. 2009 120
H5GQ1H24AFR
5.23.DUTYCYCLECORRECTOR(DCC)
AsGDDR5SGRAMscanoperatewiththePLLoffduringnormaloperation,theuseofaDutyCycleCor‐
rector(DCC)cancorrectforthedutycycleoftheWCK.DCCcanbeusedatanytime,however,risingand
fallingedgesofWCKcanbeshiftedaccordingtotheDCCtype.TheDCCshouldbeenabledbeforeWCK
trainingandshouldberunfortDCCinordertoeffectivelycorrectanyerror.
DCCcancorrectthedutycycleerrorwithintherangeof±100ps.
Figure 77. Timing Diagram of DCC Control Signals
DCCcontrolsignals
•DCCreset:TheDCCresetisusedtoinitializetheDCCcodeandshouldbeissuedanytimebeforetheWCK
enables(MRS7A11:1,A10:0)
•DCCstart:TheDCCstartisusedtoupdatetheDCCcodeandshouldbeissuedanytimeaftertheWCKisstable
(MRS7A11:0,A10:1)
•DCC
stop:TheDCCstopisusedtomakeitstoptoupdatetheDCCcodewhiletheDCCcodeisheld.Thisshould
beissuedafterenoughtimefromDCCstartifneeds(MRS7A11:0,A10:0)
Table 35DCCTimings
Parameter Symbol Min Max Unit
Requiredtimefordutycyclecorrector tDCC 150 ‐tCK
Training PLLReset
DCCstart
DCCstopornot
DCCreset
EnterWCK2CK
Training(resetWCK
dividebycircuits)
EnterWCK2CK
Training(setsdata
synchronizers,resets
FIFOpointers)
WCK#
WCK
CK#
CK
CMD
NOP NOP MRS NOP NOP MRS
NOP NOP MRS A.C
.
t
WCKTMRS
t
MRD
t
WCKTTR
t
DCC
t
LK
t
MRD
StartWCK2CKPhase
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H5GQ1H24AFR
Table 36DCCControlSignals
A11 A10 DCC
00 noDCC&DCCstop
01 DCCstart
10 DCCreset
11 RFU
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H5GQ1H24AFR
6.OPERATINGCONDITIONS
6.1.ABSOLUTEMAXIMUMRATINGS
VoltageonVddSupply
RelativetoVss...................................................‐0.5Vto+2.0V
VoltageonVddQSupply
RelativetoVss..................................................‐0.5Vto+2.0V
VoltageonVrefandInputs
RelativetoVss..................................................‐0.5Vto+2.0V
VoltageonI/OPins
RelativetoVss..................................................‐0.5VtoVddQ+0.5V
StorageTemperature(plastic)............................‐55°Cto+150°C
ShortCircuitOutputCurrent.............................50mA
*Stressesgreaterthanthoselistedmaycausepermanentdamagetothedevice.Thisisastressratingonly,andfunctionaloperationof
thedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.
Notes:
1.MeasurementproceduresforeachparametermustfollowstandardproceduresdefinedinthecurrentJEDECJESD‐51standard.
2.Theta_JAmeasuredwiththelowandhighthermalconductivitytestboarddefinedinJESD51‐9
Table 37Capacitance
PARAMETER SYMBOL MIN MAX UNITS NOTES
DeltaInput/OutputCapacitance:DQs,DBI#,EDC,
WCK,WCK# DCio 0 0.5 pF
DeltaInputCapacitance:CommandandAddress DCi100.5pF
DeltaInputCapacitance:CK,CK# DCi200.3pF
Input/OutputCapacitance:DQs,DBI#,EDC,WCK,
WCK# Cio 1.2 1.9 pF
InputCapacitance:CommandandAddress Ci10.9 1.6 pF
InputCapacitance:CK,CK#,WCK,WCK# Ci20.9 1.6 pF
InputCapacitance:CKE# Ci30.9 1.6 pF
Table 38ThermalCharacteristics
Parameter Description Value Units Notes
Theta_JA 1s
Thermalresistancejunctiontoambient
45 oC/W 1,2,4,5
33 oC/W 1,4,5(atTc115oC)
2s2p 30 oC/W 1,2,4,5
Theta_JB Thermalresistancejunctiontoboard 12 oC/W 1,3
Theta_JC Thermalresistancejunctiontocase 3 oC/W 1,6
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3.Theta_JBmeasuredwiththespecialboundaryconditiondefinedinJESD51‐8
4.Theta_JAshouldonlybeusedforcomparingthethermalperformanceofsinglepackageandnotforsystemrelatedjunction.
5.Theta_JAisthenaturalconvectionjunction‐to‐ambientairthermalresistancemeasuredinonecubicfootsealedenclosure
asdecribedinJESD51‐2.
Theenvironmentissometimesreferedtoas“still‐air”althoughnaturalconvectioncausestheairtomove.
6.Theta_JCcasesurfaceisdefinedasthe“outsidesurfaceofthepackage(case)closesttothechipmountingareawhenthat
samesurfaceisproperlyhearsunk”soastominimizetemperaturevariationacrossthatsurface.
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6.2.AC&DCCHARACTERISTICS
AllGDDR5SGRAMsaredesignedfor1.5Vtypicalvoltagesupplies.TheinterfaceofGDDR5with1.5V
VDDQwillfollowthePOD15specification.AllACandDCvaluesaremeasuredattheball.
Notes:
1.VDD/VDDQ1.6Visfor6Gbps
2.GDDR5SGRAMsaredesignedtotoleratePCBdesignswithseparateVDDandVDDQpowerregulators.
3.ACnoiseinthesystemisestimatedat50mVpk‐pkforthepurposeofDRAMdesign.
4.SourceofReferenceVoltageandcontrolofReferenceVoltageforDQandDBI#pinsisdeterminedbyVREFD,HalfVREFD,Auto
VREFD,VREFDMERGEandVREFDOffsetsmoderegisters.
5.VREFDOffsetsarenotsupportedwithVREFD2.
6.ExternalVREFCistobeprovidedbythecontrollerasthereisnootheralternativesupply.
7.DQ/DBI#inputslewratemustbegreaterthanorequalto3V/ns.TheslewrateismeasuredbetweenVREFDcrossingandVIHD(AC)
orVILD(AC)orVREFD2crossingandVIHD2(AC)orVILD2(AC).
8.ADR/CMDinputslewratemustbegreaterthanorequalto3V/ns.TheslewrateismeasuredbetweenVREFCcrossingand
VIHA(AC)orVILA(AC).
9.VIHXandVILXdefinethevoltagelevelsforthereceiverthatdetectsx32orx16modewithRESET#goingHigh.
Table 39DCOperatingConditions
Parameter Symbol Min Typ Max Unit Note
DeviceSupplyVoltage VDD 1.452 1.6 1.648 V 1
OutputSupplyVoltage VDDQ 1.452 1.6 1.648 V 1
DeviceSupplyVoltage VDD 1.455 1.5 1.545 V 2
OutputSupplyVoltage VDDQ 1.455 1.5 1.545 V 2
ReferenceVoltageforDQandDBI#pins VREFD 0.69*VDDQ 0.71*VDDQ V 3,4
ReferenceVoltageforDQandDBI#pins VREFD2 0.49*VDDQ 0.51*VDDQ V 3,4,5
ExternalReferenceVoltageforaddressand
command VREFC 0.69*VDDQ 0.71*VDDQ V 6
DCInputLogicHIGHVoltageforaddressand
command VIHA(DC) VREFC+0.15 V
DCInputLogicLOWVoltageforaddressand
command VILA(DC) VREFC‐0.15 V
DCInputLogicHIGHVoltageforDQandDBI#
pinswithVREFD VIHD(DC) VREFD+0.10 V
DCInputLogicLOWVoltageforDQandDBI#
pinswithVREFD VILD(DC) VREFD‐0.10 V
DCInputLogicHIGHVoltageforDQandDBI#
pinswithVREFD2 VIHD2
(DC) VREFD2+0.30 V
DCInputLogicLOWVoltageforDQandDBI#
pinswithVREFD2 VILD2(DC) VREFD2‐0.30 V
InputLogicHIGHVoltageforRESET#,SEN,MF VIHR VDDQ‐0.50 V
InputLogicLOWVoltageforRESET#,SEN,MF VILR 0.30 V
InputlogicHIGHvoltagefor
EDC1/2(x16modedetect) VIHX VDDQ‐0.3V9
InputlogicLOWvoltagefor
EDC1/2(x16modedetect) VILX 0.30 V9
InputLeakageCurrent
AnyInput0V<=VIN<=VDDQ
(Allotherpinsnotundertest=0V)
Il 10 μA
OutputLeakageCurrent
(DQsaredisabled;0V<=Vout<=VDDQ) Ioz 10 μA
OutputLogicLOWVoltage VOL(DC) 0.62 V
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 125
H5GQ1H24AFR
Figure 78. Voltage Waveform
Table 40ACOperatingConditions
POD15
Parameter Symbol Min Typ Max Unit Note
ACInputLogicHIGHVoltagefor
addressandcommand VIHA(AC) VREFC+0.20 V
ACInputLogicLOWVoltagefor
addressandcommand VILA(AC) VREFC‐0.20 V
ACInputLogicHIGHVoltagefor
DQandDBI#pinswithVREFD VIHD(AC) VREFD+0.15 V
ACInputLogicLOWVoltagefor
DQandDBI#pinswithVREFD VILD(AC) VREFD‐0.15 V
ACInputLogicHIGHVoltagefor
DQandDBI#pinswithVREFD2 VIHD2(AC) VREFD2+0.40 V
ACInputLogicLOWVoltagefor
DQandDBI#pinswithVREFD2 VILD2(AC) VREFD2‐0.40 V
VIL(AC)
VIL(DC)
VREF‐ACNoise
VREF‐DCNoise
VREF+DCNoise
VREF+ACNoise
VIH(DC)
VIH(AC)
VOH
VIN(AC)‐Providesmargin
betweenVOL(MAX)and
VIL(AC)
VDDQ
VOL(MAX)
SystemNoiseMargin(Power/Ground,
Crosstalk,SignalIntegrityAttenuation)
Note:VREF,VIH,VILreferto
whicheverVREFxx(VREFD,
VREFD2,orVREFC)isbeingused.
Output Input
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 126
H5GQ1H24AFR
Notes:
1.Thisprovidesaminimumof0.9Vtoamaximumof1.2V,andisnominally70%ofVDDQwithPOD15.DRAMtimingsrelativeto
CKcannotbeguaranteediftheselimitsareexceeded.
2.ForACoperations,allDCclockrequirementsmustbesatisfiedaswell.
3.ThevalueofVIXCKandVIXWCKisexpectedtoequal70%VDDQforthetransmittingdeviceandmusttrackvariationsintheDC
levelofthesame.
4.VIDCKisthemagnitudeofthedifferencebetweentheinputlevelinCKandtheinputlevelonCK#.Theinputreferencelevelfor
signalsotherthanCKandCK#isVREFC.
5.VIDWCKisthemagnitudeofthedifferencebetweentheinputlevelinWCKandtheinputlevelonWCK#.Theinputreferencelevel
forsignalsotherthanWCKandWCK#iseitherVREFD,VREFD2ortheinternalVREFD.
6.TheCKandCK#inputreferencelevel(fortimingreferencedtoCKandCK#)isthepointatwhichCKandCK#cross.Pleaserefer
totheapplicabletimingsintheACtimingstable(Table44).
7.TheWCKandWCK#inputreferencelevel(fortimingreferencedtoWCKandWCK#)isthepointatwhichWCKandWCK#cross.
PleaserefertotheapplicabletimingsintheACTimingstable(Table44).
8.VREFDiseitherVREFD,VREFD2ortheinternalVREFD.
9.TheslewrateismeasuredbetweenVREFCcrossingandVIXCK(AC).
10.TheslewrateismeasuredbetweenVREFDcrossingandVIXWCK(AC).
11.Figure illustratestheexactrelationshipbetween(CK‐CK#)or(WCK‐WCK#)andVID(AC),VID(DC)andtDVAC
12.RingbackbelowVID(DC)isnotallowed.
13.tDVACisnotmeasuredinandofitselfasacompliancespecification,butisrelieduponinmeasurementofclockoperating
conditionsandclockrelatedparameters.
Table 41ClockInputOperatingConditions
POD15
Parameter Symbol Min Max Unit Note
ClockInputMid‐PointVoltage;CKandCK# VMP(DC) VREFC‐0.10 VREFC+0.10 V 1,6
ClockInputDifferentialVoltage;CKandCK# VIDCK(DC) 0.22 V 4,6
ClockInputDifferentialVoltage;CKandCK#VIDCK(AC) 0.40 V 2,4,6
ClockInputDifferentialVoltage;WCKandWCK# VIDWCK(DC) 0.20 V 5,7
ClockInputDifferentialVoltage;WCKandWCK#VIDWCK(AC) 0.30 2,5,7
ClockInputVoltageLevel;CK,CK#,WCKandWCK#
singleendedVIN ‐0.30 VDDQ+0.30
CK/CK#Singleendedslewrate CKslew 3 V/ns 9
WCK/WCK#Singleendedslewrate WCKslew 3 V/ns 10
ClockInputCrossingPointVoltage;CKandCK# VIXCK(AC) VREFC‐0.12 VREFC+0.12 V 2,3,6
ClockInputCrossingPointVoltage;WCKandWCK# VIXWCK(AC) VREFD‐0.10 VREFD+0.10 V 2,3,7,
8
AllowedtimebeforeringbackofCK/WCKbelow
VIDCK/WCK(AC) tDVAC ps 11,12,
13
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 127
H5GQ1H24AFR
Figure 79. Clock Waveform
VIX(AC)
CK#
CK
MaximumClockLevel
MinimumClockLevel
VID(AC)
VID(DC)
VMP(DC)
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 128
H5GQ1H24AFR
Figure 80. Definition of differential ac-swing and “time above ac-level” tDVAC
0
VID(AC)MIN
tDVAC
tDVAC
halfcycle
time
DifferentialInputVoltage(i.e.WCK‐WCK#,CK‐CK#)
VID(DC)MIN
‐(VID(DC)MIN)
‐(VID(AC)MIN)
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 129
H5GQ1H24AFR
NOTE: MintRCortRFCforIDDmeasurementsisthesmallestmultipleoftCKthatmeetstheminimumoftheabsolutevalueforthe
respectiveparameter.
CommonTestconditions:
1)Deviceisconfiguredtox32mode
2)ABIandDBIareenabled
3)AllODTsareenabledwithZQ/2
4)PLLsareenabledunlessotherwisenoted
5)CRCisenabledforREADsandWRITEs,andtheEDCholdpatternisprogrammedto’1010’
6)BankgroupsareenabledifrequiredfordeviceoperationattCK(min)
7)AddressinputsincludeABI#pin
8)EachdatabyteconsistsofeightDQsandoneDBI#pin
9)DESELECTconditionduringidlecommandcycles
Table 42IDDSpecificationsandTestConditions
PARAMETER/CONDITION SYMBOL NOTES
OneBankActivatePrechargeCurrent:tCK=tCK(min);tWCK=tWCK(min);tRC=tRC(min);CKE#=
LOW;DQ,DBI#areHIGH;randombankandrowaddresses(4addressinputssetLOW)withACT
command
IDD0 1
OneBankActivateReadPrechargeCurrent:tCK=tCK(min);tWCK=tWCK(min);
tRC=tRC(min);CKE#=LOW;onebankactivated;singlereadburstwith50%datatoggleoneachdata
transfer,with4outputsperdatabytedrivenLOW;otherwiseDQ,DBI#areHIGH;randombank,row
andcolumnaddresses(4addressinputssetLOW)withACTandREADcommands;IOUT=0mA
IDD1 1
PrechargePower‐downCurrent:tCK=tCK(min);tWCK=tWCK(min);allbanksidle;
CKE#=HIGH;allotherinputsareHIGH;PLLsareoff IDD2P
PrechargeStandbyCurrent:tCK=tCK(min);tWCK=tWCK(min);allbanksidle;
CKE#=LOW;allotherinputsareHIGH IDD2N
ActivePower‐downCurrent:tCK=tCK(min);tWCK=tWCK(min);onebankactive;
CKE#=HIGH;allotherinputsareHIGH IDD3P
ActiveStandbyCurrent:tCK=tCK(min);tWCK=tWCK(min);onebankactive;
CKE#=LOW;allotherinputsareHIGH IDD3N
ReadBurstCurrent:tCK=tCK(min);tWCK=tWCK(min);CKE#=LOW;onebankineachofthe4bank
groupsactivated;continuousreadburstacrossbankgroupswith50%datatoggleoneachdata
transfer,with4outputsperdatabytedrivenLOW;randombankandcolumnaddresses(4address
inputssetLOW)withREADcommand;IOUT=0mA
IDD4R
WriteBurstCurrent:tCK=tCK(min);tWCK=tWCK(min);CKE#=LOW;onebankineachofthe4bank
groupsactivated;continuouswriteburstacrossbankgroupswith50%datatoggleoneachdata
transfer,with4inputsperdatabytesetLOW;randombankandcolumnaddresses(4addressinputs
setLOW)withWRITEcommand;nodatamask
IDD4W
RefreshCurrent:tCK=tCK(min);tWCK=tWCK(min);tRFC=tRFC(min);CKE#=LOW;
DQ,DBI#areHIGH;addressinputsareHIGH IDD5 1
SelfRefreshCurrent:CKE#=HIGH;allotherinputsareHIGH IDD6
FourBankInterleaveReadCurrent:tCK=tCK(min);tWCK=tWCK(min);CKE#=LOW;
onebankineachofthe4bankgroupsactivatedandprechargedattRC(min);continuousreadburst
acrossbankgroupswith50%datatoggleoneachdatatransfer,with4outputsperdatabytedriven
LOW;randombank,rowandcolumnaddresses(4addressinputssetLOW)withACTandREAD/
READAcommands;IOUT=0mA
IDD7
Rev. 1.0 /Nov. 2009 130
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Table 43. IDD SPECIFICATIONS AND CONDITIONS
Symbol 4.0Gbps 4.5Gbps 5.0Gbps 5.5Gbps 6.0Gbps Units
IDD0 550 590 630 670 710 mA
IDD1 590 630 670 710 750 mA
IDD2P 240 260 280 300 320 mA
IDD2N 260 280 300 320 340 mA
IDD3P 385 405 425 445 465 mA
IDD3N 540 580 620 660 700 mA
IDD4W 1300 1430 1560 1690 1820 mA
IDD4R 1370 1500 1630 1760 1890 mA
IDD5 545 580 615 650 685 mA
IDD6 60 60 60 60 60 mA
IDD7 900 1000 1100 1200 1300 mA
Symbol 4.0Gbps 4.5Gbps 5.0Gbps 5.5Gbps 6.0Gbps Units
IDD0 370 400 420 450 490 mA
IDD1 390 420 450 480 520 mA
IDD2P 170 175 185 195 210 mA
IDD2N 190 200 210 230 250 mA
IDD3P 250 260 275 290 310 mA
IDD3N 350 370 390 420 450 mA
IDD4W 830 910 990 1070 1160 mA
IDD4R 850 930 1010 1090 1080 mA
IDD5 350 370 390 420 450 mA
IDD6 60 60 60 60 60 mA
IDD7 660 710 770 840 910 mA
1. ×32 Mode IDD
2.×16 Mode IDD
Rev. 1.0 /Nov. 2009 131
H5GQ1H24AFR
PARAMETER a, b SYMBOL 6.0Gbps 5.5Gbps UNIT NOTES
MIN MAX MIN MAX
CK and WCK Timings
CK Clock cycle time PLL on tCK 0.667 2 0.727 2 ns
PLL off 0.667 20 0.727 20
CK Clock hi gh - level width tCH 0.4 70 0 .5 30 0 .470 0.530 t C K C
CK Clock low-level width tCL 0.470 0.530 0.470 0.530 tCK C
Min CK Clock half period tHP 0.470 - 0.470 - tCK
Max CK Clock f re quenc y with ba nk gr oup s di sab led fCKBG - 1500 - 1375 MHz d
Max CK Clock freq uency wit h bank group s enabled
and tCCDL=3tCK fCKBG4 - 1500 - 1375 MHz d
Max CK Clock f requency with WCK 2CK alignment
at pins fCKPIN - 1500 - 1375 MHz e
Max CK Clock freque ncy in RDQS Mode fCKRDQS - TBD - TBD MHz f
Max CK Clock frequency for device operation with
VREFD2 fCKVREFD2 - TBD - TBD MHz g
Max CK Clock frequency for WCK-to-CK
auto synchroni zation in WCK2CK training mode fCKAUTOSYNC - 1500 - 1375 MHz h
Max CK Clock frequency for device operation with
Low Frequency Mode enabled fCKLF - 900 - 900 MHz i
WCK Clock cy cle time PLL on tWCK 0.333 1 0.364 1 ns j
PLL off 0.333 10 0.364 10
WCK Clock high-level width tWCKH 0.470 0.530 0.470 0.53 0 tWCK k,l
WCK Clock low-level width tWCKL 0.470 0.530 0.470 0.530 tWCK k,l
Min WCK Clock half period tWCKHP 0.470 - 0.470 - tWCK
Command and Address Input Timings
Command input setup time tCMDS 0.25 - 0.25 - ns m,n
Command input hold time tCMDH 0.25 - 0.25 - ns m,n
Command input pulse width tCMDPW 0.60 - 0.65 - ns m,n,o
Address input s etup time tAS 0.1 - 0.1 - ns m,n,p
Address input hold time tAH 0.1 - 0.1 - ns m,n,p
Address input pulse width tAPW 0.3 - 0.32 - ns m,n,o,p
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 132
H5GQ1H24AFR
PARAMETER a, b SYMBOL 6.0Gbps 5.5Gbps UNIT NOTES
MIN MAX MIN MAX
WCK2CK Timings
WCK stop to MRS dela y fo r entering WCK2CK
training tWCK2MRS 3 - 3 - ns
MRS to WCK restart delay after entering WCK2CK
training tMRSTWCK 10 - 10 - ns q
WCK start to WCK phase mo vement delay tW CK2TR 10 - 10 - tCK
WCK phase change to phase detector out delay tWCK2PH 5 - 5 - ns
WCK Clock high-le ve l width durin g WCK2CK
training tWCKHTR 0.42 0.58 0.42 0.58 tWCK k,l,r
WCK Clock low-level width during WCK2CK
training tWCKLTR 0.42 0.58 0.42 0.58 tWCK k,l,r
WCK2CK offset when zero
offset at phase detector or at
pins
PLL on;MR6A0=0
(at phase dete cto r )
tWCK2CKPIN
-0.2 0.2 -0.2 0.2
ns s
PLL on;MR6A0=1
(at pins) -0.2 0.2 -0.2 0.2
PLL off;MR6A 0=0
(at phase dete cto r ) -0.2 0.2 -0.2 0.2
PLL off;MR6A 0=1
(at pins) -0.2 0.2 -0.2 0.2
WCK2CK phase offset upon
WCK2CK trai ning exit
MR6A0=0
(at phase dete cto r ) tWCK2CKSYNC
-0.25 0.25 -0.25 0.25 tCK
t
MR6A0=1
(at pins) -0.25 0.25 -0.25 0.25 ns
WCK2CK phase offset
MR6A0=0
(at phase dete cto r ) tWCK2CK
-0.4 0.4 -0.4 0.4 tCK
u
MR6A0=1
(at pins) -0.4 0.4 -0.4 0.4 ns
PLL Input and Output T imings
WCK to DQ/DBI# offset for
input data
PLL on tWCK2DQI 0.7 1.7 0.7 1.7 ns v
PLL off 0.7 1.7 0.7 1.7
WCK to DQ/DBI#/EDC/
offset for output data
PLL on tWCK2DQO 1.1 2.2 1.1 2.2 ns w,x
PLL off 1.1 2.2 1.1 2.2
DQ/DBI# input pulse width tDIPW 0.15 - 0.164 - ns y,z,aa
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 133
H5GQ1H24AFR
PARAMETER a, b SYMBOL 6.0Gbps 5.5Gbps UNIT NOTES
MIN MAX MIN MAX
DQ/DBI# data input valid
window
PLL on tDIVW 0.1 - 0.11 - ns y,z,ab
PLL off 0.1 - 0.11 -
DQ/DBI# input ske w w ithin double byte tDQDQI -0.1 0.1 -0.1 0.1 ns ac
DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 -0.125 0.125 ns ad
Row Access Ti mings
Active to Active command period tRC 40 - 40 - ns
Active to PRECHARGE command period tRAS 28 9*tREFI 28 9*tREFI ns ae
Active to READ command delay tRCDRD 12 - 12 - ns
Active to WRITE comma nd delay tRCDWR 10 - 10 - ns
Active to RDTR command delay tRCDRTR 10 - 10 - ns
Active to WRTR command delay tRCDWTR 10 - 10 - ns
Active to LDFF comman d delay tRCDLTR 10 - 10 - ns
REFRESH to RDTR or WRTR command delay tREFTR 10 - 10 - ns
Active bank A to Ac tive bank B command del ay same
bank group tRRDL 5.5 - 5.5 - ns af
Active bank A to Active bank B command delay
different bank groups tRRDS 5.5 - 5.5 - ns ag
Four bank activa te window tFAW 23 - 23 - ns ah
Thirty two ba nk a cti v a te win dow t32AW 184 - 184 - ns ai
READ to PRECHARGE command delay same bank
with bank groups enabled tRTPL 2 - 2 - tCK aj
READ to PRECHARGE command delay same bank
with bank groups disabled tRTPS 2 - 2 - tCK ak
PRECHARGE to PRECHARGE command delay tPPD 1 - 1 - ns
PRECHARGE command period tRP 12 - 12 - ns
WRITE recovery time tWR 12 - 12 - ns
Auto precharge write recovery + prec harge time tDAL 24 - 24 - t CK al
Column Access Timings
RD/WR bank A to RD/WR bank B command delay
same bank group tCCDL 3 - 3 - tCK af,am
RD/WR bank A to RD/WR bank B command delay
different bank groups tCCDS 2 - 2 - tCK ag,an
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 134
H5GQ1H24AFR
PARAMETER a, b SYMBOL 6.0Gbps 5.5Gbps UNIT NOTES
MIN MAX MIN MAX
LDFF to LDFF command cycle time tLTLTR 4 - 4 - tCK
LDFF(111) to LDFF command cycle time t LTL7TR 4 - 4 - tCK ao
LDFF(111 ) to RDTR command cycl e delay tLTRTR 4 - 4 - tCK
READ or RDTR to LD FF comma nd delay tRDTLT 4 - 4 - tCK
WRITE to LDFF command delay tWRTLT WL+5 - WL+5 - tCK
WRTR to RDTR command delay tWTRTR WL-
tWLmin -WL-
tWLmin -tCK
WRITE to WRTR command delay tWRWTR WL+tCR
CWL+2 -WL+tCR
CWL+2 -tCK
Internal WRITE to READ co mmand delay same bank
group tWTRL 5 - 5 - ns af
Internal WRITE to READ command delay different
bank groups tWTRS 5 - 5 - ns ag
READ or RDTR to WRITE or WRTR command
delay tRTW [CLmrs+(BL
/4)+2-
WLmrs]*tC
K
-
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
-tCKap
Write Latency tWL 4 7 4 7 tCK aq
Power-Down and Refresh Timings
CKE# min high and low pulse width tCK E 16 - 14 - tCK
Valid CK Clock requ ired after self refresh entry tCKSRE 16 - 14 - tCK
Valid CK Clock required before self refresh exit tCKSRX 16 - 14 - tCK
READ to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay tRDSRE CL+2tCK - CL+2tCK - tCK ar
WRITE to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay tWRSRETBD-TBD-tCKas
REFRESH command period tRFC 65 - 65 - ns
Exit self refresh to non-READ/WRITE command
delay tXSNRW tRFC - tRFC - ns
Exit self refresh to READ/WRITE command delay tXSRW tRFC+
tRCD -tRFC+
tRCD -tCKat
Refresh period tREF - 3 2 - 32 ms
Average periodic refresh
interval
8k rows tREFI - 3.9 - 3.9 us au
16k rows - 1.9 - 1.9
Min Power down entry to exit time tPD 16 14 tCK
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 135
H5GQ1H24AFR
PARAMETER a, b SYMBOL 6.0Gbps 5.5Gbps UNIT NOTES
MIN MAX MIN MAX
NOP/DESELECT commands require d upon power-
down and self refresh entry tCPDED4-3-tCK
Power down exit time tXPN 17 - 15 - tCK
Miscellaneous Timings
MODE REGISTER SET command period tMRD 4 - 4 - tCK
PLL enabled to PLL lock delay tLK - 5000 - 5000 tCK
PLL standby time tSTDBTY - TBD - TBD us ax
DVS voltage stabilization time tVS TBD - TBD - us
REFRESH to calibration update complete delay tKO - 40 - 40 ns
Active termina tion setup time tATS 10 - 10 - ns
Active termination hold time tATH 10 - 10 - ns
READ to data out dela y in address training mode tADR 0.5*tCK+
00.5*tCK+
10 0.5*tCK+
00.5*tCK+
10 tCK q
Address training exit to DQ in ODT state delay tADZ - 0.5*tCK+
10 -0.5*tCK+
10 ns
Vendor ID on tWRIDON - 11 - 1 1 ns
Venodr ID off tWRIDOFF - 11 - 11 ns
Temperature sensor e nable delay tTSEN 10 - 10 - us
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 136
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PARAMETER a, b SYMBOL 5.0Gbps 4.5Gbps UNIT NOTES
MIN MAX MIN MAX
CK and WCK Timings
CK Clock cycle time PLL on tCK 0.8 2 0.89 2 ns
PLL off 0.8 20 0.89 20
CK Clock hi gh - level width tCH 0.4 70 0 .5 30 0 .470 0.530 t CK C
CK Clock low-level width tCL 0.470 0.530 0.470 0.530 tCK C
Min CK Clock half period tHP 0.470 - 0.470 - tCK
Max CK Clock f re quenc y with ba nk gr oup s di sab led fCKBG - 1250 - 1 1 25 MHz d
Max CK Clock freq uency wit h bank group s enabled
and tCCDL=3tCK fCKBG4 - 1250 - 1125 MHz d
Max CK Clock f requency with WCK 2CK alignment
at pins fCKPIN - 1250 - 1125 MHz e
Max CK Clock freque ncy in RDQS Mode fCKRDQS - TBD - TBD MHz f
Max CK Clock frequency for device operation with
VREFD2 fCKVREFD2 - TBD - TBD MHz g
Max CK Clock frequency for WCK-to-CK
auto synchroni zation in WCK2CK training mode fCKAUTOSYNC - 1250 - 1125 MHz h
Max CK Clock frequency for device operation with
Low Frequency Mode enabled fCKLF - 900 - 900 MHz i
WCK Clock cy cle time PLL on tWCK 0.4 1 0.444 1 ns j
PLL off 0.4 10 0.444 10
WCK Clock high-level width tWCKH 0.470 0.530 0.470 0.53 0 tWCK k,l
WCK Clock low-level width tWCKL 0.470 0.530 0.470 0.530 tWCK k,l
Min WCK Clock half period tWCKHP 0.470 - 0.470 - tWCK
Command and Address Input Timings
Command input setup time tCMDS 0.25 - 0.25 - ns m,n
Command input hold time tCMDH 0.25 - 0.25 - ns m,n
Command input pulse width tCMDPW 0.7 - 0.7 - ns m,n,o
Address input setup time tAS 0.1 - 0.125 - ns m,n,p
Address input ho l d ti me tAH 0.1 - 0.125 - ns m,n,p
Address input pulse width tAPW 0.36 - 0.4 - ns m, n,o,p
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 137
H5GQ1H24AFR
PARAMETER a, b SYMBOL 5.0Gbps 4.5Gbps UNIT NOTES
MIN MAX MIN MAX
WCK2CK Timings
WCK stop to MRS dela y fo r entering WCK2CK
training tWCK2MRS 3 - 3 - ns
MRS to WCK restart delay after entering WCK2CK
training tMRSTWCK 10 - 10 - ns q
WCK start to WCK phase mo vement delay tW CK2TR 10 - 10 - tCK
WCK phase change to phase detector out delay tWCK2PH 5 - 5 - ns
WCK Clock high-le ve l width durin g WCK2CK
training tWCKHTR 0.42 0.58 0.42 0.58 tWCK k,l,r
WCK Clock low-level width during WCK2CK
training tWCKLTR 0.42 0.58 0.42 0.58 tWCK k,l,r
WCK2CK offset when zero
offset at phase detector or at
pins
PLL on;MR6A0=0
(at phase dete cto r )
tWCK2CKPIN
-0.2 0.2 -0.2 0.2
ns s
PLL on;MR6A0=1
(at pins) -0.2 0.2 -0.2 0.2
PLL off;MR6A 0=0
(at phase dete cto r ) -0.2 0.2 -0.2 0.2
PLL off;MR6A 0=1
(at pins) -0.2 0.2 -0.2 0.2
WCK2CK phase offset upon
WCK2CK trai ning exit
MR6A0=0
(at phase dete cto r ) tWCK2CKSYNC
-0.25 0.25 -0.25 0.25 tCK
t
MR6A0=1
(at pins) -0.25 0.25 -0.25 0.25 ns
WCK2CK phase offset
MR6A0=0
(at phase dete cto r ) tWCK2CK
-0.4 0.4 -0.4 0.4 tCK
u
MR6A0=1
(at pins) -0.4 0.4 -0.4 0.4 ns
PLL Input and Output T imings
WCK to DQ/DBI# offset for
input data
PLL on tWCK2DQI 0.7 1.7 0.7 1.7 ns v
PLL off 0.7 1.7 0.7 1.7
WCK to DQ/DBI#/EDC/
offset for output data
PLL on tWCK2DQO 1.1 2.2 1.1 2.2 ns w,x
PLL off 1.1 2.2 1.1 2.2
DQ/DBI# input pulse width tDIPW 0.18 - 0.197 - ns y,z,aa
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 138
H5GQ1H24AFR
PARAMETER a, b SYMBOL 5.0Gbps 4.5Gbps UNIT NOTES
MIN MAX MIN MAX
DQ/DBI# data input valid
window
PLL on tDIVW 0.12 - 0.13 - ns y,z,ab
PLL off 0.12 - 0.13 -
DQ/DBI# input ske w w ithin double byte tDQDQI -0.1 0.1 -0.1 0.1 ns ac
DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 -0.125 0.125 ns ad
Row Access Ti mings
Active to Active command period tRC 40 - 40 - ns
Active to PRECHARGE command period tRAS 28 9*tREFI 28 9*tREFI ns ae
Active to READ command delay tRCDRD 12 - 12 - ns
Active to WRITE comma nd delay tRCDWR 10 - 10 - ns
Active to RDTR command delay tRCDRTR 10 - 10 - ns
Active to WRTR command delay tRCDWTR 10 - 10 - ns
Active to LDFF comman d delay tRCDLTR 10 - 10 - ns
REFRESH to RDTR or WRTR command delay tREFTR 10 - 10 - ns
Active bank A to Ac tive bank B command del ay same
bank group tRRDL 5.5 - 5.5 - ns af
Active bank A to Active bank B command delay
different bank groups tRRDS 5.5 - 5.5 - ns ag
Four bank activa te window tFAW 23 - 23 - ns ah
Thirty two ba nk a cti v a te win dow t32AW 184 - 184 - ns ai
READ to PRECHARGE command delay same bank
with bank groups enabled tRTPL 2 - 2 - tCK aj
READ to PRECHARGE command delay same bank
with bank groups disabled tRTPS 2 - 2 - tCK ak
PRECHARGE to PRECHARGE command delay tPPD 1 - 1 - ns
PRECHARGE command period tRP 12 - 12 - ns
WRITE recovery time tWR 12 - 12 - ns
Auto precharge write recovery + prec harge time tDAL 24 - 24 - t CK al
Column Access Timings
RD/WR bank A to RD/WR bank B command delay
same bank group tCCDL 3 - 3 - tCK af,am
RD/WR bank A to RD/WR bank B command delay
different bank groups tCCDS 2 - 2 - tCK ag,an
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 139
H5GQ1H24AFR
PARAMETER a, b SYMBOL 5.0Gbps 4.5Gbps UNIT NOTES
MIN MAX MIN MAX
LDFF to LDFF command cycle time tLTLTR 4 - 4 - tCK
LDFF(111) to LDFF command cycle time t LTL7TR 4 - 4 - tCK ao
LDFF(111 ) to RDTR command cycl e delay tLTRTR 4 - 4 - tCK
READ or RDTR to LD FF comma nd delay tRDTLT 4 - 4 - tCK
WRITE to LDFF command delay tWRTLT WL+5 - WL+5 - tCK
WRTR to RDTR command delay tWTRTR WL-
tWLmin -WL-
tWLmin -tCK
WRITE to WRTR command delay tWRWTR WL+tCR
CWL+2 -WL+tCR
CWL+2 -tCK
Internal WRITE to READ co mmand delay same bank
group tWTRL 5 - 5 - ns af
Internal WRITE to READ command delay different
bank groups tWTRS 5 - 5 - ns ag
READ or RDTR to WRITE or WRTR command
delay tRTW
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
-
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
-tCKap
Write Latency tWL 3 7 3 7 tCK aq
Power-Down and Refresh Timings
CKE# min high and low pulse width tCK E 12 - 11 - tCK
Valid CK Clock requ ired after self refresh entry tCKSRE 12 - 11 - tCK
Valid CK Clock required before self refresh exit tCKSRX 12 - 11 - tCK
READ to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay tRDSRE CL+2tCK - CL+2tCK - tCK ar
WRITE to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay tWRSRETBD-TBD-tCKas
REFRESH command period tRFC 65 - 65 - ns
Exit self refresh to non-READ/WRITE command
delay tXSNRW tRFC - tRFC - ns
Exit self refresh to READ/WRITE command delay tXSRW tRFC+
tRCD -tRFC+
tRCD -tCKat
Refresh period tREF - 3 2 - 32 ms
Average periodic refresh
interval
8k rows tREFI - 3.9 - 3.9 us au
16k rows - 1.9 - 1.9
Min Power down entry to exit time tPD 12 11 tCK
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 140
H5GQ1H24AFR
PARAMETER a, b SYMBOL 5.0Gbps 4.5Gbps UNIT NOTES
MIN MAX MIN MAX
NOP/DESELECT commands require d upon power-
down and self refresh entry tCPDED3-3-tCK
Power down exit time tXPN 13 - 11 - tCK
Miscellaneous Timings
MODE REGISTER SET command period tMRD 4 - 4 - tCK
PLL enabled to PLL lock delay tLK - 5000 - 5000 tCK
PLL standby time tSTDBTY - TBD - TBD us ax
DVS voltage stabilization time tVS TBD - TBD - us
REFRESH to calibration update complete delay tKO - 40 - 40 ns
Active termina tion setup time tATS 10 - 10 - ns
Active termination hold time tATH 10 - 10 - ns
READ to data out dela y in address training mode tADR 0.5*tCK+
00.5*tCK+
10 0.5*tCK+
00.5*tCK+
10 tCK q
Address training exit to DQ in ODT state delay tADZ - 0.5*tCK+
10 -0.5*tCK+
10 ns
Vendor ID on tWRIDON - 11 - 1 1 ns
Venodr ID off tWRIDOFF - 11 - 11 ns
Temperature sensor e nable delay tTSEN 10 - 10 - us
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 141
H5GQ1H24AFR
PARAMETER a, b SYMBOL 4.0Gbps -UNIT NOTES
MIN MAX MIN MAX
CK and WCK Timings
CK Clock cycle time PLL on tCK 12 ns
PLL off 1 20
CK Clock hi gh - level width tCH 0.4 70 0 .5 30 tCK C
CK Clock low-level width tCL 0.470 0.530 tCK C
Min CK Clock half period tHP 0.470 - tCK
Max CK Clock f re quenc y with ba nk gr oup s di sab led fCKBG - 1000 MHz d
Max CK Clock freq uency wit h bank group s enabled
and tCCDL=3tCK fCKBG4 - 1000 MHz d
Max CK Clock f requency with WCK 2CK alignment
at pins fCKPIN - 1000 MHz e
Max CK Clock frequency in RDQS Mode fCKRDQS - TBD MHz f
Max CK Clock frequency for device operation with
VREFD2 fCKVREFD2 - TBD MHz g
Max CK Clock frequency for WCK-to-CK
auto synchroni zation in WCK2CK training mode fCKAUTOSYNC - 100 MHz h
Max CK Clock frequency for device operation with
Low Frequency Mode enabled fCKLF - 800 MHz i
WCK Clock cy cle time PLL on tWCK 0.5 1 ns j
PLL off 0.5 10
WCK Clock high-level width tWCKH 0.470 0.530 tWCK k,l
WCK Clock low-level width tWCKL 0.470 0.530 tWCK k,l
Min WCK Clock half period tWCKHP 0.470 - tWCK
Command and Address Input Timings
Command input setup time tCMDS 0.25 - ns m,n
Command input hold time tCMDH 0.25 - ns m,n
Command input pulse width tCMDPW 0.7 - ns m,n,o
Address input setup time tAS 0 .1 25 - ns m,n,p
Address input ho l d ti me tAH 0.125 - ns m,n,p
Address input pu lse width tAPW 0 .4 5 - ns m, n,o,p
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 142
H5GQ1H24AFR
PARAMETER a, b SYMBOL 4.0Gbps -UNIT NOTES
MIN MAX MIN MAX
WCK2CK Timings
WCK stop to MRS dela y fo r entering WCK2CK
training tWCK2MRS 3 - ns
MRS to WCK restart delay after entering WCK2CK
training tMRSTWCK 10 - ns q
WCK start to WCK phase mo vement delay t W CK2TR 10 - tCK
WCK phase change to phase detector out delay tWCK2PH 5 - ns
WCK Clock high-le ve l width durin g WCK2CK
training tWCKHTR 0.42 0.58 tWCK k,l,r
WCK Clock low-level width during WCK2CK
training tWCKLTR 0.42 0.58 tWCK k,l,r
WCK2CK offset when zero
offset at phase detector or at
pins
PLL on;MR6A0=0
(at phase dete cto r )
tWCK2CKPIN
-0.2 0.2
ns s
PLL on;MR6A0=1
(at pins) -0.2 0.2
PLL off;MR6A 0=0
(at phase dete cto r ) -0.2 0.2
PLL off;MR6A 0=1
(at pins) -0.2 0.2
WCK2CK phase offset upon
WCK2CK trai ning exit
MR6A0=0
(at phase dete cto r ) tWCK2CKSYNC
-0.25 0.25 tCK
t
MR6A0=1
(at pins) -0.25 0.25 ns
WCK2CK phase offset
MR6A0=0
(at phase dete cto r ) tWCK2CK
-0.4 0.4 tCK
u
MR6A0=1
(at pins) -0.4 0.4 ns
PLL Input and Output T imings
WCK to DQ/DBI# offset for
input data
PLL on tWCK2DQI 0.7 1.7 ns v
PLL off 0.7 1.7
WCK to DQ/DBI#/EDC/
offset for output data
PLL on tWCK2DQO 1.1 2.2 ns w,x
PLL off 1.1 2.2
DQ/DBI# input pulse width tDIPW 0.225 - ns y,z,aa
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 143
H5GQ1H24AFR
PARAMETER a, b SYMBOL 4.0Gbps -UNIT NOTES
MIN MAX MIN MAX
DQ/DBI# data input valid
window
PLL on tDIVW 0.15 - ns y,z,ab
PLL off 0.15 -
DQ/DBI# input ske w within double byte tDQDQI -0.1 0.1 ns ac
DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 ns ad
Row Access Ti mings
Active to Active command period tRC 40 - ns
Active to PRECHARGE command period tRAS 28 9*tREFI ns ae
Active to READ command delay tRCDRD 12 - ns
Active to WRITE comma nd delay tRCDWR 10 - ns
Active to RDTR command delay tRCDRTR 10 - ns
Active to WRTR command delay tRCDWTR 10 - ns
Active to LDFF comman d delay tRCDLTR 10 - ns
REFRESH to RDTR or WRTR command delay tREFTR 10 - ns
Active bank A to Ac tive bank B command del ay same
bank group tRRDL 5.5 - ns af
Active bank A to Active bank B command delay
different bank groups tRRDS 5.5 - ns ag
Four bank activa te window tFAW 23 - ns ah
Thirty two ba nk ac ti v a te win d ow t 32 AW 1 8 4 - ns ai
READ to PRECHARGE command delay same bank
with bank groups enabled tRTPL 2 - tCK aj
READ to PRECHARGE command delay same bank
with bank groups disabled tRTPS 2 - tCK ak
PRECHARGE to PRECHARGE command dela y tPPD 1 - ns
PRECHARGE command period tRP 12 - ns
WRITE recovery time tWR 12 - ns
Auto precharge write recovery + prec harge time tDAL 24 - tCK al
Column Access Timings
RD/WR bank A to RD/WR bank B command delay
same bank group tCCDL 3 - tCK af,am
RD/WR bank A to RD/WR bank B command delay
different bank groups tCCDS 2 - tCK ag,an
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 144
H5GQ1H24AFR
PARAMETER a, b SYMBOL 4.0Gbps -UNIT NOTES
MIN MAX MIN MAX
LDFF to LDFF command cycle time tLTLTR 4 - tCK
LDFF(111) to LDFF command cycle time t LTL7TR 4 - tCK ao
LDFF(111 ) to RDTR command cycl e delay tLTRTR 4 - tCK
READ or RDTR to LD FF comma nd delay tRDTLT 4 - tCK
WRITE to LDFF command delay tWRTLT WL+5 - tCK
WRTR to RDTR command delay tWTRTR WL-
tWLmin -tCK
WRITE to WRTR command delay tWRWTR WL+tCR
CWL+2 -tCK
Internal WRITE to READ co mmand delay same bank
group tWTRL 5 - ns af
Internal WRITE to READ command delay different
bank groups tWTRS 5 - ns ag
READ or RDTR to WRITE or WRTR command
delay tRTW
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
-tCKap
Write Latency tWL 3 7 tCK aq
Power-Down and Refresh Timings
CKE# min high and low pulse width tCKE 10 - tCK
Valid CK Clock requ ired after self refresh entry tCKSRE 10 - tCK
Valid CK Clock required before self refresh exit tCKSRX 10 - tCK
READ to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay tRDSRE CL+2tCK - tCK ar
WRITE to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay tWRSRE TBD - tCK as
REFRESH command period tRFC 65 - ns
Exit self refresh to non-READ/WRITE command
delay tXSNRW tRFC - ns
Exit self refresh to READ/WRITE command delay tXSRW tRFC+
tRCD -tCKat
Refresh period tREF - 3 2 ms
Average periodic refresh
interval
8k rows tREFI -3.9 us au
16k rows - 1.9
Min Power down entry to exit time tPD 10 tCK
Table 44. AC Timings (@1.5V)
Rev. 1.0 /Nov. 2009 145
H5GQ1H24AFR
PARAMETER a, b SYMBOL 4.0Gbps -UNIT NOTES
MIN MAX MIN MAX
NOP/DESELECT commands require d upon power-
down and self refresh entry tCPDED 2 - tCK
Power down exit time tXPN 10 - tCK
Miscellaneous Timings
MODE REGISTER SET command period tMRD 4 - tCK
PLL enabled to PLL lock delay tLK - 5000 tCK
PLL standby time tSTDBTY - TBD us ax
DVS voltage stabilization time tVS TBD - us
REFRESH to calibration update complete delay tKO - 40 ns
Active termina tion setup time tATS 10 - ns
Active termination hold time tATH 10 - ns
READ to data out dela y in address training mode tADR 0.5*tCK+
00.5*tCK+
10 tCK q
Address training exit to DQ in ODT state delay tADZ - 0.5*tCK+
10 ns
Vendor ID on tWRIDON - 11 ns
Venodr ID off tWRIDOFF - 11 ns
Temperature sensor enable delay tTSEN 10 - us
Table 44. AC Timings (@1.5V)
Rev. 1.0/Nov. 2009 146
H5GQ1H24AFR
PARAMETER a, b SYMBOL 3.2Gbps -UNIT NOTES
MIN MAX MIN MAX
CK and WCK Timings
CK Clock cycle time PLL on tCK 1.25 2 ns
PLL off 1.25 20
CK Clock hi gh - level width tCH 0.4 70 0 .5 30 tCK C
CK Clock low-level width tCL 0.470 0.530 tCK C
Min CK Clock half period tHP 0.470 - tCK
Max CK Clock f re quenc y with ba nk gr oup s di sab led fCKBG - 800 MHz d
Max CK Clock freq uency wit h bank group s enabled
and tCCDL=3tCK fCKBG4 - 800 MHz d
Max CK Clock f requency with WCK 2CK alignment
at pins fCKPIN - 800 MHz e
Max CK Clock frequency in RDQS Mode fCKRDQS - TBD MHz f
Max CK Clock frequency for device operation with
VREFD2 fCKVREFD2 - TBD MHz g
Max CK Clock frequency for WCK-to-CK
auto synchroni zation in WCK2CK training mode fCKAUTOSYNC - 800 MHz h
Max CK Clock frequency for device operation with
Low Frequency Mode enabled fCKLF - 700 MHz i
WCK Clock cy cle time PLL on tWCK 0.625 1 ns j
PLL off 0.625 10
WCK Clock high-level width tWCKH 0.470 0.530 tWCK k,l
WCK Clock low-level width tWCKL 0.470 0.530 tWCK k,l
Min WCK Clock half period tWCKHP 0.470 - tWCK
Command and Address Input Timings
Command input se tup time tCMDS 0.3 - ns m,n
Command input hold time tCMDH 0.3 - ns m,n
Command input pulse width tCMDPW 1.0 - ns m,n,o
Address input setup time tAS 0 .1 5 - ns m,n,p
Address input hold time tA H 0.15 - ns m,n,p
Address input pu lse width tAPW 0 .5 5 - ns m, n,o,p
Table 44. AC Timings (@1.35V)
Rev. 1.0/Nov. 2009 147
H5GQ1H24AFR
PARAMETER a, b SYMBOL 3.2Gbps -UNIT NOTES
MIN MAX MIN MAX
WCK2CK Timings
WCK stop to MRS dela y fo r entering WCK2CK
training tWCK2MRS 3 - ns
MRS to WCK restart delay after entering WCK2CK
training tMRSTWCK 10 - ns q
WCK start to WCK phase mo vement delay t W CK2TR 10 - tCK
WCK phase change to phase detector out delay tWCK2PH 5 - ns
WCK Clock high-le ve l width durin g WCK2CK
training tWCKHTR 0.42 0.58 tWCK k,l,r
WCK Clock low-level width during WCK2CK
training tWCKLTR 0.42 0.58 tWCK k,l,r
WCK2CK offset when zero
offset at phase detector or at
pins
PLL on;MR6A0=0
(at phase dete cto r )
tWCK2CKPIN
-0.2 0.2
ns s
PLL on;MR6A0=1
(at pins) -0.2 0.2
PLL off;MR6A 0=0
(at phase dete cto r ) -0.2 0.2
PLL off;MR6A 0=1
(at pins) -0.2 0.2
WCK2CK phase offset upon
WCK2CK trai ning exit
MR6A0=0
(at phase dete cto r ) tWCK2CKSYNC
-0.25 0.25 tCK
t
MR6A0=1
(at pins) -0.25 0.25 ns
WCK2CK phase offset
MR6A0=0
(at phase dete cto r ) tWCK2CK
-0.4 0.4 tCK
u
MR6A0=1
(at pins) -0.4 0.4 ns
PLL Input and Output T imings
WCK to DQ/DBI# offset for
input data
PLL on tWCK2DQI 0.7 1.7 ns v
PLL off 0.7 1.7
WCK to DQ/DBI#/EDC/
offset for output data
PLL on tWCK2DQO 1.1 2.2 ns w,x
PLL off 1.1 2.2
DQ/DBI# input pulse width tDIPW 0.295 - ns y,z,aa
Table 44. AC Timings (@1.35V)
Rev. 1.0/Nov. 2009 148
H5GQ1H24AFR
PARAMETER a, b SYMBOL 3.2Gbps -UNIT NOTES
MIN MAX MIN MAX
DQ/DBI# data input valid
window
PLL on tDIVW 0.19 - ns y,z,ab
PLL off 0.19 -
DQ/DBI# input ske w within double byte tDQDQI -0.1 0.1 ns ac
DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 ns ad
Row Access Ti mings
Active to Active command period tRC 48 - ns
Active to PRECHARGE command period tRAS 32 9*tREFI ns ae
Active to READ command delay tRCDRD 16 - ns
Active to WRITE comma nd delay tRCDWR 14 - ns
Active to RDTR command delay tRCDRTR 16 - ns
Active to WRTR command delay tRCDWTR 14 - ns
Active to LDFF comman d delay tRCDLTR 14 - ns
REFRESH to RDTR or WRTR command delay tREFTR 14 - ns
Active bank A to Ac tive bank B command del ay same
bank group tRRDL 12 - ns af
Active bank A to Active bank B command delay
different bank groups tRRDS 7 - ns ag
Four bank activa te window tFAW 30 - ns ah
Thirty two ba nk ac ti v a te win d ow t 32 AW 2 4 5 - ns ai
READ to PRECHARGE command delay same bank
with bank groups enabled tRTPL 2 - tCK aj
READ to PRECHARGE command delay same bank
with bank groups disabled tRTPS 2 - tCK ak
PRECHARGE to PRECHARGE command dela y tPPD 1 - ns
PRECHARGE command period tRP 16 - ns
WRITE recovery time tWR 16 - ns
Auto precharge write recovery + prec harge time tDAL 32 - tCK al
Column Access Timings
RD/WR bank A to RD/WR bank B command delay
same bank group tCCDL 3 - tCK af,am
RD/WR bank A to RD/WR bank B command delay
different bank groups tCCDS 2 - tCK ag,an
Table 44. AC Timings (@1.35V)
Rev. 1.0/Nov. 2009 149
H5GQ1H24AFR
PARAMETER a, b SYMBOL 3.2Gbps -UNIT NOTES
MIN MAX MIN MAX
LDFF to LDFF command cycle time tLTLTR 4 - tCK
LDFF(111) to LDFF command cycle time t LTL7TR 4 - tCK ao
LDFF(111 ) to RDTR command cycl e delay tLTRTR 4 - tCK
READ or RDTR to LD FF comma nd delay tRDTLT 4 - tCK
WRITE to LDFF command delay tWRTLT WL+5 - tCK
WRTR to RDTR command delay tWTRTR WL-
tWLmin -tCK
WRITE to WRTR command delay tWRWTR WL+tCR
CWL+2 -tCK
Internal WRITE to READ co mmand delay same bank
group tWTRL 5 - ns af
Internal WRITE to READ command delay different
bank groups tWTRS 5 - ns ag
READ or RDTR to WRITE or WRTR command
delay tRTW
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
-tCKap
Write Latency tWL 3 7 tCK aq
Power-Down and Refresh Timings
CKE# min high and low pulse width tCKE 11 - tCK
Valid CK Clock requ ired after self refresh entry tCKSRE 11 - tCK
Valid CK Clock required before self refresh exit tCKSRX 1 1 - tCK
READ to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay tRDSRE CL+2tCK - tCK ar
WRITE to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay tWRSRE TBD - tCK as
REFRESH command period tRFC 120 - ns
Exit self refresh to non-READ/WRITE command
delay tXSNRW tRFC - ns
Exit self refresh to READ/WRITE command delay tXSRW tRFC+
tRCD -tCKat
Refresh period tREF - 3 2 ms
Average periodic refresh
interval
8k rows tREFI -3.9 us au
16k rows - 1.9
Min Power down entry to exit time tPD 11 tCK
Table 44. AC Timings (@1.35V)
Rev. 1.0/Nov. 2009 150
H5GQ1H24AFR
PARAMETER a, b SYMBOL 3.2Gbps -UNIT NOTES
MIN MAX MIN MAX
NOP/DESELECT commands require d upon power-
down and self refresh entry tCPDED 2 - tCK
Power down exit time tXPN 10 - tCK
Miscellaneous Timings
MODE REGISTER SET command period tMRD 4 - tCK
PLL enabled to PLL lock delay tLK - 5000 tCK
PLL standby time tSTDBTY - TBD us ax
DVS voltage stabilization time tVS TBD - us
REFRESH to calibration update complete delay tKO - 40 ns
Active termina tion setup time tATS 10 - ns
Active termination hold time tATH 10 - ns
READ to data out dela y in address training mode tADR 0.5*tCK+
00.5*tCK+
10 tCK q
Address training exit to DQ in ODT state delay tADZ - 0.5*tCK+
10 ns
Vendor ID on tWRIDON - 11 ns
Venodr ID off tWRIDOFF - 11 ns
Temperature sensor enable delay tTSEN 10 - us
a. All parameters assume proper device initialization.
b. Tests for AC timing may be c onsidered at norminal supply voltage levels, but th e related specification a nd device operation a re guaranteed for the full
voltage and temperature range specified.
c. CK and CK# single-e nd ed inpu t slew ra te mu st be grea ter than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIXCK(AC)
d. Parameter fCKBG 4 i s re quire d for those devi ces su ppo rting bo th 3*tC K and 4*t CK setti ng for ba nk group s. Dev ice s sup portin g o nly 3*tCK or 4*tCK
need only to specify fCKBG.
e. Parameter fCKPIN applies when the alignment point in MR6, bit A0 is set to “at pins”, the phase difference between the WCK and CK cloc ks at the
DRAM pins is within tWCK2CKSYNC or tWCK2CK for pin mode and no phase search in WCK2CK training is performed.
f. Parameter fCKRDQS applies when RDQS mode is enabled in AR3, bit A5.
g. Parameter fCKBREFD2 applies whe n the data input reference voltage in MR7, bit A7 (Half VREFD) is set to VREFD2.
h. Parameter fCKAUT OSYNC applies when WCK2CK Auto Synchronization is enabled in MR7, bit A4.
i. Parameter fCKLF applies when Low Frequency Mode is enabled in MR7, bit A3.
j. By definiti on the norminal WCK clock cycle time always is 1/2 of the CK clock cyc le time (not including jitter).
k. WCK and WCK# single-ended input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and
VIXWCK(AC).
Table 44. AC Timings (@1.35V)
Rev. 1.0 /Nov. 2009 151
H5GQ1H24AFR
l. The phase relat ionship between WCK/WCK# and CK/CK# clocks must meet the tWCK2CK specification.
m. Command and address input timings are referenced to VREFC.
n. Command and address input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossi ng and VIHA(AC)
or VILA(AC).
o. Command and address input pulse widths are design targets. The value will be characterized but not tested on each device.
p. Address input timi ngs are only valid with ABI beging enabled and a maximum of 4 address input driven LOW.
q. Parameter may be specified as a combination of tCK and ns.
r. Parameters tWCKHTR and tWCKLTR specify the max. allowed WCK clock-to-clock phase shift during WCK2CK training. For READ and WRITE
bursts use tWCKH and tWCKL.
s. Parameter tWCK2CKPIN defines the WCK2CK phase offset range at the CK and WCK pins for ideal (pha se=0 °) clock alignment at the
GDDR5 SGRAM’s phase detector (when the alignment point in MR6, bit A0 is set to “at phase detector”), or at the WCK and CK pins (when the
alignment in MR6, bit A0 is set to “at pins”). The minimum and maximum values could be negative or positive numbers, dependi ng on the sele cted
WCK2CK alignment point, PLL-on or PLL-off mode and design implementation.
t. Parameter tWCK2CKSYNC defines the max. phase offset from the ideal (phase = 0 °) clock alignment at the GDDR5 SGRAM’s phase
detector (when the alignment point in MR6, bit A0 is set to “at the phase detector”), or at the WCK and CK pins (when the alignment point
in MR6, bit A0 is set to “at pins”), where the internal logic synchronizes the CK and WCK clocks; it is expected to be a fraction of tW CK 2 CK.
u. Parameter tWCK2CK defines the max. phase offset from the ideal (phase = 0 °) clock alignment at the GDDR5 SGRAM’ s phase detector
(when the alignme nt point in MR6, bit A0 is set to “at phase detector”) or at the WCK and CK pins (when the alignment point in MR6, bit A0 is set to
“at pins”), for stable device operation.
v . Par ameter tWCK2DQI defines the WCK to DQ/DBI# time delay range for WRITEs for PLL-on and PLL-of f mode. The minimum and maximum values
could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT .
Data training i s re quired to determine the actual tWCK2DQI value fo r reliable WRITE operation.
w. Parameter tWCK2DQO defines the WCK to DQ/DBI# time delay range for READs for PLL-on and PLL-off mode. The minimum and maxium values
could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT .
Data training is required to determind the actual tWCK2DQO value for reliable READ operation.
x. Outputs measured with equivalent load terminated with 60 Ohms to VDDQ
y. DQ/DBI# input timings are valid only with DBI being enabled and a maximum of 4 data inputs per byte driven LOW.
z. Data input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and VIHD(AC) or VILD(AC).
aa. The data input pulse width, tDIPW, defines the minimum positive or negative input pulse width for any worst-case channel required for proper
propagation of an external signal to the receiver. tDIPW is measured at the pins. tDIPW is independent of the PLL mode.
In general tDIPW is larger than tDIVW
ab. The data inpu t valid width, tDIVW, defines the time region wh ere input data must be va lid for reliable data capture at the receiver for any one worst
case channel. It accounts for jitter between data and clock at the la tching point introduced i n the path between DARM pads and the latching point.
Any additional jit ter introduced into the source signals (e.g. withi n the system before the DRAM pad) must be accounted for in the final ti min g
budget together with the chosen PLL mode an d bandwidth. tDIVW is measured at the pins. tDIVW is define d for PLL off and o n mode separately.
In the case of PLL on, tDIVW must be specified for each supported bandwidth. In general, tDIVW is smaller than tDIPW.
ac. tDQDQI defines the maximum skew among all DQ/ DBI# inputs of a double byte (when configured to ×32 mode) or a single byte (when
configured to ×16 mode) under worst case conditions. Parameter tWCK2DQI define s the mean value of the ea r liest and latest DQ/DBI# pin,
tDQDQI(min) the negative offset to tWCK2DQI for the earliest DQ/DBI# pin and tDQDQI(max) the positive offset to tWCK2DQI for the latest
DQ/DBI# pin.
ad. tDQDQO defines the maximum skew among all DQ/DBI# ou tputs of a double byte (when configured to × 32mode) or a single byte (when
configured to ×16 mode) under worst case con ditions. Parameter tWCK2DQO defines the mean value of of the earliest and latest DQ/DBI#
/EDC pin, tDQDQO(min) the negative offset to tWCK2DQO for earliest DQ/DBI#/EDC pin and tDQDQO(max) th e positive offset to tWCK2DQO
for the latest DQ/DBI#/EDC pin.
ae. For READs and WRITEs with AUTO PRECHARGE enabled the device will hold off the internal PRE CHARGE until tRAS(min) has been satisfied.
af. Parameter applies when bank groups are enabled and consecutive commands access the same bank group.
ag. Parameter applies when bank groups ar e disabled or consecutive commands access different bank group.
ah. Not more than 4 ACTIVE commands are allo we d wi th i n period.
ai. Not more than 32 ACTIVE commands are allowed within t32AW period. The parameter need not to be specified in case t32AW(min) would not be
greater than 8*tFA W(min).
aj. Parameter applies when bank groups are enabled and READ and PRECHARGE commands access the same bank.
ak. Parameter applies when bank groups are disabled or READ and PRECHARGE commands access the same bank.
al. tDAL = (tWR/tCK) + ( tRP/tCK). For each of the terms, if not already an integer, round up to the next integer.
am. tCCDL is either for gapless consecutive READ or gapless consecutive WRITE commands
an. tCCDS is either for gapless consecutive READ or RDTR (any combination), gapless consecutive WRITE, or gapl ess consecutiv e WRTR commands.
ao. The min. value does not exceed 8 tCK
ap. tR TW is not a device limit but determined by the system bus turnaround time. The di fference between tWCK2DQO and tWCK2DQI s hall be consid ered
in the calculation of the bus turnaround time.
Rev. 1.0 /Nov. 2009 152
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aq. The WRITE latency WLmrs cna be set to 3 to 7 clocks. When the WRITE latency is set to small values (3 ~ 4 clocks), the input buffers are alwa ys on,
reduc ing t he lat enc y but a dding po wer. When th e WRITE l ate ncy i s se t to la r g er va lue s (5 ~ 7 cl ocks), t he i npu t buffers are turned on wi th the WRITE
command, thus saving power.
ar. Read data includin g CRC data must hav e be en clocked out before enter ing self refres h or po we r do w n mo de .
as. Write data must have been written to the memory core and CRC data must have been cl ocked out before e ntering self refresh or power down mode.
at. Time for WCK2CK training and data training not included.
au. A maximum of 8 consecutive REFRESH commands can be posted to a GDDR5 SGRAM device, meaning that the maximum absolute interval
between any REFRESH command and the next REFRESH command is 9*tREFI.
av. Replaces parameter tLK when PLL Fast Lock has been neabled prior to the PLL enable or reset.
aw. Replaces parameter tLK when PLL Standby has been enabed and the WCK clock frequency has not charged while in standby mode.
ax. The PLL standby time tSTDBY ismeasured from self refresh entry until after self refresh exit a subsequent PLL reset is give n (with PLL Standby
enabled)
Rev. 1.0 /Nov. 2009 153
H5GQ1H24AFR
Theavailabilityofclock‐to‐data(WCK2DQ)timingsensitivityinformationprovidesthecontrollerthe
opportunitytoanticipatetheimpacttotimingsfromvariationsinenvironmentalconditions(suchas
changesinvoltageortemperature)allowingthecontrollertotakecorrectiveactionifnecessary(e.g.
realigningWCKandDQ).
VariationsinrelativetimingbetweenWCKanddataarereportedforREADandWRITEpaths.Thisspeci‐
ficationcallsoutonezoneeachforVDDQ,VDD,andTcasetemperatureoveraspecifiedrange.Vendors
maychoosetoprovideinformationforadditionalzonescovering,intotal,awiderrangeorafinergranu‐
larityorboth.
However,withinagivenzoneifanapproximatedvalue(i.e.thespecifiedslope)deviatesfromthecharac‐
terizedslopetosuchadegreethattheapproximatedWCK‐to‐DQtimedelaywouldbeinerrorbymore
than5%ofoneUIrelativetothecharacterizeddelaythenthesplittingofthiszoneintomorethanonezone
isrequired.
Allzonesandtheirassociatedspecifiedslopesmustformacontinuouspiece‐wise‐linearcurvesuchthat,
aftercalibrationduringnormaloperation,traversingtheapproximatedcurve(i.e.thesetofspecified
slopes)doesnotleadtotimedelayerrorsinexcessofthe5%ofoneUI.
Tables45,46,and47belowdescribetheminimumsetofdefinedzones.
6.3 CLOCK-TO-DATA TIMING SENSITIVITY
VDDQHigh VDDQLow Notes
Zone_VQ1 VDDQmax VDDQmin a
a.VDDQ(max)isthemaximumspecifiedoperatingvoltage.VDDQ(min)istheminimumspecifiedoperating
voltage.
Table 45. VDDQ Voltage Zone
VDDHigh VDDLow Notes
Zone_VD1 VDDmax VDDmin a
a.VDD(max)isthemaximumspecifiedoperatingvoltage.VDD(min)istheminimumspecifiedoperating
voltage.
Table 46. VDD Voltage Zone
Tca seHigh TcaseLow Notes
Zone_T1 Tcasemax 10°C a
a.Tcase(max)isthemaximumspecifiedoperatingtemperature.
Table 47. Tcase Temperature Zone
Asnoted,variationsinrelativetimingarereportedforREADandWRITEpaths.Tables48,49and50below
provideinformationforREADtimingswhileTables51,52and53provideinformationforWRITEtimings
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 154
H5GQ1H24AFR
Table 48. WCK-to-Data READ Timing Sensitivity to VDDQ
Parameter Symbol Val ues Units Notes
WCK2DQOSensitivitytovariationsinVDDQfor
zone_VQ1
PLLon tO2VQSensZ1
TBD
ps/V a,b
a.CalculationoftO2VQSensZ1isperformedasfollows:
tO2VQSensZ1equalsthequantity(tWCK2DQO(Zone_VQ1(max))‐tWCK2DQO(Zone_VQ1(min)))
dividedby(VDDQ(Zone_VQ1(max))‐VDDQ(Zone_VQ1(min)))
=(tWCK2DQO(VDDQ(max))‐tWCK2DQO(VDDQ(min)))/(VDDQ(max)‐VDDQ(min)).
b.VDD(typ),Tcase=85°C,worst‐caseprocesscorner.
PLLoff TBD
Table 49. WCK-to-Data READ Timing Sensitivity to VDD
Parameter Symbol Value s Units Notes
WCK2DQOSensitivitytovariationsinVDDforzone_VD1
PLLon tO2VDSensZ1
TBD
ps/V a,b
a.CalculationoftO2VDSensZ1isperformedasfollows:
tO2VDSensZ1equalsthequantity(tWCK2DQO(Zone_VD1(max))‐tWCK2DQO(Zone_VD1(min)))
dividedby(VDD(Zone_VD1(max))‐VDD(Zone_VD1(min)))
=(tWCK2DQO(VDD(max))‐tWCK2DQO(VDD(min)))/(VDD(max)‐VDD(min)).
b.VDDQ(typ),Tcase=85°C,worst‐caseprocesscorner.
PLLoff TBD
Table 50. WCK-to-Data READ Timing Sensitivity to Tcase
Parameter Symbol Val ue s Units Notes
WCK2DQOSensitivitytovariationsinTcaseforzone_T1
PLLon tO2TSensZ1
TBD
ps/°C a,b
a.CalculationoftO2TSensZ1isperformedasfollows:
tO2TSensZ1equalsthequantity(tWCK2DQO(Zone_T1(max))‐tWCK2DQO(Zone_T1(min)))
dividedby(Tcase(Zone_T1(max))‐Tcase(Zone_T1(min)))
=(tWCK2DQO(Tcase(max))‐tWCK2DQO(Tcase(min)))/(Tcase(max)‐Tcase(min)).
b.VDDQ(typ),VDD(typ),worst‐caseprocesscorner.
PLLoff TBD
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Rev. 1.0 /Nov. 2009 155
H5GQ1H24AFR
Tables51,52and53belowprovideinformationforWRITEtimings.
.
Table 51. WCK-to-Data WRITE Timing Sensitivity to VDDQ
Parameter Symbol Val ue s Units Notes
WCK2DQISensitivitytovariationsinVDDQforzone_VQ1
PLLon tI2VQSensZ1
TBD
ps/V a,b
a.CalculationoftI2VQSensZ1isperformedasfollows:
tI2VQSensZ1equalsthequantity(tWCK2DQI(Zone_VQ1(max))‐tWCK2DQI(Zone_VQ1(min)))
dividedby(VDDQ(Zone_VQ1(max))‐VDDQ(Zone_VQ1(min)))
=(tWCK2DQI(VDDQ(max))‐tWCK2DQI(VDDQ(min)))/(VDDQ(max)‐VDDQ(min)).
b.VDD(typ),Tcase=85°C,worst‐caseprocesscorner.
PLLoff TBD
Table 52. WCK-to-Data WRITE Timing Sensitivity to VDD
Parameter Symbol Values Units Notes
WCK2DQISensitivitytovariationsinVDDforzone_VD1
PLLon tI2VDSensZ1
TBD
ps/V a,b
a.CalculationoftO2VDSensZ1isperformedasfollows:
tI2VDSensZ1equalsthequantity(tWCK2DQI(Zone_VD1(max))‐tWCK2DQI(Zone_VD1(min)))
dividedby(VDD(Zone_VD1(max))‐VDD(Zone_VD1(min)))
=(tWCK2DQI(VDD(max))‐tWCK2DQI(VDD(min)))/(VDD(max)‐VDD(min)).
b.VDDQ(typ),Tcase=85°C,worst‐caseprocesscorner.
PLLoff TBD
Table 53. WCK-to-Data WRITE Timing Sensitivity to Tcase
Parameter Symbol Value s Units Notes
WCK2DQISensitivitytovariationsinTcaseforzone_T1
PLLon tI2TSensZ1
TBD
ps/°C a,b
a.CalculationoftI2TSensZ1isperformedasfollows:
tI2TSensZ1equalsthequantity(tWCK2DQI(Zone_T1(max))‐tWCK2DQI(Zone_T1(min)))
dividedby(Tcase(Zone_T1(max))‐Tcase(Zone_T1(min)))
=(tWCK2DQI(Tcase(max))‐tWCK2DQI(Tcase(min)))/(Tcase(max)‐Tcase(min)).
b.VDDQ(typ),VDD(typ),worst‐caseprocesscorner.
PLLoff TBD
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 156
H5GQ1H24AFR
7.PACKAGESPECIFICATION
Note) Top View (as seen thru package), MF = LOW (MF = 0)
123 7894 56 1011121314
VSSQ
VSSQ
VDDQ
VDD
VSS
DQ22
DQ20
DQ16
DQ18
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VDDQ DQ23
DQ21
DBI2#
EDC2
DQ19
DQ17
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VDDQ
VREFD
VSS VDD
CKE#
VSS
CAS#
DQ31
DQ4
DQ5
DQ7 DQ6
VDDQ
VSSQ
VDDQ
RAS#
A10
A0
WCK01
DQ0
MF
DQ3 DQ2
VSSQ EDC0
VDDQ DBI0#
VSSQ
VDD
VSS
DQ30
DQ29 DQ28
VDDQ DBI3#
VSSQ
EDC3
DQ24
VDDQ DQ27 DQ26
SEN
RESET#
A
B
C
D
F
G
H
J
E
L
M
K
N
P
T
U
R
VREFC
VREFD
VDD
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VDD
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
ABI#
DQ1
VSSQ
VSSQ
DQ25
VDDQ
VDDQ
VSSQ
A8
A7
VDD
WCK23
VDDQ
VSSQ
VSS
VDD
BA1
A5
VSS
DQ12
DQ14
BA0
A2
DQ8
DQ10
VDD
CK#
VSSQ
VDD
WE#
CS#
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VDDQ
VDDQ
DQ13
DQ15
VDDQ
DQ11
EDC1
DBI1#
ZQ
VDDQ
DQ9
VSSQ
VSSQ
VSS
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDDQ
VSS VDD
BA2
A4
BA3
A3
BYTE0BYTE1
BYTE3x32mode:ON
x16mode:OFF
x32mode:ON
x16mode:ON
VPP,
VDDQ
VSSQ
VDDQ
VDD
VSS
VSSQ
A9
A1
VSS
VSS
VDD
NC
VPP,
NC
WCK01#
A12
RFU,
NC
A11
A6
VSS
WCK23#
CK
VSS
DBI0#
VDDQ
BYTE2
Figure 81. GDDR5 SGRAM 170ball BGA Ball-out MF=0
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 157
H5GQ1H24AFR
Note)TopView(asseenthrupackage),MF=HIGH(MF=1)
123 7894 56 1011121314
VSSQ
VSSQ
VDDQ
VDD
VSS
DQ14
DQ12
DQ8
DQ10
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VDDQ DQ15
DQ13
DBI1#
EDC1
DQ11
DQ9
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VDDQ
VREFD
VSS VDD
CKE#
VSS
RAS#
DQ7
DQ28
DQ29
DQ31 DQ30
VDDQ
VSSQ
VDDQ
CAS#
A10
A0
WCK23
DQ24
MF
DQ27 DQ26
VSSQ EDC3
VDDQ DBI3#
VSSQ
VDD
VSS
DQ6
DQ5 DQ4
VDDQ DBI0#
VSSQ
EDC0
DQ0
VDDQ DQ3 DQ2
SEN
RESET#
A
B
C
D
F
G
H
J
E
L
M
K
N
P
T
U
R
VREFC
VREFD
VDD
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VDD
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ
ABI#
DQ25
VSSQ
VSSQ
DQ1
VDDQ
VDDQ
VSSQ
A8
A7
VDD
WCK01
VDDQ
VSSQ
VSS
VDD
BA3
A3
VSS
DQ20
DQ22
BA2
A4
DQ16
DQ18
VDD
CK#
VSSQ
VDD
CS#
WE#
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VDDQ
VDDQ
VDDQ
DQ21
DQ23
VDDQ
DQ19
EDC2
DBI2#
ZQ
VDDQ
DQ17
VSSQ
VSSQ
VSS
VDDQ
VSSQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDDQ
VSS VDD
BA0
A2
BA1
A5
BYTE3BYTE2
BYTE0BYTE1
x32mode:ON
x16mode:OFF
x32mode:ON
x16mode:ON
VPP,
VDDQ
VSSQ
VDDQ
VDD
VSS
VSSQ
A9
A1
VSS
VSS
VDD
NC
VPP,
NC
WCK23#
A12
RFU,
NC
A11
A6
VSS
WCK01#
CK
VSS
Figure 82. GDDR5 SGRAM 170ball BGA Ball-out MF=1
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 158
H5GQ1H24AFR
7.1.SIGNALS
Table 54. Ball-out Description
SYMBOL TYPE DESCRIPTION
CK,CK# Input Clock:CKandCK#aredifferentialclockinputs.Commandinputsarelatchedontherising
edgeofCK.AddressinputsarelatchedontherisingedgeofCKandtherisingedgeofCK#.
AlllatenciesarereferencedtoCK.CKandCK#areexternallyterminated.
WCK01,
WCK01#,
WCK23,
WCK23#
Input WriteClocks:WCKandWCK#aredifferentialclocksusedforWRITEdatacaptureandREAD
dataoutput.WCK01/WCK01#isassociatedwithDQ0‐DQ15,DBI0#,DBI1#,EDC0andEDC1.
WCK23/WCK23#isassociatedwithDQ16‐DQ31,DBI2#,DBI3#,EDC2andEDC3.
CKE# Input ClockEnable:CKE#LOWactivatesandCKE#HIGHdeactivatestheinternalclock,device
inputbuffers,andoutputdrivers.TakingCKE#HIGHprovidesPRECHARGEPOWER‐
DOWNandSELFREFRESHoperations(allbanksidle),orACTIVEPOWER‐DOWN(row
ACTIVEinanybank).CKE#mustbemaintainedLOWthroughoutreadandwriteaccesses.
ThevalueofCKE#latchedatpower‐upwithRESET#goingHighdeterminesthetermination
valueoftheaddressandcommandinputs.
CS# Input ChipSelect:CS#LOWenablesandCS#HIGHdisablesthecommanddecoder.Allcommands
aremaskedwhenCS#isregisteredHIGH.CS#providesforexternalrankselectiononsystems
withmultipleranks.CS#isconsideredpartofthecommandcode.
RAS#,
CAS#,WE#
Input CommandInputs:RAS#,CAS#,andWE#(alongwithCS#)definethecommandbeing
entered.
BA0–BA3 Input BankAddressInputs:BA0‐BA3definetowhichbankanACTIVE,READ,WRITE,or
PRECHARGEcommandisbeingapplied.BA0‐BA3alsodeterminewhichModeRegisteris
accessedwithanMODEREGISTERSETcommand.BA0‐BA3aresampledwiththerising
edgeofCK.
A0–A11
(A12)
Input AddressInputs:A0‐A11(A12)providetherowaddressforACTIVEcommands,A0‐A5(A6)
providethecolumnaddressandA8definestheautoprechargefunctionforREAD/WRITE
commands,toselectonelocationoutofthememoryarrayintherespectivebank.A8sampled
duringaPRECHARGEcommanddetermineswhetherthePRECHARGEappliestoonebank
(A8LOW,bankselectedbyBA0‐BA3)orallbanks(A8HIGH).Theaddressinputsalso
providetheop‐codeduringaMODEREGISTERSETcommandandthedatabitsduringa
LDFFcommand.A8‐A11(A12)aresampledwiththerisingedgeofCKandA0‐A7are
sampledwiththerisingedgeofCK#.
DQ0–31 I/O DataInput/Output:32‐bitdatabus
DBI#0‐3I/O
DataBusInversion.DBI#0isassociatedwithDQ0‐DQ7,DBI#1isassociatedwithDQ8‐DQ15,
DBI#2isassociatedwithDQ16‐DQ23,DBI#3isassociatedwithDQ24‐DQ31.
EDC0‐3Output
ErrorDetectionCode.ThecalculatedCRCdataistransmittedonthesepins.Inadditionthese
pinsdrivea‘hold’patternwhenidleandcanbeusedasanRDQSfunction.EDC0is
associatedwithDQ0‐DQ7,EDC1isassociatedwithDQ8‐DQ15,EDC2isassociatedwith
DQ16‐DQ23,EDC3isassociatedwithDQ24‐DQ31.
ABI# Input AddressBusInversion
VddQ Supply I/OPowerSupply.Isolatedonthedieforimprovednoiseimmunity.
VssQ Supply I/OGround:Isolatedonthedieforimprovednoiseimmunity.
Vdd Supply PowerSupply
Vss Supply Ground
Vrefd Supply ReferenceVoltageforDQ,DBI#,andEDCpins.
Vrefc Supply ReferenceVoltageforaddressandcommandpins.
Vpp Supply PumpVoltage
MF Reference MirrorFunction:VDDQCMOSinput.Mustbetiedtopowerorground.
ZQ Reference ExternalReferencePinforautocalibration
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 159
H5GQ1H24AFR
Figure clarifiestheuseoftheMF=0andMF=1ball‐outsinx16modeandwhythebytesarerenumberedto
givethecontrollertheviewofthesamebytesthatacontrollerseeswithasinglex32device.Thisisimpor‐
tantforAddressTraining,DMandEDCfunctionality.Formoredetailsseethex16enableandMFenable
section.
RFU ReservedforFutureUse
NC Notconnected
SEN Input Scanenable.VDDQCMOSinput.Mustbetiedtothegroundwhennotinuse.
RESET# Input ResetPin.VDDQCMOSinput.RESET#Lowasynchronouslyinitiatesafullchipreset.With
RESET#LowallODTsaredisabled.
Table 54. Ball-out Description
SYMBOL TYPE DESCRIPTION
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H5GQ1H24AFR
Figure 83. Byte Orientation in Clamshell Topology
x16MF=0x16MF=0
x16MF=1
x16MF=1
0
2
1
3
01
2
3
+=
TopviewthruPCB
(PCBabove)
ControllerviewTopviewthrupackage
(PCBbelow)
DQ
ADDRESS/COMMAND(exceptCS#)
Legend:
CS#
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H5GQ1H24AFR
7.2.ONDIETERMINATION(ODT)
GDDR5SGRAMssupportmultipleterminationmodesforitshighspeedinputsignals.Whenthetermina‐
tionisenabledforareceiver,animpedancedefinedforthatterminationmodeisappliedbetweenthat
inputreceiverandtheVDDQsupplyrail.ThisiscommonlyreferredtoasVDDQtermination.Registers
havebeendefinedtocontroltheterminationmodes.ADD/CMDTerminationiscontrolledusingMR1bits
A4andA5.DataterminationiscontrolledusingMR1bitsA2andA3.WCKterminationiscontrolled
usingMR3bitsA8andA9.
Table55includesallthehighspeedGDDR5SGRAMsignalswhosereceiversincludeondieterminationto
VDDQandwhethertheirterminationcanbedisabledbyADD/CMDTerm,DQTerm,orWCKTerm.A
“Yes”indicateswhetherthemoderegisterfieldcontrolsterminationforthesignal.
Table 55. Signals Affected by Termination Control Registers
ADD/CMDTerm
MR1(A4,A5)
DQTerm
MR1(A2,A3)
WCKTerm
MR3(A8,A9)
Signal x32x16 x32x16x32x16
RAS#,CAS#,WE,CS#,CKE# Yes Yes No No No No
A10/A0,A9/A1,BA0/A2,BA3/A3,
BA2/A4,BA1/A5,A11/A6,A8/A7,
A12/RFU/(NC),ABI# Yes Yes No No No No
DQ[7:0],DBI0# No No Yes Yes No No
DQ[15:8],DBI1# No Disabled Yes Disabled No Disabled
DQ[23:16],DBI2# No No Yes Yes No No
DQ[31:24],DBI3# No Disabled Yes Disabled No Disabled
WCK01,WCK01#,WCK23,WCK23# No No No No Yes Yes
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 162
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7.3.PACKAGEOUTLINE
Figure 84. Package Dimensions
Notes:
1)GDDR5packageheightspecificationiscomplianttoMO‐207RevL,variationDAA‐z
Table 56. Package Height Parameters
Nominal Variation
pkgstandoff 0.350 +/‐0.050
pkgheight 1.100 +/‐0.100
TOPVIEW SIDEVIEW
pkg
standoff
pkg
height
BOTTOMVIEW
(170ball)
13x0.8=10.4
5x0.8=4.0 0.8
12
16x0.8=12.8
14
0.8
pkg
Y
pkg
x
U
T
R
p
N
M
L
K
J
H
G
F
E
D
C
B
A
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H5GQ1H24AFR
7.4.MIRRORFUNCTION(MF)ENABLEandx16MODEENABLE
TheGDDR5SGRAMprovidesamirrorfunction(MF)pintochangethephysicallocationofthecommand,
address,data,andWCKpinsassistinginroutingdevicesbacktoback.TheMFballshouldbetieddirectly
toVSSQorVDDQdependingonthecontrollineorientationdesired.
TheGDDR5SGRAMcanoperateinax32modeorax16modetoallowaclamshellconfigurationwitha
pointtopointconnectiononthehighspeeddatasignal.Thedisabledpinsinx16modeshouldallbeina
Hi‐Zstate,non‐terminating.
Thex16modeisdetectedatpoweruponthepinatlocationC‐13whichisEDC1whenconfiguredtoMF=0
andEDC2whenconfiguredtoMF=1.Forx16modethispinistiedtoVSSQ;thepinispartofthetwobytes
thataredisabledinthismodeandthereforenotneededforEDCfunctionality.Forx32modethispinis
activeandalwaysterminatedtoVDDQinthesystemorbythecontroller.Theconfigurationissetwith
RESET#goingHigh.Oncetheconfigurationhasbeenset,itcannotbechangedduringnormaloperation.
Usuallytheconfigurationisfixedinthesystem.Detailsofthex16modedetectionaredepictedinFigure .
Acomparisonofx32modeandx16modesystemsisshowninFigure .
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H5GQ1H24AFR
Figure 85. Enabling x16 mode
RESET#
RESET# RESET#
RESET#
RESET# RESET#
RESET#
RESET# RESET#
VSSQ
VSSQ
VSSQ
1=x32
0=x16
0=x16
EDC1
EDC
EDC1
RX
enable
Termination
Controller
EDCdatafrom
otherDRAM
VDDQ
VDDQ
VDDQ
RX
RX
Controller
Controller
enable
Termination
EDC2 EDC
EDCdatafrom
otherDRAM
RX
TX
EN
RX D
EDC2
EDC1
EDC
EDC1 TX
EN
RX D
enable
Termination
x16
EDCData
EDCData
x32
EDCData
D
TX
EN
x16
GDDR5
inx16mode
MF=1
GDDR5
inx16mode
MF=0
GDDR5
inx32mode
MF=0or1
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Figure 86. System view for x32 mode vs. x16 mode
Figure86andFigure87showexamplesoftheboardchannelsandtopologiesthataresupportedin
GDDR5inordertoillustratetheexpectedusageofx16modeandtheMFpin.
Table 57. x16 mode and MF
MODE MF EDC1(MF=0)orEDC2(MF=1)
x16non‐mirrored VSSQ VSSQ
x32non‐mirrored VSSQ VDDQ(terminatedbythesystemorcontroller)
x16mirrored VDDQ VSSQ
x32mirrored VDDQ VDDQ(terminatedbythesystemorcontroller)
Byte1
Byte3
Byte2
Byte0
ADD/
CMD
ADD/
CMD
Byte1
Byte3
Byte2
Byte0
DQ0‐DQ7,DBI0#
EDC0
DQ8‐DQ15,DBI1#
EDC1
DQ16‐DQ23,DBI2#
EDC2
DQ24‐DQ31,DBI3#
EDC3
WCK01,WCK01#
WCK23,WCK23#
AddressBus
CommandBus
CK,CK#
GDDR5
x32
CK,CK#
EDC2
EDC1
RESET
RESET#
MF MF
VDDQ
VSSQ
MF
VSSQ
GDDR5
x16
GDDR5
x16
AddressBus
CommandBus
DQ0‐DQ7,DBI0#
EDC0
DQ8‐DQ15,DBI1#
EDC1
DQ16‐DQ23,DBI2#
EDC2
DQ24‐DQ31,DBI3#
EDC3
WCK01,WCK01#
WCK23,WCK23#
Controller
Controller
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responsability for use of circuits described. No patent licenses are implied.
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H5GQ1H24AFR
Figure 87. Example Channel Topologies
ForflexibilityofPCBroutingGDDR5SGRAMdevices,theball‐outincludesdefinitionofbothMF=0and
MF=1.ThefollowingsimpleblockdiagramsinFigure88demonstratesomeoftheflexibilityofPCBrout‐
ing.
(P2P)
32DQ
(P2P)
32DQ
(P22P)
ADD/CMD
16DQ
(P2P)
(P22P)
ADD/CMD
16DQ
64bitchannel
32DQ
32bitchannel
(P2P)
ADD/CMD
(P2P)
(P2P)
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H5GQ1H24AFR
Clamshellconfigurations
Singlesideconfigurations
x32MF=0
x32MF=1
DQ
ADDRESS/COMMAND(exceptCS#)
Legend:
CS#
x16MF=1
x16MF=0
x16MF=0 x16MF=1
x32MF=0 x32MF=0
x16MF=0
x16MF=1
x32MF=0 x32MF=0
Note1:32bitchannelisshownasanexample.
Alsoapplieswithx16ona16bitchannel.
1
1
x32MF=1
x32MF=1
1
x32MF=0
x32MF=0
1
x32MF=0 x32MF=1
x32MF=1 x32MF=1
x32MF=0 x32MF=1
1
x32MF=1 x32MF=1
1
Figure 88. Example GDDR5 PCB Layout Topologies
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H5GQ1H24AFR
BOUNDARY SCAN
TheGDDR5SGRAMincorporatesamodifiedboundaryscantestmode.Thismodedoesnotoperatein
accordancewithIEEEStandard1149.1‐1990.TosavethecurrentGDDR5SGRAM’sball‐out,thismodewill
scantheparalleldatainputandoutputthescanneddataonEDC0locatedatC‐2controlledbyanadd‐on
pin,SENwhichislocatedatJ‐10ofthe170ballpackage.
Scanmodeisentereddirectlyafterpower‐upwhilethedeviceisinresetstate.Thisensuresthatno
unwantedaccesscommandsarebeingexecutedpriortoscanmode.
Boundaryscandoesnotdistinguishbetweenx16andx32modes,anddataiscapturedonallpins.Theuser
hastomakesuretomaskthosebitsinthetestprogramwhicharenotwiredinthesystem.
Fornormaldeviceoperation,i.e.afterscanmodeoperation,itisrequiredthatdevicere‐initialization
occursthroughdevicepower‐downandthenpower‐up.
ItispossibletooperatetheGDDR5SGRAMwithoutusingtheboundaryscanfeature.SENshouldbetied
Lowtopreventthedevicefromenteringtheboundaryscanmode.Theotherpinswhichareusedforscan
mode(RESET#,MF,EDC0andCS#)willbeoperatingasnormalwhenSENisdeasserted.
Note:Whenthedeviceisinscanmode,mirrorfunctionisdisabled(MF=0)andnoneofthepinsareremapped.
Table 58. Boundary Scan Exit Order
BIT# BALL BIT# BALL BIT# BALL BIT# BALL BIT# BALL
1D‐513 J‐325T‐237M‐11 49 E‐13
2D‐414K‐426T‐438M‐13 50 E‐11
3D‐215K‐527U‐239L‐12 51 D‐13
4E‐416L‐328U‐440K‐10 52 C‐13
5E‐217M‐229U‐11 41 K‐11 53 B‐13
6F‐418M‐430U‐13 42 J‐13 54 B‐11
7F‐219N‐231T‐11 43 J‐12 55 A‐13
8G‐320N‐432T‐13 44 J‐11 56 A‐11
9H‐521P‐233R‐13 45 H‐11 57 A‐4
10 H‐422P‐434P‐13 46 H‐10 58 A‐2
11 J‐523P‐535N‐11 47 F‐13 59 B‐4
12 J‐424R‐236N‐13 48 F‐11 60 B‐2
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H5GQ1H24AFR
Notes:
1. WhenSENisasserted,nocommandsaretobeexecutedbytheGDDR5SGRAM.Thisappliestobothuser
commandsandmanufacturingcommandswhichmayexistwhileRESET#isdeasserted.
2. Allscanfunctionalityisvalidonlyaftertheappropriatepower‐up(Steps1‐4ofinitializationsequence).
3.Inscanmode,allODTwillbedisabled.
Table 59. Scan Pin Description
PACKAGE
BALL SYMBOL NORMAL
FUNCTION TYPE DESCRIPTION
J‐2SSHRESET#Input
ScanShift:capturethedatainputfromthepadatlogicLOW
andshiftthedataonthechainatlogicHIGH.
G‐12 SCK CS# Input
ScanClock.Notatrueclock,couldbeasinglepulseorseriesof
pulses.Allscaninputswillbereferencedtotherisingedgeof
thescanclock.
C‐2SOUTEDC0OutputScanOutput.
J‐10 SEN RFU Input ScanEnable:logicHIGHenablesscanmode.Scanmodeis
disabledatlogicLOW.MustbetiedtoVSSQwhennotinuse.
J‐1SOE#MFInput
ScanOutputEnable:enables(registeredLOW)anddisables
(registeredHIGH)SOUTdata.ThispinwillbetiedtoVDDQor
GNDthrougharesistor(typically1KOhm)fornormal
operation.Testerneedstooverdrivethispintoguaranteethe
requiredinputlogiclevelinscanmode.
Table 60. Scan AC Electrical Characteristics
PARAMETER/CONDITION SYMBOL MIN MAX UNIT
SNOTES
Clock
Clockcycletime tSCK 40 ‐ns 1
ScanCommandTime
Scanenablesetuptime tSES 20 ‐ns 1
Scanenableholdtime tSEH 20 ‐ns 1
ScancommandsetuptimeforSSH,SOE#andSOUT tSCS 14 ‐ns 1
ScancommandholdtimeforSSH,SOE#andSOUT tSCH 14 ‐ns 1
ScanCaptureTime
Scancapturesetuptime tSDS 10 ‐ns 1
Scancaptureholdtime tSDH 10 ‐ns 1
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H5GQ1H24AFR
Notes:
1. TheparameterappliesonlywhenSENisasserted.
Figure. 89 Scan Capture Timing
ScanShiftTime
Scanclocktovalidscanoutput tSAC ‐6ns1
Scanclocktoscanoutputhold tSOH 1.5 ‐ns 1
Table 60. Scan AC Electrical Characteristics
PARAMETER/CONDITION SYMBOL MIN MAX UNIT
SNOTES
SCK
SEN
t
SDS
t
SDH
Pins
under
Test
VALID
t
SES
SSH
SOE#
t
SCS
(Low)
Notatrueclock,butasinglepulse
oraseriesofpulses
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H5GQ1H24AFR
Figure. 90 Scan Shift Timing
t
SES
t
SCS
t
SCS
t
SAC
ScanOut
bit1
ScanOut
bit2ScanOut
bit3ScanOut
bit4
t
SOH
SCK
SEN
SOUT
SSH
SOE#
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V
DD
V
DDQ
V
REF
RESET#
(SSHin
ScanMode)
SEN t
SES
SCK
SOE#
t
SAC
SOUT
Pins
under
Test VALID
t
SDS
t
SDH
ScanOut
bit1
t
SCK
200us
Power‐up
VDDstable Don’tCare
t
SCS
t
SCS
t
SCS
BoundaryScanModeRESETatpower‐up
Figure 91. Scan Initialization Sequence
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H5GQ1H24AFR
Figure. 92 Internal Block Diagram
DQ2
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
DQ1
DQ3
WCK01#
SSH,ScanShiftPinRESET#
SCK,ScanClockPinCS#
SOUT,ScanOutPinEDC0
SEN,ScanEnablePinSEN
SOE#,ScanOutputEnablePinMF
Pinsundertest
DedicatedScanDFFpersignalundertest
Signalsinscanchain:
DQ[31:0],EDC[3:1],DBI#[3:0],
WCK01,WCK01#,WCK23,WCK23#,
RAS#,CAS#,WE#,CKE#,ABI#,
A[7:0]***,CK,CK#,ZQ
Note:A[7:0]***aremultiplexedpinsand
representA[12:8]andBA[3:0]
Signalsnotinthescanchain:
VDDQ,VSSQ,VDD,VSS,VREFx