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• AS7C164 (5V version)
• Commercial temperature
• Organization: 8,192 words × 8 bits
• Center power and ground pins
•High speed
- 12/15/20 ns address access time
- 6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 550 mW (AS7C164) / max @ 12 ns
• Low power consumption: STANDBY
- 11 mW (AS7C164) / max CMOS I/O
• 2.0V data retent ion
• Easy memory expansion with CE1, CE2, OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard package
-300 mil SOJ
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
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A
5
A
0
128×64×8
Array
(65,536)
Input buffer
A1
A2
A3
A4
A10
A11
A12
A
6A
7A
8A
9
I/O0
I/O7
VCC
GND
OE
CE1
WE
Column decoder
Row decoder
Control
circuit
Sense amp
CE2
3LQDUUDQJHPHQW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
WE
CE2
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
28-pin PDIP, SOJ (300 mL)
16
15
AS7C164
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-12 -15 -20 Unit
Maximum address access tim e 12 15 20 ns
Maximum output enable access time 6 7 8 ns
Maximum operating current 110 100 90 mA
Maximum CMOS standby current 2.0 2.0 2.0 mA
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The AS7C164 is a high performance CMOS 65,536-bit Static Random Access Memory (SRAM) device organized as 8,192 words × 8 bits. It is
designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6/7/8 ns are ideal for high
performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory systems.
When CE1 is High or CE2 is Low the device enters standby mode. The standard AS7C164 is guaranteed not to exceed 11.0 mW power
consumption in standby mode, and typically requires only 250 µW; it offers 2.0V data retention with maximum power of 120 µW.
A write cycle is accomplished by asserting wr ite enable (WE) and both c hip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is wr itten
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To av oid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enab le (OE) and both chip enables (CE1, CE2), with write enable (WE) High. The chip drives
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active,
output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C164 is packaged in 300 mil SOJ packages.
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NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
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Key: X = Don’t Care, L = Low, H = High
Parameter Device Symbol Min Max Unit
Voltage on VCC relative to GND AS7C164 Vt1 –0.50 +7.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.50 V
Power dissipation PD–1.0W
Storage temperature (plastic) Tstg –65 +150 oC
Ambient temperature with VCC applied Tbias –55 +125 oC
DC current into outputs (low) Iout –20mA
CE1 CE2 WE OE Data Mode
HXXXHigh ZStandby (I
SB, ISB1)
XLXXHigh ZStandby (I
SB, ISB1)
L H H H High Z Output disable (ICC)
LHHLD
out Read (ICC)
LHLXD
in Write (ICC)
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Parameter Device Symbol Min Typical Max Unit
Supply voltage AS7C164 VCC 4.5 5.0 5.5 V
Input voltage AS7C164 VIH 2.2 – VCC+1 V
VIL –0.5*
* VIL min = –3.0V for pulse width less than tRC/2.
–0.8V
Ambient operating tempera ture AS7C164 TA0–70
oC
Parameter Symbol Test Conditions De vice -12 -15 -20 UnitMin Max Min Max Min Max
Input leakage current |ILI|VCC = Max,
VIN = GND to VCC –1–1–1µA
Output leakage current |ILO|VCC = Max,
CE1 = VIH or CE2 = VIL,
VOUT = GND to VCC
–1–1–1µA
Operating po wer supply
current ICC
VCC = Max,
CE1 = VIL, CE2 = V IH,
f = fMax, IOUT = 0 mA AS7C164 – 110 – 100 – 90 mA
Standby power supply
current
ISB
VCC = Max,
CE1 = VIH or CE2 = VIL,
f = fMax
AS7C164 – 30 – 25 – 25 mA
ISB1
VCC = Max,
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V,
VIN ≤ 0.2V or
VIN ≥ VCC–0.2V, f = 0
AS7C164 – 2.0 – 2.0 – 2.0 mA
Output voltage VOL IOL = 8 mA, VCC = Min –0.4–0.4–0.4V
VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 – 2.4 – V
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE1, CE2, WE, OE Vin = 0V 5 pF
I/O capac itanc e CI/O I/O Vin = Vout = 0V 7 pF
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Parameter Symbol -12 -15 -20 Unit NotesMin Max Min Max Min Max
Read cycle time tRC 12 – 15 – 20 – ns
Address access time tAA –12–15–20ns3
Chip enable (CE1) access time tACE1 –12–15–20ns3, 12
Chip enable (CE2) access time tACE2 –12–15–20ns3, 12
Output enable (OE) access time tOE –6–7–8ns
Output hold from address change tOH 3–3–3–ns5
CE1 Low to output in low Z tCLZ1 3 – 3 – 3 – ns 4, 5, 12
CE2 High to output in low Z tCLZ2 3 – 3 – 3 – ns 4, 5, 12
CE1 High to output in high Z tCHZ1 – 3 – 4 – 5 ns 4, 5, 12
CE2 Low to output in high Z tCHZ2 – 3 – 4 – 5 ns 4, 5, 12
OE Low to output in low Z tOLZ 0–0–0–ns4, 5
OE High to output in high Z tOHZ – 3 – 4 – 5 ns 4, 5
Power up time tPU 0 – 0 – 0 – ns 4, 5, 12
Power down time tPD –12–15–20ns4, 5, 12
Undefined/don’t careFalling inputRising input
Address
DOUT Data valid
tOH
tAA
tRC
current
Supply
CE2
OE
DOUT
tOE
tOLZ
tACE1, tACE2 tCH Z1, tCHZ2
tCLZ1, tCLZ2
tPU tPD ICC
ISB
50% 50%
tOHZ
Data valid
tRC1
CE1
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Parameter Symbol -12 -15 -20 Unit NotesMin Max Min Max Min Max
Write cycle time tWC 12 – 15 – 20 – ns
Chip enable (CE1) to write end tCW1 9 – 10 – 12 – ns 12
Chip enable (CE2) to write end tCW2 9 – 10 – 12 – ns 12
Address setup to write end tAW 9 – 10 – 12 – ns
Address setup time tAS 0–0–0– ns12
Write pulse width tWP 8–9–12– ns
Write recovery time tWR 0–0–0– ns
Address hold from write end tAH 0–0–0– ns
Data valid to wr ite end tDW 6–7–8– ns
Data hold time tDH 0–0–0– ns4, 5
Write enable to output in high Z tWZ –5–5–5 ns4, 5
Output activ e from write end tOW 3–3–3– ns4, 5
tAW tAH
tWC
Address
WE
DOUT
tDH
tOW
tDW
tWZ
tWP
tAS
Data valid
DIN
tWR
tAW
Address
CE1
WE
DOUT
tCW 1, tCW2
tWP
tDW tDH
tAH
tWZ
tWC
tAS
CE2
Data valid
DIN
tWR
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1During V
CC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, and C.
4t
CLZ and tCHZ are specified with CL = 5pF as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6WE
is High for read cycle.
7CE1
and OE are Low and CE2 is High for read cycle.
8 Address valid prior to or coincident with CE1 transition Low and CE2 transition High.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be High or CE2 Low dur ing address transition s. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 ha ve identical timing.
13 2V data retention applies to the commercial operating range only.
14 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
P arameter Symbol Test conditions Min Max Unit
VCC for data retention VDR VCC = 2.0V
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V
2.0 – V
Data retention current ICCDR –60µA
Chip enable to data retention time tCDR 0–ns
Operation recovery time tRtRC –ns
VCC
CE1
tR
tCDR
Data retention mode
VCC VCC
VDR ≥ 2.0V
VIH VIH
VDR
CS2
t
R
tCDR
VIH VIH
VDR
-Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2ns
255ΩC(14)
480Ω
DRXW
GND
+5V
Figure B: 5V Output loDG
255ΩC(14)
320Ω
DRXW
GND
+5V
Figure C: 3.3V Output load
168Ω
Thevenin Equivalent:
DRXW +1.728V (5V)
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Supply voltage (V)
MIN MAX
NOMINAL
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized ICC, ISB
Normalized supply current ICC, ISB
Ambient temperature (°C)
–55 80 125
35–10
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized ICC, ISB
Normalized supply current ICC, ISB
vs. ambient temperatur e Ta
vs. supply voltage VCC
ICC
ISB
ICC
ISB
Ambient temperature (°C)
-55 80 125
35-10
0.2
1
0.04
5
25
625
Normalized ISB1 (log scale)
Normalized supply current ISB1
vs. ambient temperature Ta
VCC = VCC(NOMINAL)
Supply voltage (V)
MIN MAX
NOMINAL
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time tAA
Ambient temperature (°C)
–55 80 125
35–10
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time tAA
Cycle frequency (MHz)
075
100
5025
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized ICC
Normalized supply current ICC
vs. ambient temperature Tavs. cycle frequency 1/tRC, 1/tWC
vs. supply voltage VCC
VCC = VCC(NOMINAL)
Ta = 25°C
VCC = VCC(NOMINAL)Ta = 25°C
Output voltage (V) VCC
0
20
60
80
40
100
120
140
Output source current (mA)
Output source current IOH
Output voltage (V) VCC
Output sink current (mA)
Output sink current IOL
vs. output voltage VOL
vs. output voltage VOH
0
20
60
80
40
100
120
140
VCC = VCC(NOMINAL)PL
Ta = 25°C VCC = VCC(NOMINAL)
Ta = 25°C
Capacitance (pF)
0750 1000
500250
0
5
15
20
10
25
30
35
Change in tAA (ns)
Typical access time change ∆tAA
vs. output capacitive loading
VCC = VCC(NOMINAL)
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