© 2006 Microchip Technology Inc. Preliminary DS39663D-page 393
PIC18F87J10
Overflow Inte rru p t ...... ............... ............................. ..151
Resetting, Using the ECCP Special Event Trigger ..154
Special Event Trigger (ECCP) .................................176
TMR1H Register ......................................................151
TMR1L Register .......................................................151
Use as a Clock Source ............................................153
Use as a Real-Time Clock .......................................154
Timer2 .............................................................................. 157
Associ a te d Re g i sters ............. .............................. ....158
Interrupt ....................................................................158
Operation .................................................................157
Output ...................................................................... 158
PR2 Register ............................................................177
TMR2 to PR2 Match Interrupt ..................................177
Timer3 .............................................................................. 159
16-bit Read/Write Mode ...........................................161
Associ a te d Re g i sters ............. ................... ...............161
Operation .................................................................160
Oscillator .......................................................... 159, 161
Overflow Interrupt ............................... .... .. .. .....159, 161
Special Event Trigger (ECCP) .................................161
TMR3H Register ......................................................159
TMR3L Register .......................................................159
Timer4 .............................................................................. 163
Associ a te d Re g i sters ............. .............................. ....164
MSSP Clock Shift ....... .......... ................... ............... ..164
Operation .................................................................163
Postscaler. See Postscaler, Timer4.
PR4 Register ............................................................163
Prescaler. See Prescaler, Timer4.
TMR4 Register .........................................................163
TMR4 to PR4 Match Interrupt ..........................163, 164
Timing Diagrams
A/D Conversion .... .............. ............... .......................376
Asynchronous Reception ...................... ...................248
Asynchronous Transmission ....................................246
Asynchronous Transmission (Back to Back) ...........246
Automatic Baud Rate Calculation ............................244
Auto-Wake-up Bit (WUE) During Normal Operation 249
Auto-Wake-up Bit (WUE) During Sleep ...................249
Baud Rate Generator with Clock Arbitration ............221
BRG Overflow Sequence .........................................244
BRG Reset Due to SDAx Arbitration During Start Condi-
tion ................................................................... 230
Bus Collision During a Repeated Start Condition (Case
1) ......................................................................231
Bus Collision During a Repeated Start Condition (Case
2) ......................................................................231
Bus Collision During a Start Condition (SCLx = 0) ..230
Bus Collision During a Stop Condition (Case 1) ......232
Bus Collision During a Stop Condition (Case 2) ......232
Bus Collision During Start Condition (SDAx Only) ...229
Bus Collision for Transmit and Acknowledge ...........228
Capture/Compare/PWM (Including ECCP Modules) 366
CLKO and I/O ..........................................................361
Clock Synchronization .............................................214
Clock/Instruction Cycle ..............................................62
EUSART Synchronous Receiv e (Mast er/ Slave) ......375
EUSART Synchronous T ransm ission (Mas ter/Slav e) ....
375
Example SPI Master Mode (CK E = 0) .....................367
Example SPI Master Mode (CK E = 1) .....................368
Example SPI Slave Mode (CKE = 0) .......................369
Example SPI Slave Mode (CKE = 1) .......................370
External Clock (All Modes Except PLL) ...................359
External Memory Bus fo r Sleep ( Extended Mic rocont rol-
ler Mode) ................................ .. ........... .. .... 98, 100
External Memory Bus for TBLRD (Extended Microcon-
troller Mode) .............................................. 98, 100
Fail-Safe Clock Monitor ........................................... 287
First Start Bit Timing .... ....................... ..................... 222
Full-Bridge PWM Output ...................................... .... 181
Half-Bridge PWM Output ......................................... 180
I2C Acknowledge Sequence .................................... 227
I2C Bus Data ............................................................ 371
I2C Bus Start/Stop Bits ............................................ 371
I2C Master Mode (7 or 10-bit Transmission) ........... 225
I2C Master Mode (7-bit Reception) .......................... 226
I2C Slave Mode (10-bit Reception, SEN = 0) .......... 211
I2C Slave Mode (10-bit Reception, SEN = 0, ADMSK =
01001) ............................................................. 210
I2C Slave Mode (10-bit Reception, SEN = 1) .......... 216
I2C Slave Mode (10-bit Transmission) ..................... 212
I2C Slave Mode (7-bit Reception, SEN = 0) ............ 207
I2C Slave Mode (7-bit Reception, SEN = 0, ADMSK =
01011) ............................................................. 208
I2C Slave Mode (7-bit Reception, SEN = 1) ............ 215
I2C Slave Mode (7-bit Transmission) . ...................... 209
I2C Slave Mode General Call Address Sequence (7 or
10-bit Address Mode) ....... ................... ............ 217
I2C Stop Condition Receive or Transmit Mode ........ 227
Master SSP I 2C Bus Data ....................................... 373
Master SSP I 2C Bus Start/Stop Bits ........................ 373
Parallel Slave Port (PSP) Read ............................... 146
Parallel Slave Port (PSP) Write ............................... 145
Program Memory Read ........................................... 362
Program Memory Write ........................................... 363
PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Dis-
abled) .............................................................. 186
PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart En-
abled) .............................................................. 186
PWM Direction Change ......................................... .. 183
PWM Direction Change at Near 100% Duty Cycle . . 183
PWM Output .... ................... ............................. ........ 170
Repeated Start Condition ............... .... ..... .. .. .. .. .. .. .... 223
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) ............... 364
Send Break Character Sequenc e ............................ 250
Slave Synchron i zation ...................... ....................... 195
Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT)
........................................................................... 47
SPI Mode (Master Mode) ........................................ 194
SPI Mode (Slave Mode, CKE = 0) ........................... 196
SPI Mode (Slave Mode, CKE = 1) ........................... 196
Synchronous Reception (Master Mode, SREN) ...... 253
Synchronous Transmission ..................................... 251
Synchronous Transmiss ion (Through TXEN) . ......... 252
Time-out Sequence on Power-up (MCLR Not Tied to
VDD), Case 1 ..................................................... 46
Time-out Sequence on Power-up (MCLR Not Tied to
VDD), Case 2 ..................................................... 47
Time-out Sequence on Power-up (MCLR Tied to VDD,
VDD Rise < TPWRT) ............................................ 46
Timer0 and Timer1 External Clock .......................... 365
Transition for Entry to Idle Mode ........................... .. .. 40
Transition for Entry to SEC_RUN Mode .......... .. .. .... .. 37
Transition for Entry to Sleep Mode ... .. ....... .. .. .. .... .. .. .. 39
Transition for Two-Speed Start-up (INTRC to HSPLL) ..
285
Transition for Wake from Idle to Run Mode ............... 40