FUJITSU SEMICONDUCTOR DATA SHEET DS05-50202-3E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 16M ( x 8/ x 16) FLASH MEMORY & 4M ( x 8/ x 16) STATIC RAM MB84VD2118XA-85/MB84VD2119XA-85 FEATURES * Power supply voltage of 2.7 V to 3.6 V * High performance 85 ns maximum access time * Operating Temperature -25 C to +85 C * Package 69-ball FBGA, 56-pin TSOP(I) (Continued) PRODUCT LINE UP Flash Memory Ordering Part No. VCCf*, VCCs* = 3.0 V +0.6 V -0.3 V SRAM MB84VD2118XA-85/MB84VD2119XA-85 Max. Address Access Time (ns) 85 85 Max. CE Access Time (ns) 85 85 Max. OE Access Time (ns) 35 45 *: Both VCCf and VCCs must be in recommended operation range when either part is being accessed. PACKAGES 69-ball plastic FBGA 56-pin plastic TSOP(I) (BGA-69P-M02) (FPT-56P-M04) MB84VD2118XA-85/MB84VD2119XA-85 (Continued) 1. FLASH MEMORY * Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to "PIN DESCRIPTION") Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program * Minimum 100,000 write/erase cycles * Sector erase architecture Eight 4 K words and thirty one 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture MB84VD2118XA : Top sector MB84VD2119XA : Bottom sector * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCCf write inhibit 2.5 V * Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status (MB84VD2118XA : SA37, SA38 MB84VD2119XA : SA0, SA1) At VIH, allows removal of boot sector protection At VACC, program time will reduce by 40%. * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Please refer to "MBM29DL16XTD/BD" data sheet in detailed function 2. SRAM * Power dissipation Operating : 40 mA Max. Standby : 7 A Max. * Power down features using CE1s and CE2s * Data retention supply voltage : 1.5 V to 3.6 V * CE1s and CE2s Chip Select * Byte data control : LBs (DQ0 to DQ7) , UBs (DQ8 to DQ15) *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MB84VD2118XA-85/MB84VD2119XA-85 PIN ASSIGNMENTS (Top View) A N.C. B N.C. N.C. N.C. N.C. A7 LBS WP/ ACC WE A8 A11 C A3 A6 UBS RESET CE2S A19 A12 A15 D A2 A5 A18 RY/BY N.C. A9 A13 N.C. E N.C. A1 A4 A17 A10 A14 N.C. N.C. F N.C. A0 VSS DQ1 DQ6 SA A16 N.C. G CEf OE DQ9 DQ3 DQ4 DQ13 DQ15/ A-1 CIOf H CE1S DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS DQ8 DQ2 DQ11 CIOS DQ5 DQ14 N.C. N.C. 5 6 J K N.C. 1 2 3 4 N.C. 7 8 9 10 (BGA-69P-M02) 3 MB84VD2118XA-85/MB84VD2119XA-85 (Top View) N.C. 1 56 A16 A15 2 55 CIOf A14 3 54 VSS A13 4 53 SA A12 5 52 DQ15/A-1 A11 6 51 DQ7 A10 7 50 DQ14 A9 8 49 DQ6 A8 9 48 DQ13 A19 10 47 DQ5 N.C. 11 46 DQ12 WE 12 45 DQ4 CE2s 13 44 CIOs RESET 14 43 VCCs WP/ACC 15 42 VCCf RY/BY 16 41 DQ11 UBs 17 40 DQ3 LBs 18 39 DQ10 A18 19 38 DQ2 A17 20 37 DQ9 A7 21 36 DQ1 A6 22 35 DQ8 A5 23 34 DQ0 A4 24 33 OE A3 25 32 VSS A2 26 31 CE1s A1 27 30 CEf N.C. 28 29 A0 (FPT-56P-M04) 4 MB84VD2118XA-85/MB84VD2119XA-85 PIN DESCRIPTION Pin name A0 to A17 Function Input/Output Address Inputs (Common) I A-1, A18, A19 Address Input (Flash) I SA Address Input (SRAM) I DQ0 to DQ15 Data Inputs/Outputs (Common) I/O CEf Chip Enable (Flash) I CE1s Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I WE Write Enable (Common) I Ready/Busy Outputs (Flash) Open Drain Output O UBs Upper Byte Control (SRAM) I LBs Lower Byte Control (SRAM) I CIOf I/O Configuration (Flash) CIOf = VCCf is Word mode ( x 16), CIOf = VSS is Byte mode ( x 8) I CIOs I/O Configuration (SRAM) CIOs = VCCs is Word mode ( x 16), CIOs = VSS is Byte mode ( x 8) I Hardware Reset Pin/Sector Protection Unlock (Flash) I Write Protect / Acceleration (Flash) I RY/BY RESET WP/ACC N.C. No Internal Connection VSS Device Ground (Common) Power VCCf Device Power Supply (Flash) Power VCCs Device Power Supply (SRAM) Power 5 MB84VD2118XA-85/MB84VD2119XA-85 BLOCK DIAGRAM VCCf VSS A0 to A19 RY/BY A0 to A19 A-1 WP/ACC RESET CEf CIOf 16 M bit Flash Memory DQ0 to DQ15/A-1 DQ0 to DQ15/A-1 VCCs VSS A0 to A17 DQ0 to DQ15/A-1 SA LBs UBs WE OE CE1s CE2s CIOs 6 4 M bit Static RAM MB84VD2118XA-85/MB84VD2119XA-85 DEVICE BUS OPERATIONS Table 2.1 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Word mode; CIOs = VCCs) Operation *1, *3 Full Standby H H Output Disable L Read from Flash *2 L Write to Flash L Read from SRAM Write to SRAM DQ0 to DQ7 DQ8 to DQ15 RESET WP/ ACC *5 X High-Z High-Z H X X X High-Z High-Z X H H High-Z High-Z H X H X X X High-Z High-Z L H X X X DOUT DOUT H X H L X X X DIN DIN H X L L DOUT DOUT H L High-Z DOUT H X L H DOUT High-Z L L DIN DIN H L High-Z DIN H X L H DIN High-Z CEf CE1s CE2s OE H H Temporary Sector Group Unprotection *4 X Flash Hardware Reset X Boot Block Sector Write Protection X H X X L L H H X X L H X X L H X X L L L H H X X H X X L X X WE SA *6 X X X X H H X X X H L X H L LBs UBs X X X X X X X X X VID X X X X X X High-Z High-Z L X X X X X X X X X L Legend: L = VIL, H = VIH, X = VIL or VIH. See "ELECTRICAL CHARACTERISTICS 1. DC Characteristics" for voltage levels. *1: Other operations except for indicated this column are inhibited. *2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4: It is also used for the extended sector group protections. *5: WP/ACC = VIL; protection of boot sectors. WP/ACC = VIH; removal of boot sectors protection. WP/ACC = VACC (9V) ; Program time will reduce by 40%. *6: SA; Don't care or Open. 7 MB84VD2118XA-85/MB84VD2119XA-85 Table 2.2 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Byte mode; CIOs = VSS) Operation *1, *3 Full Standby CEf CE1s CE2s OE H H Output Disable L H X X L L H H X X L H X X L H X X L WE SA LBs *6 UBs *6 DQ0 to DQ7 WP/ DQ8 to RESET DQ15 ACC *5 X X X X X High-Z High-Z H X H H X X X High-Z High-Z X X X H H High-Z High-Z H X H H X X X High-Z High-Z L H X X X DOUT DOUT H X H L X X X DIN DIN H X Read from Flash *2 L Write to Flash L Read from SRAM H L H L H SA X X DOUT High-Z H X Write to SRAM H L H X L SA X X DIN High-Z H X Temporary Sector Group Unprotection *4 X X X X X X X X X X VID X Flash Hardware Reset X H X X L X X X X X High-Z High-Z L X Boot Block Sector Write Protection X X X X X X X X X X X L Legend: L = VIL, H = VIH, X = VIL or VIH. See "ELECTRICAL CHARACTERISTICS 1. DC Characteristics" for voltage levels. *1: Other operations except for indicated this column are inhibited. *2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4: It is also used for the extended sector group protections. *5: WP/ACC = VIL; protection of boot sectors. WP/ACC = VIH; removal of boot sectors protection. WP/ACC = VACC (9V) ; Program time will reduce by 40%. *6: LBS , UBS; Don't care or Open. 8 MB84VD2118XA-85/MB84VD2119XA-85 Table 2.3 User Bus Operations (Flash = Byte mode; CIOf = VSS, SRAM = Byte mode; CIOs = VSS) Operation *1, *3 Full Standby CEf CE1s CE2s H H Output Disable L H X X L L H H X X L H X X L H X X L DQ1/ OE WE SA LBs *6 A-1 UBs *6 DQ0 to DQ7 WP/ DQ8 to RESET DQ14 ACC *5 X X X X X X High-Z High-Z H X X H H X X X High-Z High-Z X X X X H H High-Z High-Z H X A-1 H H X X X High-Z High-Z A-1 L H X X X DOUT X H X A-1 H L X X X DIN X H X Read from Flash *2 L Write to Flash L Read from SRAM H L H X L H SA X X DOUT High-Z H X Write to SRAM H L H X X L SA X X DIN High-Z H X Temporary Sector Group Unprotection *4 X X X X X X X X X X X VID X Flash Hardware Reset H X X X L X X X X X X High-Z High-Z L X Boot Block Sector Write Protection X X X X X X X X X X X X L Legend: L = VIL, H = VIH, X = VIL or VIH. See "ELECTRICAL CHARACTERISTICS 1. DC Characteristics" for voltage levels. *1: Other operations except for indicated this column are inhibited. *2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4: It is also used for the extended sector group protections. *5: WP/ACC = VIL ; protection of boot sectors. WP/ACC = VIH ; removal of boot sectors protection. WP/ACC = VACC (9V) ; Program time will reduce by 40%. *6: LBS, UBS ; Don't care or Open. 9 MB84VD2118XA-85/MB84VD2119XA-85 FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY * Eight 4 K words, and thirty one 32 K words. * Individual-sector, multiple-sector, or bulk-erase capability. Word mode Byte mode SA38 : SA37 : SA36 : Bank 1 SA35 : MB84VD21181A SA34 : SA33 : Bank 1 SA32 : MB84VD21182A SA31 : SA30 : Bank 1 SA29 : MB84VD21183A SA28 : SA27 : Bank 1 SA26 : MB84VD21184A SA25 : SA24 : SA23 : SA22 : SA21 : SA20 : SA19 : SA18 : SA17 : SA16 : SA15 : Bank 2 SA14 : MB84VD21181A SA13 : SA12 : Bank 2 SA11 : MB84VD21182A SA10 : SA9 : Bank 2 SA8 : MB84VD21183A SA7 : Bank 2 SA6 : MB84VD21184A SA5 : SA4 : SA3 : SA2 : SA1 : SA0 : 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) MB84VD2118XA Sector Architecture (Top Boot Block) 10 0FFFFFh 0FF000h 0FE000h 0FD000h 0FC000h 0FB000h 0FA000h 0F9000h 0F8000h 0F0000h 0E8000h 0E0000h 0D8000h 0D0000h 0C8000h 0C0000h 0B8000h 0B0000h 0A8000h 0A0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 000000h 1FFFFFh 1FE000h 1FC000h 1FA000h 1F8000h 1F6000h 1F4000h 1F2000h 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h MB84VD2118XA-85/MB84VD2119XA-85 * Eight 4 K words, and thirty one 32 K words. * Individual-sector, multiple-sector, or bulk-erase capability. Word mode Byte mode SA38 : SA37 : SA36 : Bank 2 SA35 : MB84VD21194A SA34 : SA33 : Bank 2 SA32 : MB84VD21193A SA31 : SA30 : Bank 2 SA29 : MB84VD21192A SA28 : SA27 : Bank 2 SA26 : MB84VD21191A SA25 : SA24 : SA23 : SA22 : SA21 : SA20 : SA19 : SA18 : SA17 : SA16 : SA15 : SA14 : SA13 : SA12 : Bank 1 SA11 : MB84VD21194A SA10 : SA9 : Bank 1 SA8 : MB84VD21193A SA7 : SA6 : Bank 1 SA5 : MB84VD21192A SA4 : Bank 1 SA3 : MB84VD21191A SA2 : SA1 : SA0 : 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) 0FFFFFh 0F8000h 0F0000h 0E8000h 0E0000h 0D8000h 0D0000h 0C8000h 0C0000h 0B8000h 0B0000h 0A8000h 0A0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h 1FFFFFh 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 00E000h 00C000h 00A000h 008000h 006000h 004000h 002000h 000000h MB84VD2119XA Sector Architecture (Bottom Boot Block) 11 MB84VD2118XA-85/MB84VD2119XA-85 Table 3.1 Sector Address Tables (MB84VD21181) Sector Address Bank Bank 2 Bank 1 12 Sector Bank Address Address Range (Byte mode) Address Range (Word mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 1 1 1 1 1 0 0 0 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh SA32 1 1 1 1 1 0 0 1 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh SA33 1 1 1 1 1 0 1 0 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh SA34 1 1 1 1 1 0 1 1 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh SA35 1 1 1 1 1 1 0 0 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh SA36 1 1 1 1 1 1 0 1 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh SA37 1 1 1 1 1 1 1 0 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh SA38 1 1 1 1 1 1 1 1 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh MB84VD2118XA-85/MB84VD2119XA-85 Table 3.2 Sector Address Tables (MB84VD21191) Sector Address Bank Bank 1 Bank 2 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 0 0 0 000000h to 001FFFh 000000h to 000FFFh SA1 0 0 0 0 0 0 0 1 002000h to 003FFFh 001000h to 001FFFh SA2 0 0 0 0 0 0 1 0 004000h to 005FFFh 002000h to 002FFFh SA3 0 0 0 0 0 0 1 1 006000h to 007FFFh 003000h to 003FFFh SA4 0 0 0 0 0 1 0 0 008000h to 009FFFh 004000h to 004FFFh SA5 0 0 0 0 0 1 0 1 00A000h to 00BFFFh 005000h to 005FFFh SA6 0 0 0 0 0 1 1 0 00C000h to 00DFFFh 006000h to 006FFFh SA7 0 0 0 0 0 1 1 1 00E000h to 00FFFFh 007000h to 007FFFh SA8 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA11 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA23 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA32 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA33 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 1 1 1 1 1 X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh 13 MB84VD2118XA-85/MB84VD2119XA-85 Table 3.3 Sector Address Tables (MB84VD21182) Sector Address Bank Bank 2 Bank 1 14 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 1 1 1 1 1 0 0 0 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh SA32 1 1 1 1 1 0 0 1 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh SA33 1 1 1 1 1 0 1 0 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh SA34 1 1 1 1 1 0 1 1 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh SA35 1 1 1 1 1 1 0 0 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh SA36 1 1 1 1 1 1 0 1 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh SA37 1 1 1 1 1 1 1 0 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh SA38 1 1 1 1 1 1 1 1 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh MB84VD2118XA-85/MB84VD2119XA-85 Table 3.4 Sector Address Tables (MB84VD21192) Sector Address Bank Bank 1 Bank 2 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 0 0 0 000000h to 001FFFh 000000h to 000FFFh SA1 0 0 0 0 0 0 0 1 002000h to 003FFFh 001000h to 001FFFh SA2 0 0 0 0 0 0 1 0 004000h to 005FFFh 002000h to 002FFFh SA3 0 0 0 0 0 0 1 1 006000h to 007FFFh 003000h to 003FFFh SA4 0 0 0 0 0 1 0 0 008000h to 009FFFh 004000h to 004FFFh SA5 0 0 0 0 0 1 0 1 00A000h to 00BFFFh 005000h to 005FFFh SA6 0 0 0 0 0 1 1 0 00C000h to 00DFFFh 006000h to 006FFFh SA7 0 0 0 0 0 1 1 1 00E000h to 00FFFFh 007000h to 007FFFh SA8 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA11 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA23 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA32 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA33 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 1 1 1 1 1 X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh 15 MB84VD2118XA-85/MB84VD2119XA-85 Table 3.5 Sector Address Tables (MB84VD21183) Sector Address Bank Bank 2 Bank 1 16 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 1 1 1 1 1 0 0 0 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh SA32 1 1 1 1 1 0 0 1 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh SA33 1 1 1 1 1 0 1 0 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh SA34 1 1 1 1 1 0 1 1 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh SA35 1 1 1 1 1 1 0 0 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh SA36 1 1 1 1 1 1 0 1 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh SA37 1 1 1 1 1 1 1 0 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh SA38 1 1 1 1 1 1 1 1 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh MB84VD2118XA-85/MB84VD2119XA-85 Table 3.6 Sector Address Tables (MB84VD21193) Sector Address Bank Bank 1 Bank 2 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 0 0 0 000000h to 001FFFh 000000h to 000FFFh SA1 0 0 0 0 0 0 0 1 002000h to 003FFFh 001000h to 001FFFh SA2 0 0 0 0 0 0 1 0 004000h to 005FFFh 002000h to 002FFFh SA3 0 0 0 0 0 0 1 1 006000h to 007FFFh 003000h to 003FFFh SA4 0 0 0 0 0 1 0 0 008000h to 009FFFh 004000h to 004FFFh SA5 0 0 0 0 0 1 0 1 00A000h to 00BFFFh 005000h to 005FFFh SA6 0 0 0 0 0 1 1 0 00C000h to 00DFFFh 006000h to 006FFFh SA7 0 0 0 0 0 1 1 1 00E000h to 00FFFFh 007000h to 007FFFh SA8 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA11 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA23 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA32 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA33 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 1 1 1 1 1 X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh 17 MB84VD2118XA-85/MB84VD2119XA-85 Table 3.7 Sector Address Tables (MB84VD21184) Sector Address Bank Bank 2 Bank 1 18 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 1 1 1 1 1 0 0 0 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh SA32 1 1 1 1 1 0 0 1 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh SA33 1 1 1 1 1 0 1 0 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh SA34 1 1 1 1 1 0 1 1 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh SA35 1 1 1 1 1 1 0 0 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh SA36 1 1 1 1 1 1 0 1 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh SA37 1 1 1 1 1 1 1 0 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh SA38 1 1 1 1 1 1 1 1 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh MB84VD2118XA-85/MB84VD2119XA-85 Table 3.8 Sector Address Tables (MB84VD21194) Sector Address Bank Bank 1 Bank 2 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 0 0 0 000000h to 001FFFh 000000h to 000FFFh SA1 0 0 0 0 0 0 0 1 002000h to 003FFFh 001000h to 001FFFh SA2 0 0 0 0 0 0 1 0 004000h to 005FFFh 002000h to 002FFFh SA3 0 0 0 0 0 0 1 1 006000h to 007FFFh 003000h to 003FFFh SA4 0 0 0 0 0 1 0 0 008000h to 009FFFh 004000h to 004FFFh SA5 0 0 0 0 0 1 0 1 00A000h to 00BFFFh 005000h to 005FFFh SA6 0 0 0 0 0 1 1 0 00C000h to 00DFFFh 006000h to 006FFFh SA7 0 0 0 0 0 1 1 1 00E000h to 00FFFFh 007000h to 007FFFh SA8 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh SA11 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA23 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA32 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA33 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 1 1 1 1 1 X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh 19 MB84VD2118XA-85/MB84VD2119XA-85 Table 4.1 Sector Group Address (MB84VD2118XA) (Top Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 X X X SA0 0 0 0 0 1 X X X 0 0 0 1 0 X X X 0 0 0 1 1 X X X SGA2 0 0 1 X X X X X SA4 to SA7 SGA3 0 1 0 X X X X X SA8 to SA11 SGA4 0 1 1 X X X X X SA12 to SA15 SGA5 1 0 0 X X X X X SA16 to SA19 SGA6 1 0 1 X X X X X SA20 to SA23 SGA7 1 1 0 X X X X X SA24 to SA27 1 1 1 0 0 X X X 1 1 1 0 1 X X X 1 1 1 1 0 X X X SGA9 1 1 1 1 1 0 0 0 SA31 SGA10 1 1 1 1 1 0 0 1 SA32 SGA11 1 1 1 1 1 0 1 0 SA33 SGA12 1 1 1 1 1 0 1 1 SA34 SGA13 1 1 1 1 1 1 0 0 SA35 SGA14 1 1 1 1 1 1 0 1 SA36 SGA15 1 1 1 1 1 1 1 0 SA37 SGA16 1 1 1 1 1 1 1 1 SA38 SGA1 SGA8 20 SA1 to SA3 SA28 to SA30 MB84VD2118XA-85/MB84VD2119XA-85 Table 4.2 Sector Group Address (MB84VD2119XA) (Bottom Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 1 1 1 SA7 0 0 0 0 1 X X X 0 0 0 1 0 X X X 0 0 0 1 1 X X X SGA9 0 0 1 X X X X X SA11 to SA14 SGA10 0 1 0 X X X X X SA15 to SA18 SGA11 0 1 1 X X X X X SA19 to SA22 SGA12 1 0 0 X X X X X SA23 to SA26 SGA13 1 0 1 X X X X X SA27 to SA30 SGA14 1 1 0 X X X X X SA31 to SA34 1 1 1 0 0 X X X 1 1 1 0 1 X X X 1 1 1 1 0 X X X 1 1 1 1 1 X X X SGA8 SGA15 SGA16 SA8 to SA10 SA35 to SA37 SA38 21 MB84VD2118XA-85/MB84VD2119XA-85 Table 5 Flash Memory Autoselect Codes Type Manufacturer's Code MB84VD21181A MB84VD21191A MB84VD21182A MB84VD21192A Device Code MB84VD21183A MB84VD21193A MB84VD21184A MB84VD21194A Sector Group protect Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word A12 to A19 A6 A1 A0 A-1*1 Code (hEX) X VIL VIL VIL VIL 04h X VIL VIL VIH VIL 36h X 2236h X VIL VIL VIH VIL 39h X 2239h X VIL VIL VIH VIL 2Dh X 222Dh X VIL VIL VIH VIL 2Eh X 222Eh X VIL VIL VIH VIL 28h X 2228h X VIL VIL VIH VIL 2Bh X 222Bh X VIL VIL VIH VIL 33h X 2233h X VIL VIL VIH VIL 35h X 2235h Sector Group Address VIL VIH VIL VIL 01h*2 *1 : A-1 is for Byte mode. *2 : Output 01h at protected sector address and output 00h at unprotected sector address. 22 MB84VD2118XA-85/MB84VD2119XA-85 Table 6 Flash Memory Command Definitions Bus Write Command Sequence First Bus Write Cycle Second Bus Write Cycle Cycles Req'd Addr. Data Addr. Read/Reset *1 Read/Reset *1 1 Word Byte 3 Word Autoselect Chip Erase Sector Erase XXXh 555h AAAh 3 Word Byte Word Byte Word Byte F0h AAh 555h Byte Program Third Bus Write Cycle 6 6 2AAh 555h AAh 555h AAAh 555h AAAh 555h AAAh Addr. 55h 2AAh AAAh 4 Data 55h 555h AAh AAh AAh 2AAh 555h 2AAh 555h 2AAh 555h 55h 55h 55h 555h AAAh (BA) 555h (BA) AAAh 555h AAAh 555h AAAh 555h AAAh Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Data Addr. Data Addr. Data Addr. Data F0h RA RD 90h A0h PA PD 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 555h AAAh 10h 55h SA 30h Sector Erase Suspend 1 BA B0h Sector Erase Resume 1 BA 30h 20h Set to Fast Mode Word Fast Program *2 Word Reset from Fast Mode *2 Word Extended Sector Group Protection *3 Word Query *4 Hi-ROM Entry Byte Byte Byte Byte Word Byte Word Byte Hi-ROM Program *5 Word Hi-ROM Erase *5 Word Byte Byte 3 AAAh 2AAh 555h 55h 555h AAAh XXXh A0h PA PD 2 BA 90h XXXh F0h *6 4 XXXh 60h SPA 60h SPA 40h SPA SD 98h 88h A0h PA PD 55h HRA 30h 1 3 4 6 55h AAh 555h AAAh 555h AAAh 555h AAAh AAh AAh AAh 555h 4 Byte AAh 2 Word Hi-ROM Exit *5 555h 2AAh 555h 2AAh 555h 2AAh 555h 55h 55h 2AAh AAh AAAh 55h 55h 555h 555h AAAh 555h AAAh 555h AAAh (HRBA) 555h (HRBA) AAAh 80h 90h 555h AAAh XXXh AAh 00h 2AAh 555h 23 MB84VD2118XA-85/MB84VD2119XA-85 *1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. *2: This command is valid while Fast Mode. *3: This command is valid while RESET = VID. *4: The valid Address is A0 to A6. *5: This command is valid while Hi-ROM mode. *6: The data "00h" is also acceptable. Address bits A12 to A19 = X = "H" or "L" for all address commands except for Program Address (PA) , Sector Address (SA) , and Bank Address (BA) . Bus operations are defined in Table 2 "User Bus Operations". RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A15 to A19) SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). HRA = Address of the Hidden-ROM area. SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). HRA = Address of the Hidden-ROM area. MB84VD2118XA (Top Boot Type) Word mode: 0F8000h to 0FFFFFh Byte mode: 1F0000h to 1FFFFFh MB84VD2119XA (Bottom Boot Type) Word mode: 000000h to 007FFFh Byte mode: 000000h to 00FFFFh HRBA = Bank addrss of the Hidden-ROM area. MB84VD2118XA (Top Boot Type) : A15 = A16 = A17 = A18 = A19 = A20 = 1 MB84VD2119XA (Bottom Boot Type) : A15 = A16 = A17 = A18 = A19 = A20 = 0 RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected sector addresses. The system should generate the following address patterns; Word mode : 555h or 2AAh to addresses A0 to A10 Byte mode : AAAh or 555h to addresses A -1 and A0 to A10 24 MB84VD2118XA-85/MB84VD2119XA-85 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min. Max. Tstg -55 +125 C TA -25 +85 C VIN, VOUT -0.3 VCCf/VCCs Supply *1 VCCf, VCCs -0.3 +4.0 V 2 VIN -0.5 +13.0 V VIN -0.5 +10.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET and WP/ACC *1 RESET * 3 WP/ACC * VCCf + 0.4 VCCs + 0.4 V *1: Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf +0.4 V or VCCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns. *2: Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature VCCf/VCCs Supply Voltages Symbol Value Unit Min. Max. TA -25 +85 C VCCf, VCCs +2.7 +3.6 V Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 25 MB84VD2118XA-85/MB84VD2119XA-85 ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Value Test Conditions Min. Typ. Max. Unit Input Leakage Current ILI VIN = VSS to VCCf, VCCs -1.0 +1.0 A Output Leakage Current ILO VOUT = VSS to VCCf, VCCs -1.0 +1.0 A RESET Inputs Leakage Current ILIT VCCf = VCCf Max, RESET = 12.5V 35 A ACC Input Leakage Current ILIA VCCf = VCCf Max, WP/ACC = VACC Max 20 mA tCYCLE = 5 MHz Byte 13 tCYCLE = 5 MHz Word 15 tCYCLE = 1 MHz Byte 7 tCYCLE = 1 MHz Word 7 35 Byte 48 Word 50 Byte 48 Word 50 Flash VCC Active Current (Read) *1 ICC1f CEf = VIL, OE = VIH mA mA Flash VCC Active Current (Program/Erase) *2 ICC2f CEf = VIL, OE = VIH Flash VCC Active Current (Read-While-Program) *5 ICC3f CEf = VIL, OE = VIH Flash VCC Active Current (Read-While-Erase) *5 ICC4f CEf = VIL, OE = VIH Flash VCC Active Current (Erase-Suspend-Program) ICC5f CEf = VIL, OE = VIH 35 mA SRAM VCC Active Current ICC1s VCCs = VCCs Max., CE1s = VIL, tCYCLE = 10 MHz CE2s = VIH 40 mA 40 mA ICC2s CE1s = 0.2 V, CE2s = VCCs - 0.2 V, tCYCLE = 10 MHz SRAM VCC Active Current tCYCLE = 1 MHz 8 mA Flash VCC Standby Current ISB1f VCCf = VCCf Max., CEf = VCCf 0.3 V RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V 1 5 A Flash VCC Standby Current (RESET) ISB2f VCCf = VCCf Max., RESET = VSS 0.3 V WP/ACC = VCCf 0.3 V 1 5 A Flash VCC Current (Automatic Sleep Mode)*3 ISB3f VCCf = VCCf Max., CEf = VSS 0.3 V RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V VIN = VCCf 0.3 V or VSS 0.3 V 1 5 A SRAM VCC Standby Current ISB1s CE1s VCCs - 0.2V, CE2s VCCs - 0.2V 0.2 7 A SRAM VCC Standby Current ISB2s CE2s 0.2V 0.2 7 A mA mA mA (Continued) 26 MB84VD2118XA-85/MB84VD2119XA-85 (Continued) Parameter Symbol Test Conditions Input Low Level VIL Input High Level Value Unit Min. Typ. Max. -0.3 0.5 V VIH 2.4 VCC + 0.3 *6 V Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) *4 VID 11.5 12.5 V Voltage for Program Acceleration (WP/ACC) *4 VACC 8.5 9.0 9.5 V Output Low Voltage Level VOL VCCf = VCCf Min., VCCs = VCCs Min., IOL = 1.0 mA 0.4 V Output High Voltage Level VOH VCCf = VCCf Min., VCCs = VCCs Min., IOH = -0.5 mA 2.4 V Flash Low VCCf Lock-Out Voltage VLKO 2.3 2.5 V *1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remain stable for 150ns. *4: Applicable for only VCCf applying. *5: Embedded Alogorithm (program or erase) is in progress. (@5MHz) *6: VCC indicates lower of VCCf or VCCs. 27 MB84VD2118XA-85/MB84VD2119XA-85 2. AC Characteristics * CE Timing Symbol Parameter JEDEC Standard tCCR CE Recover Time Test Setup 0 CEf tCCR tCCR tCCR tCCR CE1s 28 Unit Min. * Timing Diagram for alternating SRAM to Flash CE2s Value ns MB84VD2118XA-85/MB84VD2119XA-85 * Read Only Operations Characteristics (Flash) Symbol Value (Note) JEDEC Standard Test Setup Read Cycle Time tAVAV tRC 85 ns Address to Output Delay tAVQV tACC CEf = VIL OE = VIL 85 ns Chip Enable to Output Delay tELQV tCEf OE = VIL 85 ns Output Enable to Output Delay tGLQV tOE 35 ns Chip Enable to Output High-Z tEHQZ tDF 30 ns Output Enable to Output High-Z tGHQZ tDF 30 ns Output Hold Time From Addresses, CEf or OE, Whichever Occurs First tAXQX tOH 0 ns tREADY 20 s Parameter RESET Pin Low to Read Mode Min. Max. Unit Note : Test Conditions - Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V 29 MB84VD2118XA-85/MB84VD2119XA-85 * Read Cycle (Flash) tRC Address Stable Address tACC CEf tDF tOE OE tOEH WE tCEf High-Z DQ High-Z Output Valid tRC Address Address Stable tRH tACC CEf tRP tRH tCEf RESET tOH High-Z DQ 30 Output Valid MB84VD2118XA-85/MB84VD2119XA-85 * Erase/Program Operations (Flash) Parameter Symbol Value Unit JEDEC Standard Min. Typ. Max. Write Cycle Time tAVAV tWC 85 ns Address Setup Time (WE to Addr.) tAVWL tAS 0 ns tASO 15 ns tWLAX tAH 45 ns tAHT 0 ns Data Setup Time tDVWH tDS 35 ns Data Hold Time tWHDX tDH 0 ns tOES 0 ns tOEH 0 ns 10 ns CEf High During Toggle Bit Polling tCEPH 20 ns OE High During Toggle Bit Polling tOEPH 20 ns Read Recover Time Before Write (OE to CEf) tGHEL tGHEL 0 ns Read Recover Time Before Write (OE to WE) tGHWL tGHWL 0 ns WE Setup Time (CEf to WE) tWLEL tWS 0 ns CEf Setup Time (WE to CEf) tELWL tCS 0 ns WE Hold Time (CEf to WE) tEHWH tWH 0 ns CEf Hold Time (WE to CEf) tWHEH tCH 0 ns Write Pulse Width tWLWH tWP 35 ns CEf Pulse Width tELEH tCP 35 ns Write Pulse Width High tWHWL tWPH 30 ns CEf Pulse Width High tEHEL tCPH 30 ns tWHWH1 tWHWH1 8 s 16 s tWHWH2 tWHWH2 1 s Address Setup Time to CEf Low During Toggle Bit Polling Address Hold Time (WE to Addr.) Address Hold Time from CEf or OE High During Toggle Bit Polling Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling Byte Programming Operation Word Programming Operation Sector Erase Operation *1 (Continued) 31 MB84VD2118XA-85/MB84VD2119XA-85 (Continued) Parameter Symbol Value Unit JEDEC Standard Min. Typ. Max. tVCS 50 s tVLHT 4 s Rise Time to VID * tVIDR 500 ns Rise Time to VACC tVACCR 500 ns Recover Time from RY/BY tRB 0 ns RESET Pulse Width tRP 500 ns Delay Time from Embedded Output Enable tEOE 85 ns RESET Hold Time Before Read tRH 200 ns Program/Erase Valid to RY/BY Delay tBUSY 90 ns tTOW 50 s tSPD 20 s VCCf Setup Time Voltage Transition Time * 2 2 Erase Time-out Time * 3 Erase Suspend Transition Time * 4 *1: This does not include the preprogramming time. *2: This timing is for Sector Protection Operation. *3: The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. A time-out or "tTOW" from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command (s) . *4: When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation. 32 MB84VD2118XA-85/MB84VD2119XA-85 * Write Cycle (WE control) (Flash) 3rd Bus Cycle Address Data Polling 555h tWC PA tAS PA tRC tAH CEf tCS tCH tCEf OE tGHWL tWP tOE tWHWH1 tWPH WE tOH tDS tDH DQ A0h PD DQ7 DOUT DOUT Notes : 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the x 16 mode. (The addresses differ from x 8 mode.) 33 MB84VD2118XA-85/MB84VD2119XA-85 * Write Cycle (CEf control) (Flash) 3rd Bus Cycle Address Data Polling 555h tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tWHWH1 tCPH CEf tDS tDH DQ A0h PD DQ7 DOUT Notes : 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the x 16 mode. (The addresses differ from x 8 mode.) 34 MB84VD2118XA-85/MB84VD2119XA-85 * AC Waveforms Chip/Sector Erase Operations (Flash) 555h Address tWC 2AAh tAS 555h 555h SA* 2AAh tAH CEf tCS tCH OE tGHWL tWP tWPH WE tDS tDH AAh 30h for Sector Erase 55h 80h AAh 55h DQ 10h/ 30h tVCS VCCf *: SA is the sector address for Sector Erase. Address = 555h for Chip Erase. Note : These waveforms are for the x 16 mode. (The addresses differ from x 8 mode.) 35 MB84VD2118XA-85/MB84VD2119XA-85 * AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) CEf tCH tDF tOE OE tOEH WE tCEf * DQ7 Data In DQ7 = Valid Data DQ7 High-Z tWHWH1 or 2 DQ (DQ0 to DQ6) Data In DQ0 to DQ6 = Output Flag tBUSY RY/BY *: DQ7 = Valid Data (The device has completed the Embedded operation.) 36 tEOE DQ0 to DQ6 Valid Data High-Z MB84VD2118XA-85/MB84VD2119XA-85 * AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) Address tAHT tASO tAHT tAS CEf tCEPH WE tOEPH tOEH tOEH OE tDH DQ6/DQ2 Toggle Data Data tCEf* tOE Toggle Data Toggle Data Stop Toggling Output Valid tBUSY RY/BY * : DQ6 stops toggling (The device has completed the Embedded operation) . 37 MB84VD2118XA-85/MB84VD2119XA-85 * Back-to-back Read/Write Timing Diagram (Flash) Address Read Command Read Command Read Read tRC tWC tRC tWC tRC tRC BA1 BA2 (555h) BA1 BA2 (PA) BA1 BA2 (PA) tAS tAS tACC tAH tAHT tCEf CEf tOE tCEPH OE tGHWL tOEH tDF tWP WE tDS DQ Valid Output tDH Valid Input (A0h) tDF Valid Output Valid Input Valid Output Status (PD) Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address of Bank 1. BA2 : Address of Bank 2. 38 MB84VD2118XA-85/MB84VD2119XA-85 * RY/BY Timing Diagram during Write/Erase Operations (Flash) CEf The rising edge of the last write pulse WE Entire programming or erase operations RY/BY tBUSY * RESET, RY/BY Timing Diagram (Flash) WE RESET tRP tRB RY/BY tREADY 39 MB84VD2118XA-85/MB84VD2119XA-85 * Temporary Sector Unprotection (Flash) VCCf tVIDR tVLHT tVCS VID 3V 3V RESET CEf WE tVLHT tVLHT Program or Erase Command Sequence RY/BY Unprotection Period 40 MB84VD2118XA-85/MB84VD2119XA-85 * Extended Sector Protection (Flash) VCCf tVCS RESET tVLHT tVIDR tWC tWC SGAx Address SGAx SGAy A0 A1 A6 CEf OE TIME - OUT tWP WE Data 60h 60h 40h 01h 60h tOE SGAx : Sector Group Address to be protected SGAy : Next Group Sector Address to be protected TIME-OUT : Time-Out window = 250 s (Min.) 41 MB84VD2118XA-85/MB84VD2119XA-85 * Accelerated Program (Flash) VCCf tVACCR tVCS tVLHT VACC 3V 3V WP/ACC CEf WE tVLHT Program Command Sequence RY/BY Acceleration period 42 tVLHT MB84VD2118XA-85/MB84VD2119XA-85 * Read Cycle (SRAM) Parameter Symbol Value Min. Max. Unit Read Cycle Time tRC 85 ns Address Access Time tAA 85 ns Chip Enable (CE1s) Access Time tCO1 85 ns Chip Enable (CE2s) Access Time tCO2 85 ns Output Enable Access Time tOE 45 ns LBS, UBS to Output Valid tBA 85 ns Chip Enable (CE1s Low and CE2s High) to Output Active tCOE 5 ns Output Enable Low to Output Active tOEE 0 ns UBS, LBS Enable Low to Output Active tBE 0 ns Chip Enable (CE1s High or CE2s Low) to Output High-Z tOD 35 ns Output Enable High to Output High-Z tODO 35 ns UBS, LBS Output Enable to Output High-Z tBD 50 ns Output Data Hold Time tOH 10 ns Note: Test conditions: Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to VCCs Timing measurement reference level Input: 0.5 x VCCs Output: 0.5 x VCCs 43 MB84VD2118XA-85/MB84VD2119XA-85 * Read Cycle (Note) (SRAM) tRC Address tAA tOH tCO1 CE1s tCOE tOD tCO2 CE2s tOD tOE OE tODO tOEE LBS, UBS tBA tBD tBE tCOE DQ Note : WE remains "H" for the read cycle. 44 Valid Data Out MB84VD2118XA-85/MB84VD2119XA-85 * Write Cycle (SRAM) Parameter Symbol Value Min. Max. Unit Write Cycle Time tWC 85 ns Write Pulse Width tWP 55 ns Chip Enable to End of Write tCW 70 ns Address valid to End of Write tAW 70 ns UBS, LBS to End of Write tBW 55 ns Address Setup Time tAS 0 ns Write Recovery Time tWR 0 ns WE Low to Output High-Z tODW 35 ns WE High to Output Active tOEW 0 ns Data Setup Time tDS 35 ns Data Hold Time tDH 0 ns 45 MB84VD2118XA-85/MB84VD2119XA-85 * Write Cycle (Note 3) (WE control) (SRAM) tWC Address tAS tWP tWR WE tAW tCW CE1s CE2s tCW tBW LBS, UBS tODW DOUT tOEW Note 1 Note 2 tDS DIN Note 4 Valid Data In tDH Note 4 Notes : 1. If CE1s goes "L" (or CE2s goes "H") coincident with or after WE goes "L", the output will remain at High-Z. 2. If CE1s goes "H" (or CE2s goes "L") coincident with or before WE goes "H", the output will remain at High-Z. 3. If OE is "H" during the write cycle, the outputs will remain at High-Z. 4. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 46 MB84VD2118XA-85/MB84VD2119XA-85 * Write Cycle (Note 1) (CE1s control) (SRAM) tWC Address tAS tWR tWP WE tAW tCW CE1s CE2s tCW tBW LBS, UBS tBE tCOE tODW DOUT tDS DIN Note 2 tDH Valid Data In Notes : 1. If OE is "H" during the write cycle, the outputs will remain at High-Z. 2. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 47 MB84VD2118XA-85/MB84VD2119XA-85 * Write Cycle (Note 1) (CE2s Control) (SRAM) tWC Address tAS tWP tWR WE tCW CE1s tAW CE2s tCW tBW LBS, UBS tBE tCOE tODW DOUT tDS DIN Note 2 tDH Valid Data In Notes : 1. If OE is "H" during the write cycle, the outputs will remain at High-Z. 2. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 48 MB84VD2118XA-85/MB84VD2119XA-85 * Write Cycle (Note 1) (LBs, UBs Control) (SRAM) tWC Address tWP tWR WE tCW CE1s tCW CE2s tAW tAS tBW LBS, UBS tBE tCOE tODW DOUT tDS DIN Note 2 tDH Valid Data In Notes : 1. If OE is "H" during the write cycle, the outputs will remain at High-Z. 2. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 49 MB84VD2118XA-85/MB84VD2119XA-85 ERASE AND PROGRAMMING PERFORMANCE (Flash) Limits Parameter Unit Comment Min. Typ. Max. Sector Erase Time 1 10 s Excludes programming time prior to erasure Byte Programming Time 8 300 s Excludes system-level overhead Word Programming Time 16 360 s Excludes system-level overhead Chip Programming Time 50 s Excludes system-level overhead 100,000 cycle Erase/Program Cycle DATA RETENTION CHARACTERISTICS (SRAM) Parameter Symbol Data Retention Supply Voltage VDH = 3.0 V Standby Current Chip Deselect to Data Retention Mode Time Recovery Time Value Typ. Max. VDH 1.5 3.6 V IDDS2 0.2 7* A tCDR 0 ns tR tRC ns * : 4 A Max. at TA 60 C, 1 A Max. at TA 40 C Note : tRC : Read cycle time * CE1s Controlled Data Retention Mode (Note 1) VCCs Data Retention Mode 2.7 V See Note 2 VIH VDH CE1s GND 50 tCDR See Note 2 VCCS -0.2 V Unit Min. tR MB84VD2118XA-85/MB84VD2119XA-85 * CE2s Controlled Data Retention Mode (Note 3) VCCs Data Retention Mode 2.7 V VDH VIH CE2s tCDR tR VIL 0.2 V GND Notes : 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs - 0.2 V or Vss to 0.2 V during data retention mode. Other input and input/output pins can be used between -0.3 V and Vccs + 0.3 V. 2. When CE1s is operating at the VIH Min. level (2.2 V) , the standby current is given by ISB1s during the transition of VCCs from 3.6 to 2.2 V. 3. In CE2s controlled data retention mode, input and input/output pins can be used between -0.3 V and Vccs + 0.3 V. PIN CAPACITANCE Parameter Symbol Test Setup Value Typ. Max. Unit Input Capacitance CIN VIN = 0 11 14 pF Output Capacitance COUT VOUT = 0 12 16 pF Control Pin Capacitance CIN2 VIN = 0 14 16 pF WP/ACC Pin Capacitance CIN3 VIN = 0 17 20 pF Note : Test conditions TA = 25 C, f = 1.0 MHz HANDLING OF PACKAGE Please handle this package carefully since the sides of packages are right angle. CAUTION 1. The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2. For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector using "Extended sector protect" command. 51 MB84VD2118XA-85/MB84VD2119XA-85 ORDERING INFORMATION MB84VD2118 X A -85 -PBS PACKAGE TYPE PBS = 69-ball FBGA PTS = 56-pin TSOP (I) SPEED OPTION See Product Selector Guide. Device Revision Bank Size 1 = 0.5 Mbit / 15.5 Mbit 2 = 2 Mbit / 14 Mbit 3 = 4 Mbit / 12 Mbit 4 = 8 Mbit / 8 Mbit DEVICE NUMBER/DESCRIPTION 16Mega-bit (2M x 8-bit or 1M x 16-bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 4Mega-bit (512K x 8-bit) SRAM BOOT CODE SECTOR ARCHITECTURE 84VD2118 = Top sector 84VD2119 = Bottom sector 52 MB84VD2118XA-85/MB84VD2119XA-85 PACKAGE DIMENSIONS 69-ball plastic FBGA (BGA-69P-M02) 7.20(.283) 11.000.10(.433.004) 1.25 +0.15 -0.10 +.006 -.004 5.60(.220)REF (Mounting height) .049 0.380.10 (Stand off) (.015.004) 0.80(.031) 10 9 8 0.80(.031) 8.000.10 (.315.004) 7 6 5.60(.220) REF 7.20(.283) 5 4 3 2 1 K J H G F E D C B A INDEX-MARK AREA INDEX BALL +0.10 69-O0.45 -0.05 +.004 69-O0.18 -.002 0.08(.003) M 0.10(.004) C 1999 FUJITSU LIMITED B69002S-1C-1 Dimension in mm (inches) (Continued) 53 MB84VD2118XA-85/MB84VD2119XA-85 (Continued) 56-pin plastic TSOP (I) (FPT-56P-M04) 14.000.20(.551.008) 12.400.10(.488.004) INDEX 0.40(.016) TYP 12.000.10 (.472.004) 0.180.035 (.007.001) "A" 0.10(.004) M Details of "A" part 0.25(.010) +0.05 0.145 -0.03 .006 C +.002 -.001 0.08(.003) 1.150.05 0.100.05 (.045.002) (.004.002) (Mounting height) (Stand off) 0~8 0.45/0.75 (.018/.030) 1998 FUJITSU LIMITED F56004S-1C-1 Dimension in mm (inches) 54 MB84VD2118XA-85/MB84VD2119XA-85 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0104 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.