DS05-50202-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M ( × 8/ × 16) FLASH MEMORY &
4M ( × 8/ × 16) STATIC RAM
MB84VD2118XA-85/MB84VD2119XA-85
■
■■
■FEATURES
•Power supply voltage of 2.7 V to 3.6 V
•High performance
85 ns maximum access time
•Operating Temperature
−25 °C to +85 °C
• Package 69-ball FBGA, 56-pin TSOP(I)
(Continued)
■
■■
■PRODUCT LINE UP
*: Both VCCf and VCCs must be in recommended operation range when either part is being accessed.
■
■■
■PACKAGES
Flash Memory SRAM
Ordering Part No. VCCf*, VCCs* = 3.0 V MB84VD2118XA-85/MB84VD2119XA-85
Max. Address Access Time (ns) 85 85
Max. CE Access Time (ns) 85 85
Max. OE Access Time (ns) 35 45
+0.6 V
−0.3 V
69-ball plastic FBGA 56-pin plastic TSOP(I)
(BGA-69P-M02) (FPT-56P-M04)
MB84VD2118XA-85/MB84VD2119XA-85
2
(Continued)
1. FLASH MEMORY
•Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes (Refer to “PIN DESCRIPTION”)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
•Minimum 100,000 write/erase cycles
•Sector erase architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
•Boot Code Sector Architecture
MB84VD2118XA : Top sector
MB84VD2119XA : Bottom sector
•Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
•Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
•Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
•Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
•Low VCCf write inhibit ≤ 2.5 V
•Hidden ROM (Hi-ROM) region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•WP/ACC input pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2118XA : SA37, SA38 MB84VD2119XA : SA0, SA1)
At VIH, allows removal of boot sector protection
At VACC, program time will reduce by 40%.
•Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
•Please refer to “MBM29DL16XTD/BD” data sheet in detailed function
2. SRAM
•Power dissipation
Operating : 40 mA Max.
Standby : 7 µA Max.
•Power down features using CE1s and CE2s
•Data retention supply voltage : 1.5 V to 3.6 V
•CE1s and CE2s Chip Select
• Byte data control : LBs (DQ0 to DQ7) , UBs (DQ8 to DQ15)
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VD2118XA-85/MB84VD2119XA-85
3
■
■■
■PIN ASSIGNMENTS
(Top View)
(BGA-69P-M02)
1234567 9108
A
B
C
D
E
F
G
H
J
K
N.C.
N.C. N.C.
WE A8
A19
A9
A10
DQ6
A12
A13
A14
SA A16
A15
N.C.
N.C. N.C.
N.C.
A11
CE2S
N.C.
N.C.
N.C. A7
A6
A5
A4
VSS
A3
A2
A1
A0
CEf OE
DQ0DQ10
DQ8DQ2
VCCfVCCs
DQ11
DQ12
DQ13DQ4DQ3DQ9
DQ1
A17
A18
UBSRESET
RY/BY
DQ7
DQ15/
A−1
VSS
CIOf
DQ14DQ5CIOS
N.C. N.C.
CE1S
N.C.
N.C.
N.C. N.C.
LBSWP/
ACC
MB84VD2118XA-85/MB84VD2119XA-85
4
(Top View)
(FPT-56P-M04)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
N.C.
A15
A14
A13
A12
A11
A10
A9
A8
A19
N.C.
WE
CE2s
RESET
WP/ACC
RY/BY
UBs
LBs
A18
A17
A7
A6
A5
A4
A3
A2
A1
N.C.
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A16
CIOf
VSS
SA
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
CIOs
VCCs
VCCf
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE1s
CEf
A0
MB84VD2118XA-85/MB84VD2119XA-85
5
■
■■
■PIN DESCRIPTION
Pin name Function Input/Output
A0 to A17 Address Inputs (Common) I
A-1, A18, A19 Address Input (Flash) I
SA Address Input (SRAM) I
DQ0 to DQ15 Data Inputs/Outputs (Common) I/O
CEf Chip Enable (Flash) I
CE1s Chip Enable (SRAM) I
CE2s Chip Enable (SRAM) I
OE Output Enable (Common) I
WE Write Enable (Common) I
RY/BY Ready/Busy Outputs (Flash) Open Drain Output O
UBs Upper Byte Control (SRAM) I
LBs Lower Byte Control (SRAM) I
CIOf I/O Configuration (Flash)
CIOf = VCCf is Word mode ( × 16), CIOf = VSS is Byte mode ( × 8) I
CIOs I/O Configuration (SRAM)
CIOs = VCCs is Word mode ( × 16), CIOs = VSS is Byte mode ( × 8) I
RESET Hardware Reset Pin/Sector Protection Unlock (Flash) I
WP/ACC Write Protect / Acceleration (Flash) I
N.C. No Internal Connection
VSS Device Ground (Common) Power
VCCf Device Power Supply (Flash) Power
VCCs Device Power Supply (SRAM) Power
MB84VD2118XA-85/MB84VD2119XA-85
6
■
■■
■BLOCK DIAGRAM
VCCfVSS
VCCsVSS
RY/BY
A0 to A19
A0 to A17
A0 to A19
A-1
WP/ACC
RESET
CEf
CIOf
SA
LBs
UBs
WE
OE
CE1s
CE2s
CIOs
16 M bit
Flash Memory
4 M bit
Static RAM
DQ0 to DQ15/A-1
DQ0 to DQ15/A-1
DQ0 to DQ15/A-1
MB84VD2118XA-85/MB84VD2119XA-85
7
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■■
■DEVICE BUS OPERATIONS
Table 2.1 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Word mode; CIOs = VCCs)
Legend: L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for
voltage levels.
*1:Other operations except for indicated this column are inhibited.
*2:WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3:Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4:It is also used for the extended sector group protections.
*5:WP/ACC = VIL; protection of boot sectors.
WP/ACC = VIH; removal of boot sectors protection.
WP/ACC = VACC (9V) ; Program time will reduce by 40%.
*6:SA; Don’t care or Open.
Operation *1, *3CEfCE1sCE2s OE WE SA *6LBsUBsDQ0 to
DQ7DQ8 to
DQ15 RESET WP/
ACC *5
Full Standby H HX
X X X X X High-Z High-Z H X
XL
Output Disable
HLHH H X X X High-Z High-Z
HX
X X X H H High-Z High-Z
LHX
H H X X X High-Z High-Z
XL
Read from Flash *2LHXLH X XX DOUT DOUT HX
XL
Write to Flash L HX
HL X XX D
IN DIN HX
XL
Read from SRAM H L H L H X
LL D
OUT DOUT
HXHLHigh-ZDOUT
LH DOUT High-Z
Write to SRAM H L H X L X
LL D
IN DIN
HXHLHigh-Z DIN
LH DIN High-Z
Temporary Sector
Group
Unprotection *4XXXXXXXXX X VID X
Flash Hardware
Reset XHX
X X X X X High-Z High-Z L X
XL
Boot Block Sector
Write Protection XXXXXXXXX X X L
MB84VD2118XA-85/MB84VD2119XA-85
8
Table 2.2 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Byte mode; CIOs = VSS)
Legend: L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for
voltage levels.
*1:Other operations except for indicated this column are inhibited.
*2:WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3:Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4:It is also used for the extended sector group protections.
*5:WP/ACC = VIL; protection of boot sectors.
WP/ACC = VIH; removal of boot sectors protection.
WP/ACC = VACC (9V) ; Program time will reduce by 40%.
*6:LBS , UBS; Don’t care or Open.
Operation *1, *3CEfCE1sCE2s OE WE SA LBs *6UBs *6DQ0 to
DQ7DQ8 to
DQ15 RESET WP/
ACC *5
Full Standby H HX
X X X X X High-Z High-Z H X
XL
Output Disable
HLHH H X X X High-Z High-Z
HX
X X X H H High-Z High-Z
LHX
H H X X X High-Z High-Z
XL
Read from Flash *2LHXLHX X X DOUT DOUT HX
XL
Write to Flash L HX
HLX X X D
IN DIN HX
XL
Read from SRAM H L H L H SA X X DOUT High-Z H X
Write to SRAM H L H X L SA X X DIN High-Z H X
Temporary Sector
Group
Unprotection *4XX XXXX X X X X VID X
Flash Hardware
Reset XHX
X X X X X High-Z High-Z L X
XL
Boot Block Sector
Write Protection XX XXXX X X X X X L
MB84VD2118XA-85/MB84VD2119XA-85
9
Table 2.3 User Bus Operations (Flash = Byte mode; CIOf = VSS, SRAM = Byte mode; CIOs = VSS)
Legend: L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for
voltage levels.
*1:Other operations except for indicated this column are inhibited.
*2:WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3:Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4:It is also used for the extended sector group protections.
*5:WP/ACC = VIL ; protection of boot sectors.
WP/ACC = VIH ; removal of boot sectors protection.
WP/ACC = VACC (9V) ; Program time will reduce by 40%.
*6:LBS, UBS ; Don’t care or Open.
Operation *1, *3CEfCE1sCE2sDQ1/
A-1 OE WE SA LBs *6UBs *6DQ0 to
DQ7DQ8 to
DQ14 RESET WP/
ACC *5
Full Standby H HXX X X X X X High-Z High-Z H X
XL
Output
Disable
HL H X H H X X X High-Z High-Z
HX
X X X X H H High-Z High-Z
LHX
A-1 H H X X X High-Z High-Z
XL
Read from
Flash *2LHX
A-1 LHX X X DOUT XHX
XL
Write to
Flash LHX
A-1 HLX X X DIN XHX
XL
Read from
SRAM HL H XLHSAX X D
OUT High-Z H X
Write to
SRAM HL H XXLSAX X D
IN High-Z H X
Temporary
Sector Group
Unprotection *4XX X XXXX X X X X VID X
Flash
Hardware
Reset XHXX X X X X X High-Z High-Z L X
XL
Boot Block
Sector Write
Protection XX X XXXX X X X X X L
MB84VD2118XA-85/MB84VD2119XA-85
10
■
■■
■FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Eight 4 K words, and thirty one 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
MB84VD2118XA Sector Architecture (Top Boot Block)
SA38 : 8KB (4KW)
SA37 : 8KB (4KW)
SA36 : 8KB (4KW)
SA35 : 8KB (4KW)
SA34 : 8KB (4KW)
SA33 : 8KB (4KW)
SA32 : 8KB (4KW)
SA31 : 8KB (4KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 64KB (32KW)
SA6 : 64KB (32KW)
SA5 : 64KB (32KW)
SA4 : 64KB (32KW)
SA3 : 64KB (32KW)
SA2 : 64KB (32KW)
SA1 : 64KB (32KW)
SA0 : 64KB (32KW)
Word mode Byte mode
0FFFFFh 1FFFFFh
0FF000h 1FE000h
0FE000h 1FC000h
0FD000h 1FA000h
0FC000h 1F8000h
0FB000h 1F6000h
0FA000h 1F4000h
0F9000h 1F2000h
0F8000h 1F0000h
0F0000h 1E0000h
0E8000h 1D0000h
0E0000h 1C0000h
0D8000h 1B0000h
0D0000h 1A0000h
0C8000h 190000h
0C0000h 180000h
0B8000h 170000h
0B0000h 160000h
0A8000h 150000h
0A0000h 140000h
098000h 130000h
090000h 120000h
088000h 110000h
080000h 100000h
078000h 0F0000h
070000h 0E0000h
068000h 0D0000h
060000h 0C0000h
058000h 0B0000h
050000h 0A0000h
048000h 090000h
040000h 080000h
038000h 070000h
030000h 060000h
028000h 050000h
020000h 040000h
018000h 030000h
010000h 020000h
008000h 010000h
000000h 000000h
Bank 1
MB84VD21181A
Bank 2
MB84VD21181A
Bank 1
MB84VD21182A
Bank 1
MB84VD21183A
Bank 1
MB84VD21184A
Bank 2
MB84VD21182A
Bank 2
MB84VD21183A
Bank 2
MB84VD21184A
MB84VD2118XA-85/MB84VD2119XA-85
11
• Eight 4 K words, and thirty one 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
MB84VD2119XA Sector Architecture (Bottom Boot Block)
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 8KB (4KW)
SA6 : 8KB (4KW)
SA5 : 8KB (4KW)
SA4 : 8KB (4KW)
SA3 : 8KB (4KW)
SA2 : 8KB (4KW)
SA1 : 8KB (4KW)
SA0 : 8KB (4KW)
Word mode Byte mode
0FFFFFh 1FFFFFh
0F8000h 1F0000h
0F0000h 1E0000h
0E8000h 1D0000h
0E0000h 1C0000h
0D8000h 1B0000h
0D0000h 1A0000h
0C8000h 190000h
0C0000h 180000h
0B8000h 170000h
0B0000h 160000h
0A8000h 150000h
0A0000h 140000h
098000h 130000h
090000h 120000h
088000h 110000h
080000h 100000h
078000h 0F0000h
070000h 0E0000h
068000h 0D0000h
060000h 0C0000h
058000h 0B0000h
050000h 0A0000h
048000h 090000h
040000h 080000h
038000h 070000h
030000h 060000h
028000h 050000h
020000h 040000h
018000h 030000h
010000h 020000h
008000h 010000h
007000h 00E000h
006000h 00C000h
005000h 00A000h
004000h 008000h
003000h 006000h
002000h 004000h
001000h 002000h
000000h 000000h
Bank 2
MB84VD21194A
Bank 2
MB84VD21193A
Bank 2
MB84VD21192A
Bank 2
MB84VD21191A
Bank 1
MB84VD21194A
Bank 1
MB84VD21193A
Bank 1
MB84VD21192A Bank 1
MB84VD21191A
MB84VD2118XA-85/MB84VD2119XA-85
12
Table 3.1 Sector Address Ta bles (MB84VD21181)
Bank Sector
Sector Address Address Range
(Byte mode) Address Range
(Word mode)
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
Bank 2
SA0 00000XXX000000h to 00FFFFh 000000h to 007FFFh
SA1 00001XXX010000h to 01FFFFh 008000h to 00FFFFh
SA2 00010XXX020000h to 02FFFFh 010000h to 017FFFh
SA3 00011XXX030000h to 03FFFFh 018000h to 01FFFFh
SA4 00100XXX040000h to 04FFFFh 020000h to 027FFFh
SA5 00101XXX050000h to 05FFFFh 028000h to 02FFFFh
SA6 00110XXX060000h to 06FFFFh 030000h to 037FFFh
SA7 00111XXX070000h to 07FFFFh 038000h to 03FFFFh
SA8 01000XXX080000h to 08FFFFh 040000h to 047FFFh
SA9 01001XXX090000h to 09FFFFh 048000h to 04FFFFh
SA1001010XXX0A0000h to 0AFFFFh 050000h to 057FFFh
SA1101011XXX0B0000h to 0BFFFFh 058000h to 05FFFFh
SA1201100XXX0C0000h to 0CFFFFh 060000h to 067FFFh
SA1301101XXX0D0000h to 0DFFFFh 068000h to 06FFFFh
SA1401110XXX0E0000h to 0EFFFFh 070000h to 077FFFh
SA1501111XXX0F0000h to 0FFFFFh 078000h to 07FFFFh
SA1610000XXX100000h to 10FFFFh 080000h to 087FFFh
SA1710001XXX110000h to 11FFFFh 088000h to 08FFFFh
SA1810010XXX120000h to 12FFFFh 090000h to 097FFFh
SA1910011XXX130000h to 13FFFFh 098000h to 09FFFFh
SA2010100XXX140000h to 14FFFFh 0A0000h to 0A7FFFh
SA2110101XXX150000h to 15FFFFh 0A8000h to 0AFFFFh
SA2210110XXX160000h to 16FFFFh 0B0000h to 0B7FFFh
SA2310111XXX170000h to 17FFFFh 0B8000h to 0BFFFFh
SA2411000XXX180000h to 18FFFFh 0C0000h to 0C7FFFh
SA2511001XXX190000h to 19FFFFh 0C8000h to 0CFFFFh
SA2611010XXX1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA2711011XXX1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA2811100XXX1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA2911101XXX1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA3011110XXX1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
Bank 1
SA31111110001F0000h to 1F1FFFh 0F8000h to 0F8FFFh
SA32111110011F2000h to 1F3FFFh 0F9000h to 0F9FFFh
SA33111110101F4000h to 1F5FFFh 0FA000h to 0FAFFFh
SA34111110111F6000h to 1F7FFFh 0FB000h to 0FBFFFh
SA35111111001F8000h to 1F9FFFh 0FC000h to 0FCFFFh
SA36111111011FA000h to 1FBFFFh 0FD000h to 0FDFFFh
SA37111111101FC000h to 1FDFFFh 0FE000h to 0FEFFFh
SA38111111111FE000h to 1FFFFFh 0FF000h to 0FFFFFh
MB84VD2118XA-85/MB84VD2119XA-85
13
Table 3.2 Sector Address Ta bles (MB84VD21191)
Bank Sector
Sector Address Address Range
(BYTE mode) Address Range
(WORD mode)
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
Bank 1
SA0 00000000000000h to 001FFFh 000000h to 000FFFh
SA1 00000001002000h to 003FFFh 001000h to 001FFFh
SA2 00000010004000h to 005FFFh 002000h to 002FFFh
SA3 00000011006000h to 007FFFh 003000h to 003FFFh
SA4 00000100008000h to 009FFFh 004000h to 004FFFh
SA5 0000010100A000h to 00BFFFh 005000h to 005FFFh
SA6 0000011000C000h to 00DFFFh 006000h to 006FFFh
SA7 0000011100E000h to 00FFFFh007000h to 007FFFh
Bank 2
SA8 00001XXX010000h to 01FFFFh 008000h to 00FFFFh
SA9 00010XXX020000h to 02FFFFh 010000h to 017FFFh
SA1000011XXX030000h to 03FFFFh 018000h to 01FFFFh
SA1100100XXX040000h to 04FFFFh 020000h to 027FFFh
SA1200101XXX050000h to 05FFFFh 028000h to 02FFFFh
SA1300110XXX060000h to 06FFFFh 030000h to 037FFFh
SA1400111XXX070000h to 07FFFFh 038000h to 03FFFFh
SA1501000XXX080000h to 08FFFFh 040000h to 047FFFh
SA1601001XXX090000h to 09FFFFh 048000h to 04FFFFh
SA1701010XXX0A0000h to 0AFFFFh 050000h to 057FFFh
SA1801011XXX0B0000h to 0BFFFFh 058000h to 05FFFFh
SA1901100XXX0C0000h to 0CFFFFh 060000h to 067FFFh
SA2001101XXX0D0000h to 0DFFFFh 068000h to 06FFFFh
SA2101110XXX0E0000h to 0EFFFFh 070000h to 077FFFh
SA2201111XXX0F0000h to 0FFFFFh 078000h to 07FFFFh
SA2310000XXX100000h to 10FFFFh 080000h to 087FFFh
SA2410001XXX110000h to 11FFFFh 088000h to 08FFFFh
SA2510010XXX120000h to 12FFFFh 090000h to 097FFFh
SA2610011XXX130000h to 13FFFFh 098000h to 09FFFFh
SA2710100XXX140000h to 14FFFFh 0A0000h to 0A7FFFh
SA2810101XXX150000h to 15FFFFh 0A8000h to 0AFFFFh
SA2910110XXX160000h to 16FFFFh 0B0000h to 0B7FFFh
SA3010111XXX170000h to 17FFFFh 0B8000h to 0BFFFFh
SA3111000XXX180000h to 18FFFFh 0C0000h to 0C7FFFh
SA3211001XXX190000h to 19FFFFh 0C8000h to 0CFFFFh
SA3311010XXX1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA3411011XXX1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA3511100XXX1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA3611101XXX1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA3711110XXX1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA3811111XXX1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
MB84VD2118XA-85/MB84VD2119XA-85
14
Table 3.3 Sector Address Ta bles (MB84VD21182)
Bank Sector
Sector Address Address Range
(BYTE mode) Address Range
(WORD mode)
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
Bank 2
SA0 00000XXX000000h to 00FFFFh 000000h to 007FFFh
SA1 00001XXX010000h to 01FFFFh 008000h to 00FFFFh
SA2 00010XXX020000h to 02FFFFh 010000h to 017FFFh
SA3 00011XXX030000h to 03FFFFh 018000h to 01FFFFh
SA4 00100XXX040000h to 04FFFFh 020000h to 027FFFh
SA5 00101XXX050000h to 05FFFFh 028000h to 02FFFFh
SA6 00110XXX060000h to 06FFFFh 030000h to 037FFFh
SA7 00111XXX070000h to 07FFFFh 038000h to 03FFFFh
SA8 01000XXX080000h to 08FFFFh 040000h to 047FFFh
SA9 01001XXX090000h to 09FFFFh 048000h to 04FFFFh
SA1001010XXX0A0000h to 0AFFFFh 050000h to 057FFFh
SA1101011XXX0B0000h to 0BFFFFh 058000h to 05FFFFh
SA1201100XXX0C0000h to 0CFFFFh 060000h to 067FFFh
SA1301101XXX0D0000h to 0DFFFFh 068000h to 06FFFFh
SA1401110XXX0E0000h to 0EFFFFh 070000h to 077FFFh
SA1501111XXX0F0000h to 0FFFFFh 078000h to 07FFFFh
SA1610000XXX100000h to 10FFFFh 080000h to 087FFFh
SA1710001XXX110000h to 11FFFFh 088000h to 08FFFFh
SA1810010XXX120000h to 12FFFFh 090000h to 097FFFh
SA1910011XXX130000h to 13FFFFh 098000h to 09FFFFh
SA2010100XXX140000h to 14FFFFh 0A0000h to 0A7FFFh
SA2110101XXX150000h to 15FFFFh 0A8000h to 0AFFFFh
SA2210110XXX160000h to 16FFFFh 0B0000h to 0B7FFFh
SA2310111XXX170000h to 17FFFFh 0B8000h to 0BFFFFh
SA2411000XXX180000h to 18FFFFh 0C0000h to 0C7FFFh
SA2511001XXX190000h to 19FFFFh 0C8000h to 0CFFFFh
SA2611010XXX1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA2711011XXX1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
Bank 1
SA2811100XXX1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA2911101XXX1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA3011110XXX1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA31111110001F0000h to 1F1FFFh 0F8000h to 0F8FFFh
SA32111110011F2000h to 1F3FFFh 0F9000h to 0F9FFFh
SA33111110101F4000h to 1F5FFFh 0FA000h to 0FAFFFh
SA34111110111F6000h to 1F7FFFh 0FB000h to 0FBFFFh
SA35111111001F8000h to 1F9FFFh 0FC000h to 0FCFFFh
SA36111111011FA000h to 1FBFFFh 0FD000h to 0FDFFFh
SA37111111101FC000h to 1FDFFFh 0FE000h to 0FEFFFh
SA38111111111FE000h to 1FFFFFh 0FF000h to 0FFFFFh
MB84VD2118XA-85/MB84VD2119XA-85
15
Table 3.4 Sector Address Ta bles (MB84VD21192)
Bank Sector
Sector Address Address Range
(BYTE mode) Address Range
(WORD mode)
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
Bank 1
SA0 00000000000000h to 001FFFh 000000h to 000FFFh
SA1 00000001002000h to 003FFFh 001000h to 001FFFh
SA2 00000010004000h to 005FFFh 002000h to 002FFFh
SA3 00000011006000h to 007FFFh 003000h to 003FFFh
SA4 00000100008000h to 009FFFh 004000h to 004FFFh
SA5 0000010100A000h to 00BFFFh 005000h to 005FFFh
SA6 0000011000C000h to 00DFFFh 006000h to 006FFFh
SA7 0000011100E000h to 00FFFFh007000h to 007FFFh
SA8 00001XXX010000h to 01FFFFh 008000h to 00FFFFh
SA9 00010XXX020000h to 02FFFFh 010000h to 017FFFh
SA1000011XXX030000h to 03FFFFh 018000h to 01FFFFh
Bank 2
SA1100100XXX040000h to 04FFFFh 020000h to 027FFFh
SA1200101XXX050000h to 05FFFFh 028000h to 02FFFFh
SA1300110XXX060000h to 06FFFFh 030000h to 037FFFh
SA1400111XXX070000h to 07FFFFh 038000h to 03FFFFh
SA1501000XXX080000h to 08FFFFh 040000h to 047FFFh
SA1601001XXX090000h to 09FFFFh 048000h to 04FFFFh
SA1701010XXX0A0000h to 0AFFFFh 050000h to 057FFFh
SA1801011XXX0B0000h to 0BFFFFh 058000h to 05FFFFh
SA1901100XXX0C0000h to 0CFFFFh 060000h to 067FFFh
SA2001101XXX0D0000h to 0DFFFFh 068000h to 06FFFFh
SA2101110XXX0E0000h to 0EFFFFh 070000h to 077FFFh
SA2201111XXX0F0000h to 0FFFFFh 078000h to 07FFFFh
SA2310000XXX100000h to 10FFFFh 080000h to 087FFFh
SA2410001XXX110000h to 11FFFFh 088000h to 08FFFFh
SA2510010XXX120000h to 12FFFFh 090000h to 097FFFh
SA2610011XXX130000h to 13FFFFh 098000h to 09FFFFh
SA2710100XXX140000h to 14FFFFh 0A0000h to 0A7FFFh
SA2810101XXX150000h to 15FFFFh 0A8000h to 0AFFFFh
SA2910110XXX160000h to 16FFFFh 0B0000h to 0B7FFFh
SA3010111XXX170000h to 17FFFFh 0B8000h to 0BFFFFh
SA3111000XXX180000h to 18FFFFh 0C0000h to 0C7FFFh
SA3211001XXX190000h to 19FFFFh 0C8000h to 0CFFFFh
SA3311010XXX1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA3411011XXX1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA3511100XXX1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA3611101XXX1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA3711110XXX1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA3811111XXX1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
MB84VD2118XA-85/MB84VD2119XA-85
16
Table 3.5 Sector Address Ta bles (MB84VD21183)
Bank Sector
Sector Address Address Range
(BYTE mode) Address Range
(WORD mode)
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
Bank 2
SA0 00000XXX000000h to 00FFFFh 000000h to 007FFFh
SA1 00001XXX010000h to 01FFFFh 008000h to 00FFFFh
SA2 00010XXX020000h to 02FFFFh 010000h to 017FFFh
SA3 00011XXX030000h to 03FFFFh 018000h to 01FFFFh
SA4 00100XXX040000h to 04FFFFh 020000h to 027FFFh
SA5 00101XXX050000h to 05FFFFh 028000h to 02FFFFh
SA6 00110XXX060000h to 06FFFFh 030000h to 037FFFh
SA7 00111XXX070000h to 07FFFFh 038000h to 03FFFFh
SA8 01000XXX080000h to 08FFFFh 040000h to 047FFFh
SA9 01001XXX090000h to 09FFFFh 048000h to 04FFFFh
SA1001010XXX0A0000h to 0AFFFFh 050000h to 057FFFh
SA1101011XXX0B0000h to 0BFFFFh 058000h to 05FFFFh
SA1201100XXX0C0000h to 0CFFFFh 060000h to 067FFFh
SA1301101XXX0D0000h to 0DFFFFh 068000h to 06FFFFh
SA1401110XXX0E0000h to 0EFFFFh 070000h to 077FFFh
SA1501111XXX0F0000h to 0FFFFFh 078000h to 07FFFFh
SA1610000XXX100000h to 10FFFFh 080000h to 087FFFh
SA1710001XXX110000h to 11FFFFh 088000h to 08FFFFh
SA1810010XXX120000h to 12FFFFh 090000h to 097FFFh
SA1910011XXX130000h to 13FFFFh 098000h to 09FFFFh
SA2010100XXX140000h to 14FFFFh 0A0000h to 0A7FFFh
SA2110101XXX150000h to 15FFFFh 0A8000h to 0AFFFFh
SA2210110XXX160000h to 16FFFFh 0B0000h to 0B7FFFh
SA2310111XXX170000h to 17FFFFh 0B8000h to 0BFFFFh
Bank 1
SA2411000XXX180000h to 18FFFFh 0C0000h to 0C7FFFh
SA2511001XXX190000h to 19FFFFh 0C8000h to 0CFFFFh
SA2611010XXX1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA2711011XXX1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA2811100XXX1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA2911101XXX1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA3011110XXX1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA31111110001F0000h to 1F1FFFh 0F8000h to 0F8FFFh
SA32111110011F2000h to 1F3FFFh 0F9000h to 0F9FFFh
SA33111110101F4000h to 1F5FFFh 0FA000h to 0FAFFFh
SA34111110111F6000h to 1F7FFFh 0FB000h to 0FBFFFh
SA35111111001F8000h to 1F9FFFh 0FC000h to 0FCFFFh
SA36111111011FA000h to 1FBFFFh 0FD000h to 0FDFFFh
SA37111111101FC000h to 1FDFFFh 0FE000h to 0FEFFFh
SA38111111111FE000h to 1FFFFFh 0FF000h to 0FFFFFh
MB84VD2118XA-85/MB84VD2119XA-85
17
Table 3.6 Sector Address Ta bles (MB84VD21193)
Bank Sector
Sector Address Address Range
(BYTE mode) Address Range
(WORD mode)
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
Bank 1
SA0 00000000000000h to 001FFFh 000000h to 000FFFh
SA1 00000001002000h to 003FFFh 001000h to 001FFFh
SA2 00000010004000h to 005FFFh 002000h to 002FFFh
SA3 00000011006000h to 007FFFh 003000h to 003FFFh
SA4 00000100008000h to 009FFFh 004000h to 004FFFh
SA5 0000010100A000h to 00BFFFh 005000h to 005FFFh
SA6 0000011000C000h to 00DFFFh 006000h to 006FFFh
SA7 0000011100E000h to 00FFFFh007000h to 007FFFh
SA8 00001XXX010000h to 01FFFFh 008000h to 00FFFFh
SA9 00010XXX020000h to 02FFFFh 010000h to 017FFFh
SA1000011XXX030000h to 03FFFFh 018000h to 01FFFFh
SA1100100XXX040000h to 04FFFFh 020000h to 027FFFh
SA1200101XXX050000h to 05FFFFh 028000h to 02FFFFh
SA1300110XXX060000h to 06FFFFh 030000h to 037FFFh
SA1400111XXX070000h to 07FFFFh 038000h to 03FFFFh
Bank 2
SA1501000XXX080000h to 08FFFFh 040000h to 047FFFh
SA1601001XXX090000h to 09FFFFh 048000h to 04FFFFh
SA1701010XXX0A0000h to 0AFFFFh 050000h to 057FFFh
SA1801011XXX0B0000h to 0BFFFFh 058000h to 05FFFFh
SA1901100XXX0C0000h to 0CFFFFh 060000h to 067FFFh
SA2001101XXX0D0000h to 0DFFFFh 068000h to 06FFFFh
SA2101110XXX0E0000h to 0EFFFFh 070000h to 077FFFh
SA2201111XXX0F0000h to 0FFFFFh 078000h to 07FFFFh
SA2310000XXX100000h to 10FFFFh 080000h to 087FFFh
SA2410001XXX110000h to 11FFFFh 088000h to 08FFFFh
SA2510010XXX120000h to 12FFFFh 090000h to 097FFFh
SA2610011XXX130000h to 13FFFFh 098000h to 09FFFFh
SA2710100XXX140000h to 14FFFFh 0A0000h to 0A7FFFh
SA2810101XXX150000h to 15FFFFh 0A8000h to 0AFFFFh
SA2910110XXX160000h to 16FFFFh 0B0000h to 0B7FFFh
SA3010111XXX170000h to 17FFFFh 0B8000h to 0BFFFFh
SA3111000XXX180000h to 18FFFFh 0C0000h to 0C7FFFh
SA3211001XXX190000h to 19FFFFh 0C8000h to 0CFFFFh
SA3311010XXX1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA3411011XXX1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA3511100XXX1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA3611101XXX1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA3711110XXX1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA3811111XXX1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
MB84VD2118XA-85/MB84VD2119XA-85
18
Table 3.7 Sector Address Ta bles (MB84VD21184)
Bank Sector
Sector Address Address Range
(BYTE mode) Address Range
(WORD mode)
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
Bank 2
SA0 00000XXX000000h to 00FFFFh 000000h to 007FFFh
SA1 00001XXX010000h to 01FFFFh 008000h to 00FFFFh
SA2 00010XXX020000h to 02FFFFh 010000h to 017FFFh
SA3 00011XXX030000h to 03FFFFh 018000h to 01FFFFh
SA4 00100XXX040000h to 04FFFFh 020000h to 027FFFh
SA5 00101XXX050000h to 05FFFFh 028000h to 02FFFFh
SA6 00110XXX060000h to 06FFFFh 030000h to 037FFFh
SA7 00111XXX070000h to 07FFFFh 038000h to 03FFFFh
SA8 01000XXX080000h to 08FFFFh 040000h to 047FFFh
SA9 01001XXX090000h to 09FFFFh 048000h to 04FFFFh
SA1001010XXX0A0000h to 0AFFFFh 050000h to 057FFFh
SA1101011XXX0B0000h to 0BFFFFh 058000h to 05FFFFh
SA1201100XXX0C0000h to 0CFFFFh 060000h to 067FFFh
SA1301101XXX0D0000h to 0DFFFFh 068000h to 06FFFFh
SA1401110XXX0E0000h to 0EFFFFh 070000h to 077FFFh
SA1501111XXX0F0000h to 0FFFFFh 078000h to 07FFFFh
Bank 1
SA1610000XXX100000h to 10FFFFh 080000h to 087FFFh
SA1710001XXX110000h to 11FFFFh 088000h to 08FFFFh
SA1810010XXX120000h to 12FFFFh 090000h to 097FFFh
SA1910011XXX130000h to 13FFFFh 098000h to 09FFFFh
SA2010100XXX140000h to 14FFFFh 0A0000h to 0A7FFFh
SA2110101XXX150000h to 15FFFFh 0A8000h to 0AFFFFh
SA2210110XXX160000h to 16FFFFh 0B0000h to 0B7FFFh
SA2310111XXX170000h to 17FFFFh 0B8000h to 0BFFFFh
SA2411000XXX180000h to 18FFFFh 0C0000h to 0C7FFFh
SA2511001XXX190000h to 19FFFFh 0C8000h to 0CFFFFh
SA2611010XXX1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA2711011XXX1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA2811100XXX1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA2911101XXX1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA3011110XXX1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA31111110001F0000h to 1F1FFFh 0F8000h to 0F8FFFh
SA32111110011F2000h to 1F3FFFh 0F9000h to 0F9FFFh
SA33111110101F4000h to 1F5FFFh 0FA000h to 0FAFFFh
SA34111110111F6000h to 1F7FFFh 0FB000h to 0FBFFFh
SA35111111001F8000h to 1F9FFFh 0FC000h to 0FCFFFh
SA36111111011FA000h to 1FBFFFh 0FD000h to 0FDFFFh
SA37111111101FC000h to 1FDFFFh 0FE000h to 0FEFFFh
SA38111111111FE000h to 1FFFFFh 0FF000h to 0FFFFFh
MB84VD2118XA-85/MB84VD2119XA-85
19
Table 3.8 Sector Address Ta bles (MB84VD21194)
Bank Sector
Sector Address Address Range
(BYTE mode) Address Range
(WORD mode)
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
Bank 1
SA0 00000000000000h to 001FFFh 000000h to 000FFFh
SA1 00000001002000h to 003FFFh 001000h to 001FFFh
SA2 00000010004000h to 005FFFh 002000h to 002FFFh
SA3 00000011006000h to 007FFFh 003000h to 003FFFh
SA4 00000100008000h to 009FFFh 004000h to 004FFFh
SA5 0000010100A000h to 00BFFFh 005000h to 005FFFh
SA6 0000011000C000h to 00DFFFh 006000h to 006FFFh
SA7 0000011100E000h to 00FFFFh007000h to 007FFFh
SA8 00001XXX010000h to 01FFFFh 008000h to 00FFFFh
SA9 00010XXX020000h to 02FFFFh 010000h to 017FFFh
SA1000011XXX030000h to 03FFFFh 018000h to 01FFFFh
SA1100100XXX040000h to 04FFFFh 020000h to 027FFFh
SA1200101XXX050000h to 05FFFFh 028000h to 02FFFFh
SA1300110XXX060000h to 06FFFFh 030000h to 037FFFh
SA1400111XXX070000h to 07FFFFh 038000h to 03FFFFh
SA1501000XXX080000h to 08FFFFh 040000h to 047FFFh
SA1601001XXX090000h to 09FFFFh 048000h to 04FFFFh
SA1701010XXX0A0000h to 0AFFFFh 050000h to 057FFFh
SA1801011XXX0B0000h to 0BFFFFh 058000h to 05FFFFh
SA1901100XXX0C0000h to 0CFFFFh 060000h to 067FFFh
SA2001101XXX0D0000h to 0DFFFFh 068000h to 06FFFFh
SA2101110XXX0E0000h to 0EFFFFh 070000h to 077FFFh
SA2201111XXX0F0000h to 0FFFFFh 078000h to 07FFFFh
Bank 2
SA2310000XXX100000h to 10FFFFh 080000h to 087FFFh
SA2410001XXX110000h to 11FFFFh 088000h to 08FFFFh
SA2510010XXX120000h to 12FFFFh 090000h to 097FFFh
SA2610011XXX130000h to 13FFFFh 098000h to 09FFFFh
SA2710100XXX140000h to 14FFFFh 0A0000h to 0A7FFFh
SA2810101XXX150000h to 15FFFFh 0A8000h to 0AFFFFh
SA2910110XXX160000h to 16FFFFh 0B0000h to 0B7FFFh
SA3010111XXX170000h to 17FFFFh 0B8000h to 0BFFFFh
SA3111000XXX180000h to 18FFFFh 0C0000h to 0C7FFFh
SA3211001XXX190000h to 19FFFFh 0C8000h to 0CFFFFh
SA3311010XXX1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA3411011XXX1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA3511100XXX1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA3611101XXX1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA3711110XXX1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA3811111XXX1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
MB84VD2118XA-85/MB84VD2119XA-85
20
Tabl e 4.1 Sector Group Address (MB84VD2118XA)
(Top Boot Block)
Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 00000XXX SA0
SGA1
00001XXX
SA1 to SA300010XXX
00011XXX
SGA2 001XXXXXSA4 to SA7
SGA3 0 1 0 X X X X X SA8 to SA11
SGA4 0 1 1 X X X X X SA12 to SA15
SGA5 1 0 0 X X X X X SA16 to SA19
SGA6 1 0 1 X X X X X SA20 to SA23
SGA7 1 1 0 X X X X X SA24 to SA27
SGA8
11100XXX
SA28 to SA3011101XXX
11110XXX
SGA9 11111000 SA31
SGA1011111001 SA32
SGA1111111010 SA33
SGA1211111011 SA34
SGA1311111100 SA35
SGA1411111101 SA36
SGA1511111110 SA37
SGA1611111111 SA38
MB84VD2118XA-85/MB84VD2119XA-85
21
Tabl e 4.2 Sector Group Address (MB84VD2119XA)
(Bottom Boot Block)
Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 00000000 SA0
SGA1 00000001 SA1
SGA2 00000010 SA2
SGA3 00000011 SA3
SGA4 00000100 SA4
SGA5 00000101 SA5
SGA6 00000110 SA6
SGA7 00000111 SA7
SGA8
00001XXX
SA8 to SA1000010XXX
00011XXX
SGA9 0 0 1 X X X X X SA11 to SA14
SGA10 0 1 0 X X X X X SA15 to SA18
SGA11 0 1 1 X X X X X SA19 to SA22
SGA12 1 0 0 X X X X X SA23 to SA26
SGA13 1 0 1 X X X X X SA27 to SA30
SGA14 1 1 0 X X X X X SA31 to SA34
SGA15
11100XXX
SA35 to SA3711101XXX
11110XXX
SGA16 1 1 1 1 1 X X X SA38
MB84VD2118XA-85/MB84VD2119XA-85
22
Table 5 Flash Memory Autoselect Codes
*1 : A-1 is for Byte mode.
*2 : Output 01h at protected sector address and output 00h at unprotected sector address.
Type A12 to A19 A6A1A0A-1*1Code (hEX)
Manufacturer’s Code X VIL VIL VIL VIL 04h
Device
Code
MB84VD21181A Byte XV
IL VIL VIH VIL 36h
Word X 2236h
MB84VD21191A Byte XV
IL VIL VIH VIL 39h
Word X 2239h
MB84VD21182A Byte XV
IL VIL VIH VIL 2Dh
Word X 222Dh
MB84VD21192A Byte XV
IL VIL VIH VIL 2Eh
Word X 222Eh
MB84VD21183A Byte XV
IL VIL VIH VIL 28h
Word X 2228h
MB84VD21193A Byte XV
IL VIL VIH VIL 2Bh
Word X 222Bh
MB84VD21184A Byte XV
IL VIL VIH VIL 33h
Word X 2233h
MB84VD21194A Byte XV
IL VIL VIH VIL 35h
Word X 2235h
Sector Group protect Sector Group
Address VIL VIH VIL VIL 01h*2
MB84VD2118XA-85/MB84VD2119XA-85
23
Tabl e 6 Flash Memory Command Definitions
Command
Sequence
Bus
Write
Cycles
Req’d
First Bus
Write Cycle Second Bus
Write Cycle Third Bus
Write Cycle Fourth Bus
Read/Write
Cycle Fifth Bus
Write Cycle Sixth Bus
Write Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset *11 XXXh F0h 
Read/Reset *1Word 3555h AAh 2AAh 55h 555h F0h RA RD 
Byte AAAh 555h AAAh
Autoselect Word 3555h AAh 2AAh 55h
(BA)
555h 90h 
Byte AAAh 555h (BA)
AAAh
Program Word 4555h AAh 2AAh 55h 555h A0h PA PD 
Byte AAAh 555h AAAh
Chip Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
Byte AAAh 555h AAAh AAAh 555h AAAh
Sector Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h
Byte AAAh 555h AAAh AAAh 555h
Sector Erase Suspend 1 BA B0h 
Sector Erase Resume 1 BA 30h 
Set to
Fast Mode Word 3555h AAh 2AAh 55h 555h 20h 
Byte AAAh 555h AAAh
Fast Program
*2Word 2 XXXh A0h PA PD 
Byte
Reset from
Fast Mode *2Word 2 BA 90h XXXh F0h *6 
Byte
Extended
Sector Group
Protection *3
Word 4 XXXh 60h SPA 60h SPA 40h SPA SD 
Byte
Query *4Word 155h 98h 
Byte AAh
Hi-ROM Entry Word 3555h AAh 2AAh 55h 555h 88h 
Byte AAAh 555h AAAh
Hi-ROM
Program *5Word 4555h AAh 2AAh 55h 555h A0h PA PD 
Byte AAAh 555h AAAh
Hi-ROM Erase
*5Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h HRA 30h
Byte AAAh 555h AAAh AAAh 555h
Hi-ROM Exit *5Word 4555h AAh 2AAh 55h
(HRBA)
555h 90h XXXh 00h 
Byte AAAh 555h (HRBA)
AAAh
MB84VD2118XA-85/MB84VD2119XA-85
24
*1:Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2:This command is valid while Fast Mode.
*3:This command is valid while RESET = VID.
*4:The valid Address is A0 to A6.
*5:This command is valid while Hi-ROM mode.
*6:The data “00h” is also acceptable.
Address bits A12 to A19 = X = “H” or “L” for all address commands except for Program Address (PA) ,
Sector Address (SA) , and Bank Address (BA) .
Bus operations are defined in Table 2 “User Bus Operations”.
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank address (A15 to A19)
SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0).
HRA = Address of the Hidden-ROM area.
SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0).
HRA = Address of the Hidden-ROM area.
MB84VD2118XA (Top Boot Type) Word mode: 0F8000h to 0FFFFFh
Byte mode: 1F0000h to 1FFFFFh
MB84VD2119XA (Bottom Boot Type) Word mode: 000000h to 007FFFh
Byte mode: 000000h to 00FFFFh
HRBA = Bank addrss of the Hidden-ROM area.
MB84VD2118XA (Top Boot Type) : A15 = A16 = A17 = A18 = A19 = A20 = 1
MB84VD2119XA (Bottom Boot Type) : A15 = A16 = A17 = A18 = A19 = A20 = 0
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA.
SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h
at unprotected sector addresses.
The system should generate the following address patterns;
Word mode : 555h or 2AAh to addresses A0 to A10
Byte mode : AAAh or 555h to addresses A -1 and A0 to A10
MB84VD2118XA-85/MB84VD2119XA-85
25
■
■■
■ABSOLUTE MAXIMUM RATINGS
*1:Minimum DC v oltage on input or I/O pins is –0.3 V. During voltage tr ansitions, input or I/O pins ma y undershoot
VSS to –2.0 V f or periods of up to 20 ns. Maxim um DC v oltage on input or I/O pins is VCCf +0.4 V or VCCs+0.4 V.
During voltage transitions, input or I/O pins ma y ov ershoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns.
*2:Minimum DC input v oltage on RESET pin is –0.5 V. During voltage tr ansitions, RESET pin ma y undershoot VSS
to –2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V.
Maximum DC input v oltage on RESET pin is +13.0 V which ma y ov ershoot to +14.0 V f or periods of up to 20 ns.
*3:Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/A CC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■
■■
■RECOMMENDED OPERATING CONDITIONS
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Rating Unit
Min. Max.
Storage Temperature Tstg −55 +125 °C
Ambient Temperature with Power
Applied TA−25 +85 °C
Voltage with Respect to Ground All
pins except RESET and WP/ACC *1VIN, VOUT −0.3 VCCf + 0.4 V
VCCs + 0.4
VCCf/VCCs Supply *1VCCf, VCCs−0.3 +4.0 V
RESET *2VIN −0.5 +13.0 V
WP/ACC *3VIN −0.5 +10.5 V
Parameter Symbol Value Unit
Min. Max.
Ambient Temperature TA−25 +85 °C
VCCf/VCCs Supply Voltages VCCf, VCCs+2.7 +3.6 V
MB84VD2118XA-85/MB84VD2119XA-85
26
■
■■
■ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(Continued)
Parameter Symbol Test Conditions Value Unit
Min. Typ. Max.
Input Leakage Current ILI VIN = VSS to VCCf, VCCs−1.0 +1.0 µA
Output Leakage Current ILO VOUT = VSS to VCCf, VCCs−1.0 +1.0 µA
RESET Inputs Leakage
Current ILIT VCCf = VCCf Max, RESET = 12.5V 35 µA
ACC Input Leakage
Current ILIA VCCf = VCCf Max, WP/ACC = VACC Max 20 mA
Flash VCC Active Current
(Read) *1ICC1fCEf = VIL,
OE = VIH
tCYCLE = 5 MHz Byte 13 mA
tCYCLE = 5 MHz Word 15
tCYCLE = 1 MHz Byte  7mA
tCYCLE = 1 MHz Word  7
Flash VCC Active Current
(Program/Erase) *2ICC2fCEf = VIL, OE = VIH 35 mA
Flash VCC Active Current
(Read-While-Program) *5ICC3fCEf = VIL, OE = VIH Byte 48 mA
Word 50
Flash VCC Active Current
(Read-While-Erase) *5ICC4fCEf = VIL, OE = VIH Byte 48 mA
Word 50
Flash VCC Active Current
(Erase-Suspend-Pro-
gram) ICC5fCEf = VIL, OE = VIH 35 mA
SRAM VCC Active Current ICC1sVCCs = VCCs Max.,
CE1s = VIL,
CE2s = VIH tCYCLE = 10 MHz 40 mA
SRAM VCC Active Current ICC2sCE1s = 0.2 V,
CE2s = VCCs −
0.2 V,
tCYCLE = 10 MHz 40 mA
tCYCLE = 1 MHz  8mA
Flash VCC Standby
Current ISB1fVCCf = VCCf Max., CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf ± 0.3 V 15µA
Flash VCC Standby
Current (RESET) ISB2fVCCf = VCCf Max., RESET = VSS ± 0.3 V
WP/ACC = VCCf ± 0.3 V 15µA
Flash VCC Current
(Automatic Sleep Mode)*3ISB3f
VCCf = VCCf Max., CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf ± 0.3 V
VIN = VCCf ± 0.3 V or VSS ± 0.3 V
15µA
SRAM VCC Standby
Current ISB1sCE1s ≥ VCCs − 0.2V,
CE2s ≥ VCCs − 0.2V 0.2 7 µA
SRAM VCC Standby
Current ISB2sCE2s ≤ 0.2V 0.2 7 µA
MB84VD2118XA-85/MB84VD2119XA-85
27
(Continued)
*1:The ICC current listed includes both the DC operating current and the frequency dependent component.
*2:ICC active while Embedded Algorithm (program or erase) is in progress.
*3:Automatic sleep mode enables the low power mode when address remain stable for 150ns.
*4:Applicable for only VCCf applying.
*5:Embedded Alogorithm (program or erase) is in progress. (@5MHz)
*6:VCC indicates lower of VCCf or VCCs.
Parameter Symbol Test Conditions Value Unit
Min. Typ. Max.
Input Low Level VIL −0.3 0.5 V
Input High Level VIH 2.4 VCC +
0.3 *6V
Voltage for Sector
Protection, and Temporary
Sector Unprotection
(RESET) *4
VID 11.5 12.5 V
Voltage for Program
Acceleration (WP/ACC) *4VACC 8.5 9.0 9.5 V
Output Low Voltage Level VOL VCCf = VCCf Min., VCCs = VCCs Min.,
IOL = 1.0 mA  0.4 V
Output High Voltage Level VOH VCCf = VCCf Min., VCCs = VCCs Min.,
IOH = −0.5 mA 2.4 V
Flash Low VCCf Lock-Out
Voltage VLKO 2.3 2.5 V
MB84VD2118XA-85/MB84VD2119XA-85
28
2. AC Characteristics
•CE Timing
•Timing Diagram for alternating SRAM to Flash
Parameter Symbol Test Setup Value Unit
JEDEC Standard Min.
CE Recover Time tCCR 0ns
tCCR
tCCR
tCCR
tCCR
CEf
CE1s
CE2s
MB84VD2118XA-85/MB84VD2119XA-85
29
•Read Only Operations Characteristics (Flash)
Note : Test Conditions − Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to 3.0 V
Timing measurement reference level
Input : 1.5 V
Output : 1.5 V
Parameter Symbol Test
Setup Value (Note) Unit
JEDEC Standard Min. Max.
Read Cycle Time tAVAV tRC 85 ns
Address to Output Delay tAVQV tACC CEf = VIL
OE = VIL 85 ns
Chip Enable to Output Delay tELQV tCEfOE = VIL 85 ns
Output Enable to Output Delay tGLQV tOE 35 ns
Chip Enable to Output High-Z tEHQZ tDF 30 ns
Output Enable to Output High-Z tGHQZ tDF 30 ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First tAXQX tOH 0ns
RESET Pin Low to Read Mode tREADY 20 µs
MB84VD2118XA-85/MB84VD2119XA-85
30
•Read Cyc le (Flash)
Address
CEf
OE
WE
DQ Output Valid
Address Stable
tRC
tACC
tOE tDF
tOEH
tCEf
High-Z High-Z
Address
CEf
RESET
DQ Output Valid
Address Stable
tRC
tACC
tRH
tCEftRHtRP
tOH
High-Z
MB84VD2118XA-85/MB84VD2119XA-85
31
•Erase/Program Operations (Flash)
(Continued)
Parameter Symbol Value Unit
JEDEC Standard Min. Typ. Max.
Write Cycle Time tAVAV tWC 85 ns
Address Setup Time (WE to Addr.) tAVWL tAS 0ns
Address Setup Time to CEf Low During Toggle Bit Polling tASO 15 ns
Address Hold Time (WE to Addr.) tWLAX tAH 45 ns
Address Hold Time from CEf or OE High During Toggle Bit
Polling tAHT 0ns
Data Setup Time tDVWH tDS 35 ns
Data Hold Time tWHDX tDH 0ns
Output Enable Setup Time tOES 0ns
Output Enable Hold Time Read tOEH 0ns
Toggle and Data Polling 10 ns
CEf High During Toggle Bit Polling tCEPH 20 ns
OE High During Toggle Bit Polling tOEPH 20 ns
Read Recover Time Before Write (OE to CEf) tGHEL tGHEL 0ns
Read Recover Time Before Write (OE to WE) tGHWL tGHWL 0ns
WE Setup Time (CEf to WE) tWLEL tWS 0ns
CEf Setup Time (WE to CEf) tELWL tCS 0ns
WE Hold Time (CEf to WE) tEHWH tWH 0ns
CEf Hold Time (WE to CEf) tWHEH tCH 0ns
Write Pulse Width tWLWH tWP 35 ns
CEf Pulse Width tELEH tCP 35 ns
Write Pulse Width High tWHWL tWPH 30 ns
CEf Pulse Width High tEHEL tCPH 30 ns
Byte Programming Operation tWHWH1 tWHWH1 8µs
Word Programming Operation 16 µs
Sector Erase Operation *1tWHWH2 tWHWH2 1s
MB84VD2118XA-85/MB84VD2119XA-85
32
(Continued)
*1:This does not include the preprogramming time.
*2:This timing is for Sector Protection Operation.
*3:The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will
start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the e xecution
of the Sector Erase command (s) .
*4:When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD” to suspend the erase operation.
Parameter Symbol Value Unit
JEDEC Standard Min. Typ. Max.
VCCf Setup Time tVCS 50 µs
Voltage Transition Time *2tVLHT 4µs
Rise Time to VID *2tVIDR 500 ns
Rise Time to VACC tVACCR 500 ns
Recover Time from RY/BY tRB 0ns
RESET Pulse Width tRP 500 ns
Delay Time from Embedded Output Enable tEOE 85 ns
RESET Hold Time Before Read tRH 200 ns
Program/Erase Valid to RY/BY Delay tBUSY 90 ns
Erase Time-out Time *3tTOW 50 µs
Erase Suspend Transition Time *4tSPD 20 µs
MB84VD2118XA-85/MB84VD2119XA-85
33
•Write Cycle (WE control) (Flash)
Address
WE
OE
CEf
DQ
3rd Bus Cycle
555h
A0h PD DQ7DOUT DOUT
PA PA
Data Polling
tWC
tCS
tWP
tDS
tDH
tOH
tOE
tCEf
tWPH tWHWH1
tGHWL
tCH
tAS tAH tRC
Notes : 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)
MB84VD2118XA-85/MB84VD2119XA-85
34
•Write Cycle (CEf control) (Flash)
Address
WE
OE
CEf
DQ
3rd Bus Cycle
555h
A0h PD DQ7DOUT
PA PA
Data Polling
tWC
tWS
tCP
tDS
tDH
tCPH tWHWH1
tGHEL
tWH
tAS tAH
Notes : 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)
MB84VD2118XA-85/MB84VD2119XA-85
35
•AC Waveforms Chip/Sector Erase Operations (Flash)
555h 2AAh 2AAh555h 555h
tWC
tGHWL
tAS tAH
SA*
Address
WE
OE
CEf
DQ
VCCf
tCS tCH
tVCS
tWPHtWP
tDS tDH
AAh 55h 80h AAh 55h 10h/
30h
30h for Sector Erase
Note : These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)
*: SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
MB84VD2118XA-85/MB84VD2119XA-85
36
•AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
WE
OE
CEf
DQ7
DQ
(DQ0 to DQ6)
RY/BY
Data In
Data In
DQ7 =
Valid Data
DQ0 to DQ6
Valid Data
tEOE
DQ7
DQ0 to DQ6 = Output Flag
tCH tOE tDF
tOEH
tCEf
tWHWH1 or 2
tBUSY
High-Z
High-Z
*
*: DQ7 = Valid Data (The device has completed the Embedded operation.)
MB84VD2118XA-85/MB84VD2119XA-85
37
•AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
WE
CEf
OE
DQ6/DQ2
RY/BY
Toggle
Data
Data Toggle
Data Toggle
Data Stop
Toggling Output
Valid
tDH
tOEH
tOEPH
tBUSY
tOE tCEf*
tOEH
tAHT
tCEPH
tAStAHT tASO
* : DQ6 stops toggling (The device has completed the Embedded operation) .
MB84VD2118XA-85/MB84VD2119XA-85
38
•Back-to-back Read/Write Timing Diagram (Flash)
Address
WE
OE
CEf
DQ Valid
Output Valid
Input
(A0h)
Valid
Output Valid
Output Status
Valid
Input
(PD)
tRC
tAS
tWC tRC tWC tRC
tAS
tAHT
tCEPH
tRC
Read Command Read Command Read Read
BA1 BA2
(555h) BA2
(PA) BA2
(PA)
BA1 BA1
tAH
tCEf
tOE
tGHWL tOEH tDF
tDF
tWP
tDS tDH
tACC
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address of Bank 1.
BA2 : Address of Bank 2.
MB84VD2118XA-85/MB84VD2119XA-85
39
•RY/BY Timing Diagram during Write/Erase Operations (Flash)
•RESET, RY/BY Timing Diagram (Flash)
The rising edge of the last write pulse
Entire programming
or erase operations
tBUSY
RY/BY
WE
CEf
RY/BY
RESET
WE
tREADY
tRP
tRB
MB84VD2118XA-85/MB84VD2119XA-85
40
•Temporary Sector Unprotection (Flash)
RY/BY
RESET
VCCf
3 V 3 V
CEf
WE
VID
Program or Erase Command Sequence
Unprotection Period
tVCS tVIDR tVLHT
tVLHT
tVLHT
MB84VD2118XA-85/MB84VD2119XA-85
41
•Extended Sector Protection (Flash)
VCCf
RESET
Address
A0
A1
A6
CEf
Data 60h 60h 40h 01h 60h
tVCS
tVIDR
tVLHT
tWC tWC
tWP
TIME - OUT
tOE
SGAx SGAx SGAy
OE
WE
SGAx : Sector Group Address to be protected
SGAy : Next Group Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min.)
MB84VD2118XA-85/MB84VD2119XA-85
42
• Accelerated Program (Flash)
3 V
WP/ACC
VCCf
CEf
WE
RY/BY
tVLHT Program Command Sequence
3 V
tVLHT
tVCS
tVACCR
VACC
tVLHT
Acceleration period
MB84VD2118XA-85/MB84VD2119XA-85
43
•Read Cycle (SRAM)
Note: Test conditions: Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCs
Timing measurement reference level
Input: 0.5 × VCCs
Output: 0.5 × VCCs
Parameter Symbol Value Unit
Min. Max.
Read Cycle Time tRC 85 ns
Address Access Time tAA 85 ns
Chip Enable (CE1s) Access Time tCO1 85 ns
Chip Enable (CE2s) Access Time tCO2 85 ns
Output Enable Access Time tOE 45 ns
LBS, UBS to Output Valid tBA 85 ns
Chip Enable (CE1s Low and CE2s High) to Output Active tCOE 5ns
Output Enable Low to Output Active tOEE 0ns
UBS, LBS Enable Low to Output Active tBE 0ns
Chip Enable (CE1s High or CE2s Low) to Output High-Z tOD 35 ns
Output Enable High to Output High-Z tODO 35 ns
UBS, LBS Output Enable to Output High-Z tBD 50 ns
Output Data Hold Time tOH 10 ns
MB84VD2118XA-85/MB84VD2119XA-85
44
•Read Cycle (Note) (SRAM)
Note : WE remains “H” for the read cycle.
Address
OE
CE2s
CE1s
LBS, UBS
DQ
tRC
tOH
tOD
tOD
tODO
tBD
tAA
tCO1
tCO2
tOE
tOEE
tBA
tBE
tCOE
tCOE
Valid Data Out
MB84VD2118XA-85/MB84VD2119XA-85
45
•Write Cycle (SRAM)
Parameter Symbol Value Unit
Min. Max.
Write Cycle Time tWC 85 ns
Write Pulse Width tWP 55 ns
Chip Enable to End of Write tCW 70 ns
Address valid to End of Write tAW 70 ns
UBS, LBS to End of Write tBW 55 ns
Address Setup Time tAS 0ns
Write Recovery Time tWR 0ns
WE Low to Output High-Z tODW 35 ns
WE High to Output Active tOEW 0ns
Data Setup Time tDS 35 ns
Data Hold Time tDH 0ns
MB84VD2118XA-85/MB84VD2119XA-85
46
•Write Cycle (Note 3) (WE control) (SRAM)
tWC
tAS tWP tWR
tAW
tCW
tCW
tBW
tODW
tDS tDH
tOEW
Address
WE
LBS, UBS
CE1s
CE2s
DOUT
DIN
Note 1 Note 2
Note 4Note 4 Valid Data In
Notes : 1. If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will
remain at High-Z.
2. If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output will
remain at High-Z.
3. If OE is “H” during the write cycle, the outputs will remain at High-Z.
4. Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
MB84VD2118XA-85/MB84VD2119XA-85
47
• Write Cycle (Note 1) (CE1s control) (SRAM)
tWC
tAS tWP tWR
tAW
tCW
tCW
tBW
tODW
tDS tDH
tCOE
tBE
Valid Data In
Address
WE
LBS, UBS
CE1s
CE2s
DOUT
DIN Note 2
Notes : 1. If OE is “H” during the write cycle, the outputs will remain at High-Z.
2. Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
MB84VD2118XA-85/MB84VD2119XA-85
48
•Write Cycle (Note 1) (CE2s Control) (SRAM)
Address
WE
CE1s
CE2s
LBS, UBS
DOUT
DIN Note 2 Valid Data In
tDS
tODWtCOE
tBE
tBW
tCW
tCW
tWP
tWC
tAS tWR
tAW
tDH
Notes : 1. If OE is “H” during the write cycle, the outputs will remain at High-Z.
2. Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
MB84VD2118XA-85/MB84VD2119XA-85
49
• Write Cycl e (Note 1) (LBs, UBs Control) (SRAM)
Address
WE
CE1s
CE2s
DOUT
DIN
LBS, UBS
Valid Data In
tDS
tODW
tCOE
tBE
tBWtAS
tAW
tCW
tCW
tWP
tWC
tWR
tDH
Note 2
Notes : 1. If OE is “H” during the write cycle, the outputs will remain at High-Z.
2. Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
MB84VD2118XA-85/MB84VD2119XA-85
50
■
■■
■ERASE AND PROGRAMMING PERFORMANCE (Flash)
■
■■
■DATA RETENTION CHARACTERISTICS (SRAM)
* : 4 µA Max. at TA ≤ 60 °C, 1 µA Max. at TA ≤ 40 °C
Note : tRC : Read cycle time
•CE1s Controlled Data Retention Mode (Note 1)
Parameter Limits Unit Comment
Min. Typ. Max.
Sector Erase Time 110s
Excludes programming time
prior to erasure
Byte Programming Time 8 300 µsExcludes system-level
overhead
Word Programming Time 16 360 µsExcludes system-level
overhead
Chip Programming Time 50 s Excludes system-level
overhead
Erase/Program Cycle 100,000 cycle
Parameter Symbol Value Unit
Min. Typ. Max.
Data Retention Supply Voltage VDH 1.5 3.6 V
Standby Current VDH = 3.0 V IDDS2 0.2 7* µA
Chip Deselect to Data Retention Mode Time tCDR 0ns
Recovery Time tRtRC ns
Data Retention Mode
See Note 2See Note 2
tRtCDR VCCS −0.2 V
VCCs
VIH
VDH
CE1s
2.7 V
GND
MB84VD2118XA-85/MB84VD2119XA-85
51
•CE2s Controlled Data Retention Mode (Note 3)
Notes : 1. In CE1s controlled data retention mode, input le vel of CE2s should be fix ed Vccs to Vccs − 0.2 V or Vss
to 0.2 V during data retention mode. Other input and input/output pins can be used between −0.3 V and
Vccs + 0.3 V.
2. When CE1s is operating at the VIH Min. level (2.2 V) , the standby current is given by ISB1s during
the transition of VCCs from 3.6 to 2.2 V.
3. In CE2s controlled data retention mode, input and input/output pins can be used between −0.3 V and
Vccs + 0.3 V.
■
■■
■PIN CAPACITANCE
Note : Test conditions TA = 25 °C, f = 1.0 MHz
■
■■
■HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
■
■■
■CAUTION
1. The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not
use autoselect and sector protect function by applying the high voltage (VID) to specific pins.
2. For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the
sector using “Extended sector protect” command.
Parameter Symbol Test Setup Value Unit
Typ. Max.
Input Capacitance CIN VIN = 01114pF
Output Capacitance COUT VOUT = 01216pF
Control Pin Capacitance CIN2 VIN = 01416pF
WP/ACC Pin Capacitance CIN3 VIN = 01720pF
0.2 V
Data Retention Mode
VCCs
CE2s
VDH
VIH
VIL
tCDR tR
GND
2.7 V
MB84VD2118XA-85/MB84VD2119XA-85
52
■
■■
■ORDERING INFORMATION
MB84VD2118 X A -85 -PBS
DEVICE NUMBER/DESCRIPTION
16Mega-bit (2M × 8-bit or 1M × 16-bit) Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
4Mega-bit (512K × 8-bit) SRAM
BOOT CODE SECTOR ARCHITECTURE
84VD2118 = Top sector
84VD2119 = Bottom sector
PACKAGE TYPE
PBS = 69-ball FBGA
PTS = 56-pin TSOP (I)
SPEED OPTION
See Product Selector Guide.
Device Revision
Bank Size
1 =0.5 Mbit /15.5 Mbit
2 =2 Mbit / 14 Mbit
3 =4 Mbit / 12 Mbit
4 =8 Mbit / 8 Mbit
MB84VD2118XA-85/MB84VD2119XA-85
53
■
■■
■PACKAGE DIMENSIONS
(Continued)
69-ball plastic FBGA
(BGA-69P-M02)
Dimension in mm (inches)
C
1999 FUJITSU LIMITED B69002S-1C-1
11.00±0.10(.433±.004) .049 –.004
+.006
–0.10
+0.15
1.25 (Mounting height)
0.38±0.10
(.015±.004) (Stand off)
1
2
3
4
5
6
7
8
9
10
ABCDEFGH
0.80(.031)
5.60(.220)REF
0.80(.031)
7.20(.283)
REF
5.60(.220)
INDEX BALL
69-Ø0.18 –.002
+.004
–0.05
+0.10
69-Ø0.45 M
0.08(.003)
0.10(.004)
INDEX-MARK AREA
8.00±0.10
(.315±.004)
7.20(.283)
JK
MB84VD2118XA-85/MB84VD2119XA-85
54
(Continued)
56-pin plastic TSOP (I)
(FPT-56P-M04)
Dimension in mm (inches)
0.145 +0.05
–0.03
+.002
–.001
.006
0°~8°
Details of "A" part
0.25(.010)
(.018/.030)
0.45/0.75
"A"
0.08(.003) (Mounting height)
(.045±.002)
1.15±0.05
(Stand off)
(.004±.002)
0.10±0.05
INDEX
12.00±0.10
(.472±.004)
0.10(.004) M
(.007±.001)
0.18±0.035
TYP
0.40(.016)
14.00±0.20(.551±.008)
12.40±0.10(.488±.004)
1998 FUJITSU LIMITED F56004S-1C-1
C
MB84VD2118XA-85/MB84VD2119XA-85
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
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Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
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D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
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FUJITSU MICROELECTR ONICS ASIA PTE. LTD .
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
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1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0104
FUJITSU LIMITED Printed in Japan
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Customers are advised to consult with FUJITSU sales
representatives before ordering.
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presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
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The products described in this document are designed, and
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