Features
•Single 2.5V - 3.6V or 2.7V - 3.6V Supply
•Serial Peripheral Interface (SPI) Compatible
•20 MHz Max Clock Frequency
•Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 2048 Pages (264 Bytes/Page) Main Memory
•Supports Page and Block Erase Operations
•Two 264-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Memory Array
•Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
•Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
•Hardware Data Protection Feature
•5.0V-tolerant Inputs: SI, SCK, CS, RESET, and WP Pins
•Commercial and Industrial Temperature Ranges
•Green (Pb/Halide-free/RoHS Compliant) Package Options
1. Description
The AT45DB041B is an SPI compatible serial interface Flash memory ideally suited
for a wide variety of digital voice-, image-, program code- and data-storage applica-
tions. Its 4,325,376 bits of memory are organized as 2048 pages of 264 bytes each. In
addition to the main memory, the AT45DB041B also contains two SRAM data buffers
of 264 bytes each.
The buffers allow receiving of data while a page in the main memory is being repro-
grammed, as well as reading or writing a continuous data stream. EEPROM emulation
(bit or byte alterability) is easily handled with a self-contained three step Read-Modify-
Write operation. Unlike conventional Flash memories that are accessed randomly with
multiple address lines and a parallel interface, the DataFlash uses a SPI serial inter-
face to sequentially access its data. DataFlash supports SPI mode 0 and mode 3. The
simple serial interface facilitates hardware layout, increases system reliability, mini-
mizes switching noise, and reduces package size and active pin count. The device is
optimized for use in many commercial and industrial applications where high density,
low pin count, low voltage, and low power are essential. The device operates at clock
frequencies up to 20 MHz with a typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the AT45DB041B does not require
high input voltages for programming. The device operates from a single power supply,
2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The
AT45DB041B is enabled through the chip select pin (CS) and accessed via a three-
wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial
Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
4-megabit
2.5-volt or
2.7-volt
DataFlash®
AT45DB041B
For New
Designs Use
AT45DB041D
3443D–DFLSH–2/08
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3443D–DFLSH–2/08
AT45DB041B
When the device is shipped from Atmel, the most significant page of the memory array may not
be erased. In other words, the contents of the last page may not be filled with FFH.
2. Pin Configurations and Packages
Table 2-1. Pin Configurations
Pin Name Function
CS Chip Select
SCK Serial Clock
SI Serial Input
SO Serial Output
WP Hardware Page Write Protect Pin
RESET Chip Reset
RDY/BUSY Ready/Busy
Figure 2-1. TSOP Top View Type 1
Figure 2-2. CASON – Top View through Package Figure 2-3. 8-SOIC
Figure 2-4. 28-SOIC(1)
Note: 1. The next generation DataFlash devices will not be
offered in 28-SOIC package, therefore, this pack-
age is not recommended for new designs.
Figure 2-5. CBGA Top View
through Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SI
SCK
RESET
CS
SO
GND
VCC
WP
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
SI
SCK
RESET
CS
SO
GND
VCC
WP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
D
E
12 3
NC
VCC
WP
RESET
NC
NC
GND
RDY/BSY
SI
NC
SCK
CS
SO
NC
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AT45DB041B
3. Block Diagram
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB041B is divided into three levels of
granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page-by-page basis; however, the optional
erase operations can be performed at the block or page level.
Figure 4-1. Memory Architecture Diagram
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)
I/O INTERFACE
SCK
CS
RESET
VCC
GND
RDY/BUSY
WP
SOSI
SECTOR 0 = 8 Pages
2112 bytes (2K + 64)
SECTOR 1 = 248 Pages
65,472 bytes (62K + 1984)
Block = 2112 bytes
(2K + 64)
8 Pages
SECTOR 0
SECTOR 1
Page = 264 bytes
(256 + 8)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 2046
PAGE 2047
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 2045
BLOCK 1
SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 254
BLOCK 255
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
SECTOR 2
SECTOR 5 = 512 Pages
135,168 bytes (128K + 4K)
BLOCK 2
SECTOR 2 = 256 Pages
67,584 bytes (64K + 2K)
SECTOR 3 = 512 Pages
135,168 bytes (128K + 4K)
SECTOR 4 = 512 Pages
135,168 bytes (128K + 4K)
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AT45DB041B
5. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with
the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling the SCK pin controls the loading of
the opcode and the desired buffer or main memory address location through the SI (serial input)
pin. All instructions, addresses and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA8 - BFA0 to denote
the nine address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA10 - PA0 and BA8 - BA0 where PA10 - PA0
denotes the 11 address bits required to designate a page address and BA8 - BA0 denotes the
nine address bits required to designate a byte address within the page.
5.1 Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two data buffers. The DataFlash supports two categories of read modes in relation to
the SCK signal. The differences between the modes are in respect to the inactive state of the
SCK signal as well as which clock cycle data will begin to be output. The two categories, which
are comprised of four modes total, are defined as Inactive Clock Polarity Low or Inactive Clock
Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer to Table 5-3 on page 10
for a complete list) is used to select which category will be used for reading. Please refer to the
“Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle
sequences for each mode.
5.1.1 Continuous Array Read
By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be
clocked into the device followed by 24 address bits and 32 don’t care bits. The first four bits of
the 24-bit address sequence are reserved for upward and downward compatibility to larger and
smaller density devices (see Notes under “Command Sequence for Read/Write Operations” dia-
gram). The next 11 address bits (PA10 - PA0) specify which page of the main memory array to
read, and the last nine bits (BA8 - BA0) of the 24-bit address sequence specify the starting byte
address within the page. The 32 don’t care bits that follow the 24 address bits are needed to ini-
tialize the read operation. Following the 32 don’t care bits, additional clock pulses on the SCK
pin will result in serial data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t care
bits, and the reading of data. When the end of a page in main memory is reached during a Con-
tinuous Array Read, the device will continue reading at the beginning of the next page with no
delays incurred during the page boundary crossover (the crossover from the end of one page to
the beginning of the next page). When the last bit in the main memory array has been read, the
device will continue reading back at the beginning of the first page of memory. As with crossing
over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
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AT45DB041B
A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR
specification. The Continuous Array Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
5.1.2 Main Memory Page Read
A Main Memory Page Read allows the user to read data directly from any one of the 2048 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read, an opcode of 52H or D2H must be clocked into the device fol-
lowed by 24 address bits and 32 don’t care bits. The first four bits of the 24-bit address
sequence are reserved bits, the next 11 address bits (PA10 - PA0) specify the page address,
and the next nine address bits (BA8 - BA0) specify the starting byte address within the page.
The 32 don’t care bits which follow the 24 address bits are sent to initialize the read operation.
Following the 32 don’t care bits, additional pulses on SCK result in serial data being output on
the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bits, the don’t care bits, and the reading of data. When the end of a page in main mem-
ory is reached during a Main Memory Page Read, the device will continue reading at the
beginning of the same page. A low-to-high transition on the CS pin will terminate the read oper-
ation and tri-state the SO pin.
5.1.3 Buffer Read
Data can be read from either one of the two buffers, using different opcodes to specify which
buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode
of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the eight bits of the
opcode must be followed by 15 don’t care bits, nine address bits, and eight don’t care bits. Since
the buffer size is 264 bytes, nine address bits (BFA8 - BFA0) are required to specify the first byte
of data to be read from the buffer. The CS pin must remain low during the loading of the opcode,
the address bits, the don’t care bits, and the reading of data. When the end of a buffer is
reached, the device will continue reading back at the beginning of the buffer. A low-to-high tran-
sition on the CS pin will terminate the read operation and tri-state the SO pin.
5.1.4 Status Register Read
The status register can be used to determine the device’s Ready/Busy status, the result of a
Main Memory Page to Buffer Compare operation, or the device density. To read the status reg-
ister, an opcode of 57H or D7H must be loaded into the device. After the last bit of the opcode is
shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on
the SO pin during the next eight clock cycles. The five most significant bits of the status register
will contain device information, while the remaining three least-significant bits are reserved for
future use and will have undefined values. After bit 0 of the status register has been shifted out,
the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting
again with bit 7. The data in the status register is constantly updated, so each repeating
sequence will output new data.
Table 5-1. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY COMP0111XX
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AT45DB041B
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is
not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level
once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and once
the device is no longer busy, the state of SO will change from 0 to 1. There are eight operations
which can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main
Memory Page to Buffer Compare, Buffer to Main Memory Page Program with Built-in Erase,
Buffer to Main Memory Page Program without Built-in Erase, Page Erase, Block Erase, Main
Memory Page Program, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using
bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the
data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does
not match the data in the buffer.
The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the
AT45DB041B, the four bits are 0, 1, 1 and 1. The decimal value of these four binary bits does
not equate to the device density; the four bits represent a combinational code relating to differing
densities of Serial DataFlash devices, allowing a total of sixteen different density configurations.
5.2 Program and Erase Commands
5.2.1 Buffer Write
Data can be shifted in from the SI pin into either buffer 1 or buffer 2. To load data into either
buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, must be followed by 15 don’t care
bits and nine address bits (BFA8 - BFA0). The nine address bits specify the first byte in the
buffer to be written. The data is entered following the address bits. If the end of the data buffer is
reached, the device will wrap around back to the beginning of the buffer. Data will continue to be
loaded into the buffer until a low-to-high transition is detected on the CS pin.
5.2.2 Buffer to Main Memory Page Program with Built-in Erase
Data written into either buffer 1 or buffer 2 can be programmed into the main memory. To start
the operation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be followed by the four
reserved bits, 11 address bits (PA10 - PA0) that specify the page in the main memory to be writ-
ten, and nine additional don’t care bits. When a low-to-high transition occurs on the CS pin, the
part will first erase the selected page in main memory to all 1s and then program the data stored
in the buffer into the specified page in the main memory. Both the erase and the programming of
the page are internally self-timed and should take place in a maximum time of tEP. During this
time, the status register will indicate that the part is busy.
5.2.3 Buffer to Main Memory Page Program without Built-in Erase
A previously erased page within main memory can be programmed with the contents of either
buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or 89H for buffer 2,
must be followed by the four reserved bits, 11 address bits (PA10 - PA0) that specify the page in
the main memory to be written, and nine additional don’t care bits. When a low-to-high transition
occurs on the CS pin, the part will program the data stored in the buffer into the specified page in
the main memory. It is necessary that the page in main memory that is being programmed has
been previously erased. The programming of the page is internally self-timed and should take
place in a maximum time of tP. During this time, the status register will indicate that the part is
busy.
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3443D–DFLSH–2/08
AT45DB041B
Successive page programming operations without doing a page erase are not recommended. In
other words, changing bytes within a page from a “1” to a “0” during multiple page programming
operations without erasing that page is not recommended.
5.2.4 Page Erase
The optional Page Erase command can be used to individually erase any page in the main
memory array allowing the Buffer to Main Memory Page Program without Built-in Erase com-
mand to be utilized at a later time. To perform a Page Erase, an opcode of 81H must be loaded
into the device, followed by four reserved bits, 11 address bits (PA10 - PA0), and nine don’t care
bits. The 11 address bits are used to specify which page of the memory array is to be erased.
When a low-to-high transition occurs on the CS pin, the part will erase the selected page to 1s.
The erase operation is internally self-timed and should take place in a maximum time of tPE. Dur-
ing this time, the status register will indicate that the part is busy.
5.2.5 Block Erase
A block of eight pages can be erased at one time allowing the Buffer to Main Memory Page Pro-
gram without Built-in Erase command to be utilized to reduce programming times when writing
large amounts of data to the device. To perform a Block Erase, an opcode of 50H must be
loaded into the device, followed by four reserved bits, eight address bits (PA10 - PA3), and 12
don’t care bits. The eight address bits are used to specify which block of eight pages is to be
erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected
block of eight pages to 1s. The erase operation is internally self-timed and should take place in a
maximum time of tBE. During this time, the status register will indicate that the part is busy.
Table 5-2. Block Erase Addressing
PA10 PA9 PA8 PA 7 PA6 PA5 PA 4 PA3 PA2 PA 1 PA0 Blo ck
0 0000000XXX 0
0 0000001XXX 1
0 0000010XXX 2
0 0000011XXX 3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1111100XXX252
1 1111101XXX253
1 1111110XXX254
1 1111111XXX255
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AT45DB041B
5.2.6 Main Memory Page Program Through Buffer
This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program
with Built-in Erase operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and
then programmed into a specified page in the main memory. To initiate the operation, an 8-bit
opcode, 82H for buffer 1 or 85H for buffer 2, must be followed by the four reserved bits and 20
address bits. The 11 most significant address bits (PA10 - PA0) select the page in the main
memory where data is to be written, and the next nine address bits (BFA8 - BFA0) select the first
byte in the buffer to be written. After all address bits are shifted in, the part will take data from the
SI pin and store it in one of the data buffers. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS
pin, the part will first erase the selected page in main memory to all 1s and then program the
data stored in the buffer into the specified page in the main memory. Both the erase and the pro-
gramming of the page are internally self-timed and should take place in a maximum of time tEP.
During this time, the status register will indicate that the part is busy.
5.3 Additional Commands
5.3.1 Main Memory Page to Buffer Transfer
A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start
the operation, an 8-bit opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by the
four reserved bits, 11 address bits (PA10 - PA0) which specify the page in main memory that is
to be transferred, and nine don’t care bits. The CS pin must be low while toggling the SCK pin to
load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of the
page of data from the main memory to the buffer will begin when the CS pin transitions from a
low to a high state. During the transfer of a page of data (tXFR), the status register can be read to
determine whether the transfer has been completed or not.
5.3.2 Main Memory Page to Buffer Compare
A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate
the operation, an 8-bit opcode, 60H for buffer 1 and 61H for buffer 2, must be followed by 24
address bits consisting of the four reserved bits, 11 address bits (PA10 - PA0) which specify the
page in the main memory that is to be compared to the buffer, and nine don’t care bits. The CS
pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don’t
care bits from the SI pin. On the low-to-high transition of the CS pin, the 264 bytes in the
selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2. During
this time (tXFR), the status register will indicate that the part is busy. On completion of the com-
pare operation, bit 6 of the status register is updated with the result of the compare.
5.3.3 Auto Page Rewrite
This mode is only needed if multiple bytes within a page or multiple pages of data are modified in
a random fashion. This mode is a combination of two operations: Main Memory Page to Buffer
Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of data is first
transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1
or buffer 2) is programmed back into its original page of main memory. To start the rewrite oper-
ation, an 8-bit opcode, 58H for buffer 1 or 59H for buffer 2, must be followed by the four reserved
bits, 11 address bits (PA10 - PA0) that specify the page in main memory to be rewritten, and
nine additional don’t care bits. When a low-to-high transition occurs on the CS pin, the part will
first transfer data from the page in main memory to a buffer and then program the data from the
buffer back into same page of main memory. The operation is internally self-timed and should
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3443D–DFLSH–2/08
AT45DB041B
take place in a maximum time of tEP. During this time, the status register will indicate that the
part is busy.
If a sector is programmed or reprogrammed sequentially page-by-page, then the programming
algorithm shown in Figure 17-1 on page 27 is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sector, then the programming algorithm
shown in Figure 17-2 on page 28 is recommended. Each page within a sector must be
updated/rewritten at least once within every 10,000 cumulative page erase/program operations
in that sector.
5.4 Operation Mode Summary
The modes described can be separated into two groups – modes which make use of the Flash
memory array (Group A) and modes which do not make use of the Flash memory array (Group
B).
Group A modes consist of:
1. Main Memory Page Read
2. Main Memory Page to Buffer 1 (or 2) Transfer
3. Main Memory Page to Buffer 1 (or 2) Compare
4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase
5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase
6. Page Erase
7. Block Erase
8. Main Memory Page Program through Buffer
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
If a Group A mode is in progress (not fully completed) then another mode in Group A should not
be started. However, during this time in which a Group A mode is in progress, modes in Group B
can be started.
This gives the Serial DataFlash the ability to virtually accommodate a continuous data stream.
While data is being programmed into main memory from buffer 1, data can be loaded into buffer
2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
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AT45DB041B
Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity
Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3).
Table 5-3. Read Commands
Command SCK Mode Opcode
Continuous Array Read Inactive Clock Polarity Low or High 68H
SPI Mode 0 or 3 E8H
Main Memory Page Read Inactive Clock Polarity Low or High 52H
SPI Mode 0 or 3 D2H
Buffer 1 Read Inactive Clock Polarity Low or High 54H
SPI Mode 0 or 3 D4H
Buffer 2 Read Inactive Clock Polarity Low or High 56H
SPI Mode 0 or 3 D6H
Status Register Read Inactive Clock Polarity Low or High 57H
SPI Mode 0 or 3 D7H
Table 5-4. Program and Erase Commands
Command SCK Mode Opcode
Buffer 1 Write Any 84H
Buffer 2 Write Any 87H
Buffer 1 to Main Memory Page Program with Built-in Erase Any 83H
Buffer 2 to Main Memory Page Program with Built-in Erase Any 86H
Buffer 1 to Main Memory Page Program without Built-in Erase Any 88H
Buffer 2 to Main Memory Page Program without Built-in Erase Any 89H
Page Erase Any 81H
Block Erase Any 50H
Main Memory Page Program through Buffer 1 Any 82H
Main Memory Page Program through Buffer 2 Any 85H
Table 5-5. Additional Commands
Command SCK Mode Opcode
Main Memory Page to Buffer 1 Transfer Any 53H
Main Memory Page to Buffer 2 Transfer Any 55H
Main Memory Page to Buffer 1 Compare Any 60H
Main Memory Page to Buffer 2 Compare Any 61H
Auto Page Rewrite through Buffer 1 Any 58H
Auto Page Rewrite through Buffer 2 Any 59H
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AT45DB041B
5.5 Pin Descriptions
5.5.1 Serial Input (SI)
The SI pin is an input-only pin and is used to shift data into the device. The SI pin is used for all
data input including opcodes and address sequences.
5.5.2 Serial Output (SO)
The SO pin is an output-only pin and is used to shift data out from the device.
5.5.3 Serial Clock (SCK)
The SCK pin is an input-only pin and is used to control the flow of data to and from the
DataFlash. Data is always clocked into the device on the rising edge of SCK and clocked out of
the device on the falling edge of SCK.
5.5.4 Chip Select (CS)
The DataFlash is selected when the CS pin is low. When the device is not selected, data will not
be accepted on the SI pin, and the SO pin will remain in a high-impedance state. A high-to-low
transition on the CS pin is required to start an operation, and a low-to-high transition on the CS
pin is required to end an operation.
5.5.5 Write Protect (WP)
If the WP pin is held low, the first 256 pages of the main memory cannot be reprogrammed. The
only way to reprogram the first 256 pages is to first drive the protect pin high and then use the
program commands previously mentioned. If this pin and feature are not utilized it is recom-
mended that the WP pin be driven high externally.
5.5.6 RESET
A low state on the reset pin (RESET) will terminate the operation in progress and reset the inter-
nal state machine to an idle state. The device will remain in the reset condition as long as a low
level is present on the RESET pin. Normal operation can resume once the RESET pin is brought
back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended
that the RESET pin be driven high externally.
5.5.7 READY/BUSY
This open drain output pin will be driven low when the device is busy in an internally self-timed
operation. This pin, which is normally in a high state (through a 1 kΩ external pull-up resistor),
will be pulled low during programming operations, compare operations, and during page-to-
buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
12
3443D–DFLSH–2/08
AT45DB041B
6. Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device
will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a high-
to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be
automatically selected on every falling edge of CS by sampling the inactive clock state. After
power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms
before an operational mode is started.
Note: r = Reserved Bit
P = Page Address Bit
B = Byte/Buffer Address Bit
x = Don’t Care
Table 6-1. Detailed Bit-level Addressing Sequence
Opcode Opcode
Address Byte Address Byte Address Byte
Additional
Don’t Care
Bytes
Required
50H 01010000r r r r PPPPPPPPxxxxxxxxxxxx N/A
52H 01010010r r r r PPPPPPPPPPPBBBBBBBBB 4 Bytes
53H 01010011r r r r PPPPPPPPPPPxxxxxxxxx N/A
54H 01010100x x x x x x x x x x x x x x x BBBBBBBBB 1 Byte
55H 01010101r r r r PPPPPPPPPPPxxxxxxxxx N/A
56H 01010110x x x x x x x x x x x x x x x BBBBBBBBB 1 Byte
57H 01010111 N/A N/A N/A N/A
58H 01011000r r r r PPPPPPPPPPPxxxxxxxxx N/A
59H 01011001r r r r PPPPPPPPPPPxxxxxxxxx N/A
60H 01100000r r r r PPPPPPPPPPPxxxxxxxxx N/A
61H 01100001r r r r PPPPPPPPPPPxxxxxxxxx N/A
68H 01101000r r r r PPPPPPPPPPPBBBBBBBBB 4 Bytes
81H 10000001r r r r PPPPPPPPPPPxxxxxxxxx N/A
82H 10000010r r r r PPPPPPPPPPPBBBBBBBBB N/A
83H 10000011r r r r PPPPPPPPPPPxxxxxxxxx N/A
84H 10000100x x x x x x x x x x x x x x x BBBBBBBBB N/A
85H 10000101r r r r PPPPPPPPPPPBBBBBBBBB N/A
86H 10000110r r r r PPPPPPPPPPPxxxxxxxxx N/A
87H 10000111x x x x x x x x x x x x x x x BBBBBBBBB N/A
88H 10001000r r r r PPPPPPPPPPPxxxxxxxxx N/A
89H 10001001r r r r PPPPPPPPPPPxxxxxxxxx N/A
D2H 11010010r r r r PPPPPPPPPPPBBBBBBBBB 4 Bytes
D4H 11010100x x x x x x x x x x x x x x x BBBBBBBBB 1 Byte
D6H 11010110x x x x x x x x x x x x x x x BBBBBBBBB 1 Byte
D7H 11010111 N/A N/A N/A N/A
E8H 11101000r r r r PPPPPPPPPPPBBBBBBBBB 4 Bytes
R
eserve
d
R
eserve
d
R
eserve
d
R
eserve
d
PA
10
PA
9
PA
8
PA
7
PA
6
PA
5
PA
4
PA
3
PA
2
PA
1
PA0
BA
8
BA
7
BA
6
BA
5
BA
4
BA
3
BA
2
BA
1
BA
0
13
3443D–DFLSH–2/08
AT45DB041B
Note: 1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an opera-
tional mode is started.
Note: 1. Icc1 during a buffer read is 20mA maximum.
7. Absolute Maximum Ratings*
Temperature under Bias ............................... -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature .................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
8. DC and AC Operating Range
AT45DB041B (2.5V Version) AT45DB041B
Operating Temperature
(Case)
Com. 0°C to 70°C0°C to 70°C
Ind. – -40°C to 85°C
VCC Power Supply(1) 2.5V to 3.6V 2.7V to 3.6V
9. DC Characteristics
Symbol Parameter Condition Min Typ Max Units
ISB Standby Current CS, RESET, WP = VCC, all inputs
at CMOS levels 210µA
ICC1(1) Active Current, Read
Operation
f = 20 MHz; IOUT = 0 mA;
VCC = 3.6V 410mA
ICC2
Active Current,
Program/Erase Operation VCC = 3.6V 15 35 mA
ILI Input Load Current VIN = CMOS levels 1 µA
ILO Output Leakage Current VI/O = CMOS levels 1 µA
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 1.6 mA; VCC = 2.7V 0.4 V
VOH Output High Voltage IOH = -100 µA VCC - 0.2V V
14
3443D–DFLSH–2/08
AT45DB041B
10.1 Input Test Waveforms and Measurement Levels
tR, tF < 3 ns (10% to 90%)
10.2 Output Test Load
10. AC Characteristics
Symbol Parameter
AT45DB041B
(2.5V Version) AT45DB041B
UnitsMin Max Min Max
fSCK SCK Frequency 15 20 MHz
fCAR SCK Frequency for Continuous Array Read 15 20 MHz
tWH SCK High Time 30 22 ns
tWL SCK Low Time 30 22 ns
tCS Minimum CS High Time 250 250 ns
tCSS CS Setup Time 250 250 ns
tCSH CS Hold Time 250 250 ns
tCSB CS High to RDY/BUSY Low 200 200 ns
tSU Data In Setup Time 10 5 ns
tHData In Hold Time 15 10 ns
tHO Output Hold Time 0 0 ns
tDIS Output Disable Time 20 18 ns
tVOutput Valid 25 20 ns
tXFR Page to Buffer Transfer/Compare Time 300 250 µs
tEP Page Erase and Programming Time 20 20 ms
tPPage Programming Time 14 14 ms
tPE Page Erase Time 8 8 ms
tBE Block Erase Time 12 12 ms
tRST RESET Pulse Width 10 10 µs
tREC RESET Recovery Time 1 1 µs
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
2.0
0.8
2.4V
DEVICE
UNDER
TEST
30 pF
15
3443D–DFLSH–2/08
AT45DB041B
11. AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup
and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-
ing that is compatible with SPI Mode 3.
11.1 Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
11.2 Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
11.3 Reset Timing (Inactive Clock Polarity Low Shown)
Note: The CS signal should be in the high state before the RESET signal is deasserted.
CS
SCK
SI
SO
tCSS
VALID IN
tHtSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK
SI
SO
tCSS
VALID IN
tH
tSU
tWL tWH tCSH
tCS
tV
HIGH Z VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK
RESET
SO
HIGH IMPEDANCE HIGH IMPEDANCE
SI
tRST
tREC tCSS
16
3443D–DFLSH–2/08
AT45DB041B
11.4 Command Sequence for Read/Write Operations (except Status Register Read)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 4M bits or smaller.
3. For densities larger than 4M bits, the “r” bits become the most significant Page Address bit for the appropriate density.
SI CMD 8 bits 8 bits 8 bits
MSB
Reserved for
larger densities
Page Address
(PA10-PA0)
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
LSBr r r r X X X X X X X X X X X X X X X X X X X X
17
3443D–DFLSH–2/08
AT45DB041B
12. Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
12.1 Main Memory Page Program through Buffers
12.2 Buffer Write
12.3 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
FLASH MEMORY ARRAY
PAGE (256 BYTES)
BUFFER 2 (256 BYTES)BUFFER 1 (256 BYTES)
I/O INTERFACE
SI
BUFFER 1 TO
PAGE PROGRAM
PAGE PROGRAM
THROUGH BUFFER 2
BUFFER 2 TO
PAGE PROGRAM
PAGE PROGRAM
THROUGH BUFFER 1
BUFFER 1
WRITE
BUFFER 2
WRITE
SI
CMD n n+1 Last Byte
· Completes writing into selected buffer
· Starts self-timed erase/program operation
CS
r r r r, PA10-7 PA6-0, BFA8 BFA7-0
SI
CMD X X···X, BFA8 BFA7-0 nn+1 Last Byte
· Completes writing into selected buffer
CS
SI
CMD r r r r, PA10-7 PA6-0, X
CS
Starts self-timed erase/program operation
X
Each transition represents
8 bits and 8 clock c
y
cles
n = 1st byte read
n+1 = 2nd byte read
18
3443D–DFLSH–2/08
AT45DB041B
13. Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
13.1 Main Memory Page Read
13.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
13.3 Buffer Read
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)
I/O INTERFACE
MAIN MEMORY
PAGE TO
BUFFER 1
MAIN MEMORY
PAGE TO
BUFFER 2
MAIN MEMORY
PAGE READ
BUFFER 1
READ
BUFFER 2
READ
SO
SI CMD r r r r, PA10-7 PA6-0, BA8 BA7-0 X XXX
CS
n n+1
SO
SI CMD r r r r, PA10-7 PA6-0, X X
Starts reading page data into buffer
CS
SO
SI CMD XX···X, BFA8 BFA7-0
CS
n n+1SO
X
Each transition represents
8 bits and 8 clock c
y
cles
n = 1st byte read
n+1 = 2nd byte read
19
3443D–DFLSH–2/08
AT45DB041B
14. Detailed Bit-level Read Timing – Inactive Clock Polarity Low
14.1 Continuous Array Read (Opcode: 68H)
14.2 Main Memory Page Read (Opcode: 52H)
14.3 Buffer Read (Opcode: 54H or 56H)
SI
01XX
CS
SO
SCK
12 63 64 65 66 67 68
HIGH-IMPEDANCE
D7D6D5D2D1D0D7D6D5
DATA OUT
BIT 0
OF
PAGE n+1
BIT 2111
OF
PAGE n
LSB MSB
t
SU
t
V
SI
01010 XXX
CS
SO
SCK
12345 60 61 62 63 64 65 66 67
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
SI
01010 XXX
CS
SO
SCK
12345 36 37 38 39 40 41 42 43
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
20
3443D–DFLSH–2/08
AT45DB041B
14.4 Status Register Read (Opcode: 57H)
SI
01010111
CS
SO
SCK
12345 7891011 12 16 17
HIGH-IMPEDANCE
D7D6D5
STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
t
SU
t
V
6
D1D0D7
LSB MSB
21
3443D–DFLSH–2/08
AT45DB041B
15. Detailed Bit-level Read Timing – Inactive Clock Polarity High
15.1 Continuous Array Read (Opcode: 68H)
15.2 Main Memory Page Read (Opcode: 52H)
15.3 Buffer Read (Opcode: 54H or 56H)
SI 01XXX
CS
SO
SCK 12 63 64 65 66 67
HIGH-IMPEDANCE D7D6D5D2D1D0D7D6D5
BIT 0
OF
PAGE n+1
BIT 2111
OF
PAGE n
LSB MSB
tSU
tVDATA OUT
SI
01010 XXX
CS
SO
SCK
12345 61 62 63 64 65 66 67
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
D4
68
SI
01010 XXX
CS
SO
SCK
12345 37 38 39 40 41 42 43
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
D4
44
22
3443D–DFLSH–2/08
AT45DB041B
15.4 Status Register Read (Opcode: 57H)
SI
01010111
CS
SO
SCK
12345 7891011 12 17 18
HIGH-IMPEDANCE
D7D6D5
STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
t
SU
t
V
6
D4D0D7
LSB MSB
D6
23
3443D–DFLSH–2/08
AT45DB041B
16. Detailed Bit-level Read Timing – SPI Mode 0
16.1 Continuous Array Read (Opcode: E8H)
16.2 Main Memory Page Read (Opcode: D2H)
16.3 Buffer Read (Opcode: D4H or D6H)
SI 11XXX
CS
SO
SCK 12 62 63 64 65 66 67
HIGH-IMPEDANCE D7D6D5D2D1D0D7D6D5
DATA OUT
BIT 0
OF
PAGE n+1
BIT 2111
OF
PAGE n
LSB MSB
tSU
tV
SI
11010 XXX
CS
SO
SCK
12345 60 61 62 63 64 65 66 67
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
t
SU
t
V
D4
SI 11010 XXX
CS
SO
SCK 12345 36 37 38 39 40 41 42 43
XX
HIGH-IMPEDANCE
COMMAND OPCODE
t
SU
D7D6D5
DATA OUT
MSB
t
V
D4
24
3443D–DFLSH–2/08
AT45DB041B
16.4 Status Register Read (Opcode: D7H)
SI 11010111
CS
SO
SCK 12345 7891011 12 16 17
HIGH-IMPEDANCE STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
tSU
6
D1D0D7
LSB MSB
D7D6D5
tV
D4
25
3443D–DFLSH–2/08
AT45DB041B
17. Detailed Bit-level Read Timing – SPI Mode 3
17.1 Continuous Array Read (Opcode: E8H)
17.2 Main Memory Page Read (Opcode: D2H)
17.3 Buffer Read (Opcode: D4H or D6H)
SI 11XXX
CS
SO
SCK 12 63 64 65 66 67
HIGH-IMPEDANCE D7D6D5D2D1D0D7D6D5
BIT 0
OF
PAGE n+1
BIT 2111
OF
PAGE n
LSB MSB
tSU
tVDATA OUT
SI 11010 XXX
CS
SO
SCK 12345 61 62 63 64 65 66 67
XX
HIGH-IMPEDANCE D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
D4
68
SI
11010 XXX
CS
SO
SCK
12345 37 38 39 40 41 42 43
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
t
SU
t
V
D4
44
26
3443D–DFLSH–2/08
AT45DB041B
17.4 Status Register Read (Opcode: D7H)
SI
11010111
CS
SO
SCK
12345 7891011 12 17 18
HIGH-IMPEDANCE
D7D6D5
STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
t
SU
t
V
6
D4D0D7
LSB MSB
D6
27
3443D–DFLSH–2/08
AT45DB041B
Figure 17-1. Algorithm for Sequentially Programming or Reprogramming the Entire Array
Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-
page.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.
START
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
END
provide address
and data
BUFFER WRITE
(84H, 87H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
28
3443D–DFLSH–2/08
AT45DB041B
Figure 17-2. Algorithm for Randomly Modifying Data
Notes: 1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000
cumulative page erase/program operations.
2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000
cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note
AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
START
MAIN MEMORY PAGE
TO BUFFER TRANSFER
(53H, 55H)
INCREMENT PAGE
ADDRESS POINTER
(2)
AUTO PAGE REWRITE
(2)
(58H, 59H)
END
provide address of
page to modify
If planning to modify multiple
bytes currently stored within
a page of the Flash array
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
BUFFER WRITE
(84H, 87H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
Table 17-1. Sector Addressing
PA10 PA 9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 - PA0 Secto r
0 0000000 X 0
0 0 0XXXXX X 1
0 0 1XXXXX X 2
0 1XXXXXX X 3
1 0XXXXXX X 4
1 1XXXXXX X 5
29
3443D–DFLSH–2/08
AT45DB041B
18. Ordering Information
Note: 1. The next generation DataFlash devices will not be offered in 28-SOIC package, therefore, this package is not recommended
for new designs.
18.1 Standard Package Options
fSCK
(MHz)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
20 10 0.01
AT45DB041B-CC
AT45DB041B-CNC
AT45DB041B-RC
AT45DB041B-SC
AT45DB041B-TC
14C1
8CN3
28R(1)
8S2
28T
Commercial
(0°C to 70°C)
2.7V to 3.6V
20 10 0.01
AT45DB041B-CI
AT45DB041B-CNI
AT45DB041B-RI
AT45DB041B-SI
AT45DB041B-TI
14C1
8CN3
28R(1)
8S2
28T
Industrial
(-40°C to 85°C)
2.7V to 3.6V
15 10 0.01
AT45DB041B-RC-2.5
AT45DB041B-CNC-2.5
AT45DB041B-SC-2.5
AT45DB041B-TC-2.5
28R
8CN3
8S2
28T
Commercial
(0°C to 70°C)
2.5V to 3.6V
18.2 Green Package Options (Pb/Halide-free/RoHS Compliant)
fSCK
(MHz)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
20 10 0.01
AT45DB041B-CU
AT45DB041B-CNU
AT45DB041B-RU
AT45DB041B-SU
AT45DB041B-TU
14C1
8CN3
28R(1)
8S2
28T
Industrial
(-40°C to 85°C)
2.7V to 3.6V
Package Type
14C1 14-ball, 3 x 5 Array Plastic Chip-scale Ball Grid Array (CBGA)
8CN3 8-pad (6 mm x 8 mm ) Chip Array Small Outline No Lead Package (CASON)
28R 28-lead, 0.330" Wide, Plastic Gull Wing Small Outline Package (SOIC)
8S2 8-lead, 0.210" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)
30
3443D–DFLSH–2/08
AT45DB041B
19. Packaging Information
19.1 14C1 – CBGA
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
14C1, 14-ball (3 x 5 Array), 4.5 x 7 x 1.4 mm Body, 1.0 mm Ball
Pitch Chip-scale Ball Grid Array Package (CBGA) A
14C1
04/11/01
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
A
B
C
D
E
321
4.0 (0.157)
1.25 (0.049) REF
0.46 (0.018)
DIA BALL TYP
2.0 (0.079)
7.10(0.280)
6.90(0.272)
1.40 (0.055) MAX
0.30 (0.012)MIN
4.60(0.181)
4.40(0.173)
1.00 (0.0394) BSC
NON-ACCUMULATIVE
1.50 (0.059) REF
A1 ID
1.00 (0.0394) BSC
NON-ACCUMULATIVE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
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AT45DB041B
19.2 8CN3 – CASON
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8CN3, 8-pad (6 x 8 x 1.0 mm Body), Lead Pitch 1.27 mm,
Chip Array Small Outline No Lead Package (CASON) B
8CN3
7/10/03
Notes: 1. All dimensions and tolerance conform to ASME Y 14.5M, 1994.
2. The surface finish of the package shall be EDM Charmille #24-27.
3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2o.
4. Metal Pad Dimensions.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 1.0
A1 0.17 0.21 0.25
b 0.41 TYP 4
D 7.90 8.00 8.10
E 5.90 6.00 6.10
e 1.27 BSC
e1 1.095 REF
L 0.67 TYP 4
L1 0.92 0.97 1.02 4
Pin1 Pad Corner
Marked Pin1 Indentifier
0.10 mm
TYP
4
3
2
1
5
6
7
8
Top View
L
b
e
L1
e1
Side View
A1
A
Bottom View
E
D
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3443D–DFLSH–2/08
AT45DB041B
19.3 28R – SOIC(1)
Note: 1. The next generation DataFlash devices will not be offered in 28-SOIC package, therefore, this package is not recommended
for new designs.
A 2.39 – 2.79
A1 0.050 – 0.356
D 18.00 – 18.50 Note 1
E 11.70 – 12.50
E1 8.59 – 8.79 Note 1
B 0.356 – 0.508
C 0.203 – 0.305
L 0.94 – 1.27
e 1.27 TYP
PIN 1
0º ~ 8º
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
28R, 28-lead, 0.330" Body Width,
Plastic Gull Wing Small Outline (SOIC) C
28R
5/18/2004
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A
E
C
A1
E1
e
D
L
B
Note: 1. Dimensions D and E1 do not include mold Flash
or protrusion. Mold Flash or protrusion shall not exceed
0.25 mm (0.010").
33
3443D–DFLSH–2/08
AT45DB041B
19.4 8S2 – EIAJ SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
4/7/06
8S2D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
θ 0° 8°
e 1.27 BSC 4
θ
θ
1
1
N
N
E
E
TOP VIEW
TOP VIEW
C
C
E1
E1
END VIEW
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
SIDE VIEW
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3443D–DFLSH–2/08
AT45DB041B
19.5 28T – TSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP) C
28T
12/06/02
PIN 1 0º ~ 5º
D1 D
Pin 1 Identifier Area
b
e
EA
A1
A2
c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.90 1.00 1.05
D 13.20 13.40 13.60
D1 11.70 11.80 11.90 Note 2
E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.55 BASIC
3443D–DFLSH–2/08
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