© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 4 1Publication Order Number:
KAI−1020/D
KAI-1020
1000 (H) x 1000 (V) Interline
CCD Image Sensor
Description
The KAI−1020 Image Sensor is a one megapixel interline CCD with
integrated clock drivers and on-chip correlated double sampling.
The progressive scan architecture and global electronic shutter
provide excellent image quality for full motion video and still image
capture.
The integrated clock drivers allow for easy integration with CMOS
logic timing generators. The sensor features a fast line dump for
high-speed sub-window readout and single (30 fps) or dual (48 fps)
output operation.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture Interline CCD, Progressive Scan
Total Number of Pixels 1028 (H) × 1008 (V)
Number of Effective Pixels 1004 (H) × 1004 (V)
Number of Active Pixels 1000 (H) × 1000 (V)
Number of Outputs 1 or 2
Pixel Size 7.4 mm (H) × 7.4 mm (V)
Active Image Size 7.4 mm (H) × 7.4 mm (V)
10.5 mm (Diagonal)
2/3″ Optical Format
Aspect Ratio 1:1
Saturation Signal 40,000 e−
Output Sensitivity 12 mV/e−
Quantum Efficiency
ABA (500 nm)
CBA (620 nm, 540 nm, 460 nm)
FBA (600 nm, 540 nm, 460 nm)
44%
33%, 39%, 41%
39%, 42%, 44%
Dark Noise 50 e− rms
Dark Current (Typical) < 0.5 nA/cm2
Dynamic Range 58 dB
Blooming Suppression 100 X
Image Lag < 10 e−
Smear < 0.03%
Maximum Data Rate 40 MHz/Channel (2 Channels)
Frame Rate
Progressive Scan, One Output
Progressive Scan, Dual Outputs
Interlaced Scan, One Output
30 fps
48 fps
49 fps
Integrated Vertical Clock Driver
Integrated Correlated Double Sampling (CDS)
Integrated Electronic Shutter Driver
Package 68 Pin PGA or 64 Pin CLCC
Cover Glass AR Coated, 2 Sides
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
Features
•10-Bits Dynamic Range at 40 MHz
•Large 7.4 mm Square Pixels for High
Sensitivity
•Progressive Scan (Non-Interlaced)
•Integrated Correlated Double Sampling
(CDS) Up to 40 MHz
•Integrated Electronic Shutter Driver
•Reversible HCCD Capable of 40 MHz
Operation All Timing Inputs 0 to 5 V
•Single or Dual Video Output Operation
•Progressive Scan or Interlaced
•Fast Dump Gate for High Speed
Sub-Window Readout
•Anti-Blooming Protection
Applications
•Machine Vision
•Medical
•Scientific
•Surveillance
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Figure 1. KAI−1020 Interline
CCD Image Sensor
See detailed ordering and shipping information on page 2 o
f
this data sheet.
ORDERING INFORMATION
KAI−1020
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ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−1020 IMAGE SENSOR
Part Number Description Marking Code
KAI−1020−AAA−JP−BA Monochrome, No Microlens, PGA Package,
Taped Clear Cover Glass, No Coatings, Standard Grade KAI−1020
Serial Number
KAI−1020−ABB−FD−AE Monochrome, Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−1020−ABB
Serial Number
KAI−1020−ABB−FD−BA Monochrome, Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−1020−ABB−JP−AE Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Engineering Sample
KAI−1020−ABB−JP−BA Monochrome, Telecentric Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Standard Grade
KAI−1020−ABB−JB−AE Monochrome, Telecentric Microlens, PGA Package,
Clear Cover Glass (No Coatings), Engineering Sample
KAI−1020−ABB−JB−BA Monochrome, Telecentric Microlens, PGA Package,
Clear Cover Glass (No Coatings), Standard Grade
KAI−1020−ABB−JD−AE Monochrome, Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−1020−ABB−JD−BA Monochrome, Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−1020−FBA−FD−AE Gen2 Color (Bayer RGB), Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−1020−FBA
Serial Number
KAI−1020−FBA−FD−BA Gen2 Color (Bayer RGB), Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−1020−FBA−JD−AE Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−1020−FBA−JD−BA Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−1020−CBA−FD−AE* Gen1 Color (Bayer RGB), Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−1020CM
Serial Number
KAI−1020−CBA−FD−BA* Gen1 Color (Bayer RGB), Telecentric Microlens, CLCC Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−1020−CBA−JD−AE* Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−1020−CBA−JD−BA* Gen1 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
*Not recommended for new designs.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number Description
KAI−1020−12−40−A−EVK Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
KAI−1020
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DEVICE DESCRIPTION
Architecture
Figure 2. Block Diagram
8 12 2 1000 2 12 8
812 2 500 500 2 12 8
2 Buffer Rows
2 Buffer Rows
4 Dark Rows
Fast Line Dump
1000 (H) y 1000 (V)
Active Pixels
12 Dark Columns
2 Buffer Columns
12 Dark Columns
2 Buffer Columns
8 Empty Pixels
8 Empty Pixels
VOUT2VOUT1
Single
or
Dual Output
GG
R
BGG
R
B
GG
R
BGG
R
B
Pixel 1,1
There are 4 light shielded rows followed 1004 photoactive
rows. The first 2 and the last 2 photoactive rows are buffer
rows giving a total of 1000 lines of image data.
In the single output mode all pixels are clocked out of the
Video 1 output in the lower left corner of the sensor. The first
8 empty pixels of each line do not receive charge from the
vertical shift register. The next 12 pixels receive char ge from
the left light-shielded edge followed by 1004
photo-sensitive pixels and finally 12 more light shielded
pixels from the right edge of the sensor. The first and last 2
photosensitive pixels are buffer pixels giving a total of 1000
pixels of image data.
In the dual output mode the clocking of the right half of the
horizontal CCD is reversed. The left half of the image is
clocked out V ideo 1 and the right half of the image is clocked
out Video 2. Each row consists of 8 empty pixels followed
by 12 light shielded pixels followed by 502 photosensitive
pixels. When reconstructing the image, data from Video 2
will have to be reversed in a line buf fer and appended to the
Video 1 data.
KAI−1020
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Physical Description
Pin Description and Device Orientation
Pin Grid Array
When viewed from the top with the pin 1 index to the
upper left, the center of the photoactive pixel array is offset
0.006″ above the physical center of the package. The pin 1
index is located in the corner of the package above pins L2
and K1. When operated in single output mode the first pixel
out of the sensor will be in the corner closest to VOUT1B
(pin L9). The HCCD is parallel to the row of pins A10 to
L10. In the pictures below, the VCCD transfers charge
down.
Figure 3. Pin 1 Location
KAI−1020
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Pin Grid Array Pin Description
Figure 4. PGA Package Pin Description (Top View)
R2
C11
S2B
D11
H1BR
E11
H1S
F11
GND
G11
H2BL
H11
S1A
J11
T1
K11 T2
B11
VDD
L10 VOUT2B
A10
S2A
C10
H2BR
D10
GND
E10
H2S
F10
H1BL
G10
S1B
H10
R1
J10
K10 VDD
B10
C1D1E1F1G1H1J1K1 B1
VSUB
L2
V1IN
A2
C2D2E2F2G2H2J2
V2IN
K2 B2
GND
B9
VDD
B8
V1S5
B7
V1OUT
B6
V1LOW
B5
SHC2
B4
SH
B3
VOUT2A
A9
V1
A8
V1MID
A7
A6
SHD1C1
A5
SHC1
A4
VSH15
A3
GND
K9
VDD
K8
V2B
K7
V2S9
K6
V2A
K5
V2MID
K4
V2LOW
K3
VOUT1B
L9
VOUT1A
L8
FD
L7
V2S5
L6
VSUB
L5
V2HIGH
L4
V2OUT
L3
Pin 1 Index
Table 4. PIN DESCRIPTION
Pin Label Function
K2 V2IN VCCD Gate Phase 2 Input
L2 VSUB Substrate Voltage Input
K3 V2LOW VCCD Phase 2 Clock Driver Low
L3 V2OUT VCCD Phase 2 Clock Driver Output
K4 V2MID VCCD Phase 2 Clock Driver Mid
L4 V2HIGH VCCD Phase 2 Clock Driver High
K5 fV2A VCCD Phase 2 Clock Driver Input A
L5 VSUB Substrate Voltage Input
K6 V2S9 VCCD Phase 2 Clock Driver +9 V
L6 V2S5 VCCD Phase 2 Clock Driver +5 V Fast Dump Clock Driver +5 V
K7 fV2B VCCD Phase 2 Clock Driver Input B
L7 fFD Fast Dump Clock Driver Input
KAI−1020
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Table 4. PIN DESCRIPTION (continued)
Pin FunctionLabel
K8 VDD1 Video 1 CDS +15 V
L8 VOUT1A Video 1 CDS Output A
K9 GND Ground (0 V)
L9 VOUT1B Video 1 CDS Output B
L10 VDD1 Video 1 CDS +15 V Supply
K11 fT1 Video 1 CDS Transfer Clock Input
J10 fR1 Video 1 CDS Reset Clock Input
J11 fS1A V ideo 1 CDS Sample A Clock Input
H10 fS1B Video 1 CDS Sample B Clock Input
H11 fH2BL HCCD Left Phase 2 Barrier Clock Input
G10 fH1BL HCCD Left Phase 1 Barrier Clock Input
G11 GND Ground (0 V)
F10 fH2S HCCD Storage Phase 2 Clock Input
F11 fH1S HCCD Storage Phase 1 Clock Input
E10 GND Ground (0 V)
E11 fH1BR HCCD Right Phase 1 Barrier Clock Input
D10 fH2BR HCCD Right Phase 2 Barrier Clock Input
D11 fS2B Video 2 CDS Sample B Clock Input
C10 fS2A Video 2 CDS Sample A Clock Input
C11 fR2 Video 2 CDS Reset Clock Input
B11 fT2 Video 2 CDS Transfer Clock Input
B10 VDD2 Video 2 CDS +15 V
A10 VOUT2B Video 2 CDS Output B
B9 GND Ground (0 V)
A9 VOUT2A Video 2 CDS Output A
B8 VDD2 Video 2 CDS +15 V
A8 fV1 VCCD Phase 1 Clock Driver Input
B7 V1S5 VCCD Phase 1 Clock Driver +5 V
A7 V1MID VCCD Phase 1 Clock Driver Mid
B6 V1OUT VCCD Phase 1 Clock Driver Output
B5 V1LOW VCCD Phase 1 Clock Driver Low
A5 SHD1C1 Shutter Driver Connection
B4 SHC2 Shutter Driver Connection
A4 SHC1 Shutter Driver Connection
B3 fSH Shutter Driver Clock Input
A3 VSH15 Shutter Driver +15 V
A2 V1IN VCCD Gate Phase 1 Input
1. All pins not listed must be unconnected.
KAI−1020
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Leadless Chip Carrier
Figure 5. LCC Package Pin Description (Top View)
116
1764
32
3348
49
8
24
40
56
R2
S2A
S2B
H2BR
H1BR
GND
H1S
H2S
GND
H1BL
H2BL
S1B
S1A
R1
T1
VDD
V1IN
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
V2IN
VSUB
V2LOW
V2OUT
V2MID
V2HIGH
V2A
N/C
V2S9
V2S5
V2B
FD
VDD
VOUT1A
VOUT1B
GND
VSH15
SH
SHC1
SHC2
SHD1C1
V1LOW
V1OUT
V1MID
V1S5
V1
VDD
VOUT2A
GND
VOUT2B
VDD
T2
Table 5. PIN DESCRIPTION
Pin Label Function
1 V2IN VCCD Gate Phase 2 Input
2 VSUB Substrate Voltage Input
3 V2LOW VCCD Phase 2 Clock Driver Low
4 V2OUT VCCD Phase 2 Clock Driver Output
5 V2MID VCCD Phase 2 Clock Driver Mid
6 V2HIGH VCCD Phase 2 Clock Driver High
7 V2A VCCD Phase 2 Clock Driver Input A
8 N/C No Connect
9 V2S9 VCCD Phase 2 Clock Driver +9 V
10 V2S5 VCCD Phase 2 Clock Driver +5 V Fast Dump Clock Driver +5 V
11 V2B VCCD Phase 2 Clock Driver Input B
12 FD Fast Dump Clock Driver Input
KAI−1020
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Table 5. PIN DESCRIPTION (continued)
Pin FunctionLabel
13 VDD Video CDS +15 V
14 VOUT1A Video 1 CDS Output A
15 GND Ground (0 V)
16 VOUT1B Video 1 CDS Output B
17 VDD Video CDS +15 V
18 T1 Video 1 CDS Transfer Clock Input
19 R1 Video 1 CDS Reset Clock Input
20 S1A Video 1 CDS Sample A Clock Input
21 S1B Video 1 CDS Sample B Clock Input
22 H2BL HCCD Left Phase 2 Barrier Clock Input
23 H1BL HCCD Left Phase 1 Barrier Clock Input
24 GND Ground (0 V)
25 H2S HCCD Storage Phase 2 Clock Input
26 H1S HCCD Storage Phase 1 Clock Input
27 GND Ground (0 V)
28 H1BR HCCD Right Phase 1 Barrier Clock Input
29 H2BR HCCD Right Phase 2 Barrier Clock Input
30 S2B Video 2 CDS Sample B Clock Input
31 S2A Video 2 CDS Sample A Clock Input
32 R2 Video 2 CDS Reset Clock Input
33 T2 Video 2 CDS Transfer Clock Input
34 VDD Video CDS +15 V
35 VOUT2B Video 2 CDS Output B
36 GND Ground (0 V)
37 VOUT2A Video 2 CDS Output A
38 VDD Video CDS +15 V
39 V1 VCCD Phase 1 Clock Driver Input
40 V1S5 VCCD Phase 1 Clock Driver +5 V
41 V1MID VCCD Phase 1 Clock Driver Mid
42 V1OUT VCCD Phase 1 Clock Driver Output
43 V1LOW VCCD Phase 1 Clock Driver Low
44 SHD1C1 Shutter Driver Connection
45 SHC2 Shutter Driver Connection
46 SHC1 Shutter Driver Connection
47 SH Shutter Driver Clock Input
48 VSH15 Shutter Driver +15 V
49 V1IN VCCD Gate Phase 1 Input
50−64 N/C No Connect
KAI−1020
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IMAGING PERFORMANCE
Table 6. SPECIFICATIONS
Description Symbol Min. Nom. Max. Unit Notes Sampling
Plan*
OPTICAL SPECIFICATION
Peak Quantum Efficiency QEMAX 42 45 − % 1 Design
Peak Quantum Efficiency Wavelength lQE − 490 − nm 1 Design
Microlens Acceptance Angle (Horizontal) QQEH±12 ±13 − Degrees 2 Design
Microlens Acceptance Angle (Vertical) QQEV±25 ±30 − Degrees 2 Design
Quantum Efficiency at 540 nm QE(540) 38 40 − % 1 Design
Photoresponse Non-Uniformity PNU − 5 − % Design
Maximum Photoresponse Non-Linearity NL − 2 − % 3, 4, 18 Die
Maximum Gain Difference Between
Outputs DG− 10 − % 3, 4, 18 Die
Maximum Signal Error caused by
Non-Linearity Differences DNL − 1 − % 3, 4, 18 Die
Dark Center Uniformity − − 12 e− rms 19, 20 Die
Dark Global Uniformity − − 2 mV pp 19, 20 Die
Global Uniformity − − 5 % rms 19, 20 Die
Global Peak to Peak Uniformity − − 15 %pp 19, 20 Die
Center Uniformity − − 0.7 % rms 19, 20 Die
CCD SPECIFICATIONS
Vertical CCD Charge Capacity Vne 54 60 − ke−Design
Horizontal CCD Charge Capacity Hne 110 120 − ke−Design
Photodiode Charge Capacity Pne 38 42 − ke−5 Die
Dark Current ID− 0.2 0.5 nA/cm26 Die
Image Lag Lag − < 10 50 e−7 Design
Anti-Blooming Factor XAB 100 300 − 1, 8, 9,
10, 11 Design
Vertical Smear Smr − −75 −72 dB 1, 8, 9 Design
CDS OUTPUT SPECIFICATION
Power Dissipation PD− 213 − mW 12 Design
Bandwidth F−3dB − 140 − MHz 12 Design
Max Off−chip Load CL− 10 − pF 13 Design
Gain AV− 0.70 − 12 Design
Sensitivity DV/DN− 13 − mV/e−12 Design
Output Impedance R − 160 − W12 Design
Saturation Voltage VSAT − 500 − mV 5, 12 Die
Output Bias Current IOUT − 3.0 − mA Design
GENERAL − MONOCHROME
Total Camera Noise ne−T − 42 − e− rms 6, 14 Design
Dynamic Range DR − 60 − dB 15 Design
GENERAL − COLOR
Total Camera Noise ne−T − 50 − e− rms 6, 14 Design
Dynamic Range DR − 58 − dB 15 Design
KAI−1020
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Table 6. SPECIFICATIONS (continued)
Description Sampling
Plan*
NotesUnitMax.Nom.Min.Symbol
POWER
Single Channel CDS − 213 − mW 12
VCCD clock driver − 71 − mW 16
Electronic shutter driver − 1.1 − mW
HCCD − 122 − mW 16, 17
Total Power − 407 − mW 12, 16
*Sampling plan defined as “Die” indicates that every device is verified against the specified performance limits. Sampling plan defined as
“Design” indicates a sampled test or characterization, at the discretion of ON Semiconductor, against the specified performance limits.
1. Measured with F/4 imaging optics.
2. Value is the angular range of incident light for which the quantum efficiency is at least 50% of QEMAX at a wavelength of lQE. Angles are
measured with respect to the sensor surface normal in a plane parallel to the horizontal axis (QQEH) o r in a p la ne parallel to the vertical axis
(QQEV).
3. Value is over the range of 10% to 90% of photodiode saturation.
4. Value is for the sensor operated without binning.
5. This value depends on the substrate voltage setting. Higher photodiode saturation charge capacities will lower the anti-blooming
specification. Substrate voltage will be specified with each part for 42 ke−.
6. Measured at 40°C, 40 MHz HCCD frequency.
7. This is the first field decay lag at 70% saturation. Measured by strobe illumination of the device at 70% of photodiode saturation, and then
measuring the subsequent frame’s average pixel output in the dark.
8. Measured with a spot size of 100 vertical pixels, no electronic shutter.
9. Measured with green light (500 nm to 580 nm).
10.A blooming condition is defined as when the spot size doubles in size.
11.Anti-blooming factor is the light intensity which causes blooming divided by the light intensity which first saturates the photodiodes.
12.Single output power, 3 mA load.
13.With total output load capacitance of CL= 10 pF between the outputs and AC ground.
14. Includes system electronics noise, dark pattern noise and dark current shot noise at 40 MHz. Total noise measured on the KAI−1020
evaluation board.
15.Uses 20LOG (Pne /n
e−T)
16.At 30 frames/sec, single output.
17.This includes the power of the external HCCD clock driver.
18.For the sampling plan, measured at 10 MHz
19.Tested at 27°C and 40°C
20.See Tests
KAI−1020
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TYPICAL PERFORMANCE CUR VES
Monochrome Quantum Efficiency
Figure 6. Monochrome Quantum Efficiency
Absolute Quantum Efficiency
Wavelength (nm)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
300 400 500 600 700 800 900 1000
Without Cover Glass
Without Cover Glass, without Microlens
Color (Bayer RGB) Quantum Efficiency
Figure 7. Color (Bayer RGB) Quantum Efficiency
0350 400 450 500 550 600 650 700 750 800 850 900 950 1000
Absolute Quantum Efficiency
Wavelength (nm)
0.1
0.2
0.3
0.4
0.5
KAI−1020
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Photoresponse vs. Angle
The horizontal curve is where the incident light angle is varied in a plane parallel to the HCCD.
The vertical curve is where the incident light angle is varied in a plane perpendicular to the HCCD.
Figure 8. Photoresponse vs. Angle
0
10
20
30
40
50
60
70
80
90
100
110
−35 −30 −25 −20 −15 −10 −5 0 5 10 15 20 25 30 35
Photoresponse (Relative)
Angle (Degrees)
Horizontal
Vertical
Sensor Power
Figure 9. Power
KAI−1020 Power (Single Output)
0
100
200
300
400
500
0 5 10 15 20 25 30
Frames/Sec
Power (mW)
HCCD
VCCD
Total Power
KAI−1020
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Frame Rate
Figure 10. Frame Rate 1000 y 750 Pixels
Frame Rate (75% Subsample 1000 y 750 Pixels)
0
10
20
30
40
50
60
0 5 10 15 20 25 30 35 40
Pixel Frequency (MHz)
Frames/Sec
Single Output
Dual Output
Figure 11. Frame Rate 1000 y 250 Pixels
Frame Rate (25% Subsample 1000 y 250 Pixels)
0
20
40
60
80
100
0 5 10 15 20 25 30 35 40
Pixel Frequency (MHz)
Frames/Sec
Single Output
Dual Output
Figure 12. Frame Rate 1000 y 1000 Pixels
Frame Rate (1000 y 1000 Pixels)
0
10
20
30
40
50
0 5 10 15 20 25 30 35 40
Pixel Frequency (MHz)
Frames/Sec
Single Output
Dual Output
Figure 13. Frame Rate 1000 y 500 Pixels
Frame Rate (50% Subsample 1000 y 500 Pixels)
0
10
20
30
40
50
0 5 10 15 20 25 30 35 40
Pixel Frequency (MHz)
Frames/Sec
60
70
80
Single Output
Dual Output
Figure 14. Frame Rate 1000 y 1000 Pixels Interlaced
Frame Rate (1000 y 1000 Pixels) Interlaced
0
10
20
30
40
50
0 5 10 15 20 25 30 35 40
Pixel Frequency (MHz)
Frames/Sec
60
70
80
Single Output
Dual Output
KAI−1020
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DEFECT DEFINITIONS
Table 7. SPECIFICATIONS
Name Definition Maximum Temperature(s)
Tested at (5C) Notes Sampling
Plan
Dark Field Major Bright Defective Pixel Defect ≥ 28 mV 10 27, 40 1 Die
Bright Field Major Dark or Bright
Defective Pixel Defect ≥ 11% 10 27, 40 Die
Bright Field Minor Dark Defective Pixel Defect ≥ 5% 20 in Zone 2 27, 40 8 Die
Dark Field Minor Bright Defective Pixel Defect ≥ 14 mV 100 27, 40 2 Die
Bright Field Dead Dark Pixel Defect ≥ 40% 027, 40 5 Die
Bright Field Nearly Dead Dark Pixel Defect ≥ 20% 0 in Zone 1
1 in Zone 2 27, 40 5, 8 Die
Dark Field Saturated Bright Pixel Defect ≥ 106 mV 027, 40 3 Die
Dark Field Minor Cluster Defect A Group of 2 to 10
Contiguous Dark Field Minor
Defective Pixels
027, 40 4 Die
Bright Field Minor Cluster Defect A Group of 2 to 10
Contiguous Bright Field Minor
Defective Pixels
2 in Zone 2 27, 40 4, 8 Die
Major Cluster Defect A Group of 2 to 10
Contiguous Major Defective
Pixels
027, 40 4 Die
Column Defect A Group of More than 10
Contiguous Major Defective
Pixels along a Single Column
027, 40 Die
Column Average Magnitude Within ±0.4% of Regional
Average (5 Columns) 027, 40 6, 7 Die
1. The defect threshold was determined by using a threshold of 8 mV at an integration time of 33 milliseconds and scaling it by the actual
integration time used of 117 ms. [8 mV ⋅ (117 ms / 33 ms) = 28 mV]
2. The defect threshold was determined by using a threshold of 4mV at an integration time of 33 milliseconds and scaling it by the actual
integration time used of 117 ms. [4 mV ⋅ (117 ms / 33 ms) = 14 mV]
3. The defect threshold was determined by using a threshold of 30 mV at an integration time of 33 milliseconds and scaling it by the actual
integration time used of 117 ms. [30 mV ⋅ (117 ms / 33 ms) = 106 mV]
4. The maximum width of any cluster defect is 2 pixels.
5. Only dark defects.
6. Local average is centered on column.
7. See Test Regions of Interest for region used.
8. See Figure 18 for zone 1 and 2 definitions.
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are referenced to pixel 1, 1 in the defect map (see
Figure 16: Regions of Interest).
KAI−1020
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TEST DEFINITIONS
Table 8. TEST CONDITIONS
Name Definition Notes
Frame Time 117 ms 1
Horizontal Clock Frequency 10 MHz
Light source (LED) Continuous Green Illumination Centered at 530 nm 2
Operation Nominal Operating Voltages and T iming
1. Electronic shutter is not used. Integration time equals frame time.
2. Green LED used: Nichia NSPG500S.
Test System Conversion Factors
KAI−1020 Output Sensitivity: 13 mV per e−
Test System Gain (Measured): 0.25 mV per ADU
Test System Gain (Calculated): 19 e− per ADU
Tests
Dark Field Center Uniformity
This test is performed under dark field conditions. Only
the center 100 by 100 pixels of the sensor are used for this
test (pixels 431, 431 to pixel 530, 530). See Figure 17.
Dark Field Center Uniformity +Standard Deviation of Center 100 by 100 Pixels in Electrons @ǒDPS Integration Time
Actual Integration Time UsedǓ
Units: mV rms. DPS Integration Time: Device Performance Specification Integration Time = 33 ms.
Dark Field Global Uniformity
This test is performed under dark field conditions.
The sensor is partitioned into 100 sub regions of interest,
each of which is 100 by 100 pixels in size. See Figure 15.
The average signal level of each of the 100 sub regions of
interest is calculated. The signal level of each of the sub
regions of interest is calculated using the following formula:
Signal of ROI[i] +(ROI Average in ADU *
Units : mVpp (millivolts Peak to Peak)
*Horizontal Overclock Average in ADU) @
@mV per Count
Where i = 1 to 100. During this calculation on the 100 sub
regions of interest, the maximum and minimum signal levels
are found. The dark field global uniformity is then calculated
as the maximum signal found minus the minimum signal
level found.
Global Uniformity
This test is performed with the light source illuminated to
a level such that the output of the sensor is at 70% of
saturation (approximately 364 mV). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 520 mV. Global uniformity
is defined as:
Global Uniformi ty +100 @ǒActive Area Standard Deviation
Active Area Signal Ǔ
Active Area Signal = Active Area Average − H. Overclock Average
Units : % rms
Global Peak to Peak Uniformity
This test is performed with the light source illuminated to
a level such that the output of the sensor is at 70% of
saturation (approximately 364 mV). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 520 mV. The sensor is
partitioned into 100 sub regions of interest, each of which is
100 by 100 pixels in size. See Figure 15. The average signal
level of each of the 100 sub regions of interest (ROI) is
calculated. The signal level of each of the sub regions of
interest is calculated using the following formula:
Signal of ROI[i] +(ROI Average in ADU *
*Horizontal Overclock Average in ADU) @
@mV per Count
Where i = 1 to 100. During this calculation on the 100 sub
regions of interest, the maximum and minimum signal levels
are found. The global peak to peak uniformity is then
calculated as:
Global Uniformity +Maximum Signal *Minimum Signal
Active Area Signal
Units : % pp
Center Uniformity
This test is performed with the light source illuminated to
a level such that the output of the sensor is at 70% of
saturation (approximately 364 mV). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 520 mV. Defects are
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16
excluded for the calculation of this test. This test is
performed on the center 100 by 100 pixels (See Test Regions
of Interest and Figure 17) of the sensor. Center uniformity is
defined as:
Center ROI Uniformity +100 @ǒCenter ROI Standard Deviation
Center ROI Signal Ǔ
Center ROI Signal = Center ROI Average − H. Overclock Average
Units : % rms
Dark Field Defect Test
This test is performed under dark field conditions. The
sensor i s partitioned into 100 sub regions of interest, each of
which is 100 by 100 pixels in size (see Figure 15). In each
region of interest, the median value of all pixels is found. For
each region of interest, a pixel is marked defective if it is
greater than or equal to the median value of that region of
interest plus the defect threshold specified.
Bright Field Defect Test
This test is performed with the light source illuminated to
a level such that the output of the sensor is at 70% of
saturation (approximately 364 mV). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 520 mV. The average signal
level of all active pixels is found. The bright and dark
thresholds are set as:
Dark Defect Threshold = Active Area Signal @Threshold
Bright Defect Threshold = Active Area Signal @Threshold
The sensor is then partitioned into 100 sub regions of
interest, each of which is 100 by 100 pixels in size. See
Figure 15: Test Sub Regions of Interest. In each region of
interest, the average value of all pixels is found. For each
region of interest, a pixel is marked defective if it is greater
than or equal to the median value of that region of interest
plus the bright threshold specified or if it is less than or equal
to the median value of that region of interest minus the dark
threshold specified.
Example for major bright field defective pixels:
•Average value of all active pixels is found to be 365 mV.
•Dark defect threshold: 365 mV ⋅ 11% = 40 mV
•Bright defect threshold: 365 mV ⋅ 11% = 40 mV
•Region of interest #1 selected. This region of interest is
pixels 1, 1 to pixels 100,100.
♦Median of this region of interest is found to be
366 mV.
♦Any pixel in this region of interest that is
≥(366 + 40 mV) 406 mV in intensity will be marked
defective.
♦Any pixel in this region of interest that is
≤(366 −40 mV) 324 mV in intensity will be marked
defective.
•All remaining 99 sub regions of interest are analyzed
for defective pixels in the same manner.
Bright Field Minor Defect Test
This test is performed with the light source illuminated to
a level such that the output of the sensor is at 70% of
saturation (approximately 364 mV). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 520 mV. The average signal
level of all active pixels is found. The dark threshold is set
as:
Dark Defect Threshold = Active Area Signal @Threshold
The sensor is then partitioned into 2500 sub regions of
interest, each of which is 20 by 20 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is less than or equal to the median value of that region of
interest minus the dark threshold specified.
Example for bright field minor defective pixels:
•Average value of all active pixels is found to be
365 mV.
•Dark defect threshold: 365 mV ⋅ 5% = 18 mV
•Region of interest #1 selected. This region of interest is
pixels 1, 1 to pixels 20, 20.
♦Median of this region of interest is found to be
366 mV.
♦Any pixel in this region of interest that is
≤(366 −18 mV) 348 mV in intensity will be marked
defective.
•All remaining 2499 sub regions of interest are analyzed
for defective pixels in the same manner.
Bright Field Column Average Magnitude Test
This test is performed with the light source illuminated to
a level such that the output of the sensor is at 70% of
saturation (approximately 364 mV). Prior to this test being
performed the substrate voltage has been set such that the
charge capacity of the sensor is 520 mV. A column is marked
as defective if
100 @Abs ǒAvg(Column n) *Avg(Avg(Column x))
Avg(Avg(Column x)) Ǔu0.4
Where x = n−2 to n+2
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Table 9. TEST REGIONS OF INTEREST
Name Definition
Number of Pixels 1027 (H) × 1008 (V)
Number of Photo Sensitive Pixels 1004 (H) × 1004 (V)
Number of Active Pixels 1000 (H) × 1000 (V)
Active Area ROI Pixel (1, 1) to Pixel (1000, 1000)
Column Magnitude Test ROI Pixel (11, 11) to Pixel (990, 990)
1. Only the active pixels are used for performance and defect tests. See Figure 16.
Test Sub Regions of Interest
Figure 15. Test Sub Regions of Interest
Pixel
(1,1)
Pixel
(1000,1000)
12345678910
11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40
41 42 43 44 45 46 47 48 49 50
51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70
71 72 73 74 75 76 77 78 79 80
81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100
Signal Level Calculation
Signal levels are calculated by using the average of the
region of interest under test and subtracting off the
horizontal overclock region. The test system timing is
configured such that the sensor is overclocked in both the
vertical and horizontal directions. See Figure 16 for
a pictorial representation of the regions.
Example: To determine the active area average in millivolts,
the following calculation used:
Active Area Signal (mV) +(Active Area Average − Horizontal Overclock Average) @mV per Count
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Figure 16. Regions of Interest
Vertical Overclock
Horizontal Overclock
2 Buffer Rows
4 Dark Rows
2 Buffer Rows
Pixel 1,1
VOUT1
12 Dark Columns
2 Buffer Columns
12 Dark Columns
2 Buffer Columns
Center Region of Interest
Figure 17. Center Region of Interest
1,1 1000,1
1000,10001,1000
450,450
549,549
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OPERATION
Single or Dual Output
Figure 19. Single or Dual Output Mode of Operation
502 8
1004
502
8
8
Video 1
Video 1 Video 2
12
12
12
12
1004 × 1004
Photoactive Pixels
4 Dark Rows
12 Dark Columns
0 Dark Rows
12 Dark Columns
1004 × 1004
Photoactive Pixels
4 Dark Rows
12 Dark Columns
0 Dark Rows
12 Dark Columns
The KAI−1020 is designed to read the image out of one
output at 30 frames/second or two outputs at
48 frames/second. In the dual output mode the right half of
the horizontal shift register reverses its direction of charge
transfer. The left half of the image is read out of video 1 and
the right half of the image is read out of video 2.
There are no dark reference rows at the top and 4 dark rows
at the bottom o f the image sensor. The 4 dark rows should not
be used for a dark reference level. The dark rows will contain
smear signal from bright light sources. Use the 12 dark
columns o n the left or right side of the image sensor as a dark
reference.
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The KAI−1020 Pixel
The pixel is 7.4 mm square. It consists of a light sensitive
photodiode and an optically shielded vertical shift register.
The vertical shift register is a charge-coupled device
(VCCD). Each pixel is covered by a microlens to increase
the light gathering efficiency of the photodiode.
Under normal operation, the image capture process begins
with a 4 ms long pulse on the electronic shutter trigger input
fSH. The electronic shutter empties all charge from every
photodiode in the pixel array.
The photodiodes start collecting light on the falling edge
of the fSH pulse. For each photon that is incident upon the
7.4 mm square area of the pixel, the probability of an electron
being generated in the photodiode is given by the quantum
efficiency (QE). At the end of the desired integration time,
a 10 ms pulse on fV2B transfers the charge (electrons)
collected in the photodiode into the VCCD. The integration
time ends on the falling edge of fV2B.
Figure 20. Pixel
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High Level Block Diagram
Figure 21. High Level Block Diagram
VCCD
Phase 2
Driver
VCCD
Phase 1
Driver
Pixel Array
Substrate
Electronic
Shutter
Driver
CDS 2
Fast Dump
Driver
CDS 1
HCCD
KAI−1020
fV1
fSH
fT2
fR2
fS2A
fS2B
VOUT2A
VOUT2B
fH2S
fH1BR
fH2BR
fH1S
fH1BL
fH2BL
fV2A
fV2B
fFD
fT1
fR1
fS1A
fS1B
VOUT1A
VOUT1B
All timing inputs are driven by 5 V logic. The image
sensor has integrated clock drivers to generate the proper
voltages for the internal CCD gates. There are two VCCD
clock drivers. Both the phase 1 and phase 2 VCCD drivers
control the shifting of charge through the VCCD.
The phase 2 driver also controls the transfer of charge from
the photodiodes to the VCCD.
There is an integrated fast dump driver, which allows an
entire row of pixels to be quickly discarded without clocking
the row through the HCCD.
An integrated electronic shutter driver generates a > 30 V
pulse on the substrate to simultaneously empty every
photodiode on the image sensor.
Each of the two outputs has a correlated double sampling
circuit to simplify the analog signal processing in the
camera. The horizontal clock timing selects which outputs
are active.
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Main Timing
Figure 22. Timing Flow Chart
Vertical Frame
Timing
Horizontal Line
Timing
Repeat for
1008 Lines
Vertical Frame Timing
Figure 23. Vertical Frame Timing
t
VP
0
5
0
5
0
5
0
5
0
5
fV1
fV2A
fV2B
fH1S
fH2S
t
V3 tVCCD
t
VP
The vertical frame timing may begin once the last pixel of
the image sensor has been read out of the HCCD.
The beginning of the vertical frame timing is at the rising
edge o f fV2A. After the rising edge of fV2A there must be
a delay o f t VP ms before a pulse o f t V3 ms on fV2B and fV1.
The charge is transferred from the photodiodes to the VCCD
during the time tV3. The falling edge of fV2B marks the end
of the photodiode integration time. After the pulse on fV2B
the fV1 and fV2A should remain idle for tVP ms before the
horizontal line timing period begins. This allows the clock
and well voltages time to settle for efficient charge transfer
in the VCCD.
All HCCD and CDS timing inputs should run
continuously through the vertical frame timing period. For
an extremely short integration time, it is allowed to place an
electronic shutter pulse on fSH at any time during the
vertical frame timing. The fSH and fV2B pulses may be
overlapped. The integration time will be from the falling
edge of fSH to the falling edge of fV2B.
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Horizontal Line Timing
Figure 24. Horizontal Line Timing
fV1
fV2A
fV2B
fH1S
fH2S
tVCCD
tP
KAI−1020 HCCD
522 Pixels 522 Pixels
Video 2
Timing Inputs
fH1BL
fH2BL
fH1BR
fH2BR
0
5
0
5
0
5
0
5
0
5
fH1S
fH2S
tVCCD
When the fV2A and fV1 timing inputs are pulsed, charge
in every pixel of the VCCD is shifted one row towards the
HCCD. The last row next to the HCCD is shifted into the
HCCD. When the VCCD is shifted, the timing signals to the
HCCD must be stopped. fH1S must be stopped in the high
state and fH2S must be stopped in the low state. The HCCD
clocking may begin tVCCD ms after the falling edge of the
fV2A and fV1 pulse. The timing inputs to the CDS should
run continuously through the horizontal line timing.
The HCCD has a total of 1036 pixels. The 1028 vertical
shift registers (columns) are shifted into the center 1028
pixels of the HCCD. There are 8 pixels at both ends of the
HCCD which receive no charge from a vertical shift register.
The first 8 clock cycles of the HCCD will be empty pixels
(containing no electrons). The next 12 clock cycles will
contain only electrons generated by dark current in the
VCCD and photodiodes. The next 1004 clock cycles will
contain photo-electrons (image data). Finally, the last 12
clock cycles will contain only electrons generated by dark
current in the VCCD and photodiodes. Of the 12 dark
columns, the first and last dark columns should not be used
for determining the zero signal level. Some light does leak
into the first and last dark columns. Only use the center 10
columns of the 12 column dark reference.
When the HCCD is shifting valid image data, the timing
inputs to the electronic shutter driver (fSH), VCCD driver
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(fV2A, fV2B, fV1), and fast dump drivers (fFD) should
be held at the low level. This prevents unwanted noise from
being introduced into the CDS circuit.
The HCCD is a type of charge coupled device known as
a pseudo-two phase CCD. This type of CCD has the ability
to shift charge in two directions. This allows the entire image
to be shifted out to the video 1 output CDS, or to the video 2
output CDS (left/right image reversal). The HCCD is split
into two equal halves of 522 pixels each. When operating the
sensor in single output mode the two halves of the HCCD are
shifted in the same direction. When operating the sensor in
dual output mode the two halves of the HCCD are shifted in
opposite directions. The direction of char ge transfer in each
half is controlled by the fH1BL, fH2BL, fH1BR,
and fH2BR timing inputs.
Single Output
To direct all pixels to the video 1 output make the
following HCCD connections:
fH1S = fH1BL, fH2BR
ąfH2S = ffH2BL, fH1BR
To direct all pixels to the video 2 output make the
following HCCD connections:
fH1S = fH2BL, fH1BR
ąfH2S =ffH1BL, fH2BR
In each case the first 8 pixels will contain no electrons,
followed by 12 dark reference pixels containing only
electrons generated by dark current, followed by 1004
photo-active pixels, followed by 12 dark reference pixels.
The HCCD must be clocked for at least 1028 cycles.
The VCCD may be clocked immediately after the 1028th
HCCD clock cycle.
If the sensor is to be permanently operated in single output
mode through video 1, then VDD2 (pins B8, and B10) may
be connected to GND. This disables the video 2 CDS and
lowers the power consumption.
If the sensor is to be permanently operated in single output
mode through video 2, then VDD1 and VDD2 supplies must
be +15 V. The VDD1 supplies must always be at +15 V for
the sensor to operate properly.
Dual Output
To use both outputs for faster image readout, make the
following HCCD connections:
fH1S = fH1BL, fH1BR
fH2S = fH2BL, fH2BR
For both outputs the first 8 HCCD clock cycles contain n o
electrons, followed by 12 dark reference pixels containing
only dark current electrons, followed by 502 photo-active
pixels. This adds up to 522 pixels, but the HCCD should be
clocked for at least 523 cycles before the next VCCD line
shift takes place. The extra HCCD clock cycle ensures that
the signal from the last pixel exits the CDS circuit before the
VCCD drivers switch the gate voltages. This extra cycle is
not needed for the single output modes because in that case,
the last pixel is from a column of the dark reference which
is not used. See the section on correlated double sampling
for a description of the one pixel delay in the CDS ci rcuit.
Electronic Shutter
Substrate Voltage
The voltage on the substrate, pins L1 and L5, determines
the charge capacity of the photodiodes. When VSUB is 8 V
the photodiodes will be at their maximum charge capacity.
Increasing VSUB above 8 V decreases the charge capacity
of the photodiodes until 30 V when the photodiodes have
a charge capacity of zero electrons. Therefore, a short pulse
on VSUB, with a peak amplitude greater than 30 V, empties
all photodiodes and provides the electronic shuttering
action.
Substrate Voltage and Anti-Blooming
It may appear the optimal substrate voltage setting is 8 V
to obtain the maximum charge capacity and dynamic range.
While setting VSUB to 8 V will provide the maximum
dynamic range, it will also provide the minimum
anti-blooming protection.
The KAI−1020 VCCD has a charge capacity of 60,000
electrons (60 ke−). If the VSUB voltage is set such that the
photodiode holds more than 60 ke−, then when the charge is
transferred from a full photodiode to VCCD, the VCCD will
overflow. This overflow condition manifests itself in the
image by making bright spots appear elongated in the
vertical direction. The size increase of a bright spot is called
blooming when the spot doubles in size.
The blooming can be eliminated by increasing the voltage
on VSUB to lower the charge capacity of the photodiode.
This ensures the VCCD charge capacity is greater than the
photodiode capacity. There are cases where an extremely
bright spot will still cause blooming in the VCCD. Normally,
when the photodiode is full, any additional electrons
generated by photons will spill out of the photodiode.
The excess electrons are drained harmlessly out to the
substrate. There is a maximum rate at which the electrons
can be drained to the substrate.
If that maximum rate is exceeded, (say, for example, by
a very bright light source) then it is possible for the total
amount of charge in the photodiode to exceed the VCCD
capacity. This results in blooming.
The amount of anti-blooming protection also decreases
when the integration time is decreased.
There is a compromise between photodiode dynamic
range (controlled by VSUB) and the amount of
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26
anti-blooming protection. A low VSUB voltage provides the
maximum dynamic range and minimum (or no)
anti-blooming protection. A high VSUB voltage provides
lower dynamic range and maximum anti-blooming
protection. The optimal setting of VSUB is written on the
container in which each KAI−1020 is shipped. The given
VSUB voltage for each sensor is selected to provide
anti-blooming protection for bright spots at least 100 times
saturation, while maintaining at least 500 mV of dynamic
range.
A detailed discussion of anti-blooming and smear may be
found in IEEE Transactions on Electron Devices vol. 39
no. 11, pg. 2508.
Extremely bright light can potentially harm solid state
imagers such as Charge-Coupled Devices (CCDs). Refer to
Application Note Using Interline CCD Image Sensors in
High Intensity Visible Lighting Conditions.
Electronic Shutter Timing
The electronic shutter provides a method of precisely
controlling the image exposure time without any
mechanical components. If an integration time of tINT is
desired, then the substrate voltage of the sensor is pulsed to
at least 30 V tINT seconds before the photodiode to VCCD
transfer pulse on fV2B. The lar ge substrate voltage pulse is
generated by the KAI−1020. The electronic shutter is
triggered by a 5 V pulse on fSH. Use of the electronic
shutter does not have to wait until the previously acquired
image has been completely read out of the VCCD.
The electronic shutter pulse may be added to the end of the
horizontal line timing and just after the last pixel has been
read out of the HCCD. fH1S and fH2S must be clocked
during the electronic shutter pulse.
Figure 25. Electronic Shutter Timing
fV1
fV2A
fV2B
fH1S
fH2S
t
VCCD
0
5
0
5
0
5
0
5
0
5
0
5
fSH
t
VCCD
t
VCCD
t
VCCD
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Fast Dump
The KAI−1020 has the ability to rapidly discard (fast
dump, FD) entire lines of the image. The fast dump is a drain
attached to the last row of the VCCD just before the HCCD.
When the fast dump is activated by taking fFD high, charge
from the VCCD goes into the drain instead of into the
HCCD.
Figure 26. Fast Dump Timing
fV1
fV2A
fV2B
fH1S
fH2S
t
VCCD
fFD
0
5
0
5
0
5
0
5
0
5
0
5
t
P
t
VCCD
t
VCCD
t
VCCD
t
VCCD
t
VCCD
This timing diagram shows how two lines are dumped and
the third is read out. fFD should go high once the last pixel
of the preceding line has been read out. Cycle the VCCD for
the number of rows to be dumped. The above timing
diagrams shows two rows being dumped. When the proper
number of rows have been dumped bring fFD low. Then
clock the VCCD through one more cycle to shift a row into
the HCCD.
The fast dump can be used to sub-sample the image for
increased frame rates. For example, by dumping the even
numbered lines, the image will be sub-sampled by a factor
of 2 and the frame rate will almost increase by a factor of 2.
Horizontal sub-sampling is not possible. The HCCD must
always be cycled for the entire number of pixels in one line.
Another way to increase the frame rate is through
sub-windowing. For example, suppose only the center 512
lines of the image are needed. Turn on the fast dump and
clock the VCCD for 256 lines. Then turn off the fast dump
and clock the VCCD (and HCCD) for 512 lines. Finally, turn
the fast dump on again and clock the VCCD for 240 lines.
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Binning and Interlaced Modes
Binning i s a readout mode of progressive scan CCD image
sensors where more than one row at a time is clocked into the
HCCD before reading out the HCCD. This timing mode
sums two or more rows together. It increases the frame rate
because there are fewer total rows to read out of the HCCD.
The following timing diagram shows how two rows are
summed together:
Figure 27. Binning Line Timing
fV1
fV2A
fV2B
fH1S
fH2S
t
VCCD
fFD
t
P
0
5
0
5
0
5
0
5
0
5
0
5
t
VCCD
t
VCCD
t
VCCD
When binning two rows together only 504 rows need to b e
read out of the HCCD instead of the normal 1008 rows.
The HCCD will hold up to two VCCD rows of full signal
without blooming. Binning more than two rows may cause
horizontal blooming for saturated signal levels.
Interlaced readout is a form of binning. To read out the
even field use binning to sum together rows 0+1,
rows 2+3, ... rows 1006+1007. To read out the odd field use
binning to read out rows 0+1+2, rows 3+4, rows 5+6, ....
rows 1005+1006, rows 1007+1008. The odd field may also
be read out as row 0, rows 1+2, rows 3+4, ....
rows 1005+1006. See the Interlaced – Field Integration
section for an example of interlaced timing.
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Correlated Double Sampling (CDS)
Figure 28. Correlated Double Sampling Block Diagram
CTA
f
SA
fSB
f
T
fRCSA
CTB
CSB
C
HCCD
Output
VDD
VOUTA
VOUTB
VREF
VDD
Correlated double sampling is a method of measuring the
amount o f char ge in each pixel. The electrons in the last pixel
of the HCCD are transferred onto a very small sensing
capacitor, C, on the falling edge of fH2S. The voltage on C
will change by about 20 mV for each electron that was in the
HCCD. The process of measuring the amount of charge
begins by resetting the value of C to an internally generated
reference voltage, Vref. A short pulse on fR at the rising
edge o f fH2S will reset C. After C has been reset, its voltage
is sampled and stored on CSA by a short pulse on switch
fSA. Then on the falling edge of fH2S, electrons are
transferred onto the capacitor, C. The new voltage on C is
sampled and stored on C SB by a short pulse on switch fSB.
These two sampled voltages are then transferred to
capacitors C TA and CTB by a short pulse on fT. fT and fR
generally occur at the same time. An external operational
amplifier i s used to subtract the two voltages on VOUTA and
VOUTB. The output of the op-amp will be proportional to
the number of electrons contained in one pixel. Note that it
takes one entire pixel clock cycle for the value of the pixel
to appear on VOUTA and VOUTB. The A and B outputs of
the CDS circuit will be in the range of 7 to 11 V.
CDS Timing Edge Alignment
1. The edge alignments of the CDS timing pulses
fSA, fSB, fT, and fR are critical to proper
operation of the CDS circuit.
2. The falling edge of fR must not overlap the rising
edge of fSA
3. The falling edge of fSA must come at the same
time or before the falling edge of fH2
4. The rising edge of fSB must come after the falling
edge of fH2
5. The falling edge of fSB must come before the
rising edge of fR
6. The rising edge of fR may come before the rising
edge of fH2
7. fT should always be driven by the same timing
signal as fR
8. The pulse widths should be set such that fR, fSA,
and fSB are 1/3 of tP
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Figure 29. Correlated Double Sampling Timing
fR
fSA
fSB
fH2
fT
t
P
0
5
0
5
0
5
0
5
0
5
tP/3 tP/3 tP/3
Disabling the CDS
There may be instances when the camera designer may
want to use an external CDS. Such cases may occur at pixel
clock frequencies 20 MHz or slower where integrated CDS,
analog to digital converter (A/D), and auto offset/gain
circuits are available. These external CDS circuits require
the raw unprocessed video waveform. The raw video can b e
obtained by permanently turning on the fSA, fSB, and fT
switches by connecting them to a voltage in the range of 8
to 10 V (the V2HIGH supply voltage, for example). Then
place a load of 4 mA to 5 mA on VOUTA and a load of
0.1 mA on VOUTB. VOUTA will be the raw video output
suitable for external CDS circuits. The 5 mA load may be
a 2.0 kW resistor and the 0.1 mA load may be an 80 kW
resistor to GND. An external CDS is not recommended for
pixel frequencies above 20 MHz.
KAI−1020
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31
Timing and Voltage Specifications
Table 10. ABSOLUTE MAXIMUM RATINGS
Minimum Maximum Units Notes
Temperature Operation without Damage −50 70 °C
Storage −55 70 °C
Voltage between Pins VSUB to GND 8 20 V
VDD to GND 0 17 V
fV1 to fV2, fFD to fV1, fV2 −10 10 V
fH1 to fH2 −8 8 V
fR, fT, fSA, fSB to GND −9 12 V
fH1, fH2 to fV1, fV2 −9 10 V
Current Video Output Bias Current 0 7 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. For electronic shuttering VSUB may be pulsed to 35 V for up to 10 ms.
2. Note that the current bias affects the amplifier bandwidth.
Table 11. TIMING
Time Minimum Nominal Maximum Units
tP25 25 500 ns
tVCCD 3.6 3.6 10 ms
tVP 20 25 40 ms
tV3 8 10 15 ms
Table 12. BIAS VOLTAGES
Bias Minimum
(V) Nominal
(V) Maximum
(V) Peak Current
(mA) Peak Current
Frequency Avg. Current
(mA)
V1S5 4 5 6 2 2L 0.13
V1MID −1.5 −1.2 −1.0 110 L 3
V1LOW −9.5 −9 −8.5 110 L 3
V2S5 4 5 6 2 2L 0.5
V2S9 8 9 10 2 F 0.3
V2HIGH 8 9 10 110 L 0.01
V2MID −1.5 −1.2 −1.0 110 L 3
V2LOW −9.5
−9.5 −9
−9 −8.5
−8.5 110
220 L
F3.8
3.8
VDD1 14.5 15 15.5 − − 14
VDD2 14.5 15 15.5 − − 14
VSH15 14 15 16 1 F 0.08
VSUB 8 * 14 − − 0.03
1. Average currents are for 30 frames/second.
2. Peak switching currents are for less than 1 ms duration.
3. L = once per line time, 2L = twice per line time, F = once per frame time.
4. Substrate bias voltage for a 500 mV output range is written on the shipping container for each part.
KAI−1020
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32
Power Up Sequence
1. Power up VSUB, V1LOW, V2LOW first
2. Then power up VDD, VSH15, V2S5, V1S5,
V1MID, V2MID and V2HIGH
3. Then after the coupling capacitors on all of the
timing inputs have charged, begin clocking the
timing inputs.
Any positive voltage should never be allowed to go
negative. Any negative voltage should never be allowed to
go positive.
Note that the shutter driver clock input does not use
a coupling capacitor. It must be driven directly from a 5 V
logic buffer as shown in the evaluation board schematic.
Table 13. PULSE AMPLITUDES
Clock Min. Amplitude
(V) Coupling
Min. Coupling
Capacitor Value
(mF)
Max. Coupling
Capacitor Value
(mF)
fSH 3.5 DC − −
fH1 4.7 AC 0.1 0.47
fH2 4.7 AC 0.1 0.47
fSA 4.7 AC 0.01 0.47
fSB 4.7 AC 0.01 0.47
fR4.7 AC 0.01 0.47
fT4.7 AC 0.01 0.47
fV1 4.0 AC 0.01 0.47
fV2A 4.0 AC 0.01 0.47
fV2B 4.0 AC 0.01 0.47
fFD 4.0 AC 0.1 0.47
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Timing Examples
Progressive Scan
Figure 30. Progressive Scan Timing Example
FD
Progressive Scan, No Electronic Shutter
Exposure Time = Frame Time
Repeat 1008 Times
1028 Clock Cycles Single Output
523 Clock Cycles Dual Output
SH
H2
H1
V1
V2A
V2B
Progressive Scan, Using Electronic Shutter
Frame Time
Exposure Time
This Line has 7.2 ms more HCCD Move this Pulse in Increments of One
Line Time to Change the Exposure Time
FD
SH
H2
H1
V1
V2A
V2B
KAI−1020
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Fast Line Dump
Figure 31. Fast Line Dump Timing Example
Fast Dump Timing, Reads Out the Center 500 Rows
Exposure Time = Frame Time
Repeat 1008 Times
1028 Clock Cycles Single Output
523 Clock Cycles Dual Output
Fast Dump Timing with Electronic Shutter, Reads Out the Center 500 Rows
Frame Time
Exposure Time
FD
SH
H2
H1
V1
V2A
V2B
Repeat 500 Times Repeat 252 Times
Repeat 500 Times
Repeat 252 Times
Repeat 252 Times
SH Pulse Width = 3.6 ms, Total Interval = 7.2 ms
FD
SH
H2
H1
V1
V2A
V2B
KAI−1020
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Interlaced − Field Integration
Figure 32. Interlaced − Field Integration Timing Example
Even Interlaced Field
Exposure Time = Frame Time
1028 Clock Cycles Single Output
523 Clock Cycles Dual Output
Odd Interlaced Field
Exposure Time = Frame Time
FD
SH
H2
H1
V1
V2A
V2B
Repeat 504 Times
Repeat 503 Times
FD
SH
H2
H1
V1
V2A
V2B
These Two
Pulses Add Two
Rows Together
KAI−1020
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37
Horizontal CCD Drive Circuit
Figure 34. HCCD Drive Block Diagram
Single Output Only Dual Output Only
Selectable Single or Dual Output
The HCCD clock inputs should be driven by buffers
capable of driving a capacitance of 60 pF and having a full
voltage swing of at least 4.7 V. A 74AC04 or equivalent is
recommended t o drive the HCCD. The HCCD requires a 0 V
to –5 V clock. A negative clock level is easily obtained by
capacitive coupling and a diode to clamp the high level to
GND. Every HCCD clock input has a 300 kW on chip
resistor to GND.
The inputs to the above circuits, H1 and H2, are 5 V logic
from the timing generator (a programmable gate array for
example). If the camera is to have selectable single or dual
output modes of operation, then the timing logic needs to
generate two extra signals for the H1BR and H2BR timing.
For single output mode program the timing such that
H1BR = H2 and H2BR = H1. For dual output mode
program the timing such that H1BR = H1 and H2BR = H2.
KAI−1020
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38
Vertical CCD
The VCCD clock inputs, fV2A, fV2B, fV1, and fFD
have a capacitive load of approximately 10 pF. Each input
is connected to V2LOW and V1LOW by a 60 kW internal
resistor. There is also an internal diode connected to
V2LOW and V1LOW. The 5 V logic drivers must be
connected to the sensor inputs through capacitors. These
inputs require a clock of at least 4 V amplitude. Most PGA’s
can drive these inputs directly. The external capacitor and
internal diode level shift the 0 V to 5 V input to V2LOW to
V2LOW + 5.
The on chip VCCD clock drivers switch their outputs,
V1OUT and V2OUT, between the supply voltages V1LOW,
V1MID, V2LOW, V2MID, and V2HIGH. The truth table
correlating the voltage on V1OUT and V2OUT to the timing
inputs is:
Table 14.
fV1 V1OUT
H V1MID
L V1LOW
fV2A fV2B V2OUT
L L V2LOW
H L V2MID
L H V2HIGH
H H V2HIGH
NOTE: L = Logic Low level; H = Logic High level
The output of the VCCD driver is connected to the VCCD
gates by wiring V1OUT to V1IN and V2OUT to V2IN. The fast dump driver has no external output. It is wired
internally to the VCCD fast dump gate.
Figure 35. VCCD Block Diagram
KAI−1020
Inputs
Timing
Generator
Outputs
KAI−1020
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Electronic Shutter
The electronic shutter input, fSH, is the only input driven
directly by CMOS logic. No capacitive coupling is required.
fSH (pin B3) has approximately a 10 pF load. The logic low
level must be less than 0.5 V and the logic high level must
be greater than 3.5 V. Most programmable gate arrays can
drive fSH directly. The on chip electronic shutter driver is
a charge pumping circuit. It uses C1, C2, D1, and D2 to
generate a > 25 V pulse that is added onto the substrate DC
bias voltage. The substrate bias voltage is set by a trim-pot
R2 or by some programmable voltage source. The substrate
bias voltage absolutely MUST be adjustable. The camera
designer CAN NOT rely on every KAI−1020 image sensor
requiring the same substrate bias. An adjustment range of 8
to 13 V must be allowed. Each image sensor has the optimal
substrate bias voltage (as measured on the VSUB pin)
printed on the shipping container.
Figure 36. Electronic Shutter Block Diagram
The minimum allowed voltage on VSUB is 8 V. Lower
voltages may destroy the CDS and clock driver circuits.
NOTE: Extremely bright light can potentially harm solid
state imagers such as Charge-Coupled Devices
(CCDs). Refer to Application Note Using
Interline CCD Image Sensors in High Intensity
Visible Lighting Conditions.
KAI−1020
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CDS Timing Inputs
The CDS timing inputs fR, fT, fSA, and fSB should be
driven by CMOS logic with fast rise and fall times and an
amplitude of at least 4.7 V. The capacitance of each pin on
the sensor is approximately 10 pF. The pulses are level
shifted positive by 1 V or 2 V on the sensor. If driving this
input directly from a programmable gate array, be aware tha t
some PGA’s do not have outputs with amplitudes of 4.7 V.
It is recommended that the CDS timing inputs be driven by
a 74AC04 to insure a 5 V pulse amplitude with fast edges.
Figure 37. Correlated Double Sampling Block Diagram
Dual Output Single Output Only
If the camera will only operate in single output mode then
the fR2, fT2, fS2A, and fS2B inputs should be connected to GND. All CDS timing inputs must be coupled with
a capacitor.
KAI−1020
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CDS Output Circuit
Figure 38. Correlated Double Sampling Output Circuit Block Diagram
In the above schematic the differential video outputs
VOUTB and VOUTA are subtracted by op-amp U2A.
The video outputs will have a DC level of 7 to 11 V. U2B
then inverts the signal and applies a gain of 2.1 relative to t he
offset voltage. The output of U2B will match the 500 mV
output range of the KAI−1020 to the 1 V input range of the
analog to digital converter (A/D).
VOUTB will swing in the negative direction with
increasing light level. The output of U2A will swing in the
positive direction with increasing light level. The output of
U2B (input to the A/D) will swing in the negative direction.
This means the A/D output will be 0 counts when the image
sensor is saturated. The digital data will have to be inverted
before being transmitted to a digital image capture device.
See the KAI−1020 evaluation board schematic for a simple
method of inverting the data with no additional components.
The offset will have to be dynamically adjusted to match
the zero light level of the image sensor. A circuit should
examine the digital data in the dark reference columns and
adjust the offset voltage of U2B to maintain a constant zero
reference level in the A/D converter. The dynamic
adjustment of the offset voltage will remove most
temperature dependent drifts. Small temperature-dependent
gain changes will still be present. See the KAI−1020
evaluation board schematic for an example of a circuit to
generate the offset voltage.
This output circuit provides 10 bits of dynamic range on
the KAI−1020 evaluation board. It is not the optimum
circuit. For optimum differential common mode noise
rejection and linearity, the CDS output circuit should take
into account the 160 W impedance of the CDS output drive
transistor.
KAI−1020
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42
Power Supplies
Figure 39. Power Supply Block Diagram
+15V VSH15(A3)
VDD1(K8,L10)
VDD2(B10,B8)
+5V V2S5(L6)
V1S5(B7)
+9V V2HIGH(L4)
V2S9(K6)
−9V V2HIGH(K3)
V1LOW(K6)
GND V1MID(A7)
V2MID(K4)
0.1u
D2 D4
The V1MID and V2MID connections must be set to –1.0
to –1.5 V. Since V1MID and V2MID only sink current, two
diodes can be used to set this voltage.
If the sensor is to use only the single output mode, then
VDD2(B10,B8) can be connected to GND. VOUT2A(A9)
and VOUT2B(A10) also should be connected to GND in the
single output only mode.
KAI−1020
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50
Parts List
Table 15. PARTS LIST
C1 PCAP, 4.7 mF
C2 CAP, 0.1 mF
C3 CAP, 1 mF
C4−9 CAP, 0.1 mF
C10 CAP, 4.7 mF
C11, C12 CAP, 0.1 mF
C13−15 CAP, 4.7 mF
C16 CAP, 0.1 mF
C17 CAP, 1 mF
C18−21 CAP, 0.1 mF
C22 CAP, 4.7 mF
C23, C24 CAP, 0.1 mF
C25 CAP, 4.7 mF
C26 CAP, 0.1 mF
C27 CAP, 4.7 mF
C28 CAP, 0.1 mF
C29 CAP, 4.7 mF
C30 CAP, 0.1 mF
C31 CAP, 4.7 mF
C32−38 CAP, 0.1 mF
C39 CAP, 4.7 mF
C40−52 CAP, 0.1 mF
C53−55 CAP, 4.7 mF
C56−58 CAP, 0.1 mF
C59 CAP, 4.7 mF
C60−63 CAP, 0.1 mF
C64 CAP, 4.7 mF
C65−72 CAP, 0.1 mF
D1−3 MMBD914
D4, D5 MMBD2837
R1 VRES, 10 kW
R2 RES, 470 W
R3 RES, 1 kW
R7 RES, 20 W
R8 RESNET
R9 RES, 100 W
R10, R11 RES, 1 kW
R12 RES, 2 kW
R13 RES, 1 kW
R14 RESNET
R15 RESNET
R16, R17 RES, 1 kW
R18 RES, 2 kW
R19 RES, 1 kW
R20 RES, 470 W
R21 RES, 1 kW
R23 RES, 5.6 kW
R24 RES, 2 kW
R25 RES, 20 W
R26 RES, 2 kW
R27 RES, 100 W
R28 RESNET
R29 RES, 2 kW
R30 RES, 200 W
R31 RES, 200 W
R32 RES, 1.24 kW
R33 RES, 220 W
R34 RES, 1.24 kW
R35 RES, 220 W
R36 RES, 1.5 kW
R43 RES, 100 kW
R44 RES, 200 W
R45 RES, 100 kW
R46 RES, 200 W
SW1 DIP8 4 POS DIP SW
SW2 DIAL 16 POS ROTARY
U1 KAI1020 IMAGE SENSOR
U2 AD9042/SO A/D ANALOG DEV
U3 OPAMP DUAL,
OPA2650U BURR BROWN
U4 AD9042/SO A/D ANALOG DEV
U5 OPAMP DUAL,
OPA2650U BURR BROWN
U6 DS90C031 NATIONAL
U7 LM337L
U8 LAT1032E TQFP100 LATTICE SEMI
U9 74AC04
U10 DELAY10 DATA DELAY
DEV 711 2.5 ns
U11 74AC04
U12 LAT1016 LATTICE SEMI
U13 OPAMP−DUAL,
LMC6492BEM NATIONAL
U14 OSC\SO 80 MHz
U15−20 DS90C031 NATIONAL
U21 LM317L
U22, U23 NC7SZ126 FAIRCHILD
L1−4 FB FERRITE BEAD
J1 SCSI−100
J2 HEADER10 POWER CONN
J3 SIP\8P PROGRAM CONN
J4 LATCON PROGRAM CONN
KAI−1020
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51
Digital Output Connector
The output connector is a 100 pin female SCSI type
connector, pin compatible with the National Instruments
PCI−1424 digital frame grabber, part number 777662−02.
The interface cable is available from National Instruments,
part number 185012−02.
Output 1 Pin
Data 0+ 1
Data 0− 2
Data 1+ 3
Data 1− 4
Data 2+ 5
Data 2− 6
Data 3+ 7
Data 3− 8
Data 4+ 9
Data 4− 10
Data 5+ 11
Data 5− 12
Data 6+ 13
Data 6− 14
Data 7+ 15
Data 7− 16
Data 8+ 17
Data 8− 18
Data 9+ 19
Data 9− 20
Data 10+ 21
Data 10− 22
Data 11+ 23
Data 11− 24
Output 2 Pin
Data 0+ 51
Data 0− 52
Data 1+ 53
Data 1− 54
Data 2+ 55
Data 2− 56
Data 3+ 57
Data 3− 58
Data 4+ 59
Data 4− 60
Data 5+ 61
Data 5− 62
Data 6+ 63
Data 6− 64
Data 7+ 65
Data 7− 66
Data 8+ 67
Data 8− 68
Data 9+ 69
Data 9− 70
Data 10+ 71
Data 10− 72
Data 11+ 73
Data 11− 74
Sync Pin
Pixel+ 49
Pixel− 50
Line+ 43
Line− 44
Frame+ 41
Frame− 42
Field Index 45
GND 99
GND 100
All other pins have no connection. All outputs are driven
by low voltage differential line drivers (LVDS) except for
the field index which is TTL.
KAI−1020
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52
Power Connector
Figure 47. Power Connector Block Diagram
+15
GND
−15
GND
+5
+15
GND
−15
GND
+5
0.1″
0.1″
The evaluation board requires +15 V, −15 V, and +5 V.
The current draw for each supply is:
Table 16.
Supply Current (mA)
+15 62
−15 18
+5 780
Table 17. MODE SWITCH
Switch ON OFF
1Fast Dump OFF Fast Dump ON
21 Output 2 Outputs
3 − −
4Progressive Scan Interlaced
When the fast dump is activated the timing dumps the first
256 lines, then reads out 512 lines of image data, and finally
it dumps the last 240 lines. The resulting image is 1000
columns by 512 rows. The interlaced mode timing is not
programmed to support fast dumping.
Table 18. EXPOSURE SWITCH
(All exposure times are in ms. Electronic shuttering is not programmed into the timing generator for interlaced mode.)
Exposure Setting FD OFF: 1 Output FD OFF: 2 Outputs FD ON: 1 Output FD ON: 2 Outputs
0 33,300 20,600 20,600 14,160
1 16,400 10,160 6,000 4,400
2 7,960 4,960 3,000 2,540
3 3,740 2,320 1,860 1,840
4 1,616 1,016 1,700 1,700
5 564 362 824 824
KAI−1020
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Substrate Voltage Trim
This variable resistor allows the substrate voltage to be
varied from 0 V to 15 V. Adjusting this voltage will change
the charge capacity and anti-blooming of the pixel
photodiodes. Do not adjust the voltage below 8 V.
Evaluation Board Notes
Timing
The main timing is generated by a programmable gate
array U8. The HCCD drive is setup for selectable single or
dual output by inverting the H2BR and H2BL timing signals
depending on the setting of the mode switch SW1.
The short pulses for fR, fT, fSA, and fSB are generated
by combining (logical and/or) the outputs of the delay line
U10. Each tap on U10 delays the system clock by 2.5 ns.
The amount of noise in the KAI−1020 will have a strong
dependence on the stability of the timing inputs. The most
sensitive inputs are the HCCD and the CDS timing inputs.
The evaluation board uses one PGA (U8) to hold all of the
counters and to generate the CDS timing. This is not the
optimum arrangement. Though gray code counters were
used, some fixed pattern column noise can be seen in the
image from the counters inside U8. The counters inside U8
cause small disturbances o f the HCCD and CDS timing. One
solution to eliminate this noise source is to separate the
counters and CDS pulse generation into two separate PGA’ s.
One PGA would contain all of the counters for the rows and
columns, and send a HCCD gating signal to a second PGA.
The second PGA would output the HCCD clock as well as
form the CDS timing pulses from the multi-tap delay line
U10. This second PGA would contain no counters.
Output Channel
The output circuit is identical to section 0. The two
op-amps U5A and U5B present an inverted signal to the
ADC U4. The offset circuit will maintain the digital output
of U4 at 4080 when the image sensor is in the dark.
The output of U4 will be zero when the image sensor is
saturated with light. The digital data is inverted by swapping
the high and low outputs of the differential line drivers on the
output connector.
Automatic Offset
U12 is used to control the automatic offset circuit. U8
sends a signal to U12 on the line BLKLEV when the output
of the analog to digital converter corresponds to the center
10 columns of the KAI1020 dark reference. When U12
receives the signal from U8, U12 compares the outputs of
the A/D converters to the number 4080. If the output is above
or below 4080, U12 enables the buffers U22 and U23 and
sets their inputs to cause the integrators U13A and U13B to
raise or lower the offset voltages.
A separate PGA (U12) is used to monitor the output of the
A/D converters. This function should not be combined with
U8 into one PGA. If only one PGA is used then the digital
data will cause noise in the timing outputs to the image
sensor. This is especially true when the A/D outputs are near
a major bit boundary, such as 2048 or 1024. At these bit
boundaries there are a large number of bits changing value
that would disturb the stability of the HCCD and CDS
clocking.
The automatic offset updates the offset every line. This
does cause some noise in the image because the offset
changes slightly each line time. An improved offset circuit
would measure the offset error along the entire column and
then correct the offset voltage once per frame.
KAI−1020
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55
Oscilloscope Traces
This section contains oscilloscope traces of signals measured on the KAI−1020 pins. Some of the timing signals are not 0
to 5 V because the KAI−1020 has level shifted the signals. All signals were measured on the KAI−1020 evaluation board.
CDS Timing
Figure 48. CDS Timing Oscilloscope Traces
KAI−1020 40 MHz Timing
−6
−4
−2
0
2
4
6
8
10
0 5 10 15 20 25 30 35 40 45 50
Times (ns)
Volts
H2S
R
SB
SA
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58
STORAGE AND HANDLING
Table 19. CLIMATIC REQUIREMENTS
Description Symbol Min. Max. Units Notes
Storage Temperature TST −55 70 °C 1
Humidity RH 5 90 % 2
1. Long-term exposure toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade MTTF.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference Manual (SOLDERRM/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
KAI−1020
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61
Cover Glass
Pin Grid Array Cover Glass
Figure 53. PGA Cover Glass
NOTES:
1. Dust/Scratch 10 microns max
2. Substrate: SCHOTT D−263T eco or Equivalent
3. Epoxy: NCO−150HB
Thickness 0.002−0.005″ [0.05−0.13]
4. Double-Side AR Coating Reflectance
a. 420−435 nm < 2.0%
b. 435−630 nm < 0.8%
c. 630−680 nm < 2.0%
5. Units: IN [MM]
KAI−1020
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Leadless Chip Carrier Cover Glass
Figure 54. LCC Cover Glass
NOTES:
1. Dust/Scratch 10 microns max
2. Substrate: SCHOTT D−263T eco or Equivalent
3. Epoxy: NCO−150HB
Thickness 0.002−0.005″ [0.05−0.13]
4. Double-Side AR Coating Reflectance
a. 420−435 nm < 2.0%
b. 435−630 nm < 0.8%
c. 630−680 nm < 2.0%
5. Units: IN [MM]
KAI−1020
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63
Cover Glass Transmission
Figure 55. Cover Glass Transmission
0
10
20
30
40
50
60
70
80
90
100
200 300 400 500 600 700 800 900
Transmission (%)
Wavelength (nm)
AR Coated Used on Both
Package Configurations
KAI−1020 AR Glass
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent − Marking.pdf. S CILLC r eserves the r ight to make changes without f urther n otice to any product s herein. S CILLC makes n o warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all l iabilit y, including without limitation special, consequential o r i ncident al d amages. “Typical” paramet ers w hich m ay b e provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application b y c ust omer’s technical e xperts. SCILLC does not c onvey a ny l icense u nder its patent r ight s n or the rights of o thers. SCILLC products a re n ot d esigned, i nt ended,
or authorized for use as c omponent s i n s yst ems i nt ended f or s urgic al i m plant i nt o the body, or other applications intended t o s upport o r s ust ain life, o r for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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