Low Noise, 1 GHz
FastFET Op Amps
Data Sheet ADA4817-1/ADA4817-2
Rev. F Document Feedback
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FEATURES
High speed
−3 dB bandwidth (G = 1, RL = 100 Ω): 1050 MHz
Slew rate: 870 V/μs
0.1% settling time: 9 ns
Input bias current: 2 pA typical
Input capacitance
Common-mode capacitance: 1.3 pF typical
Differential mode capacitance: 0.1 pF typical
Low input noise
Voltage noise: 4 nV/√Hz at 100 kHz
Current noise: 2.5 fA/√Hz at 100 kHz
Low distortion: −90 dBc at 10 MHz (G = 1, RL = 1 kΩ)
orms a pole in the lo: 40 mA
Supply quiescent current per amplifier: 19 mA typical
Powered down supply quiescent current per amplifier:
1.5 mA typical
APPLICATIONS
Photodiode amplifiers
Data acquisition front ends
Instrumentation
Filters
ADC drivers
Output buffers
CONNECTION DIAGRAMS
07756-001
3–IN
4+IN
1PD
2FB
6NIC
5–V
S
8+V
S
7OUT
ADA4817-1
TOP VIE W
(Not to Scale)
NOTES
1. NIC = NO INTE RNAL CONNECTION.
Figure 1. 8-Lead LFCSP (CP-8-13)
FB
–IN
+IN
–V
S
PD
+V
S
OUT
NIC
NOTES
1. NIC = NO INT E RNAL CONNECTION.
ADA4817-1
TOP VIEW
(No t t o S cal e)
07756-002
1
2
3
4
8
7
6
5
Figure 2. 8-Lead SOIC (RD-8-1)
07756-003
ADA4817-2
TOP VIEW
(No t to Scale)
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
–IN1
+IN1
NIC
–V
S2
–V
S1
OUT1
+V
S1
PD1
FB1
NIC
+IN2
–IN2
OUT2
+V
S2
PD2
FB2
NOTES
1. NIC = NO INTERNAL CONNECTIO N.
Figure 3. 16-Lead LFCSP (CP-16-20)
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 2 of 31
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications ..................................................................................... 5
±5 V Operation ............................................................................. 5
5 V Operation ............................................................................... 6
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
Maximum Safe Power Dissipation ............................................. 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Test Circuits ..................................................................................... 18
Theory of Operation ...................................................................... 19
Closed-Loop Frequency Response ........................................... 19
Noninverting Closed-Loop Frequency Response .................. 19
Inverting Closed-Loop Frequency Response ............................. 19
Wideband Operation ................................................................. 20
Driving Capacitive Loads .......................................................... 20
Thermal Considerations ............................................................ 20
Power-Down Operation ............................................................ 21
Capacitive Feedback ................................................................... 21
Higher Frequency Attenuation ................................................. 22
Layout, Grounding, and Bypassing Considerations .................. 23
Signal Routing ............................................................................. 23
Power Supply Bypassing ............................................................ 23
Grounding ................................................................................... 23
Exposed Pad ................................................................................ 23
Leakage Currents ........................................................................ 24
Input Capacitance ...................................................................... 24
Input-to-Input/Output Coupling ............................................. 24
Applications Information .............................................................. 25
Low Distortion Pinout ............................................................... 25
Wideband Photodiode Preamp ................................................ 25
High Speed JFET Input Instrumentation Amplifier.............. 27
Active Low-Pass Filter (LPF) .................................................... 28
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 31
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 3 of 31
REVISION HISTORY
6/2018—Rev. E to Rev. F
Changes to Input Common-Mode Voltage Range, Table 1 ......... 5
Changes to Input Common-Mode Voltage Range, Table 2 ......... 7
1/2018—Rev. D to Rev. E
Changes to Figure 57 ...................................................................... 21
10/2017—Rev. C to Rev. D
Changes to Features Section and Applications Section ...................... 1
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 6
Changes to Thermal Resistance Section, Table 4, and Maximum
Safe Power Dissipation Section ....................................................... 8
Changes to Figure 5 ........................................................................... 9
Changes to Figure 7 ......................................................................... 10
Reorganized Typical Performance Characteristics Layout ........ 11
Added Figure 32 through Figure 37; Renumbered Sequentially .... 15
Added Figure 38 through Figure 43 .............................................. 16
Added Figure 44 and Figure 45 ..................................................... 17
Changes to Noninverting Closed-Loop Frequency Response
Section, Inverting Closed-Loop Frequency Response Section,
and Figure 54 Caption .................................................................... 19
Changes to Thermal Considerations Section .............................. 20
Added Figure 57 and Figure 58 ..................................................... 21
Changes to Power-Down Operation Section and Table 8 ......... 21
Changed Exposed Paddle Section to Exposed Pad Section ...... 23
Changes to Wideband Photodiode Preamp Section .................. 25
Change to Table 9 ............................................................................ 26
Changes to Active Low Pass Filter (LPF) Section ....................... 28
Updated Outline Dimensions ........................................................ 30
Changes to Ordering Guide ........................................................... 31
5/2016—Rev. B to Rev. C
Changed CP-8-2 to CP-8-13 ........................................ Throughout
Changes to Figure 1, Figure 2, and Figure 3 .................................. 1
Changes to Figure 5, Table 5, Figure 6, and Table 6 ...................... 6
Changes to Figure 7 and Table 7 ..................................................... 7
Updated Outline Dimensions ........................................................ 24
Changes to Ordering Guide ........................................................... 25
5/2013—Rev. A to Rev. B
Changes to Figure 3 .......................................................................... 1
Changes to Figure 7 .......................................................................... 7
Updated Outline Dimensions ........................................................ 24
Changes to Ordering Guide ........................................................... 25
3/2009—Rev. 0 to Rev. A
Added 8-Lead SOIC Package ............................................ Universal
Changes to Features Section and General Description Section .. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Figure 4 .......................................................................... 5
Changes to Figure 9, Figure 11, and Figure 12 .............................. 8
Changes to Figure 21, Figure 22, and Figure 24 .......................... 10
Changes to Figure 33 ...................................................................... 12
Added Figure 34; Renumbered Sequentially ............................... 12
Changes to Thermal Considerations Section and Power-Down
Operation Section ........................................................................... 15
Changes to Capacitive Feedback Section and Figure 46 ............ 16
Added Higher Frequency Attenuation Section, Figure 47,
Figure 48, and Figure 49; Renumbered Sequentially.................. 16
Updated Outline Dimensions ........................................................ 24
Changes to Ordering Guide ........................................................... 25
11/2008—Revision 0: Initial Version
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 4 of 31
GENERAL DESCRIPTION
The ADA4817-1 (single) and ADA4817-2 (dual) FastFET™ amplifiers
are unity-gain stable, ultrahigh speed, voltage feedback amplifiers
with FET inputs. These amplifiers were developed with the Analog
Devices, Inc., proprietary eXtra fast complementary bipolar
(XFCB) process, which allows the amplifiers to achieve ultralow
noise (4 nV/√Hz; 2.5 fA/√Hz) as well as very high input impedances.
With 1.3 pF of input capacitance, low noise (4 nV/√Hz), low offset
voltage (2 mV maximum), and 1050 MHz −3 dB bandwidth, the
ADA4817-1/ADA4817-2 are ideal for data acquisition front ends as
well as wideband transimpedance applications, such as photodiode
preamps.
With a wide supply voltage range from 5 V to 10 V and the ability
to operate on either single or dual supplies, the ADA4817-1/
ADA4817-2 are designed to work in a variety of applications inclu-
ding active filtering and analog-to-digital converter (ADC) driving.
The ADA4817-1 is available in a 3 mm × 3 mm, 8-lead LFCSP and
8-lead SOIC, and the ADA4817-2 is available in a 4 mm × 4 mm,
16-lead LFCSP. These packages feature a low distortion pinout
that improves second harmonic distortion and simplifies circuit
board layout. They also feature an exposed pad that provides a
low thermal resistance path to the printed circuit board (PCB).
The EPAD enables more efficient heat transfer and increases
reliability. These products are rated to work over the extended
industrial temperature range (−40°C to +105°C).
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 5 of 31
SPECIFICATIONS
±5 V OPERATION
TA = 25°C, +VS = 5 V, −V S = −5 V, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to ground, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT = 0.1 V p-p 1050 MHz
VOUT = 2 V p-p 200 MHz
VOUT = 0.1 V p-p, G = 2 390 MHz
Gain Bandwidth Product VOUT = 0.1 V p-p ≥410 MHz
Full Power Bandwidth VIN = 3.3 V p-p, G = 2 60 MHz
0.1 dB Flatness VOUT = 2 V p-p, RL = 100 Ω, G = 2 60 MHz
Slew Rate VOUT = 4 V step 870 V/µs
Settling Time to 0.1% VOUT = 2 V step, G = 2 9 ns
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion
f = 1 MHz
V
OUT
= 2 V p-p, R
L
= 1 kΩ
HD2 −113 dBc
HD3 −117 dBc
f = 10 MHz VOUT = 2 V p-p, RL = 1 kΩ
HD2 −90 dBc
HD3 −94 dBc
f = 50 MHz VOUT = 2 V p-p, RL = 1 kΩ
HD2 −64 dBc
HD3 −66 dBc
Input Voltage Noise f = 100 kHz 4 nV/√Hz
Input Current Noise f = 100 kHz 2.5 fA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.4 2 mV
TMIN to TMAX, SOIC 6 mV
T
MIN
to T
MAX
, LFCSP
4
mV
Input Offset Voltage Drift TMIN to TMAX, SOIC 25 80 µV/°C
TMIN to TMAX, LFCSP 10 50 µV/°C
Input Bias Current 2 20 pA
TMIN to TMAX 75 135 pA
Input Bias Offset Current 1 10 pA
TMIN to TMAX 110 pA
Open-Loop Gain 62 65 dB
INPUT CHARACTERISTICS
Input Resistance Common mode 500 GΩ
Input Capacitance Common mode 1.3 pF
Differential mode 0.1 pF
Input Common-Mode Voltage Range −VS to (+VS − 2.8) V
Common-Mode Rejection VCM = ±0.5 V −77 −90 dB
V
CM
= ±0.5 V, T
MIN
to T
MAX
−73
dB
VCM = −4.2 V to 2.2 V, TMIN to TMAX −65 dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = ±2.5 V, G = 2 8 ns
Output Voltage Swing
High RL = 100 Ω +VS − 1.5 +VS − 1.3 V
RL = 100 Ω, TMIN to TMAX +VS − 1.65 V
RL = 1 kΩ +VS − 1.1 +VS – 1 V
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 6 of 31
Parameter Test Conditions/Comments Min Typ Max Unit
RL = 1 kΩ, TMIN to TMAX +VS − 1.4 V
Low RL = 100 Ω −VS + 1.4 −VS + 1.5 V
RL = 100 Ω, TMIN to TMAX −VS + 1.65 V
RL = 1 kΩ −VS + 1 −VS + 1.1 V
R
L
= 1 kΩ, T
MIN
to T
MAX
−V
S
+ 1.2
V
Linear Output Current 1% output error 40 mA
Short-Circuit Current Sinking 100 mA
Sourcing 170 mA
POWER-DOWN
PD Pin Voltage Enabled, TMIN to TMAX >+VS − 0.9 V
Powered down, TMIN to TMAX <+VS − 3.5 V
Turn On Time 0.3 µs
Turn Off Time 1 µs
Input Leakage Current PD = +VS 0.3 3 µA
PD = −VS 34 61 µA
POWER SUPPLY
Operating Range 5 10 V
Quiescent Current per Amplifier 19 21 mA
Powered Down Quiescent Current 1.5 3 mA
Positive Power Supply Rejection +VS = 4.5 V to 5.5 V, −VS = −5 V −67 −72 dB
Negative Power Supply Rejection +VS = 5 V, −VS = −4.5 V to −5.5 V −67 −72 dB
5 V OPERATION
TA = 25°C, +VS = 3 V, −V S = −2 V, G = 1, RF = 348 Ω for G > 1, RL = 100 Ω to ground, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
V
OUT
= 0.1 V p-p
500
MHz
VOUT = 1 V p-p 160 MHz
VOUT = 0.1 V p-p, G = 2 280 MHz
Full Power Bandwidth VIN = 1 V p-p, G = 2 95 MHz
0.1 dB Flatness VOUT = 1 V p-p, G = 2 32 MHz
Slew Rate VOUT = 2 V step 320 V/µs
Settling Time to 0.1% VOUT = 1 V step, G = 2 11 Ns
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion
f = 1 MHz VOUT = 1 V p-p, RL = 1 kΩ dBc
HD2 −87 dBc
HD3 −88
f = 10 MHz VOUT = 1 V p-p, RL = 1 kΩ
HD2 −68 dBc
HD3
−66
dBc
f = 50 MHz VOUT = 1 V p-p, RL = 1 kΩ
HD2 −57 dBc
HD3 −55 dBc
Input Voltage Noise f = 100 kHz 4 nV/√Hz
Input Current Noise f = 100 kHz 2.5 fA/√Hz
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 7 of 31
Parameter Test Conditions/Comments Min Typ Max Unit
DC PERFORMANCE
Input Offset Voltage 0.5 2.3 mV
TMIN to TMAX, SOIC 6.5 mV
TMIN to TMAX, LFCSP 5 mV
Input Offset Voltage Drift
T
MIN
to T
MAX
, SOIC
25
75
µV/°C
TMIN to TMAX, LFCSP 10 45 µV/°C
Input Bias Current 2 20 pA
TMIN to TMAX 50 70 pA
Input Bias Offset Current 1 10 pA
TMIN to TMAX 65 pA
Open-Loop Gain 61 63 dB
INPUT CHARACTERISTICS
Input Resistance Common mode 500 GΩ
Input Capacitance
Common mode
1.3
pF
Differential mode 0.1 pF
Input Common-Mode Voltage Range −VS to (+VS − 2.9) V
Common-Mode Rejection VCM = ±0.25 V −72 −83 dB
VCM = ±0.3 V, TMIN to TMAX −70 dB
V
CM
= ±0.8 V, T
MIN
to T
MAX
−59
dB
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = ±1.25 V, G = 2 13 ns
Output Voltage Swing
High RL = 100 Ω +VS − 1.3 +VS − 1.2 V
RL = 100 Ω, TMIN to TMAX +VS − 1.4 V
RL = 1 kΩ +VS − 1.1 +VS − 1 V
RL = 1 kΩ, TMIN to TMAX +VS − 1.2 V
Low RL = 100 Ω −VS + 1 −VS + 1.1 V
RL = 100 Ω, TMIN to TMAX −VS + 1.2 V
RL = 1 kΩ −VS + 0.9 −VS + 1 V
RL = 1 kΩ, TMIN to TMAX −VS + 1.1 V
Linear Output Current 1% output error 20 mA
Short-Circuit Current Sinking 40 mA
sourcing
130
mA
POWER-DOWN
PD Pin Voltage Enabled, TMIN to TMAX >+VS − 0.9 V
Powered down, T
MIN
to T
MAX
<+V
S
− 3.5
V
Turn On Time 0.2 µs
Turn Off Time 0.7 µs
Input Leakage Current PD = +VS 0.2 3 µA
PD = −VS 31 53 µA
POWER SUPPLY
Operating Range 5 10 V
Quiescent Current per Amplifier 14 16 mA
Powered Down Quiescent Current
1.5
2.8
mA
Positive Power Supply Rejection +VS = 4.75 V to 5.25 V, −VS = 0 V −66 −71 dB
Negative Power Supply Rejection +VS = 5 V, −VS = −0.25 V to +0.25 V −63 −69 dB
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 8 of 31
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 10.6 V
Power Dissipation See Figure 4
Common-Mode Input Voltage Range −VS − 0.5 V to +VS + 0.5 V
Differential Input Voltage ±VS
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Table 4.
Package Type θJA θ
JC Unit
CP-8-13 94 29 °C/W
RD-8-1 79 29 °C/W
CP-16-20 64 14 °C/W
MAXIMUM SAFE POWER DISSIPATION
The maximum safe power dissipation for the ADA4817-1/
ADA4817-2 is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C (which is
the glass transition temperature), the properties of the plastic
change. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4817-1/
ADA4817-2. Exceeding a junction temperature of 150C for an
extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
die due to the ADA4817-1/ADA4817-2 drive at the output.
The quiescent power is the voltage between the supply pins
(VS) multiplied by the quiescent current (IS).
PD = Quiescent Power + (Total Drive Power − Load
Power) (1)
2
–
2
SOUT OUT
DSS
LL
VV V
PVI RR
(2)
Consider root mean square (rms) output voltages. If RL is
referenced to −VS, as in single-supply operation, the total drive
power is VS × IOUT. If the rms signal levels are indeterminate,
consider the worst-case scenario, when VOUT = VS/4 for RL to
midsupply.
2
/4
S
DSS
L
V
PVI R (3)
In single-supply operation with RL referenced to −VS, the worst-
case situation is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. More
metal directly in contact with the package leads and exposed
pad from metal traces, through holes, ground, and power planes
also reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
8-lead LFCSP (single 94°C/W), 8-lead SOIC (single 79°C/W),
and 16-lead LFCSP (dual 64°C/W) packages on JEDEC
standard 4-layer boards. θJA values are approximations.
3.5
0
–40
AMBIE NT TEMPERATURE (°C)
MAXIMUM POWE R DISSIPAT ION ( W)
3.0
2.5
2.0
1.5
1.0
0.5
–30 –20 –10 010 20 30 40 50 60 70 80 90 100
ADA4817-1, LFCSP
ADA4817-2, LF CS P
07756-008
ADA4817-1, S OI C
Figure 4. Maximum Safe Power Dissipation vs. Ambient Temperature for
a 4-Layer Board
ESD CAUTION
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 9 of 31
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
07756-005
NOTES
1. NI C = NO I NTERNAL CONNECTION.
2. EXPOSED PAD. CAN BE CO NNE CTED
TO GND, –VSPLANE, OR LEFT FLOATING.
3
–IN
4
+IN
1
PD
2FB
6NIC
5–VS
8+VS
7OUT
ADA4817-1
TOP VIEW
(No t t o Scal e)
Figure 5. ADA4817-1 Pin Configuration (8-Lead LFCSP)
Table 5. ADA4817-1 Pin Function Descriptions (8-Lead LFCSP)
Pin No. Mnemonic Description
1 PD Power-Down. Do not leave floating.
2 FB Feedback Pin.
3 −IN Inverting Input.
4 +IN Noninverting Input.
5 −VS Negative Supply.
6 NIC No Internal Connection.
7 OUT Output.
8 +VS Positive Supply.
EPAD Exposed Pad. Can be connected to GND, −VS plane, or left floating.
FB
–IN
+IN
–VS
PD
+VS
OUT
NIC
07756-006
1
2
3
4
8
7
6
5
NOTES
1. NI C = NO I NTERNAL CONNECTI ON.
2. EXPOSED PAD. CAN BE CO NNE CTED TO GND,
−VS PLANE, OR LEFT FLOATING.
ADA4817-1
TOP VIEW
(No t t o Scal e)
Figure 6. ADA4817-1 Pin Configuration (8-Lead SOIC)
Table 6. ADA4817-1 Pin Function Descriptions (8-Lead SOIC)
Pin No. Mnemonic Description
1 FB Feedback Pin.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 −VS Negative Supply.
5 NIC No Internal Connection.
6 OUT Output.
7 +VS Positive Supply.
8 PD Power-Down. Do not leave floating.
EPAD Exposed Pad. Can be connected to GND, −VS plane, or left floating.
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 10 of 31
07756-107
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
ADA4817-2
TOP VIEW
(No t t o Scal e)
–IN1
+IN1
NIC
–VS2
–VS1
OUT1
+VS1
PD1
FB1
NIC
+IN2
–IN2
OUT2
+VS2
PD2
FB2
NOTES
1. NI C = NO I NTERNAL CONNECTION.
2. EXPOSED PAD. CAN BE CO NNE CTED
TO GND, –VSPLANE, OR LEFT FLOATING.
Figure 7. ADA4817-2 Pin Configuration (16-Lead LFCSP)
Table 7. ADA4817-2 Pin Function Descriptions (16-Lead LFCSP)
Pin No. Mnemonic Description
1 −IN1 Inverting Input 1.
2 +IN1 Noninverting Input 1.
3, 11 NIC No Internal Connection.
4 −VS2 Negative Supply 2.
5 OUT2 Output 2.
6 +VS2 Positive Supply 2.
7 PD2 Power-Down 2. Do not leave floating.
8 FB2 Feedback Pin 2.
9 −IN2 Inverting Input 2.
10 +IN2 Noninverting Input 2.
12 −VS1 Negative Supply 1.
13 OUT1 Output 1.
14 +VS1 Positive Supply 1.
15 PD1 Power-Down 1. Do not leave floating.
16 FB1 Feedback Pin 1.
EPAD Exposed Pad. Can be connected to GND, −VS plane, or left floating.
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 11 of 31
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, G = 1, (RF = 348 Ω for G > 1), RL = 100 Ω to ground, small signal VOUT = 100 mV p-p, large signal VOUT = 2 V p-p,
unless otherwise noted.
6
–12
100k 10G
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
1M 10M 100M 1G
3
0
–3
–6
–9
07756-066
G=1,SINGLEG=1,DUAL
G = 2
G=5
Figure 8. Small Signal Frequency Response for Various Gains (LFCSP)
6
–12
100k 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
1M 10M 100M 1G
3
0
–3
–6
–9
V
S
= 10V, LFCSP
V
S
= 10V, SOIC
07756-007
V
S
=5V, LFCSP
V
S
= 5V, SOIC
Figure 9. Small Signal Frequency Response for Various Supplies
9
–9
100k 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
1M 10M 100M 1G
6
3
0
–3
–6
07756-068
C
L
=2.2pF
C
L
=6.6pF
C
L
=4.4pF
C
L
=0pF
G = 2
R
F
=274Ω
Figure 10. Small Signal Frequency Response for Various CL
–12
100k 10G
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
1M 10M 100M 1G
6
3
0
–3
–6
–9
07756-009
G = 2
G = 1, DUAL
G = 5
G=1,SINGLE
Figure 11. Large Signal Frequency Response for Various Gains
6
–12
100k 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
1M 10M 100M 1G
3
0
–3
–6
–9
V
S
= 10V
V
S
=5V
07756-010
V
OUT
= 1V p-p
Figure 12. Large Signal Frequency Response for Various Supplies
9
–9
100k 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
1M 10M 100M 1G
6
3
0
–3
–6
07756-011
R
F
= 274Ω
R
F
= 348Ω
R
F
= 200Ω
G = 2
Figure 13. Small Signal Frequency Response for Various RF
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 12 of 31
0.5
–0.5
100k 10G
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
1M 10M 100M 1G
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
07756-012
G=2,SS
G=2,LS
G = 1, LS
G=1,SS
Figure 14. 0.1 dB Flatness Frequency Response vs. Gain and Output Voltage
–20
–140
100k 100M
FREQUENCY (Hz)
DISTORTION (dBc)
–40
–60
–80
–100
–120
1M 10M
07756-014
HD2, R
L
= 100Ω
HD2, R
L
= 1kΩ
HD3, R
L
= 1kΩ
HD3, R
L
= 100Ω
Figure 15. Distortion vs. Frequency for Various Loads, VOUT = 2 V p-p
–
20
–140
100k 100M
FREQUENCY (Hz)
DISTORTION (dBc)
–40
–60
–80
–100
–120
1M 10M
07756-016
HD3, V
S
= 10V
HD3, V
S
= 5V
HD2, V
S
= 10V
HD2, V
S
= 5V
Figure 16. Distortion vs. Frequency for Various Supplies, G = 2, VOUT = 2 V p-p
6
3
0
–3
–6
–9
–12
100k 1M 10M 100M 1G 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
07756-036
T
A
= +25°C, SINGLE
T
A
= +25°C, DUAL
T
A
= –40°C, SINGLE
T
A
= –40°C, DUAL
T
A
= +105°C, SINGLE
T
A
= +105°C, DUAL
Figure 17. Small Signal Frequency Response vs. Temperature
–
20
–140
100k 100M
FREQUENCY (Hz)
DISTORTION (dBc)
–40
–60
–80
–100
–120
1M 10M
07756-013
HD2, V
S
= 10V HD3, V
S
= 10V
HD2, V
S
= 5V
HD3, V
S
= 5V
Figure 18. Distortion vs. Frequency for Various Supplies, VOUT = 2 V p-p
–
20
–140
06
OUTPUT VOLTAGE (V p-p)
DISTORTION (dBc)
–40
–60
–80
–100
–120
12345
07756-017
HD2, R
L
= 100Ω
f
C
= 1MHz
HD2, R
L
= 1kΩ
HD3, R
L
= 100Ω
HD3, R
L
= 1kΩ
Figure 19. Distortion vs. Output Voltage for Various Loads
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 13 of 31
0.075
0.050
0.025
0
–0.025
–0.050
–0.075
OUTPUT VOLTAGE (V)
TIME (5ns/DIV)
07756-022
SINGLE, SOIC
R
F
= 0Ω
R
L
= 100Ω
V
S
= ±5V
G = +1
DUAL, LFCSP
SINGLE, CSP
Figure 20. Small Signal Transient Response vs. Package
6
–6
TIME (10ns/DIV)
OUTPUT VOLTAGE (V)
4
2
0
–2
–4
2 × V
IN
07756-019
G = 2
V
OUT
Figure 21. Output Overdrive Recovery
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
OUTPUT VOLTAGE (V)
TIME (5ns/DIV)
07756-021
DUAL
SINGLE
DUAL, C
F
= 0.5pF
SINGLE, NO C
F
V
S
= 5V
G = 2
Figure 22. Small Signal Transient Response
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
OUTPUT VOLTAGE (V)
TIME (5ns/DIV)
07756-024
DUAL, LFCSP
R
F
= 0Ω
R
L
= 100Ω
V
S
= ±5V
G = +1
SINGLE,SOIC
SINGLE, CSP
Figure 23. Large Signal Transient Response vs. Package
0.5
0.4
0.3
0.2
0.1
0
–0.3
–0.2
–0.1
–0.4
–0.5
SETTLING TIME (%)
TIME (5ns/DIV)
07756-023
SETTLING TIME
Figure 24. 0.1% Short-Term Settling Time
0
–100
100k 1G
FREQUENCY (Hz)
PSRR (dB)
–10
–20
–30
–40
–50
–60
–70
–80
–90
1M 10M 100M
07756-032
–PSRR
+PSRR
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 14 of 31
–
20
–25
–30
–35
–40
–45
–50
–55
–60
–65
10k 100k 10M 1G
CMRR (dB)
FREQUENCY (Hz)
07756-029
Figure 26. Common-Mode Rejection Ratio (CMRR) vs. Frequency
100
0.01
100k 1G100M10M1M
OUTPUT IMPEDANCE ()
FREQUENCY (Hz)
10
1
0.1
07756-030
Figure 27. Output Impedance vs. Frequency
1000
1
10 100M
FREQUENCY (Hz)
INPUT VOLTAGE NOISE (nV/ Hz)
100 1k 10k 100k 1M 10M
10
100
07756-026
Figure 28. Input Voltage Noise vs. Frequency
24
22
20
18
16
14
12
10
–40 –20 0 20 40 60 80 100
QUIESCENT CURRENT (mA)
TEMPERATURE (°C)
07756-033
V
S
= ±5V
V
S
= +5V
Figure 29. Quiescent Current vs. Temperature for Various Supply Voltages
1.6
1.4
1.5
1.3
1.2
1.1
1.0
0.9
0.8
–40 –20 0 20 40 60 80 100
OUTPUT SATURATION VOLTAGE (V)
TEMPERATURE (°C)
07756-034
-
V
S
= ±5V
V
S
= +5V
–V
S
+ V
OUT
–V
S
+ V
OUT
+V
S
– V
OUT
+V
S
– V
OUT
R
L
= 100
Figure 30. Output Saturation Voltage vs. Temperature
07756-015
70
60
50
40
30
20
10
0
0
–45
–90
–135
–180–10
10k 100k 1M 10M 100M 1G
PHASE (Degrees)
OPEN-LOOP GAIN (dB)
FREQUENCY (Hz)
GAIN
PHASE
Figure 31. Open-Loop Gain and Phase vs. Frequency
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 15 of 31
0
5
10
15
20
25
30
35
40
–2.0
–1.8
–1.6
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
PERCENT OF AMPLIFIERS
OFFSET VOLTAGE (mV)
07756-400
VS= ±5V
Figure 32. Input Offset Voltage Histogram
(VS = ±5 V), LFCSP Only
0–4 –3 –2 –1 0 1 2 3 4
2
4
6
8
10
12
14
NUMBER O F HI TS
VOS (mV)
07756-335
VS= ±5V
TA = +105°C
TA = –40° C
Figure 33. Input Offset Voltage Histogram over Temperature
(VS = ±5 V), LFCSP Only
24
18
21
15
12
9
6
3
0–6 –4 –2 0
V
OS
(mV)
2 4 6
NUMBER O F HI TS
07756-334
V
S
= ±5V
T
A
= +105°C
T
A
= –40° C
Figure 34. Input Offset Voltage Histogram over Temperature
(VS = ±5 V), SOIC Only
0
5
10
15
20
25
30
35
40
–2.0
–1.8
–1.6
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
PERCENT OF AMPLIFIERS
OFFSET VOLTAGE (mV)
07756-401
VS= ±5V
Figure 35. Input Offset Voltage Histogram
(VS = ±5 V), SOIC Only
0–4 –3 –2 –1 0 1 2 3 4
2
4
6
8
10
12
14
NUMBER O F HI TS
VOS (mV)
07756-338
VS= 5V
TA = +105°C
TA = –40° C
Figure 36. Input Offset Voltage Histogram over Temperature
(VS = 5 V), LFCSP Only
24
18
21
15
12
9
6
3
0
–6 –4 –2 0
V
OS
(mV)
246
NUMBER O F HI TS
07756-337
V
S
= 5V
T
A
= +105°C
T
A
= –40° C
Figure 37. Input Offset Voltage Histogram over Temperature
(VS = 5 V), SOIC Only
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 16 of 31
–5
–4
–3
–2
–1
0
1
2
3
4
5
–60 –40 –20 020 40 60 80 100 120
OFFSET VOLTAGE (mV)
TEMPERATURE(°C)
V
S
= ±5V
SOIC
LFCSP
07756-340
Figure 38. Offset Voltage vs. Temperature
(VS = ±5 V)
0
1
2
3
4
5
6
7
8
9
10
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
NUMBER O F AMP LI FIE RS
INPUT OFFSET VOLTAGE DRIFT (µV/˚C)
LFCSP SOIC
07756-336
V
S
= ±5V
Figure 39. Input Offset Voltage Drift Histogram
(VS = ±5V)
30
20
25
15
10
5
0–70–80
07556-341
NUMBER O F AMP LI FIE RS
INPUT BI AS CURRE NT (pA)
–60 –50 –40 –30 –20 –10 010 20 30 40 50 60 70 80
VS= ±5V
TA = 105° C
TA = 25° C
Figure 40. Input Bias Current Histogram over Temperature
(VS = ±5 V)
–5
–4
–3
–2
–1
0
1
2
3
4
5
–60 –40 –20 020 40 60 80 100 120
OFFSET VOLTAGE (mV)
TEMPERATURE(°C)
V
S
= 5V
SOI
C
LFCSP
07756-343
Figure 41. Offset Voltage vs. Temperature
(VS = 5 V)
0
1
2
3
4
5
6
7
8
9
10
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
NUMBER O F AMP LI FIE RS
INPUT OFFSET VOLTAGE DRIFT (µV/˚C)
LFCSP SOIC
07756-339
V
S
= 5V
Figure 42. Input Offset Voltage Drift Histogram
(VS = 5 V)
30
20
25
15
10
5
0–70–80
07556-344
NUMBER O F AMP LI FIE RS
INPUT BI AS CURRE NT (pA)
–60 –50 –40 –30 –20 –10 010 20 30 40 50 60 70 80
VS= 5V
TA = 105° C
TA = 25° C
Figure 43. Input Bias Current Histogram over Temperature
(VS = 5 V)
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 17 of 31
–500
–400
–300
–200
–100
0
100
200
300
400
500
COMMON-MODE REJECTION RATIO (µV/V)
COMMON-MODE VOLTAGE (V)
07756-342
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
V
S
= ±5V
Figure 44. Common-Mode Rejection vs. Common-Mode Voltage,
VS = ±5 V
–1000
–600
–600
–400
–200
0
200
400
600
800
1000
–1.0 –0.8 –0.6 –0.4 –0.2 00.2 0.4 0.6 1.0
0.8
COMMON-MODE REJECTIONRATIO (µV/V)
COMMON-MODE VOLTAGE (V)
07756-345
V
S
=5V
Figure 45. Common-Mode Rejection vs. Common-Mode Voltage,
VS = 5 V
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 18 of 31
TEST CIRCUITS
The output feedback pins are used for ease of layout as shown in Figure 46 to Figure 51.
V
IN
V
OUT
0.1µF 0.1µF
0.1µF
10µF +V
S
–V
S
49.9Ω
R
L
+
10µF
+
07756-147
Figure 46. G = 1 Configuration
V
OUT
0.1µF
49.9Ω
+V
S
–V
S
R
L
10µF
+
AC
07756-145
Figure 47. Positive Power Supply Rejection
VIN
VOUT
0.1µF
0.1µF
10µF +VS
–VS
49.9Ω
RL
0.1µF
CL
+
10µF
+
RF
RSNUB
RG
07756-142
Figure 48. Capacitive Load Configuration
V
IN
V
OUT
0.1µF 0.1µF
0.1µF
10µF +V
S
–V
S
49.9Ω
R
L
+
10µF
+
R
F
R
G
07756-141
Figure 49. Noninverting Gain Configuration
0.1µF
V
OUT
+V
S
–V
S
R
L
10µF
+
AC
49.9Ω
07756-148
Figure 50. Negative Power Supply Rejection
V
IN
V
OUT
0.1µF 0.1µF
0.1µF
10µF +V
S
–V
S
1kΩ
1kΩ
1kΩ
1kΩ
53.6Ω
R
L
+
10µF
+
07756-146
Figure 51. Common-Mode Rejection
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 19 of 31
THEORY OF OPERATION
The ADA4817-1/ADA4817-2 are voltage feedback operational
amplifiers that combine new architecture for FET input operational
amplifiers with the eXFCB process from Analog Devices,
resulting in an outstanding combination of speed and low noise.
The innovative high speed FET input stage handles common-
mode signals from the negative supply to within 2.7 V of the
positive rail. This stage is combined with an H-bridge to attain an
870 V/μs slew rate and low distortion, in addition to 4 nV/√Hz
input voltage noise. The amplifier features a high speed output
stage capable of driving heavy loads sourcing and sinking up to
40 mA of linear current. Supply current and offset current are
laser trimmed for optimum performance. These specifications
make the ADA4817-1/ADA4817-2 a great choice for high speed
instrumentation and high resolution data acquisition systems.
Their low noise, picoampere input current, precision offset, and
high speed make them superb preamps for fast photo-diode
applications.
CLOSED-LOOP FREQUENCY RESPONSE
The ADA4817-1/ADA4817-2 are classic voltage feedback
amplifiers with an open-loop frequency response that can be
approximated as the integrator response shown in Figure 54. Basic
closed-loop frequency response for inverting and noninverting
configurations can be derived from the schematics shown in
Figure 52 and Figure 53.
R
F
A
V
OUT
R
G
V
IN
V
E
07756-044
Figure 52. Noninverting Configuration
RF
VE
A
VOUT
RG
VIN
07756-045
Figure 53. Inverting Configuration
NONINVERTING CLOSED-LOOP FREQUENCY
RESPONSE
Solving for the transfer function,
2
2
CROSSOVER G F
O
I F G CROSSOVER G
fRR
V
VRRS f R
(4)
where:
fCROSSOVER is the frequency where the open-loop gain of the
amplifier equals 0 dB.
VO is the output voltage.
VI is the input voltage.
At dc,
OFG
IG
VRR
VR
(5)
The closed-loop −3 dB frequency is
G
3dB CROSSOVER
FG
R
ff RR
(6)
INVERTING CLOSED-LOOP FREQUENCY RESPONSE
Solving for the transfer function,
2
2
CROSSOVER F
O
I F G CROSSOVER G
fR
V
VRRS f R
(7)
At dc
OF
IG
VR
VR
(8)
Solve for closed-loop −3 dB frequency by
3G
dB CROSSOVER
FG
R
ff RR
(9)
FREQUENCY (MHz)
80
60
0.1 1000
OPEN-LOOP GAIN (A) (dB)
1 10010
40
20
0
f
CROSSOVER
= 410MHz
A = (2π×
f
CROSSOVER
)/s
07756-046
Figure 54. Open-Loop Gain vs. Frequency
The closed-loop bandwidth is inversely proportional to the noise
gain of the op amp circuit, (RF + RG)/RG. This simple model is
accurate for noise gains above 2. The actual bandwidth of circuits
with noise gains at or below 2 is higher than those predicted
with this model due to the influence of other poles in the
frequency response of the real op amp.
Figure 55 shows the dc errors of the voltage feedback amplifier.
For both inverting and noninverting configurations,
VOUT (error) =
GF GF
bS bFOS
GG
RR RR
IR IRV
RR
(10)
where Ib is the bias current.
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 20 of 31
R
F
A
R
G
I
b
–
R
S
I
b
+
+V
OS
–
07756-047
V
OUT
V
IN
Figure 55. DC Errors of the Voltage Feedback Amplifier
The voltage error due to Ib+ and Ib− is minimized if RS = RF || RG
(though with the ADA4817-1/ADA4817-2 input currents in the
picoamp range, this is likely not a concern). To include common-
mode effects and power supply rejection effects, total VOS can be
modeled by
ΔΔ
SCM
OS OSnom
VV
VV PSR CMR (11)
where:
VOS is the offset voltage.
nom
OS
V is the offset voltage specified at nominal conditions.
ΔVS is the change in power supply from nominal conditions.
PSR is the power supply rejection.
ΔVCM is the change in common-mode voltage from nominal
conditions.
CMR is the common-mode rejection.
WIDEBAND OPERATION
The ADA4817-1/ADA4817-2 provides excellent performance as a
high speed buffer. Figure 52 shows the circuit used for wideband
characterization for high gains. The impedance at the summing
junction (RF || RG) forms a pole in the loop response of the
amplifier with the input capacitance of the amplifier of 1.3 pF.
This pole can cause peaking and ringing if its frequency is too
low. Feedback resistances of 100 Ω to 400 Ω are recommended
because they minimize the peaking and they do not degrade
the performance of the output stage. Peaking in the frequency
response can also be compensated for with a small feedback
capacitor (CF) in parallel with the feedback resistor, or a series
resistor in the noninverting input, as shown in Figure 56.
The distortion performance depends on the following variables:
The closed-loop gain of the application
Whether it is inverting or noninverting
Amplifier loading
Signal frequency and amplitude
Board layout
The best performance is usually obtained in the G + 1
configuration with no feedback resistance, big output
load resistors, and small board parasitic capacitances.
DRIVING CAPACITIVE LOADS
In general, high speed amplifiers have a difficult time driving
capacitive loads. This is particularly true in low closed-loop
gains, where the phase margin is the lowest.
The difficulty arises because the load capacitance, CL, forms a
pole with the output resistance, RO, of the amplifier. The pole can
be described by the following equation:
1
2π
P
OL
fRC (12)
If this pole occurs too close to the unity-gain crossover point,
the phase margin degrades. Degradation is due to the additional
phase loss associated with the pole.
Note that such capacitance introduces significant peaking in the
frequency response. Larger capacitance values can be driven but
must use a small series resistor, RSNUB, at the output of the amplifier,
as shown in Figure 56. Adding RSNUB creates a zero that cancels
the pole introduced by the load capacitance. Typical values for
RSNUB can range from 10 Ω to 50 Ω. The value is typically based on
the circuit requirements. Figure 56 also shows another way to
reduce the effect of the pole created by the capacitive load (CL) by
placing a capacitor (CF) in the feedback loop parallel to the
feedback resistor Typical capacitor values can range from 0.5 pF to
2 pF. Figure 59 shows the effect of adding a feedback capacitor to
the frequency response.
V
IN
V
OUT
0.1µF
0.1µF
10µF
+
V
S
–V
S
49.9Ω
R
L
0.1µF
C
L
+
10µF
+
R
F
R
SNUB
C
F
R
G
0
7756-143
Figure 56. RSNUB or CF Used to Reduce Peaking
THERMAL CONSIDERATIONS
With 10 V power supplies and 19 mA quiescent current, the
ADA4817-1/ADA4817-2 dissipate 190 mW with no load. This
implies that with the thermal resistances listed in Table 4, the
junction temperature is typically almost 25°C higher than the
ambient temperature. The ADA4817-1/ADA4817-2 can maintain
a constant bandwidth over temperature; therefore, an initial
ramp up of the current consumption during warm-up is
expected. VOS can change up to 0.3 mV due to warm-up effects
for an ADA4817-1/ADA4817-2 on ± 5 V. The input bias current
typically increases by a factor of 1.7 for every 10°C rise in
temperature.
Heavy loads increase power dissipation and raise the chip
junction temperature as described in the Absolute Maximum
Ratings section. Take care not to exceed the rated power
dissipation of the package.
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 21 of 31
POWER-DOWN OPERATION
The ADA4817-1/ADA4817-2 are equipped with separate power-
down pins (PD) for each amplifier that allow the user the ability
to reduce the quiescent supply current when an amplifier is
inactive from 19 mA to below 2 mA. The power-down
threshold levels are referenced to the +VS pin. The amplifier is
enabled when the PD pin voltage is within 0.9 V of the +VS
supply. The amplifier is disabled when the PD pin voltage is at
least 3.5 V from the +VS supply. Table 8 shows the required
thresholds for power-down with supplies of ±5 V and 3 V, −2 V,
over temperature. If the PD pin is not used, connect it to the
positive power supply to ensure proper start-up.
Table 8. PD Pin Control
Supply Voltages ±5 V +3 V, −2 V
Amplifier Enabled >4.1 V >2.1 V
Amplifier Disabled <1.5 V <−0.5 V
When the amplifier is powered down with the supplies of +3 V
and −2 V, t he PD pin needs to be driven below ground to ensure
the power-down. This may be a problem if a microcontroller is
being used to drive the PD pin. The circuit in Figure 57 can be
added to ensure that the required threshold is met.
+V
S
+V
S
–V
S
PD
Q1
2N3904
RF5
11kΩ RF6
20kΩ
RF4
3.6kΩ
RF1
3.6kΩ
PD_CONTROL
0V TO 3.3V
500ns TO 10µ s
+
RF3
1kΩ
Q2
2N3906
07756-358
Figure 57. Power-Down Circuit
The plot in Figure 58 shows that the PD pin is driven to the
positive rail when the microcontroller logic is high, and to the
negative rail when the microcontroller logic is low. The RF5 and
RF6 resistors must be chosen to be sufficiently high so that
minimal current is drawn by the circuit.
07756-359
CH1 2.00V
CH2 2.00V
CH3 200mV
M400ms
25.0kS/s 100k POINTS
A CH1 2.48V
1
2
3
T –516.000ms
IN
PD
OUT
Figure 58. Power-Down Operation
CAPACITIVE FEEDBACK
Due to package variations and pin to pin parasitics between the
single and the dual models, the ADA4817-2 has a little more
peaking then the ADA4817-1, especially at a gain of 2. The
recommended method to tame the peaking is to place a
feedback capacitor across the feedback resistor. Figure 59 shows
the small signal frequency response of the ADA4817-2 at a gain of
2 vs. CF. At first, no CF was used to show the peaking; but then
two other values of 0.5 pF and 1 pF were used to show how to
reduce the peaking or even eliminate it. If the power consumption
is a factor in the system, using a larger feedback capacitor is
acceptable as long as a feedback capacitor is used across it to
control the peaking, as shown in Figure 59.
However, if power consumption is not an issue, a lower value
feedback resistor, such as 200 Ω, does not require any additional
feedback capacitance to maintain flatness and lower peaking.
9
6
3
0
–3
–6
–91M 10M 100M 1G 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY ( Hz )
07756-049
RF = 348Ω
G = 2
VS = 10V
VOUT = 100mV p-p
RL = 100Ω
CF = 1pF
CF = 0.5pF NO CF
Figure 59. Small Signal Frequency Response vs. Feedback Capacitor
(ADA4817-2)
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 22 of 31
HIGHER FREQUENCY ATTENUATION
There is another package variation problem between the SOIC
and the LFCSP package. The SOIC package shows approximately
1 dB to 1.5 dB of additional peaking at a gain of 1, due to the
parasitic capacitances in the SOIC package, which is not
recommended for very high frequency parts that exceed 1 GHz. A
good approach to reduce the peaking is to place a resistor, RS, in
series with the noninverting input, which creates a first-order
pole formed by RS and CIN, the common-mode input
capacitance.
Figure 60 shows the higher frequency attenuation, which
reduces the peaking but also reduces the −3 dB bandwidth.
–9
–6
–3
0
3
6
1M 10M 100M 1G 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY ( Hz )
R
S
= 100Ω
R
S
= 75Ω
R
S
= 50Ω
R
S
= 0Ω
07756-247
R
L
= 100Ω
V
S
= ±5V
V
OUT
= 0.1V p-p
G = 1
Figure 60. Small Signal Frequency Response for Various RS (SOIC)
As shown in Figure 60, the peaking dropped by almost 2 dB
when RS = 0 Ω to RS = 100 Ω, and in return, the −3 dB bandwidth
dropped from 1 GHz to 700 MHz. To maintain the −3 dB
bandwidth and to reduce peaking, an RLC circuit is recommended
instead of RS, as shown in Figure 61.
L
10nH
R
120Ω
C
2pF
07756-248
Figure 61. RLC Circuit
The R in parallel to the series LC forms a notch that can be
shaped to compensate for the peaking produced by the amplifier.
The result is a smooth 1 GHz −3 dB bandwidth, 250 MHz 0.1 dB
flatness, and less than 1 dB of peaking. Place this circuit in the
path of the noninverting input when the ADA4817-1/ADA4817-2
are used at a gain of 1. The RLC values may need adjustment
depending on the source impedance and the flatness and
bandwidth required. Figure 62 shows the frequency response
after the RLC circuit is in place.
–9
–6
–3
0
3
6
1M 10M 100M 1G 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY ( Hz )
RLC
NO RL C
07756-249
RL = 100Ω
VS = 10V
VOUT = 100mV p-p
G = 1
Figure 62. Frequency Response with RLC Circuit
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 23 of 31
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
Laying out the PCB is usually the last step in the design process
and often proves to be one of the most critical. A good design can
be rendered useless because of poor layout. Because the
ADA4817-1/ADA4817-2 can operate into the radio frequency
(RF) spectrum, high frequency board layout considerations
must be taken into account. The PCB layout, signal routing, power
supply bypassing, and grounding all must be addressed to
ensure optimal performance.
SIGNAL ROUTING
The ADA4817-1/ADA4817-2 feature a low distortion pinout
with a dedicated feedback pin that allows a compact layout. The
dedicated feedback pin reduces the distance from the output to
the inverting input, which greatly simplifies the routing of the
feedback network.
When laying out the ADA4817-1/ADA4817-2 as a unity-gain
amplifier, it is recommended to place a short but wide trace
between the dedicated feedback pins and the inverting input to
the amplifier to minimize stray parasitic inductance.
To minimize parasitic inductances, use ground planes under
high frequency signal traces. However, remove the ground
plane from under the input and output pins to minimize the
formation of parasitic capacitors, which degrades phase margin.
Run signals are susceptible to noise pickup on the internal
layers of the PCB, which can provide maximum shielding.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, properly bypass the ADA4817-1/
ADA4817-2 power supply pins.
A parallel connection of capacitors from each of the power
supply pins to ground works best. Paralleling different values
and sizes of capacitors helps ensure that the power supply pins
see a low ac impedance across a wide band of frequencies,
which is important for minimizing the coupling of noise into
the amplifier. Starting directly at the power supply pins, place
the smallest value and sized component on the same side of the
board as the amplifier, and as close as possible to the amplifier,
and connect it to the ground plane. Repeat this process for the
next largest value capacitor. It is recommended to use a 0.1 µF
ceramic, 0508 case for the ADA4817-1/ADA4817-2.
The 0508 case offers low series inductance and excellent high
frequency performance. The 0.1 µF provides low impedance at
high frequencies. Place a 10 µF electrolytic capacitor in parallel
with the 0.1 µF. The 10 µF electrolytic capacitor provides low ac
impedance at low frequencies. Smaller values of electrolytic
capacitors can be used depending on the circuit requirements.
Additional smaller value capacitors help provide a low
impedance path for unwanted noise out to higher frequencies
but are not always necessary.
Placement of the capacitor returns (grounds) is also important.
Returning the grounds of the capacitor close to the amplifier
load is critical for distortion performance. Keeping the distance of
the capacitors short, but equal from the load, is optimal for
performance.
In some cases, bypassing between the two supplies can help to
improve PSRR and to maintain distortion performance in
crowded or difficult layouts. Bypassing is another option to
improve performance.
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduces the trace inductance. A series
inductance with the parallel capacitance can form a tank circuit,
which can introduce high frequency ringing at the output. This
additional inductance can also contribute to increased distortion
due to high frequency compression at the output. Minimize the
use of vias in the direct path to the amplifier power supply pins
because vias can introduce parasitic inductance, which can lead to
instability. When required to use vias, choose multiple large
diameter vias because this lowers the equivalent parasitic
inductance.
GROUNDING
The use of ground and power planes is encouraged as a method
of providing low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce stray
trace inductance and to provide a low thermal path for the
amplifier. Do not use ground and power planes under any of
the pins. The mounting pads and the ground or power planes
can form a parasitic capacitance at the input of the amplifier. Stray
capacitance on the inverting input and the feedback resistor form
a pole, which degrades the phase margin, leading to instability.
Excessive stray capacitance on the output also forms a pole,
which degrades phase margin.
EXPOSED PAD
The ADA4817-1/ADA4817-2 feature an exposed pad, which
lowers the thermal resistance by 25% compared to a standard
SOIC plastic package. The exposed pad of the ADA4817-1/
ADA4817-2 floats internally, which provides the maximum
flexibility and ease of use. It can be connected to the ground plane
or to the negative power supply plane. In cases where thermal
heating is not an issue, the exposed pad can be left floating.
The use of thermal vias or heat pipes can also be incorporated
into the design of the mounting pad for the exposed pad. These
additional vias help to lower the overall junction to ambient
temperature (θJA). Using a heavier weight copper on the surface
to which the exposed paddle of the amplifier is soldered can
greatly reduce the overall thermal resistance seen by the
ADA4817-1/ADA4817-2.
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 24 of 31
LEAKAGE CURRENTS
Poor PCB layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the ADA4817-1/ADA4817-2. Any
voltage differential between the inputs and nearby runs sets up
leakage currents through the PCB insulator, for example, 1 V/
100 GΩ = 10 pA. Similarly, any contaminants, such as skin oils
on the board, can create significant leakage. To reduce leakage
significantly, put a guard ring (shield) around the inputs and
input leads that are driven to the same voltage potential as the
inputs. This way there is no voltage potential between the inputs
and surrounding area to set up any leakage currents. For the
guard ring to be completely effective, it must be driven by a
relatively low impedance source and it must completely surround
the input leads on all sides (above and below) when using a
multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring helps to
reduce the absorption. In addition, low absorption materials,
such as Teflon® or ceramic, can be necessary in some instances.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can
be sensitive to parasitic capacitance between the inputs and
ground. A few picofarads of capacitance reduces the input
impedance at high frequencies, in turn increasing the gain of
the amplifier, causing peaking of the frequency response or
even oscillations if severe enough. It is recommended to place
the external passive components connected to the input pins
as close as possible to the inputs to avoid parasitic capacitance.
The ground and power planes must be kept at a small distance
from the input pins on all layers of the board.
INPUT-TO-INPUT/OUTPUT COUPLING
To minimize capacitive coupling between the inputs and outputs,
ensure that the output signal traces are not parallel with the
inputs. In addition, ensure that the input traces are not close to
each other. A minimum of 7 mils between the two inputs is
recommended.
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 25 of 31
APPLICATIONS INFORMATION
LOW DISTORTION PINOUT
The ADA4817-1/ADA4817-2 feature a low distortion pinout
from Analog Devices. The new pinout provides two advantages
over the traditional pinout. The first advantage is improved
second harmonic distortion performance, which is accomplished
by the physical separation of the noninverting input pin and the
negative power supply pin. The second advantage is the
simplification of the layout due to the dedicated feedback pin and
easy routing of the gain set resistor back to the inverting input
pin. This pinout allows a compact layout, which helps to
minimize parasitics and increase stability.
The designer does not need to use the dedicated feedback pin to
provide feedback for the ADA4817-1/ADA4817-2. The output
pin of the ADA4817-1/ADA4817-2 can still be used to provide
feedback to the inverting input of the ADA4817-1/ADA4817-2.
WIDEBAND PHOTODIODE PREAMP
The wide bandwidth and low noise of the ADA4817-1/
ADA4817-2 make it an ideal choice for transimpedance amplifiers,
such as those used for signal conditioning with high speed photo-
diodes. Figure 63 shows a current to voltage converter with an
electrical model of a photodiode. The basic transfer function is
1
PHOTO F
OUT
FF
IR
VsC R (13)
where:
IPHOTO is the output current of the photodiode.
RF and CF are the parallel combination that sets the signal
bandwidth.
R
SH
= 10
11
Ω
R
F
C
F
C
M
C
M
C
D
C
S
V
B
I
PHOTO
07756-048
V
OUT
Figure 63. Wideband Photodiode Preamp
The stable bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product of the amplifier, and the total
capacitance at the summing junction of the amplifier, including the
photodiode capacitance (CS) and the amplifier input capacitance.
RF and the total capacitance produce a pole in the loop
transmission of the amplifier that can result in peaking and
instability. Adding CF creates a zero in the loop transmission
that compensates for the effect of the pole and reduces the
signal bandwidth. It can be shown that the signal bandwidth
obtained with a 45° phase margin (f(45)) is defined by
(45) 2( )
CR
FSMD
f
fRCCC
(14)
where:
fCR is the amplifier crossover frequency.
RF is the feedback resistor.
CS is the source capacitance including the photodiode and the
board parasitic.
CM is the common-mode capacitance of the amplifier.
CD is the differential capacitance of the amplifier.
The CF value that produces f(45) is shown to be
2
SMD
F
FCR
CC C
CRf
(15)
The frequency response shows less peaking if larger CF values
are used.
Figure 64 shows the preamplifier output noise over frequency.
VEN (C
F
+ C
S
+ C
M
+ C
D
)/C
F
VOLTAGE NOISE (nV/ Hz)
FREQUENCY (Hz)
NOISE DUE TO AMPLIFIER
VEN
f
2
f
3
f
1
R
F
NOISE
f
1
= 1
2R
F
(C
F
+ C
S
+ C
M
+ C
D
)
f
2
= 1
2R
F
C
F
f
3
=
f
CR
(C
F
+ C
S
+ C
M
+ C
D
)/C
F
07756-043
Figure 64. Photodiode Voltage Noise Contributions
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 26 of 31
45
40
35
30
25
20
15
10
5
0
–5
0.1 1 10 100 1000
MAGNITUDE (dB)
FREQUENCY (MHz)
07756-051
G = 63V/V
RL = 100Ω
VS = 10V
VOUT = 6V p-p
Figure 65. Photodiode Preamp Frequency Response
The pole in the loop transmission translates to a zero in the
noise gain of the amplifier, leading to an amplification of the
input voltage noise over frequency.
The loop transmission zero introduced by CF limits the
amplification. The noise gain bandwidth extends past the pre-
amp signal bandwidth and is eventually rolled off by the decreasing
loop gain of the amplifier. The current equivalent noise from the
inverting terminal is typically negligible for most applications.
The innovative architecture used in the ADA4817-1/ADA4817-2
makes balancing both inputs unnecessary, as opposed to traditional
FET input amplifiers. Therefore, minimizing the impedance
seen from the noninverting terminal to ground at all frequencies is
critical for optimal noise performance.
Integrating the square of the output voltage noise spectral
density over frequency and then taking the square root allows
the user to obtain the total rms output noise of the preamp.
Table 9 summarizes approximations for the amplifier and
feedback and source resistances. Noise components for an
example preamp with RF = 50 kΩ, CS = 30 pF, and CF = 0.5 pF
(bandwidth of about 6.4 MHz) are also listed. VEN is the
equivalent voltage noise and IEN is the equivalent current
noise.
Table 9. RMS Noise Contributions of Photodiode Preamp
Contributor Expression RMS Noise with RF = 50 kΩ, CS = 30 pF, CF = 0.5 pF
RF
2
41.57
F
kT R f 94 μV
VEN Amp
31.57
SMDF
F
CC C C
VEN f
C
777.5 μV
IEN Amp
21.57
F
IEN R f 0.4 μV
Total 783 μV
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 27 of 31
HIGH SPEED JFET INPUT INSTRUMENTATION
AMPLIFIER
Figure 66 shows an example of a high speed instrumentation
amplifier with a high input impedance using the ADA4817-1/
ADA4817-2. The dc transfer function is
2
1F
OUT N P
G
R
VVV R (16)
For G = 1, it is recommended that the feedback resistors for the
two preamps be set to 0 Ω and the gain resistor be open.
The system bandwidth for G = 1 is 400 MHz. For gains higher
than 2, the bandwidth is set by the preamp, and it can be
approximated by
In-amp−3 dB = (fCR × RG)/(2 × RF)
The match of resistor ratios, R1:R2 to R3:R4, primarily determine
the common-mode rejection of the in-amp and it is estimated by
12
112
O
CM
V
V (17)
The summing junction impedance for the preamps is equal
to RF || 0.5(RG). Keep this value relatively low to improve the
bandwidth response like in the previous example.
V
CC
V
EE
10µF0.1µF
10µF0.1µF
R
S1
V
N
R2
350Ω
V
P
ADA4817-1 V
O
R
G
V
CC
V
EE
V
CC
V
EE
R4
350Ω
R
S2
10µF0.1µF
10µF0.1µF
R1
350Ω
R3
350Ω
R
F
= 500Ω
R
F
= 500Ω
10µF0.1µF
10µF0.1µF
07756-050
ADA4817-2
U1
ADA4817-2
U2
Figure 66. High Speed Instrumentation Amplifier
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 28 of 31
ACTIVE LOW-PASS FILTER (LPF)
Active low-pass filters are used in many applications such as
antialiasing filters and high frequency communication
intermediate frequency (IF) strips.
With a 410 MHz gain bandwidth product and high slew rate,
the ADA4817-1/ADA4817-2 is an ideal candidate for active
filters. Moreover, thanks to the low input bias current provided
by the FET stage, the ADA4817-1/ADA4817-2 eliminate any dc
errors. Figure 67 shows the frequency response of 90 MHz and
45 MHz LPFs. In addition to the bandwidth requirements, the slew
rate must be capable of supporting the full power bandwidth of the
filter. In this case, a 90 MHz bandwidth with a 2 V p-p output
swing requires at least 870 V/μs. This performance is achievable
at 90 MHz only because of the wide bandwidth and high slew
rate of the ADA4817-1/ADA4817-2.
The circuit shown in Figure 68 is a 4-pole, Sallen-Key LPF. The
filter comprises two identical cascaded Sallen-Key LPF sections,
each with a fixed gain of G = 2. The net gain of the filter is equal
to G = 4 or 12 dB. The actual gain shown in Figure 67 is 12 dB.
This gain does not take into account the output voltage being
divided in half by the series matching termination resistor, RT,
and the load resistor.
Setting the resistors equal to each other greatly simplifies the
design equations for the Sallen-Key filter. To achieve 90 MHz,
set the R value to 182 Ω. However, if the R value is doubled, the
corner frequency is cut in half to 45 MHz, which is a
straightforward approach to tune the filter by multiplying the R
value (182 Ω) by the ratio of 90 MHz and the new corner
frequency in megahertz. Figure 67 shows the output of each stage
of the filter and the two different filters corresponding to R =
182 Ω and R = 365 Ω. It is not recommended to increase the
corner frequency beyond 90 MHz due to bandwidth and slew
rate limitations, unless unity-gain stages are acceptable.
Resistor values are kept low for minimal noise contribution,
offset voltage, and optimal frequency response. Due to the low
capacitance values used in the filter circuit, the PCB layout and
minimization of parasitics is critical. A few picofarads can detune
the corner frequency, fC, of the filter. The capacitor values
shown in Figure 68 actually incorporate some stray PCB
capacitance.
Capacitor selection is critical for optimal filter performance.
Capacitors with low temperature coefficients, such as NPO
ceramic capacitors and silver mica, are good choices for filter
elements.
15
–42
100k 1G
FREQUENCY (Hz)
MAGNITUDE (dB)
12
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
1M 10M 100M
07756-062
OUT2, f = 90MHz
OUT1, f = 90MHz
OUT1, f = 45MHz
OUT2, f = 45MHz
Figure 67. Low-Pass Filter Response
U1
C1
3.9pF
C2
5.6pF
R
R
T
49.9Ω
R
R1
348Ω
R
R2
348Ω
R
T
49.9Ω
+IN1
–5V
+5V
0.1µF
0.1µF
10µF
10µF
U2
C3
3.9pF
C4
5.6pF
R
R3
348Ω
R4
348Ω
–5V
+5V
0.1µF
0.1µF
10µF
10µF
OUT2
07756-054
OUT1
Figure 68. 4-Pole, Sallen-Key LPF (ADA4817-2)
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 29 of 31
0.15
–0.15 TIME (5ns/DIV)
VOLTAGE (V)
0.10
0.05
0
–0.05
–0.10
45MHz
90MHz
07756-063
Figure 69. Small Signal Transient Response (Low-Pass Filter)
1.2
–1.2 TIME (5ns/DIV)
VOLTAGE (V)
0.8
0.4
0
–0.4
–0.8
45MHz
90MHz
07756-064
Figure 70. Large Signal Transient Response (Low-Pass Filter)
ADA4817-1/ADA4817-2 Data Sheet
Rev. F | Page 30 of 31
OUTLINE DIMENSIONS
8
1
5
4
0.30
0.25
0.20
PIN 1 INDEX
AREA
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 M AX
0.02 NO M
0.50
BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFIGURAT IO N AND
FUNCTION DES CRI P TI ONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-229- WEED- 4
TOP VI EW BOTTOM VIEW
SIDE VIEW
PKG-003886
02-10-2017-A
SEATING
PLANE
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 71. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
COMPLIANT TO JEDE C S TANDARDS MS-012-AA
06-02-2011-B
1.27
0.40
1.75
1.35
2.29
2.29
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 M AX
0.05 NO M
3.81 REF
0.25
0.17
8°
0°
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
14
5
1.27 BSC
SEATING
PLANE
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFIGURAT IO N AND
FUNCTION DES CRI P TI ONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VIEW
0.51
0.31
1.65
1.25
Figure 72. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP]
(RD-8-1)
Dimensions shown in millimeters
Data Sheet ADA4817-1/ADA4817-2
Rev. F | Page 31 of 31
*COMPLIANT
TO
JEDEC S TANDARDS M O-220 - WG GC-3
WITH EXCEPTIO N TO T HE EXPOSED PAD.
1
0.65
BSC
16
5
8
9
12
13
4
4.10
4.00 SQ
3.90
0.50
0.40
0.30
0.80
0.75
0.70 0.05 M A X
0.02 NOM
0.20 RE F
0.25 MI N
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
*2.40
2.35 SQ
2.30
03-30-2017-B
BO T TOM VIEW
TOP VIEW
SIDE VIEW
EXPOSED
PAD
PKG-004024
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PRO P ER CONNE CTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT IO N AND
FUNCTION DES CRIPT IO NS
SECT IO N OF THI S DATA SHE ET.
Figure 73.16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature
Range Package Description
Package
Option
Ordering
Quantity
Marking
Code
ADA4817-1ACPZ-RL −40°C to +105°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 5000 H1F
ADA4817-1ACPZ-R7 −40°C to +105°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 1500 H1F
ADA4817-1ARDZ −40°C to +105°C 8-Lead Standard Small Outline Package with Exposed Pad RD-8-1 1
ADA4817-1ARDZ-RL −40°C to +105°C 8-Lead Standard Small Outline Package with Exposed Pad RD-8-1 2500
ADA4817-1ARDZ-R7 −40°C to +105°C 8-Lead Standard Small Outline Package with Exposed Pad RD-8-1 1000
ADA4817-2ACPZ-RL −40°C to +105°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-20 5000
ADA4817-2ACPZ-R7 −40°C to +105°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-20 1500
ADA4817-2ACP-EBZ Evaluation Board for 16-Lead LFCSP
1 Z = RoHS Compliant Part.
©2008–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07756-0-6/18(F)
