500DBAC156M250ABF - Silicon Labs

Si500D

DIFFERENTIAL OUTPUT SILICON OSCILLATOR

Features

Specifications

Quartz-free, MEMS-free, and PLL-free all-silicon

oscillator

Any output frequencies from 0.9 to 200 MHz

Short lead times

Excellent temperature stability (±20 ppm)

Highly reliable startup and operation

High immunity to shock and vibration

Low jitter: <1.5 ps rms

0 to 85 °C operation includes 10-year aging in hot

environments

Footprint compatible with industry-

standard 3.2 x 5.0 mm XOs

CMOS, SSTL, LVPECL, LVDS, and HCSL

versions avail abl e

Driver stopped, tri-state, or powerdown

operation

RoHS compliant

1.8, 2.5, or 3.3 V options

Low power

More than 10x better fit rate than

competing crystal solutions

Parameters Condition Min Typ Max Units

Frequency Range 0.9 — 200 MHz

Frequency Stability

Temperature stability,

0 to +70 °C — ±10 — ppm

Temperature stability,

0 to +85 °C — ±20 — ppm

Total stability,

0 to +70 °C operation1— — ±150 ppm

Total stability,

0 to +85 °C operation2— — ±250 ppm

Operating Temperature Commercial 0 — 70 °C

Extended commercial 0 — 85 °C

Storage Temperature –55 — +125 °C

Supply Voltage 1.8 V option 1.71 — 1.98 V

2.5 V option 2.25 — 2.75 V

3.3 V option 2.97 — 3.63 V

Notes:

1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,

first-year aging at 25 °C, shock, vibration, and one solder reflow.

2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,

ten-year aging at 85 °C, shock, vibration, and one solder reflow.

3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding

output clock termination recommendations.

4. VTT = .5 x VDD.

5. VTT = .45 x VDD.

Si500D

2 Rev. 1.1

Supply Current

LVPECL — 34.0 36.0 mA

Low Power LVPECL — 19.3 22.2 mA

LVDS — 14.9 16.5 mA

HCSL — 25.3 29.3 mA

Diff erential CMOS(3.3 V option,

10 pF on each output, 200 MHz) —3336mA

Differential CMOS(3.3 V option,

1 pFon each output, 40 MHz) —16—mA

Differential SSTL-3.3 — 24.5 27.7 mA

Differential SSTL-2.5 — 24.3 26.7 mA

Differential SSTL-1.8 — 22.2 25 mA

Tri-State — 9.7 10.7 mA

Powerdown — 1.0 1.9 mA

Output Symmetry VDIFF = 0 46 – 13 ns/TCLK — 54 + 13 ns/TCLK %

Rise and Fall Times (20/80%)3LVPECL/LVDS — — 460 ps

HCSL/Differential SSTL — — 800 ps

Differential CMOS, 15 pF, >80 MHz — 1.1 1.6 ns

LVPECL Output Option

(DC coupling, 50  to VDD – 2.0 V)3Mid-level VDD – 1.5 — VDD – 1.34 V

Diff swing .720 — .880 VPK

Low Power LVPECL Output Option

(AC coupling, 100  Differential

Load)3

Mid-level — N/A — V

Diff swing .68 — .95 VPK

LVDS Output Option (2.5/3.3 V)

(RTERM = 100  diff)3Mid-level 1.15 — 1.26 V

Diff swing 0.25 — 0.45 VPK

LVDS Output Option (1.8 V)

(RTERM = 100  diff)3Mid-level 0.85 — 0.96 V

Diff swing 0.25 — 0.45 VPK

HCSL Output Option3Mid-level 0.35 — 0.425 V

Diff swing 0.65 — 0.82 VPK

DC termination per pad 45 — 55 

CMOS Output Voltage3 VOH, sourcing 9 mA VDD –0.6 — — V

VOL, sinking 9 mA — — 0.6 V

SSTL-1.8 Outp ut Volta ge 4VOH VTT + 0.375 — — V

VOL ——V

TT – 0.375

SSTL-2.5 Outp ut Volta ge 4VOH VTT + 0.48 — — V

VOL ——V

TT – 0.48

SSTL-3.3 Outp ut Volta ge 5VOH VTT + 0.48 — — V

VOL ——V

TT – 0.48

Powerup Time From time VDD crosses min spec

supply ——2ms

OE Deassertion to Clk Stop — — 250 + 3 x TCLK ns

Return from Output Driver Stopped

Mode — — 250 + 3 x TCLK ns

Return From Tri-State Time — — 12 + 3 x TCLK µs

Parameters Condition Min Typ Max Units

Notes:

1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,

first-year aging at 25 °C, shock, vibration, and one solder reflow.

2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,

ten-year aging at 85 °C, shock, vibration, and one solder reflow.

3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding

output clock termination recommen dations.

4. VTT = .5 x VDD.

5. VTT = .45 x VDD.

Si500D

Rev. 1.1 3

Return From Powerdown Time — — 2 ms

Period Jitt er (1-sigma) Non-CMOS — 1 2 ps

RMS

CMOS, CL=7pF — 1 3 ps

RMS

Integrated Phase Ji tter

1.0 MHz – min(20 MHz,

0.4 x FOUT),non-CMOS —0.61

RMS

1.0 MHz – min(20 MHz,

0.4 x FOUT),CMOS format —0.71.5

RMS

Parameters Condition Min Typ Max Units

Notes:

1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,

first-year aging at 25 °C, shock, vibration, and one solder reflow.

2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,

ten-year aging at 85 °C, shock, vibration, and one solder reflow.

3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding

output clock termination recommen dations.

4. VTT = .5 x VDD.

5. VTT = .45 x VDD.

Si500D

4 Rev. 1.1

Package Specifications

Figure 1. Recommended Land Pattern Figure 2. Top Mark

Table 1. Package Diagram Dimensions (mm)

Dimension Min Nom Max Dimension Min Nom Max

A 0.80 0.85 0.90 L1 0.00 0.05 0.10

A1 0.00 0.03 0.05 aaa — — 0.10

b 0.59 0.64 0.69 bbb — — 0.10

D 3.20 BSC. ccc — — 0.08

e 1.27 BSC. ddd — — 0.10

E 4.00 BSC. eee — — 0.05

L 0.95 1.00 1.05

Table 2. Pad Connections

1OE

2NC—Make no external

connection to this pin

3GND

4 Output

5 Complementary Output

6VDD

Dimension (mm)

C1 2.70

E 1.27

X1 0.75

Y1 1.55

Table 3. Tri-State/Powerdown/Driver Stopped

Function on OE (3rd Option Code)

AB C D E F

Open Active Active Active Active Active Active

Level Active Tri-

State Active Power-

down Active Driver

Stopped

Level Tri-

State Active Power-

down Active Driver

Stopped Active

0CCCCC

TTTTTTYY

0 = Si500

CCCCC = mark code

TTTTTT = assembly manufacturing code

YY = year

WW = work week

Si500D

Rev. 1.1 5

Environmental Compliance

Ordering Information

The Si500D supports a variety of options including frequency, output format, supply voltage, and tri-

state/powerdown. Specific device configurations are programmed into the Si500D at time of shipment.

Configurations are specified using the figure below. Silicon Labs provides a web-based part number utility that can

be used to simplify part number configuration. Refer to www.silabs.com/SiliconXOPartnumber to access this t ool.

The Si500D XO series is supplied in a ROHS-compliant, Pb-free, 6-pad, 3.2 x 4.0 mm package. Tape and reel

packaging is available as an ordering option.

Parameter Conditions/Test Method

Mechanical Shock MIL-STD-883, Method 2002.4

Mechanical Vibration MIL-STD-883, Method 2007.3 A

Resistance to Soldering Heat MIL-STD-202, 260 C° for 8 seconds

Solderability MIL-STD-883, Method 2003.8

Damp Heat IEC 68-2-3

Moisture Sensitivity Level J-STD-020, MSL 3

500D X X

Si500

Differential

Oscillator

VDD

3.3

2.5

1.8

Format

LVPECL

Low Power LVPECL

LVDS

HCSL

Dual Output CMOS

Differential CMOS

Dual Output SSTL

Differential SSTL

LVPECL

Low Power LVPECL

LVDS

HCSL

Dual Output CMOS

Differential CMOS

Dual Output SSTL

Differential SSTL

LVDS

HCSL

Dual Output CMOS

Differential CMOS

Dual Output SSTL

Differential SSTL

1st Option Code

2nd Option Code

Stability (ppm, max)

XXXMXXXX A C X R

Frequency

xMxxxxx: fOUT < 10 MHz

xxMxxxx: 10 MHz < fOUT < 100 MHz

xxxMxxx: fOUT > 100 MHz

R = Tape & Reel

Blank = Cut-T ape

Product R evi sion = C

Package

A 3.2 x 4 .0 mm SMD

3rd Optio n Code

Tri-State/Powerdown/

Output Driver Stopped

OE active high/tristate

OE active low/tristate

OE active high/powerdown

OE active low/powerdown

OE active high/driver stopped

OE active low/driver stopped

Oper. Temp Range

F 0 to 70 °C

*H 0 to 85 °C

A ±150

B ±250

*Note: Only +250 p pm is supported.

Si500D

6 Rev. 1.1

DOCUMENT CHANGE LIST

Revision 0.2 to Revision 0.3

Revision B to Revision C updated in Ordering Information

0 to 85 C° Operating Temperature Range option added

Revision 0.3 to Revision 1.0

Clarified SSTL specifications.

Revised Differential CMOS supply current values.

Clarified Differential CMOS supply current loading

conditions.

Revision 1.0 to Revision 1.1

Updated Ordering information for ±250 ppm from 0 to

+85 °C.

Updated jitter from 1.5 ps to 1.5 ps rms.

Updated operating temperature to include extended

commercial at 0 to +85 °C.

Updated features to include LVPECL, LVDS, and HCSL.

Si500D

Rev. 1.1 7

NOTES:

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers

using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific

device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories

reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy

or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply

or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific

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