MTB75N05HDT4 - ON Semiconductor

August, 2006 − Rev. 7

1Publication Order Number:

MTB75N05HD/D

MTB75N05HD

Preferred Device

Power MOSFET

75 Amps, 50 Volts

N−Channel D2PAK

This Power MOSFET is designed to withstand high energy in the

avalanche and commutation modes. The energy efficient design also

offers a drain−to−source diode with a fast recovery time. Designed for

low voltage, high speed switching applications in power supplies,

converters and PWM motor controls, these devices are particularly

well suited for bridge circuits where diode speed and commutating

safe operating areas are critical and offer additional safety margin

against unexpected voltage transients.

•Avalanche Energy Specified

•Source−to−Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

•Diode is Characterized for Use in Bridge Circuits

•IDSS and VDS(on) Specified at Elevated Temperature

•Short Heatsink Tab Manufactured − Not Sheared

•Specially Designed Leadframe for Maximum Power Dissipation

wThese devices are available in Pb−free package(s). Specifications herein

apply to both standard and Pb−free devices. Please see our website at

www.onsemi.com for specific Pb−free orderable part numbers, or

contact your local ON Semiconductor sales office or representative.

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain−to−Source Voltage VDSS 50 Volts

Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 50

Gate−to−Source Voltage − Continuous VGS ±20

Drain Current − Continuous

Drain Current − Continuous @ 100°C

Drain Current − Single Pulse (tp ≤ 10 μs)

IDM

225

Amps

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ TA = 25°C

(minimum footprint, FR−4 board)

PD125

1.0

2.5

Watts

W/°C

Watts

Operating and Storage Temperature

Range

TJ, Tstg −55 to

150

°C

Single Pulse Drain−to−Source Avalanche

Energy − Starting TJ = 25°C

(VDD = 25 V, VGS = 10 V, Peak

IL = 75 A, L = 0.177 mH, RG = 25 Ω)

EAS 500 mJ

Thermal Resistance

− Junction to Case

− Junction to Ambient

− Junction to Ambient (minimum foot-

print, FR−4 board)

RθJC

RθJA

1.0

62.5

°C/W

Maximum Temperature for Soldering

Purposes, 1/8″ from case for 10 s

TL260 °C

MTB75N05HD

YWW

MARKING DIAGRAM

& PIN ASSIGNMENT

MARKING DIAGRAM

& PIN ASSIGNMENT

Gate

Drain

Source

75 AMPERES

50 VOLTS

RDS(on) = 9.5 mΩ

Device Package Shipping

ORDERING INFORMATION

MTB75N05HD D2PAK 50 Units/Rail

D2PAK

CASE 418B

STYLE 2

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N−Channel

MTB75N05HD = Device Code

Y = Year

WW = Work Week

MTB75N05HDT4 D2PAK 800/Tape & Reel

Preferred devices are recommended choices for future use

and best overall value.

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ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Cpk ≥ 2) (Note 2)

(VGS = 0, ID = 250 μAdc)

Temperature Coefficient (Positive)

V(BR)DSS

−

54.9

−

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 50 V, VGS = 0)

(VDS = 50 V, VGS = 0, TJ = 125°C)

IDSS

−

100

μAdc

Gate−Body Leakage Current

(VGS = ±20 Vdc, VDS = 0)

IGSS

− − 100

nAdc

ON CHARACTERISTICS (Note 1)

Gate Threshold Voltage (Cpk ≥ 1.5) (Note 2)

(VDS = VGS, ID = 250 μAdc)

Threshold Temperature Coefficient (Negative)

VGS(th)

2.0

−

6.3

4.0

−

Vdc

mV/°C

Static Drain−to−Source On−Resistance (Note 3) (Cpk ≥ 3.0) (Note 2)

(VGS = 10 Vdc, ID = 20 Adc)

RDS(on)

−7.0 9.5

mΩ

Drain−to−Source On−Voltage (VGS = 10 Vdc) (Note 3)

(ID = 75 A)

(ID = 20 Adc, TJ = 125°C)

VDS(on)

−

0.63

−

0.34

Vdc

Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc) gFS 15 − − mhos

DYNAMIC CHARACTERISTICS (Note 2)

Input Capacitance (VDS = 25 V, VGS = 0, (Cpk ≥ 2.0)

f = 1.0 MHz) (Cpk ≥ 2.0)

(Cpk ≥ 2.0)

Ciss −2600 3900 pF

Output Capacitance Coss −1000 1300

Transfer Capacitance Crss −230 300

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

(VDD = 25 V, ID = 75 A,

VGS = 10 V,

RG = 9.1 Ω)

td(on) −15 30 ns

Rise Time tr−170 340

Turn−Off Delay Time td(off) −70 140

Fall Time tf−100 200

Gate Charge

(VDS = 40 V, ID = 75 A,

VGS = 10 V)

QT−71 100 nC

Q1−13 −

Q2−33 −

Q3−26 −

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (Note 2) (IS = 75 A, VGS = 0) (Cpk ≥ 10)

(IS = 20 A, VGS = 0)

(IS = 20 A, VGS = 0, TJ = 125°C)

VSD

−

0.97

0.80

0.68

−

1.00

−

Vdc

Reverse Recovery Time

(IS = 37.5 A, VGS = 0,

dIS/dt = 100 A/μs)

trr −57 −ns

ta−40 −

tb−17 −

Reverse Recovery Stored Charge QRR −0.17 −μC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)

(Measured from drain lead 0.25″ from package to center of die)

−

3.5

4.5

−

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

−7.5 −

1. Pulse Test: Pulse Width ≤300 μs, Duty Cycle ≤ 2%.

2. Reflects Typical Values. Cpk = Absolute Value of (SPEC − AVG) / 3 * SIGMA).

3. For accurate measurements, good Kelvin contact required.

4. Switching characteristics are independent of operating junction temperature.

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TYPICAL ELECTRICAL CHARACTERISTICS (Note 5)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)

RDS(on), DRAIN−TO−SOURCE RESISTANCE

(NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)

IDSS, LEAKAGE (nA)

160

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

ID, DRAIN CURRENT (AMPS)

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

Figure 3. On−Resistance versus Drain Current

and Temperature

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

Figure 5. On−Resistance Variation with

Temperature

Figure 6. Drain−To−Source Leakage

Current versus Voltage

5 V

TJ = 25°C

100

012345

160

ID, DRAIN CURRENT (AMPS)

120

00123 5 8

0.014

0.012

0.01

0.006

0.004

ID, DRAIN CURRENT (AMPS)

TJ = 100°C

25°C

−55 °C

VGS = 10 V

0.009

0.008

0.005 0

ID, DRAIN CURRENT (AMPS)

20 40 60 80 100 120

TJ = 25°C

1.5

0.5

−50

TJ, JUNCTION TEMPERATURE (°C)

−25 0 25 50 75 100 125 150

VGS = 10 V

ID = 37.5 A

1000

100

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

015304050

25°C

100°C

VGS = 10 V

TJ = −55°C

25°C

100°C

0.008

0.002

0.007

0.006

140 160

10000

120

140

1.5 2.5 3.5 4.50.5

140

100

647

40 60 80 100 120 140

510 2025 35 45

TJ = 125°C

7 V

6 V

5. Pulse Tests: Pulse Width ≤250 μs, Duty Cycle ≤ 2%.

VDS ≥ 10 V

15 V

VGS = 10 V

VGS = 0 V

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POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (Δt)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The published capacitance data is difficult to use for

calculating rise and fall because drain−gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (IG(AV)) can be made from a

rudimentary analysis of the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a

resistive load, VGS remains virtually constant at a level

known as the plateau voltage, VSGP

. Therefore, rise and fall

times may be approximated by the following:

tr = Q2 x RG/(VGG − VGSP)

tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn−on and turn−off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in a RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG − VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the off−state condition when

calculating td(on) and is read at a voltage corresponding to the

on−state when calculating td(off).

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is affected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board−mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Figure 7. Capacitance Variation

VGS VDS

8000

6000

2000

1000

4000

5 0 5 10152025

TJ = 25°C

VDS = 0 VGS = 0

7000

5000

3000

Ciss

Crss

Ciss

Coss

Crss

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Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

QG, TOTAL GATE CHARGE (nC)

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

25 50

Q1Q2

1000

100

RG, GATE RESISTANCE (OHMS)

1 10 100

TJ = 25°C

ID = 75 A

TJ = 25°C

ID = 75 A

VDD = 35 V

VGS = 10 V

VGS

VDS

td(off)

td(on)

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode

are very important in systems using it as a freewheeling or

commutating diode. Of particular interest are the reverse

recovery characteristics which play a major role in

determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of

the body diode itself. The body diode is a minority carrier

device, therefore it has a finite reverse recovery time, trr, due

to the storage of minority carrier charge, QRR, as shown in

the typical reverse recovery wave form of Figure 12. It is this

stored charge that, when cleared from the diode, passes

through a potential and defines an energy loss. Obviously,

repeatedly forcing the diode through reverse recovery

further increases switching losses. Therefore, one would

like a diode with short trr and low QRR specifications to

minimize these losses.

The abruptness of diode reverse recovery effects the

amount of radiated noise, voltage spikes, and current

ringing. The mechanisms at work are finite irremovable

circuit parasitic inductances and capacitances acted upon by

high di/dts. The diode’s negative di/dt during ta is directly

controlled by the device clearing the stored charge.

However, the positive di/dt during tb is an uncontrollable

diode characteristic and is usually the culprit that induces

current ringing. Therefore, when comparing diodes, the

ratio of tb/ta serves as a good indicator of recovery

abruptness and thus gives a comparative estimate of

probable noise generated. A ratio of 1 is considered ideal and

values less than 0.5 are considered snappy.

Compared to ON Semiconductor standard cell density

low voltage MOSFETs, high cell density MOSFET diodes

are faster (shorter trr), have less stored charge and a softer

reverse recovery characteristic. The softness advantage of

the high cell density diode means they can be forced through

reverse recovery at a higher di/dt than a standard cell

MOSFET diode without increasing the current ringing or the

noise generated. In addition, power dissipation incurred

from switching the diode will be less due to the shorter

recovery time and lower switching losses.

0.9

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

IS, SOURCE CURRENT (AMPS)

0 0.2 0.4 0.6 0.8 1

TJ = 25°C

VGS = 0 V

0.1 0.3 0.5 0.7

IS, SOURCE CURRENT (AMPS)

t, TIME (ns)

Figure 11. Reverse Recovery Time (trr)

−120

−20

−30

−40

−100 −60 −20 20 40 60 80

−10

−80 −40 0

di/dt = 300 A/μsSTANDARD CELL DENSITY

HIGH CELL DENSITY

trr

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SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain−to−source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

junction temperature and a case temperature (TC) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance −

General Data and Its Use.”

Switching between the off−state and the on−state may

traverse any load line provided neither rated peak current

(IDM) nor rated voltage (VDSS) is exceeded, and that the

transition time (tr, tf) does not exceed 10 μs. In addition the

total power averaged over a complete switching cycle must

not exceed (TJ(MAX) − TC)/(RθJC).

A power MOSFET designated E−FET can be safely used

in switching circuits with unclamped inductive loads. For

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and must be adjusted for operating

conditions differing from those specified. Although industry

practice is to rate in terms of energy, avalanche energy

capability is not a constant. The energy rating decreases

non−linearly with an increase of peak current in avalanche

and peak junction temperature.

Although many E−FETs can withstand the stress of

drain−to−source avalanche at currents up to rated pulsed

current (IDM), the energy rating is specified at rated

continuous current (ID), in accordance with industry

custom. The energy rating must be derated for temperature

as shown in the accompanying graph (Figure 12). Maximum

energy at currents below rated continuous ID can safely be

assumed to equal the values indicated.

TJ, STARTING JUNCTION TEMPERATURE (°C)

EAS, SINGLE PULSE DRAIN−TO−SOURCE

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

0.1 1 100

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

100

1000

AVALANCHE ENERGY (mJ)

ID, DRAIN CURRENT (AMPS)

RDS(on) LIMIT

THERMAL LIMIT

PACKAGE LIMIT

0.1 25 50 75 100 12510

VGS = 20 V

SINGLE PULSE

TC = 25°C

500

300

200

100

ID = 75 A

400

100 μs

175150

450

350

250

150

1 ms

10 ms

10 μs

t, TIME (s)

Figure 14. Thermal Response

0.1

0.01

1.0E−05 1.0E+01

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANC

(NORMALIZED)

RθJC(t) = r(t) RθJC

RθJC = 1.0°C/W MAX

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) − TC = P(pk) RθJC(t)

P(pk)

DUTY CYCLE, D = t1/t2

0.2

0.05

0.02

0.01

0.1

1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00

D = 0.5

SINGLE PULSE

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0.5

1.5

2.0

2.5

25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (°C)

PD, POWER DISSIPATION (WATTS)

Figure 15. D2PAK Power Derating Curve

RθJA = 50°C/W

Board material = 0.065 mil FR−4

Mounted on the minimum recommended footprint

Collector/Drain Pad Size ≈450 mils x 350 mils

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PACKAGE DIMENSIONS

D2PAK

CASE 418B−03

ISSUE D

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

SEATING

PLANE

−T−

0.13 (0.005) T

231

3 PL

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.340 0.380 8.64 9.65

B0.380 0.405 9.65 10.29

C0.160 0.190 4.06 4.83

D0.020 0.035 0.51 0.89

E0.045 0.055 1.14 1.40

G0.100 BSC 2.54 BSC

H0.080 0.110 2.03 2.79

J0.018 0.025 0.46 0.64

K0.090 0.110 2.29 2.79

S0.575 0.625 14.60 15.88

V0.045 0.055 1.14 1.40

−B−

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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