ATMEGA162U-8AC - Atmel Corporation

Features

•High-performance, Low-power AVR® 8-bit Microcontroller

•Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cy cle Multipli er

•Non-volatile Program and Data Memories

– 16K Bytes of In-System Self-programmable Flash

Enduran ce: 10,0 00 W r ite /Eras e Cycles

– Optional Boot Code Section with Independent Lock Bits

In-Syst em Programming by On-chip Boot Pr ogra m

True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K Bytes Internal SRAM

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

•JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses , a nd L ock Bits throug h the J TAG Interface

•Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two 16-bi t Timer/ Count ers w ith Sep arate Prescalers, Compare Modes, and

Capture Modes

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comp arator

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended

Standby

•I/O and Pack age s

– 35 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF

•Operating Voltages

– 1.8 - 3.6V for ATmega162V

– 2.4 - 4.0V for ATmega162U

– 2.7 - 5.5V for ATmega162L

– 4.5 - 5.5V for ATmega162

•Speed Grades

– 0 - 1 MHz for ATmega162V

– 0 - 8 MHz for ATmega162L/U

– 0 - 16 MHz for ATmega162

8-bit

ATmega162

ATmega162V

ATmega162U

ATmega162L

Advance

Information

Rev. 2513C–AVR–09/02

2ATmega162(V/U/L) 2513C–AVR–09/02

Pin Configurations Figure 1. Pinout ATme ga1 62

Disclaimer Typical v alues co ntaine d in this da ta sh eet are ba sed o n simula tions and chara cteriz a-

tion of othe r AVR microc ontro llers m anufac tured o n the sa me pro cess tec hnolo gy. Min

and Max values will be available after the device is characterized.

(OC0/T0) PB0

(OC2/T1) PB1

(RXD1/AIN0) PB2

(TXD1/AIN1) PB3

(SS/OC3B) PB4

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

(RXD0) PD0

(TXD0) PD1

(INT0/XCK1) PD2

(INT1/ICP3) PD3

(TOSC1/XCK0/OC3A) PD4

(OC1A/TOSC2) PD5

(WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

VCC

PA0 (AD0/PCINT0)

PA1 (AD1/PCINT1)

PA2 (AD2/PCINT2)

PA3 (AD3/PCINT3)

PA4 (AD4/PCINT4)

PA5 (AD5/PCINT5)

PA6 (AD6/PCINT6)

PA7 (AD7/PCINT7)

PE0 (ICP1/INT2)

PE1 (ALE)

PE2 (OC1B)

PC7 (A15/TDI/PCINT15)

PC6 (A14/TDO/PCINT14)

PC5 (A13/TMS/PCINT13)

PC4 (A12/TCK/PCINT12)

PC3 (A11/PCINT11)

PC2 (A10/PCINT10)

PC1 (A9/PCINT9)

PC0 (A8/PCINT8)

PA4 (AD4/PCINT4)

PA5 (AD5/PCINT5)

PA6 (AD6/PCINT6)

PA7 (AD7/PCINT7)

PE0 (ICP1/INT2)

GND

PE1 (ALE)

PE2 (OC1B)

PC7 (A15/TDI/PCINT15)

PC6 (A14/TDO/PCINT14)

PC5 (A13/TMS/PCINT13)

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

(RXD0) PD0

VCC

(TXD0) PD1

(INT0/XCK1) PD2

(INT1/ICP3) PD3

(TOSC1/XCK0/OC3A) PD4

(OC1A/TOSC2) PD5

(WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

VCC

(A8/PCINT8) PC0

(A9/PCINT9) PC1

(A10/PCINT10) PC2

(A11/PCINT11) PC3

(TCK/A12/PCINT12) PC4

PB4 (SS/OC3B)

PB3 (TXD1/AIN1)

PB2 (RXD1/AIN0)

PB1 (OC2/T1)

PB0 (OC0/T0)

GND

VCC

PA0 (AD0/PCINT0)

PA1 (AD1/PCINT1)

PA2 (AD2/PCINT2)

PA3 (AD3/PCINT3)

PDIP

12 14 16 18 20 22

13 15 17 19 21

44 42 40 38 36 34

43 41 39 37 35

TQFP/MLF

ATmega162(V/U/L)

2513C–AVR–09/02

Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC archite cture. By executing p owerful instr uctions in a si ngle cloc k cycle,

the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the sys-

tem designer to optimize power consumption versus processing speed.

Block Diagram Figure 2. Block Diagram

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

OSCILLATOR

TIMERS/

COUNTERS

INTERRUPT

UNIT

STACK

POINTER

EEPROM

SRAM

STATUS

USART0

PROGRAM

COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

PROGRAMMING

LOGIC

SPI

COMP.

INTERFACE

PORTA DRIVERS/BUFFERS

PORTA DIGITAL INTERFACE

GENERAL

PURPOSE

REGISTERS

ALU

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

PORTB DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

XTAL1

XTAL2

RESET

CONTROL

LINES

VCC

GND

PA0 - PA7 PC0 - PC7

PD0 - PD7PB0 - PB7

AVR CPU

INTERNAL

CALIBRATED

OSCILLATOR

PORTE

DRIVERS/

BUFFERS

PORTE

DIGITAL

INTERFACE

PE0 - PE2

USART1

4ATmega162(V/U/L) 2513C–AVR–09/02

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connec ted to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega162 provides the following features: 16K bytes of In-System Programmable

Flash with Read-While-Wri te capabilities, 512 bytes EEP ROM, 1K bytes SRAM, an

external memor y interface, 35 general purpos e I/O lines, 32 general purpose working

registers, a JTAG interface for Boundary-scan, On-chip Debugging support and pro-

gramming, four flexible Timer/Counters with compare modes, internal and external

interrupts, two serial programmable USARTs, a programmable Watchdog Timer with

Internal Osc illato r , an SPI s er ial por t, a nd fi ve sof tware s ele ct abl e power saving modes.

The I dle mo de s tops the CPU while all owing t he S RAM, Time r/Co unters , SP I po rt, an d

interrupt system to continue functioning. The Power-down mode saves the register con-

tent s but fr eezes the Oscil lator , disabl ing all other ch ip fun ctions until th e next inte rrup t

or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,

allowing the user to maintain a timer base while the rest of the device is sleeping. In

Standb y mo de , the cry stal /reson ator Osc illato r i s run ning whi le th e r est of th e de vice is

sleeping. This allows very fast start-up combined with low-power consumption. In

Exten ded Stand by mode, b oth the mai n Oscillat or and the As ynchrono us Timer co n-

tinue to run.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The On-chip ISP Flash all ows the program memory to be reprogrammed In- System

through an SPI serial interface, by a conventional non-volatile memory programmer, or

by an O n-chi p Boo t Progr am run ning on the AVR core . The B oot P rogram can use any

interface to downl oad the Application P rogram in the Appli cation Flash memory. Soft-

ware in the Bo ot F l ash s ec ti on wil l continue to r un whi le the A pplic ati on F lash se cti on is

updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU

with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is

a powerful microcontroller that provides a highly flex ible and c ost effectiv e solution to

many embedded control applications.

The ATmega162 AVR is supported with a full suite of program and system development

tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-

cuit Emulators, and evaluation kits.

ATmega161 and

ATmega162

Compatibility

The A Tmega 162 i s a hig hly c omplex mic rocon trolle r wh ere th e nu mber of I /O l ocatio ns

supersedes the 64 I/O loca tions reserve d in the AVR instruction set. To ensure bac k-

ward compatibi lity with the ATmeg a161, all I/O loca tions present in ATmega161 have

the same locations in ATmega162. Some additional I/O locations are added in an

Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM

space). These locations can be reached by using LD/ LDS/LDD and ST/STS/STD

inst ruction s only, not by u sing IN and OU T instru ctions . The rel ocation of the interna l

RAM space may still be a problem for ATmega161 users. Also, the increased number of

Interrupt Vectors might be a problem if the code uses absolute addresses. To solve

these problems , an ATmega 161 compatibili ty mode can be selected by program ming

the fuse M161C. In th is mode, none of the functions in the E xtended I/O space ar e in

use, so the internal RAM is located as in ATmega161. Also, the Extended Interrupt Vec-

tors are removed. The ATmega162 is 100% pin compatible with ATmega161, and can

replace the ATmega161 on current Printed Circuit Boards. However, the location of

Fuse bits and the electrical characteristics differs between the two devices.

ATmega162(V/U/L)

2513C–AVR–09/02

ATmega161 Compatibility

Mode Programming the M161C will change the following functionality:

• The extended I/O map will be configured as internal RAM once the M161C Fuse is

programmed.

• The timed sequence for changing the Watchdog Time-out period is disabled. See

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page

54 for details.

• The double buffering of the USART Receive Registers is disabled. See “AVR

USART vs. AVR UART – Compatibility” on page 165 for details.

• Pin change interrupts are not supported (Contol Registers are located in Extended

I/O).

• One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible.

Note that the shared UBRRHI Register in ATmega161 is split into two separate registers

in ATmega162, UBRR0H and UBRR1H. The location of these registers will not be

affected by the ATmega161 compatibility fuse.

Pin Descriptions

VCC Digital supply voltage

GND Ground

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. When pins PA0 to PA7 are used as inputs and are externally

pulled low, they will source current if the internal pull-up resistors are activated. The Port

A pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Port A a lso s erves th e func tions o f var ious spe cial featur es of th e ATmega 162 as liste d

on page 70.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and sourc e capability . As inputs, P ort B pins that are exte rnally pu lled low wil l source

current if the pull-u p resistors are activat ed. The Port B pins are tri-s tated when a re set

condition becomes active, even if the clock is not running.

Port B a lso s erves th e func tions o f var ious spe cial featur es of th e ATmega 162 as liste d

on page 70.

Port C (PC7..PC0) Port C is an 8-bit bi-di rectiona l I/O port with interna l pull-up re sistors ( selecte d for each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, P ort C pins that ar e externally pu lled low will source

current if the pull-up re sistors ar e activated. T he Port C pins are tr i-stated w hen a reset

condition becomes active, even if the clock is not running. If the JTAG interface is

enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be acti-

vated even if a Reset occurs.

Port C als o serv es the fu nction s of the J TAG i nterfa ce and ot her spec ial fe atures of th e

ATmega162 as listed on page 73.

6ATmega162(V/U/L) 2513C–AVR–09/02

Port D (PD7..PD0) Port D is an 8-bit bi-di rectiona l I/O port with interna l pull-up re sistors ( selecte d for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, P ort D pins that ar e externally pu lled low will source

current if the pull-up re sistors ar e activated. T he Port D pins are tr i-stated w hen a reset

condition becomes active, even if the clock is not running.

Port D als o serves the funct ions of various special feature s of the ATme ga162 as liste d

on page 76.

Port E(PE 2..PE0) Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port E output buffers have symmetrical drive characteristics with both high sink

and sourc e capability . As inputs, P ort E pins that are exte rnally pu lled low wil l source

current if the pull-u p resistors are activat ed. The Port E pins are tri-s tated when a re set

condition becomes active, even if the clock is not running.

Port E a lso s erves th e func tions o f var ious spe cial featur es of th e ATmega 162 as liste d

on page 79.

RESET Reset in put . A l ow le vel o n thi s pin for longe r th an the mi ni mum p uls e le ngth wi ll gener-

ate a Reset, even if the clock is not running. The minimum pulse length is given in Table

18 on page 46. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the Inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the Inverting Oscillator amplifier.

About Code Examples This documentation contains simple code examples that briefly show how to use various

parts of the device. Thes e code exam ples assume th at the part speci fic header file is

include d before compil ation. Be aware that no t all C compi ler vendo rs inclu de bit defin i-

tions in the header files and interrupt handling in C is compiler dependent. Please

confirm with the C compiler documentation for more details.

ATmega162(V/U/L)

2513C–AVR–09/02

AVR CPU Core

Introduction This section discusses the AVR core architecture in general. The main function of the

CPU core is to ensure correct program execution. The CPU must therefore be able to

access memories, perform calculations, control peripherals, and handle interrupts.

Architectur al Overview Figure 3. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separ ate memories and bus es for program and data. Instructio ns in the progra m

memory are executed with a single level pipelining. While one instruction is being exe-

cuted, the next instruction is pre-fetched from the program memory. This concept

enables instructions to be executed in every clock cycle. The program memory is In-

System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with

a single clock cycle a ccess ti me. This al lows sin gle-cyc le Arit hmetic Logi c Unit (ALU)

operation. In a typical ALU operation, two operands are output from the Register File,

the operation is executed, and the result is stored back in the Register File – in one

clock cycle.

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

8ATmega162(V/U/L) 2513C–AVR–09/02

Six of the 3 2 reg isters can be u sed a s thre e 16 -bit in dire ct ad dress regi ster point ers for

Data Space addressing – enabling efficient address calculations. One of the these

address pointers can also be used as an address pointer for look up tables in Flash Pro-

gram memory. These added function registers are the 16-bit X-, Y-, and Z-register,

described later in this section.

The A LU su pport s ari thmet ic and log ic o peration s be tween regi ster s or b etw een a con-

stant and a register. Single register operations can also be ex ecuted in the ALU. After

an arithmetic operation, the Status Register is updated to reflect information about the

result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions,

able to d irect ly addr ess the wh ole ad dress space. M ost AVR instruc tions have a sin gle

16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Progr am Flash memory s pace is di vided in two sec tions, the Boot P rogram secti on and

the Application Program section. Both sections have dedic ated Lock bits for write and

read/write protection. The SPM instruction that writes into the Application Flash memory

section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program counter (PC) is

stored on the Stack. The Stack i s effectively allocated in the general data S RAM, and

consequ entl y th e S tac k s ize is o nl y li mited by th e total S RA M si ze an d the usage of the

SRAM . All user prog rams must in itialize the SP in the res et routine (b efore subr outines

or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O

space. The data SRAM can easily be accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexibl e interrupt mod ule has its c ontrol regis ters in the I/O space with an additional

Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt

Vect or in the Inte rrupt Vec tor ta ble. T he interr upts ha ve prior ity in ac cord ance with the ir

Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control

Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as

the Data Space locations following those of the Register File, 0x20 - 0x5F.

ALU – Arit hmetic Logic

Unit The high- performance AVR ALU ope rates in dire ct connection with all the 32 gene ral

purpose worki ng regist ers. Within a single clock cy cle, arithmetic opera tions between

general purpose registers or betwe en a register an d an immediate are executed . The

ALU operations are divided into three main categories – arithmetic, logical, and bit-func-

tions. Some implementations of the architecture also provide a powerful multiplier

supporting both signed/unsigned multiplication and fractional format. See the “Instruc-

tion Set” section for a detailed description.

Status Regist er The Sta tus Reg ister contains info rm ati on abo ut th e res ul t of the mos t rec en tly ex ecuted

arithme tic i nstruct ion . This i nform ation ca n be used for alteri ng pro gram flow in orde r to

perform conditi onal operations. Note that the Status Register is updated after all ALU

operations, as specified in the Instruction Set Reference. This will in many cases

remove the need for using the dedicated comp are instructions, resulting in faster and

more compact code.

The Status Register is not automatically stored when entering an i nterrupt routine and

restored when returning from an interrupt. This must be handled by software.

ATmega162(V/U/L)

2513C–AVR–09/02

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ-

ual inter rupt enabl e contr ol is then perform ed in separate contr ol reg isters . If the Globa l

Interrupt Enable Register is cleared, no ne of the interrupts are enabled independent of

the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt

has occu rred, and is set by the RE TI instruc tion to ena ble su bseque nt inter rupts. T he I-

bit can also be set and cleared by the application with the SEI and CLI instructions, as

described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source or

destination for the operated bit. A bit from a register in the Register File can be copied

into T by the BST instruction, and a bit in T can be copied into a bit in a regis ter in the

• Bit 5 – H: Half Carry Flag

The Hal f Carry Flag H i ndicates a ha lf car ry in some arith metic operati ons. Ha lf ca rry is

useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is al way s an ex cl us ive o r b etwe en th e ne gati v e fla g N an d th e T wo’ s Co mpl e-

ment Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V suppor ts two’s complement arithmetics. See

the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negativ e Flag N indicate s a negative resu lt in an arithmet ic or logic oper ation. See

the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Car ry Flag C indi cates a ca rry in an ari thmetic or logic oper ation. S ee the “Instru c-

tion Set Description” for detailed information.

Bit 76543210

I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

10 ATmega162(V/U/L) 2513C–AVR–09/02

General Purpose

achiev e th e re qui re d p er forma nc e a nd flexibilit y, the fol lo wing inpu t/ou tput s ch eme s are

supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers,

and most of them are single cycle instructions.

As show n in Figure 4, each regis ter is als o assigned a data mem ory addre ss, mappin g

them directly into the first 32 locations of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to

index any register in the file.

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

ATmega162(V/U/L)

2513C–AVR–09/02

The X-register, Y-register, and

Z-register The registers R26..R31 have some added functions to their general purpose usage.

These registers are 16-bit address pointers for indirect addressing of the Data Space.

The three indirect address registers X, Y, and Z are defined as described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed dis-

placemen t, automatic increment, and automatic decrement (see the instruction set

reference for details).

Stac k Pointer The Stack is mainly used for storing temporary data, for storing local variables and for

storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis-

ter always poi nts to the top of the S tac k. Note tha t the Sta ck is implem ent ed as gro win g

from hi gher memory locations to lower memo ry location s. This im plies that a Stack

PUSH command decreases the Stack Pointer.

The Stack P ointer poi nts to the data SRAM s tack area wher e the Subrouti ne and Inter-

rupt Stacks are located. This Stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above 0x 60. The Stack Pointer is decrem ented by one

when data is pushed onto the Stack with the PUSH instruction, and it is decremented by

two when the return address is pushed onto the Stack with subroutine call or interrupt.

The Stack Pointer is incremented by one when data is popped fr om the Stack with the

POP in structi on, and it is increme nted by two when dat a is poppe d from the S tack with

return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num-

ber of bits actually used is implementation dependent. Note that the data space in some

implementations of the AVR architecture is so small that only SPL is needed. In this

case, the SPH Register will not be present.

15 XH XL 0

X - register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y - register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z - register 7 0 7 0

R31 (0x1F) R30 (0x1E)

Bit 151413121110 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

00000000

12 ATmega162(V/U/L) 2513C–AVR–09/02

Instruction Execution

Timing This section describes the general access timing concepts for instruction execution. The

AVR CPU is driv en by the CPU clock clkCPU, di rect ly gener ated fr om the sele cted c lock

source for the chip. No internal clock division is used.

Figure 6 shows the parallel instruction fetches and instruction executions enabled by the

Harvard architecture and the fast-access Register File concept. This is the basic pipelin-

ing concept to obtain up to 1 MIPS per MHz with the corresponding unique r esults for

functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 7. Single Cycle ALU Operation

Reset and Interrupt

Handling The AVR provides several different interrupt sources. These interrupts and the separate

Reset Vector each have a separate program vector in the program memory space. All

interrupts are assigned individual enable bits which must be written logic one together

with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

Depending on the Program Counter value, interrupts may be automatically disabled

when Boot Loc k bits BLB02 or B LB1 2 a re progr a mme d. Thi s fea tur e impr ov es s oft war e

security. See the section “Memory Programming” on page 228 for details.

The lowest addresses in the program memory space are by default defined as the Reset

and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 55.

The list also determines the priority levels of the different interrupts. The lower the

addres s the high er is the pr io rity level. RES ET has the hi gh est prior it y, and nex t is INT0

– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of

the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register

(GICR). Refer to “Interrupts” on page 55 for more information. The Reset Vector can

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

ATmega162(V/U/L)

2513C–AVR–09/02

also be moved to the s tart of th e Boot F lash se ction by prog rammi ng the BOOT RST

Fuse, see “Boot Loader Support – Read-While-Write Self-programming” on page 214.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts

are disabled. T he user software can write lo gic one to the I-bit to enable ne sted inter-

rupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is

automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type i s triggered by an event that

sets th e interrupt flag. For these interrupts, th e Program Counte r is vecto red to the

actual Interrupt Vector in order to execute the interrupt handling routine, and hardware

clears the corresponding interrupt flag. Inter rupt flags can also be cleared by writing a

logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the

corresponding inter rupt enable bit is clear ed, the interrupt flag will be set and remem-

bered unt il the i nter rupt is ena ble d, or th e fla g is cle ar ed by s oftwa re. Simi la rl y, if on e or

more interrupt conditions occur while the global interrupt enable bit is cleared, the corre-

sponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable

bit is set, and will then be executed by order of priority.

The sec ond type of i nterrupts will trigger as long as the interrup t condition i s present.

These interrup ts do not neces saril y have inte rrup t fla gs. I f the interr upt c onditi on dis ap-

pears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and exe-

cute one more instruction before any pending interrupt is served.

Note that the Status Regist er is not automatic ally sto re d whe n ente ring an interru pt r ou-

tine, nor restored when returning from an interrupt routine. This must be handled by

software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately

disabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta-

neousl y with the CLI i nstruc tion . The foll owing examp le s hows h ow th is c an be us ed t o

avoid interrupts during the timed EEPROM write sequence..

Assembly Code Examp le

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

14 ATmega162(V/U/L) 2513C–AVR–09/02

When us ing the SEI i nstruc tion to enable in terrupts, the ins truc tion fol lowin g SEI will be

executed before any pending interrupts, as shown in this example.

Interrupt Response Time The int errupt executio n respon se for all th e enable d AVR inter rupts is four cloc k cycles

minimum. After four clock cycles the program vector address for the actual interrupt

handling routine is executed. During this four clock cycle period, the Program Counter is

pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this

jump t akes three cloc k cycles. If an inte rrupt occurs durin g executio n of a multi-cyc le

instruction, this instruction is completed before the interrupt is served. If an interrupt

occurs when the MCU is in sleep mode, the interrupt execution response time is

increased by four clock cycles. This increase comes in addition to the start-up time from

the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four

clock cycles, th e Pr og ra m Co unt e r ( two by t es ) is pop p ed back fr om th e St ac k, th e Stack

Pointer is incremented by two, and the I-bit in SREG is set.

Assembly Code Examp le

sei ; set global interrupt enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set global interrupt enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

ATmega162(V/U/L)

2513C–AVR–09/02

AVR ATmega162

Memories This section describes the different memories in the ATmega162. The AVR architecture

has two main memory spaces, the Data Memory and the Program Memory space. In

additio n, the AT mega162 features an EEPROM Memory fo r data s torage. Al l three

memory spaces are linear and regular.

In-System

Reprogrammable Flash

Program Memory

The ATm ega 162 cont ains 16K bytes On -chip In -Syst em Rep rogram mable F lash mem -

ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is

organized as 8K x 16. For software security, the Flash Program memory space is

divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega162 Program Counter (PC) is 13 bits wide, thus addressing the 8K program

memory locations. The operation of Boot Program section and associated Boot Lock

bits for software protection are descr ibed in detail in “ Boot Loader Sup port – Read-

While-Write Self-programming” on page 214. “Memory Programming” on page 228 con-

tains a detailed description on Flash data serial downloading using the SPI pins or the

JTAG interface.

Constant tables can be allocated within the entire program memory address space (see

the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execu-

tion Timing” on page 12.

Figure 8. Program Memory Map(1)

Note: 1. The address reflects word addresses.

0x0000

0x1FFF

Program Memory

Application Flash Section

Boot Flash Section

16 ATmega162(V/U/L) 2513C–AVR–09/02

SRAM Data Me mory Figure 9 shows how the ATmega162 SRAM Memory is organized. Memory configura-

tion B refers to the ATmega161 compatibility mode, configuration A to the non-

compatible mode.

The ATmeg a162 is a complex microcontrol ler with more per ipheral units than can be

supported within the 64 location reserved in the Opcode for the IN and OUT instructions.

For the Extended I /O space from 0x60 - 0xFF in SRAM, only the ST/S TS/STD and

LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the

ATmega162 is in the ATmega161 compatibility mode.

In Normal mode, the first 1280 Data Memory locations address both the Register File,

the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 loca-

tions ad dr ess the Register Fi le , th e next 64 lo ca tio n th e s ta ndar d I/O m emo ry, then 160

locations of Extended I/ O memory, and the next 1024 locations address the internal

data SRAM.

In ATmega161 compatibility mode, the lower 1120 Data Memory locations address the

address the Register File and I/O Memory, and the next 1024 locations address the

internal data SRAM.

An optional exter nal data SRAM can be used with the ATmega162. This S RAM will

occupy an a re a i n the re mai ni ng a ddres s lo cat ion s i n th e 64K addres s sp ace . T hi s a re a

starts at the address following the internal SRAM. The Register File, I/O, Extended I/O

and Internal SRAM uses the occupies the lowest 1280 bytes in Normal mode, and the

lowest 1120 bytes in the ATmega161 compatibility mode (Extended I/O not present), so

when using 64KB (65,536 bytes) of External Memory, 64,256 Bytes of External Memory

are available in Normal mode, and 64,416 Bytes in ATmega161 compatibility mode. See

“External Memory Interface” on page 24 for details on how to take advantage of the

external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data

memory locations, the external data SRAM is accessed using the same instructions as

for the internal data memory access . When the internal data memories a re accessed,

the read and write strobe pins (PD7 and PD6) are inac tive during the whole access

cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR

Accessing external SRAM takes one additional clock cycle per byte compared to access

of the inter nal SRAM. Thi s means that the commands LD, ST, LDS, STS, LDD, STD,

PUSH, and POP take one additional clock cycle. If the Stack is placed in external

SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the

2-byt e Program Counter is pus hed and pop ped, and ex ternal mem ory access does not

take adv antage of the in terna l pipe line m emory a ccess. When e xter nal SR AM int erface

is used with wait-state, one-byte external access takes two, three, or four additional

clock cycles for one, two, and three wait-states respectively. Interrupt, subroutine calls

and returns will need five, seven, or nine clock cycles more than specified in the instruc-

tion set manual for one, two, and three wait-states.

The five different addressing modes for the data memory cover: Direct, Indirect with Dis-

placeme nt, Indirec t, Indirect with Pre- decrement, and Indirec t with P ost-incremen t. In

the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base

addres s given by the Y- or Z-r egister.

ATmega162(V/U/L)

2513C–AVR–09/02

When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y, and Z are decremented or incremented.

The 32 gene ral purpo se work ing regi sters, 64 (+160) I/O Register s, and the 10 24 bytes

of internal data SRAM in the ATmega162 are all accessible through all these addressing

modes. The Register File is described in “General Purpose Register File” on page 10.

Figure 9. Data Memory Map

Data Memory Access Times This sec tion descr ibes the gener al acces s timing conce pts for inter nal memory access.

The internal data SRAM access is performed in two clkCPU cycle s as de sc ri be d in Fi gu re

10.

Figure 10. On-chip Data SRAM Access Cycles

32 Registers

64 I/O Registers

Internal SRAM

(1024 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x0460

0x045F

0xFFFF

0x0060

Data Memory

External SRAM

(0 - 64K x 8)

Memory configuration B

32 Registers

64 I/O Registers

Internal SRAM

(1024 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x04FF

0xFFFF

0x0060 - 0x00FF

Data Memory

External SRAM

(0 - 64K x 8)

Memory configuration A

160 Ext I/O Reg. 0x0100

0x0500

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read Write

CPU

Memory Access Instruction Next Instruction

18 ATmega162(V/U/L) 2513C–AVR–09/02

EEPROM Data Memory The ATmega162 contains 512 bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPROM has an

enduran ce of at least 100 ,000 wri te/erase c ycles. Th e access be tween the EEPRO M

and th e CPU is desc ribed in the follo wing , specify ing the E EPROM Address Regist ers,

the EEPROM Data Register, and the EEPROM Control Register.

“Memory Programming” on page 228 contains a detailed description on EEPROM Pro-

gramming in SPI, JTAG, or Parallel Programming mode.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A selftiming function, how-

ever, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In

heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This

causes t he devi ce for s ome period of time to run a t a vol tage lowe r than sp ecified as

minimu m for the cloc k freq uen cy us ed. S ee “ Prev enting EE PROM C orr uption ” on pag e

22. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-

lowed. Refer to the description of the EEPROM Control Register for details on this.

When the E EPROM is read, the CPU is halted for four clock c ycles before the nex t

instruction is executed. When the EEPROM is written, the CPU is halted for two clock

cycles before the next instruction is executed.

The EEPROM Address

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega162 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address

in the 512 bytes EEPROM space. The EEPR OM data bytes are addressed linearly

between 0 and 511. The initial value of EEAR is undefined. A proper value must be writ-

ten before the EEPROM may be accessed.

Bit 151413121110 9 8

–––––––EEAR8EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/WriteRRRRRRRR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 X

XXXXXXXX

ATmega162(V/U/L)

2513C–AVR–09/02

The EEPROM Data Register –

EEDR

• Bits 7..0 – EEDR7.0: EEPROM Data

For the E EPRO M write oper ation, the EE DR Regi ster c ontains t he data to be writt en to

the EEPRO M in the ad dress gi ven by the EEAR Regist er. For th e EEPROM read ope r-

atio n, the EEDR contains th e data read out from th e EEPROM at the addre ss given by

EEAR.

The EEPROM Control

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega162 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enable s the EEPROM Ready Interrupt if the I bit in SREG is set.

Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a

constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be

written. When EEMWE is set, setting EEWE within four clock cycles will write data to the

EEPRO M at the s elected addr ess If EEM WE is zero, setting EEW E will hav e no effec t.

When EEMWE has been written to one by software, hardware clears the bit to zero after

four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable signal EEWE is the write strobe to the EEPROM. When

addres s and data are c orrect ly set up, the EEWE bit m ust be wr itten to one t o wri te the

value i nto the E EPROM . The E EMWE bi t must b e wri tten to on e before a lo gical one is

written to EEWE, otherwise no EEPROM write takes place. The following procedure

should be followed when writing the EEPROM (the order of steps 3 and 4 is not

essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be pr ogrammed during a CPU write to the F lash memory. T he

software mu st check that the Flash programming is comple ted before i nitiating a n ew

EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing

the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

– – – – EERIE EEMWE EEWE EERE EECR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 X 0

20 ATmega162(V/U/L) 2513C–AVR–09/02

can be omitted. Se e “Boot Loa der Support – Read-While- Write Self-programm ing” on

page 214 for details about boot programming.

Caution: An interrupt be tween ste p 5 and s tep 6 wi ll mak e the writ e cy cl e fai l, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM i s i nter rup tin g a nother EE PROM ac c ess, th e E E AR or E E DR R egi st er will b e

modified, c ausing the interrupted E EPROM acces s to fail. It i s recommende d to have

the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed , the EEWE bit is cleared by hardware. The

user software can poll this bit and wait for a zero before writing the next byte. When

EEWE h as been set, the CPU is hal ted for two cycles before the nex t instruction is

executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the

correct ad dress is set up in the EEAR Regis ter, the EERE bit mu st be written to a lo gic

one to trigger the EEPROM read. The EEPROM read access takes one instruction, and

the requested data is available immediately. When the EEPROM is read, the CPU is

halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation

is in progress, it is neither possible to read the EEPROM, nor to change the EEAR

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical

programming time for EEPROM access from the CPU.

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings

Table 1. EEPROM Programming Time

Symbol Number of Calibrated RC

Oscillator Cycles(1) Typ Programming Time

EEPROM write (from CPU) 8448 8.5 ms

ATmega162(V/U/L)

2513C–AVR–09/02

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g., by disabling inter-

rupts globally) so that no interrupts will occur during execution of these functions. The

examples also assume that no Flash Boot Loader is present in the software. If such

code i s pr esen t, the EEPRO M w rite f uncti on m ust also wait for any on going SPM co m-

mand to finish.

Assembly Code Examp le

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

22 ATmega162(V/U/L) 2513C–AVR–09/02

The next code examples show assembly and C functions for reading the EEPROM. The

example s assume that int errupts a re contr olled so that no interrupts will o ccur durin g

execution of these functions.

Preventing EEPROM

Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply volt-

age is to o low for the CP U and th e EEPR OM to oper ate pr operly . These issu es are th e

same as for board level systems using EEPROM, and the same design solutions should

be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too

low. First, a regular write sequence to the EEPROM requires a minimum voltage to

operate c orrectly. Secon dly, the CPU itself ca n execu te instructions inc orrectly, if the

supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design

recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done b y enabli ng the int ernal Brow n-out Detec tor (BOD). If the detec tion

level of the in ternal BOD does not matc h the needed dete ction leve l, an externa l low

VCC Reset Pr otect ion c ircuit can be used. I f a Reset oc curs while a writ e oper ation is in

progress, the write operation will be completed provided that the power supply voltage is

sufficient.

Assembly Code Examp le

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

ATmega162(V/U/L)

2513C–AVR–09/02

I/O Memory The I/O s pace defi nition of the ATmega 162 is shown in “Regi ster Sum mary” on pa ge

272.

All ATmega162 I/Os and peripherals are placed in the I/O space. All I/O locations may

be accessed by the L D/LDS/LDD and ST/STS/STD instructions, transfe rring data

between the 32 general purpose working regis ters and the I/O space. I/O Registers

within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI

instructions. In these registers, the value of single bits can be checked by using the

SBIS a nd SBIC ins tructio ns. Refe r to the in structi on set sec tion for m ore deta ils. Whe n

using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be

used. When addressing I/O Registers as data space using LD and ST instructions, 0x20

must be ad ded to these addresses. The ATmega162 is a complex microcon troller with

more pe riphera l units than c an be supp orted withi n the 64 locat ion reser ved in Opc ode

for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,

only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O

space is replac ed with SRAM locations when the ATmega162 is in the A Tmega161

compatibility mode.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the s tatus flags a re c leared by wri ting a logic al one to th em. Not e t hat the CBI

and SBI instructions will operate on all bits in the I/O Register, writing a one back into

any flag read as set, th us clearin g the flag . The CBI and SBI instr uctions work with r eg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

24 ATmega162(V/U/L) 2513C–AVR–09/02

External Memory

Interface With all t he feat ures the E xternal Memory Inter face pr ovide s, it is well suit ed to operate

as an interface to memory devices such as external SRAM and FLASH, and peripherals

such as LCD-display, A/D, and D/A. The main features are:

•Four Different Wait-state Settings (Including No Wait-state)

•Independent Wait-state Setting for Different External Memory Sectors (Configurable

Sector Size)

•The Number of Bits Dedicated to Address High Byte is Selectable

•Bus Keepers on Data Lines to Minimize Current Consumption (Optional)

Overview When the eX ternal MEMory (XMEM) is enabled, address space outside the internal

SRAM becomes available using the dedicated external memory pins (see Figure 1 on

page 2, Table 29 on page 68, Table 35 on page 73, and Table 41 on page 79). The

memory configuration is shown in Figure 11.

Figure 11. External Memory with Sector Select

Note: 1. Address depends on the ATmega161 compability Fuse. See “SRAM Data Memory”

on page 16 and Figure 9 on page 17 for details.

Using the External Memory

Interface The interface consists of:

• AD7:0: Multiplexed low-order address bus and data bus

• A15:8: High-order address bus (configurable number of bits)

• ALE: Address latch enable

•RD

: Read strobe.

•WR: Write strobe.

0x0000

0x04FF/0x045F(1)

External Memory

(0-64K x 8)

0xFFFF

Internal Memory

SRL[2..0]

SRW11

SRW10

SRW01

SRW00

Lower Sector

Upper Sector

0x0500/0x0460(1)

ATmega162(V/U/L)

2513C–AVR–09/02

The control bits for the External Memory Interface are located in three registers, the

MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and

the Special Function IO Register – SFIOR.

When the XMEM interface is enabled, it will override the settings in the Data Direction

registers corresponding to the ports dedicated to the interface. For details about this port

override, see the alternate functions in section “I/O-Ports” on page 61. The XMEM inter-

face will autodetect whether an access is internal or external. If the access is external,

the XMEM interface will output address, data, and the control signals on the ports

according to Figure 13 (this figure shows the wave forms without wait-states). When

ALE g oes from high t o low, th ere i s a va lid addr ess on AD7:0 . ALE is lo w duri ng a da ta

transfe r. When the X MEM in terface i s enabl ed, also an inter nal acces s will caus e acti v-

ity on address- , data- an d ALE port s, but the R D and WR strobe s wi ll n ot to ggle du ring

intern al acces s. Whe n the Ext ernal M emory In terface i s disabl ed, the normal p in and

data d irecti on se ttings a re use d. Note that when t he XM EM in terface is dis abled, the

address space above the internal SRAM boundary is not mapped into the internal

SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal

latch (typically “74x573” or equivalent) which is transparent when G is high.

Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address la tch must be

selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.

When operating at conditions above these frequencies, the typical old style 74HC series

latch becom es ina dequ ate . The ex ter na l me mory int er fac e is de signed in com pl ian ce to

the 74AHC series latch. However, most latches can be used as long they comply with

the main timing parameters. The main parameters for the address latch are:

• D to Q propagation delay (tpd).

• Data setup time before G low (tsu).

• Data (address) hold time after G low (th).

The external memory interface is designed to guaranty minimum address hold time after

G is ass erted low o f th = 5 ns ( refer to tLAXX_LD/tLLAXX_ST in Table 116 to T able 123 on

page 268). The D to Q propagation delay (tpd) must be taken into consider ation when

calculating the access time requirement of the external component. The data setup time

before G low (tsu) must not exceed ad dress valid to ALE low (tAVLLC) minus PCB wiring

delay (dependent on the capacitive load).

Figure 12. External SRAM Connected to the AVR

D[7:0]

A[7:0]

A[15:8]

SRAM

AD7:0

ALE

A15:8

AVR

26 ATmega162(V/U/L) 2513C–AVR–09/02

Pull-up and Bus Keeper The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port reg-

ister is w ritten to one. To reduc e power c onsum ption in s leep m ode, it is reco mmende d

to disable the pull-ups by writing the Port register to zero before entering sleep.

The XMEM i nterface also provides a bus keeper on th e AD7:0 lines. The B us Keeper

can be disabled and enabled in software as described in “Special Function IO Register –

SFIOR” on page 30. When enabled, the Bus Keeper will keep the previous value on the

AD7:0 bus while these lines are tri-stated by the XMEM interface.

Timing Exter nal memory devices have various timing requirements. To meet these require-

ments, the A Tme ga162 XMEM in terface pro vides four dif ferent wait- state s as s hown in

Table 3. It is important to consider the timing specification of the external memory

device before selecting the wait-state. The most important parameters are the access

time for the external memory in conjunction with the set-up requirement of the

ATmeg a162. The access time fo r the ex ternal me mory is de fined to be the time fro m

receiving the chip select/address until the data of this address actually is driven on the

bus. The access time cannot exceed the time from the ALE pulse is asserted low until

data must be stable during a read sequence (tLLRL+ tRLRH - tDVRH in Table 116 to Table

123 on page 268). Th e differ en t wai t-sta tes are s et up in s of twar e. As an ad dit ion al fea-

ture, it is possible to divide the external memory space in two sectors with individual

wait-state s etti ngs. T his m ak es it pos sib le to connec t two diff erent m emo ry devic es with

different timing requirements to the same XMEM interface. For XMEM interface timing

details, please refer to Figure 116 to Figure 119, and Table 116 to Table 123.

Note that the XMEM interfac e is asynchronou s and that the wav eforms in the figures

below are related to the internal system clock. The skew between the internal and exter-

nal clock (XTAL1) is not guaranteed (it varies between devices, temperature, and supply

voltage). Consequently, the XMEM interface is not suited for synchronous operation.

Figure 13. External Data Memory Cycles without Wait-state

(SRWn1 = 0 and SRWn0 =0)(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector).

The ALE pulse in period T4 is only present if the next instruction accesses the RAM

(internal or external).

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector)

The ALE pulse in period T5 is only present if the next instruction accesses the RAM

(internal or external).

Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector).

The ALE pulse in period T6 is only present if the next instruction accesses the RAM

(internal or external).

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLK

CPU

)

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

T4 T5

28 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector).

The ALE pulse in period T7 is only present if the next instruction accesses the RAM

(internal or external).

XMEM Register

Description

MCU Control Register –

MCUCR

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,

A15: 8, AL E, WR, and RD are activated as the alternate pin functions. The SRE bit over-

rides any pin direction settings in the respective Data Direction Registers. Writing SRE

to zero, disables the External Memory Interface and the normal pin and data direction

settings are used.

• Bit 6 – SRW10: Wait State Select Bit

For a detail ed d es crip tio n, s ee comm on descriptio n for the SRW n bi ts bel ow ( EMC UCR

description).

Extended MCU Control

• Bit 6..4 – SRL2, SRL1, SRL0: Wait State Sector Limit

It is po ssible to config ure diffe rent wa it-sta tes for diff erent externa l memory addres ses.

The external memory address space can be divided in two sectors that have separate

wait-state bits. The SRL2, SRL1, and SRL0 bits select the splitting of these sectors, see

Table 2 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and

the entire external memory address space is treated as one sector. When the entire

SRAM add re ss s pac e i s co nfig ur ed as one se cto r, the wai t-sta tes ar e c onf igu re d by th e

SRW11 and SRW10 bits.

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

DataPrev. data Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

T4 T5 T6

Bit 76543210

SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

ATmega162(V/U/L)

2513C–AVR–09/02

• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait-state Select Bits for Upper

Sector

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of

the external memory address space, see Table 3.

• Bit 3..2 – SRW01, SRW00: Wait-state Select Bits for Lower Sector

The SRW01 and SRW00 bits control the number of wait-states for the lower sector of

the external memory address space, see Table 3.

Note: 1. n = 0 or 1 (lower/upper sector).

For further detai ls of th e tim ing and wait-states of the External Memory Inte rfac e, se e

Figure 13 to Figure 16 how the setting of the SRW bits affects the timing.

Table 2. Sector Limits with Different Settings of SRL2..0

SRL2 SRL1 SRL0 Sector Limits

000Lower sector = N/A

Upper sector = 0x1100 - 0xFFFF

001Lower sector = 0x1100 - 0x1FFF

Upper sector = 0x2000 - 0xFFFF

010Lower sector = 0x1100 - 0x3FFF

Upper sector = 0x4000 - 0xFFFF

011Lower sector = 0x1100 - 0x5FFF

Upper sector = 0x6000 - 0xFFFF

100Lower sector = 0x1100 - 0x7FFF

Upper sector = 0x8000 - 0xFFFF

101Lower sector = 0x1100 - 0x9FFF

Upper sect or = 0xA000 - 0xFFFF

110Lower sector = 0x1100 - 0xBFFF

Upper sector = 0xC000 - 0xFFFF

111Lower sector = 0x1100 - 0xDFFF

Upper sect or = 0xE000 - 0xFFFF

Table 3. Wait-states(1)

SRWn1 SRWn0 Wait-states

0 0 No wait-states

0 1 Wait one cycle during re ad/wr ite strobe

1 0 Wait two cycles during read/write strobe

11Wait two cycles during read/write and wait one cycle before driving out

new addres s

30 ATmega162(V/U/L) 2513C–AVR–09/02

Special Function IO Register –

SFIOR

• Bit 6 – XMBK: External Memory Bus Keeper Enable

Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper

is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface

has tri-stated the lines. Writing XMBK to zero disables the Bus Keeper. XMBK is not

quali fied wit h SRE, so even if th e XMEM i nterfa ce is dis abled, th e bus keep ers are s till

activated as long as XMBK is one.

• Bit 6..3 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memory is enabled, all Port C pins are used for the high address

byte by default. If the full 60KB address space is not required to access the external

memory, some, or all, Port C pins can be released for normal Port Pin function as

described in Table 4. As described in “Using all 64KB Locations of External Memory” on

page 32, it is po ss ib le to use the XMM n bi ts to ac c ess al l 64K B l oca tio ns of the ex ter na l

memory.

Using all Locations of

External Memory Smaller than

64 KB

Since the ex ternal memo ry is mappe d after the int ernal me mory as sho wn in Figur e 11,

the external memory is not addressed when addressing the first 1,280 bytes of data

space . It may appea r that the firs t 1,280 bytes of the extern al memory are inacce ssibl e

(external memory addresses 0x0000 to 0x04FF). However, when connecting an exter-

nal memory smaller than 64 KB, for example 32 KB, these locations are easily accessed

simply by addressing from address 0x8000 to 0x84FF. Since the External Memory

Addres s bit A15 is not conn ec ted to the ex ter na l memor y , addre ss es 0x8 000 to 0x 84FF

will appear as addresses 0x0000 to 0x04FF for the external memory. Addressing above

addres s 0x84FF is no t recommende d, since thi s will address an external me mory loca-

tion that is already accessed by another (lower) address. To the Application software,

the external 32 KB memory will appear as one linear 32 KB address space from 0x0500

to 0x84FF. This is illustrated in Figure 17. Memory configuration B refers to the

ATmega161 compatibility mode, configuration A to the non-compatible mode.

Bit 7654321 0

TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0000000 0

Ta bl e 4 . Port C Pins Released as Normal Port Pins when the External Memory is

Enabled

XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins

0 0 0 8 (Full 60 KB space) None

0017 PC7

0106 PC7 - PC6

0115 PC7 - PC5

1004 PC7 - PC4

1013 PC7 - PC3

1102 PC7 - PC2

1 1 1 No Address high bi ts Full Port C

ATmega162(V/U/L)

2513C–AVR–09/02

When the device is set in ATmega161 compatibility mode, the internal address space is

1,120 bytes. This implies that the first 1,120 bytes of the external memory can be

access ed at addr esses 0x80 00 to 0x8 45F. T o t he A pplica tion softw are, th e ex tern al 32

KB memory will appear as one linear 32 KB address space from 0x0460 to 0x845F.

Figure 17. Address Map with 32 KB External Memory

0x0000

0x04FF

0xFFFF

0x0500

0x7FFF

0x8000

0x84FF

0x8500

0x0000

0x04FF

0x0500

0x7FFF

Memory Configuration A Memory Configuration B

Internal Memory

(Unused)

AVR Memory Map External 32K SRAM

External

Memory

0x0000

0x045F

0xFFFF

0x0460

0x7FFF

0x8000

0x845F

0x8460

0x0000

0x045F

0x0460

0x7FFF

Internal Memory

(Unused)

AVR Memory Map External 32K SRAM

External

Memory

32 ATmega162(V/U/L) 2513C–AVR–09/02

Using all 64KB Locations of

Exte rnal Mem o r y Since the ex ternal memo ry is mappe d after the int ernal me mory as sho wn in Figur e 11,

only 64,256 Bytes of external memory are available by default (address space 0x0000

to 0x05FF is reserved for internal memory). However, it is possible to take advantage of

the entire external memory by masking the hi gher address bits to zero. This can be

done by using the XMMn bits and control by software the most significant bits of the

address. By setting Port C to output 0x00, and releasing the most significant bits for nor-

mal Port Pin operation, the Memory Interface will address 0x0000 - 0x1FFF. See code

example below.

Note: 1. The example code assumes that the part specific header file is included.

Care must be exercised using this option as most of the memory is masked away.

Assembly Code Examp le(1)

; OFFSET is defined to 0x2000 to ensure

; external memory access

; Configure Port C (address high byte) to

; output 0x00 when the pins are released

; for normal Port Pin operation

ldi r16, 0xFF

out DDRC, r16

ldi r16, 0x00

out PORTC, r16

; release PC7:5

ldi r16, (1<<XMM1)|(1<<XMM0)

out SFIOR, r16

; write 0xAA to address 0x0001 of external

; memory

ldi r16, 0xaa

sts 0x0001+OFFSET, r16

; re-enable PC7:5 for external memory

ldi r16, (0<<XMM1)|(0<<XMM0)

out SFIOR, r16

; store 0x55 to address (OFFSET + 1) of

; external memory

ldi r16, 0x55

sts 0x0001+OFFSET, r16

C Code Example(1)

#define OFFSET 0x2000

void XRAM_example(void)

{

unsigned char *p = (unsigned char *) (OFFSET + 1);

DDRC = 0xFF;

PORTC = 0x00;

SFIOR = (1<<XMM1) | (1<<XMM0);

*p = 0xaa;

SFIOR = 0x00;

*p = 0x55;

}

ATmega162(V/U/L)

2513C–AVR–09/02

System Clock and

Clock Op tions

Clock Systems and their

Distribution Figure 18 presents the principal clock sy stems in the AVR and their distribution. All of

the clocks need not be active at a given time. In order to reduce power consumption, the

clocks to modules not bein g used can be halted by usin g different sleep m odes, as

descr ibed in “Power Ma nagement and Sl eep Modes” on page 41. The clock syste ms

are detailed below.

Figure 18. Clock Distribution

CPU clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR

core. Examples of such modules are the General Purpose Register File, the Status Reg-

ister and the data m emor y holdin g the Sta ck Poi nter. Hal ting th e C PU cloc k inh ibits the

core from performing general operations and calculations.

I/O clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and

USART. The I/O clock is also used by the External Interrupt module, but note that some

external interr upts are detected by asynchronou s logic, allowing such interr upts to be

detected even if the I/O clock is halted.

Flash clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually

active simultaneously with the CPU clock.

Asynchronous Timer clock –

clkASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked

direct ly fr om a n e xte rn al 32 k Hz c lock c rys tal . Th e ded ic ated c lo ck domain al lo ws us in g

this Timer/Counter as a realtime counter even when the device is in sleep mode.

General I/O

Modules

Asynchronous

Timer/Counter CPU Core RAM

clk

I/O

clk

ASY

AVR Clock

Control Unit clk

CPU

Flash and

EEPROM

clk

FLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Timer/Counter

Oscillator Crystal

Oscillator Low-frequency

Crystal Oscillator

External Clock

34 ATmega162(V/U/L) 2513C–AVR–09/02

Clock Sources The device has the following clock source options, selectable by F lash Fuse bits as

shown below. The clock from the selected source is input to the AVR clock generator,

and routed to the appropriate modules.

Note: For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the

CPU w akes up from Powe r-d own or Po wer-s ave, th e selec ted clo ck sour ce is use d to

time the start-up, ensuring stable Oscillator operation before instruction execution starts.

When the CPU starts from Reset, there is an addi tional delay allowing the power to

reach a stable level before commencing normal operation. The Watchdog Oscillator is

used for timing this realtime part of the start-up time. The number of WDT Oscillator

cycles used for each Time-out is shown in Table 6. The frequency of the Watchdog

Oscilla tor is v olta ge dependen t as sh own i n “AT me ga1 62 T ypi ca l Character istic s – Pr e-

liminary Data” on page 271.

Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10” and CKDIV8 programmed. The

default clock source setting is therefore the Internal RC Oscillator with longest startup

time and an initial sys tem clock pr escaling of 8. This default setting ensures that all

users can make their desired clock source setting using an In-System or Parallel

programmer.

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can

be configured for use as an On-chip Oscillator, as shown in Figure 19. Either a quartz

crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value

of the capacitors depends on the crystal or resonator in use, the amount of stray capac-

itance, and the electromagnetic noise of the environment. Some initial guidelines for

choosing capacitors for use with crystals are given in Table 7. For ceramic resonators,

the capacitor values given by the manufacturer should be used.

Table 5. Device Clocking Options Select

Device Clocking Option CKSEL3..0

External Crystal/Ceramic Resonator 1111 - 1000

External Low -fr equ enc y Cr ys tal 0111 - 0100

Calibrated Internal RC Oscillator 0010

External Cloc k 0000

Reserved 0011, 0001

Table 6. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

4.1 ms 4.3 ms 4K (4,096 )

65 ms 69 ms 64K (65,536)

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 19. Crystal Oscillator Connections

The Oscillator can operate in four different modes, each optimized for a specific fre-

quency range. The oper ating mode is selected by the fuses CKSEL3:1 as shown in

Table 7.

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 F use together wit h the SUT1..0 Fus es select the start-up times as shown

in Table 8.

Table 7. Crystal Oscillator Operating Modes

CKSEL3:1 Frequency Range

(MHz)(1) Recommended Range for Capacitors C1 and

C2 for Use with Crystals (pF)

100(2) 0.4 - 0.9 –

101 0.9 - 3.0 12 - 22

110 3.0 - 8.0 12 - 22

111 8.0 - 12 - 22

Table 8. Start-up Times for the Crystal Oscillator Clock Selection

CKSEL0 SUT1:0

Start-up Time from

Power-down and

Power-save Additional Delay from

Reset (VCC = 5.0V) Recommended

Usage

000 258 CK

(1) 4.1 ms Ceramic resonator,

fast rising power

001 258 CK

(1) 65 ms Ceramic resonator,

sl owly rising power

010 1K CK

(2) – Ceramic resonator,

BOD enabled

011 1K CK

(2) 4.1 ms Ceramic resonator,

fast rising power

100 1K CK

(2) 65 ms C eramic resonator,

sl owly rising power

XTAL2

XTAL1

GND

36 ATmega162(V/U/L) 2513C–AVR–09/02

Notes: 1. These options should only be used when not operating close to the maximum fre-

quency of the de vice, and only if freque ncy sta bi lity at s tart-u p is not i mp ortan t for th e

application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure fre-

quency stability at start-up. They can also be used with crystals when not operating

close to the maximum frequency of the device, and if frequency stability at start-up is

not important for the application.

Low-frequency Crystal

Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre-

quency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0100”,

“0101”, “0110” or “0111”. The crystal should be connected as s hown in Figure 19. If

CKSEL equals “0110” or “0111”, the internal capacitors on XTAL1 and XTAL2 are

enabled, thereby removing the need for external capacitors. The internal capacitors

have a nominal value of 10 pF.

When this Oscillator is selected, start-up times are determined by the SUT Fuses (real

time-ou t from R eset) and CKSEL0 (number o f clock cycles) as sh own in Ta ble 9 an d

Table 10.

Note: 1. These options should only be used if frequency stability at start-up is not important for

the application.

1 01 16K CK – Crystal O scillator,

BOD enabled

1 10 16K CK 4.1 ms Crys tal Oscillator,

fast rising power

1 11 16K CK 65 ms Crystal Oscillator,

sl owly rising power

Table 8. Start-up Times for the Crystal Oscillator Clock Selection (Continued)

CKSEL0 SUT1:0

Start-up Time from

Power-down and

Power-save Additional Delay from

Reset (VCC = 5.0V) Recommended

Usage

Table 9. Start-up Delay from Reset when Low-frequency Crystal Oscillator is Selected

SUT1:0 Additional Delay from Reset (VCC = 5.0V) Recommended Usage

00 0 ms Fast rising power or BOD enabled

01 4.1 ms Fast rising power or BOD enabled

10 65 ms Slowly rising power

11 Reserved

Table 10. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

CKSEL1:0 Internal Capacitors

Enabled?

Start-up Time from

Power-down and

Power-save Recommended Usage

00(1) No 1K CK

01 No 32K CK Stable Frequency at start-up

10(1) Yes 1K CK

11 Yes 32K CK Stable Frequency at start-up

ATmega162(V/U/L)

2513C–AVR–09/02

Calibrated Inte rnal RC

Oscillator The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is

nominal value at 3V and 25°C. If 8.0 MHz frequency exceed the specification of the

device (de pen ds on V CC), the CK DIV8 Fu se mus t be program med in or der to divi de the

internal frequ ency by 8 during star t-up. See “Sy stem Clock Pres caler” on p age 39 for

more details. This clock may be selected as the system clock by programming the

CKSEL Fus es as shown in T able 11 . If selecte d, it wil l operate with no ex tern al compo-

nents. During Reset, hardware loads the calibration byte into the OSCCAL Register and

thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration gives

a frequency within ± 1% of the nominal frequency. When this Oscillator is used as the

chip cl oc k, the W atc hd og O sci ll ato r wi ll s til l b e us ed f or the W atc hd og Ti mer an d fo r th e

Reset Time-out. For more information on the pre-programmed calibration value, see the

section “Calibration Byte” on page 231.

Note: 1. The device is shipped with this option selected.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as

shown in Table 12. XTAL1 and XTAL2 should be left unconnected (NC).

Note: 1. The device is shipped with this option selected.

Oscillator Calibration Register

– OSCCAL

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the Internal Oscillator to remove pro-

cess variations from the Oscillator frequency. This is done automatically during Chip

Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-

zero va lues to this registe r will incr ease th e frequen cy of the Inter nal Osc illato r. Writin g

0x7F to the register giv es the highest available frequency. T he calibrated Oscillator is

used to t ime EEPR OM and Fl ash access . If EEPRO M or Flash is writte n, do not cal i-

brate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash

write may fail.

Table 11. Internal Calibrated RC Oscillator Operating Modes

CKSEL3:0 Nominal Frequency

0010(1) 8.0 MHz

Table 12. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

SUT1:0 Start-up Time from Power-

down and Power-save Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

00 6 CK – BOD enab led

01 6 CK 4.1 ms Fast rising power

10(1) 6 CK 65 ms Slowly rising power

11 Reserved

Bit 76543210

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value Device Specific Calibration Value

38 ATmega162(V/U/L) 2513C–AVR–09/02

Exter nal Cloc k To drive the d ev ice fr om an ex te rn al cl ock s ourc e, X T AL 1 sh oul d be driv en as sho wn i n

Figure 20. To run the device on an external clock, the CKSEL Fuses must be pro-

grammed to “0000”.

Figure 20. External Clock Drive Configuration

When this cl ock sourc e is sele cted, sta rt-u p times are d etermine d by the SU T Fuses as

shown in Table 14.

When applying an external clock, it is required to avoid sudden changes in the applied

clock frequency to ensure stable operation of the MCU. A variation in frequency of more

than 2% from one clock cycle to the next can lead to unpredictable behavior. It is

required to ensure that the MCU is kept in reset during such changes in the clock

frequency.

Note that the System Clock Presc aler can be used to implement r un-time ch anges of

the internal clock frequency while still ensuring stable operation. Refer to “System Clock

Prescaler” on page 39 for details.

Table 13. Internal RC Oscillator Frequency Range.

OSCCAL Value Min Frequency in Percentage of

Nominal Frequency Max Frequency in Percentage of

Nominal Frequency

0x00 50% 100%

0x3F 75% 150%

0x7F 100% 200%

0x80 - 0xFF Reserv ed

Table 14. Start-up Times for the External Clock Selection

SUT1..0

Start-up Time from

Power-down and

Power-save Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

00 6 CK – BOD enabled

01 6 CK 4.1 ms Fast rising power

10 6 CK 65 ms Slowl y rising power

11 Reserved

EXTERNAL

CLOCK

SIGNAL

ATmega162(V/U/L)

2513C–AVR–09/02

Clock output buffer When the CKOUT Fuse is programmed, the system clock will be output on PortB 0. This

mode is suitable when chip clock is used to drive other circuits on the system. The clock

will be ou tput also durin g Reset an d the normal op eration of Po rtB will be over ridden

when the fuse is programmed. Any clock sources, including Internal RC Oscillator, can

be selected when PortB 0 serves as clock output.

If the system clock prescaler is used, it is the divided system clock that is output when

the CKOUT Fuse is programmed. See “System Clock Prescaler” on page 39. for a

description of the system clock prescaler.

Timer/Counter Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the

crystal is connected directly between the pins. The Oscillator provides internal capaci-

tors on TOSC1 and TOSC2, thereby removing the need for external capacitors. The

internal cap acitors have a nominal valu e of 10 pF. The Oscillator is optimized for use

with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not

recommended.

System Clock P rescal er The ATmega162 system clock can be divided by setting the Clock Prescale Register –

CLKPR. T his feature can be use d to decrease powe r consum ption when the re quire-

ment for pr ocessi ng power is lo w. This can be used wit h all cl ock source op tions , and it

will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkCPU,

and clkFLASH are divided by a factor as shown in Table 15. Note that the clock frequency

of clkASY ( asynchronously Timer/Counter) only will be scaled if the Timer/Counter is

clocked synchronously.

Clock Prescale Register –

CLKPR

• Bit 7 – CPCE: Clock Prescaler Change Enable

The CPCE bit must be written to logic one to enable change of the CLKPS bits. CPCE is

cleared b y har dware four cy cles af ter i t is wri tten or when CL KPS is writ ten. Se ttin g the

CPCE bit will disable interrupts, as explained in the CLKPS description below.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits defi ne the d ivisio n facto r betwe en the selec ted cl ock so urce and the inter nal

syst em clock. T hese bits can be wri tten run- time to var y the clock freque ncy to suit th e

appli cation re quirem ents. As th e divid er divides the master clock input to the MC U, the

speed of all synchronous peripherals is reduced when a division factor is used. The divi-

sion factors are given in Table 15.

To avoid unintentional changes of clock frequency, a spec ial write procedure must be

followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CPCE) bit to one and all other bits in

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to

CPCE.

Caution: An interrup t bet ween step 1 an d s tep 2 wil l make the time d sequence fa il. It is

recomm end ed to ha ve the G lo bal I nterr upt Flag c le ared du ri ng th es e ste ps t o avoid t his

problem.

Bit 76543210

CPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

40 ATmega162(V/U/L) 2513C–AVR–09/02

The CKDIV8 Fuse determines the initial value o f the CLKPS bits. If CKDIV8 is unpro-

grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits

are reset to “0100”, giving a division factor of 8 at start up. This feature should be used if

the selected cloc k source has a higher frequency than the maximum frequency of the

device at the present operating conditions. Note that any value can be written to the

CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must

ensure that a sufficient division factor is chosen if the selected clock source has a higher

frequen cy than the maxi mum frequency of the device at the pres ent operating c ondi-

tions. The device is shipped with the CKDIV8 Fuse programmed.

Table 15. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

00001

00012

00104

00118

010016

010132

011064

0111128

1000256

1001Reserved

1010Reserved

1011Reserved

1100Reserved

1101Reserved

1110Reserved

1111Reserved

ATmega162(V/U/L)

2513C–AVR–09/02

Power Management

and Sleep Modes Sleep mo des en abl e th e ap pli cati on to sh ut down unus ed mod ul es in t he M CU, th er eby

saving power. The AVR provides various sleep modes allowing the user to tailor the

power consumption to the application’s requirements.

To enter any of the fiv e s leep mo des , the SE bit i n MCU CR mus t be writte n to lo gi c on e

and a SLEEP instruc tion must be executed. The SM 2 bit in MCUCSR, the SM 1 bit in

MCUCR, and the SM0 bit in the EMCUCR Register select which sleep mode (Idle,

Power-down, Power-save, Standby, or Extended Standby) will be activated by the

SLE EP in struction. S e e Tab l e 16 for a s um ma ry . I f an en a bl e d i n t err up t o cc ur s wh il e t he

MCU is in a sleep mode, the MCU wakes up. The MCU is then hal ted for four cycles in

addi t io n t o t he s tar t - up ti me , exe cu t es th e int e rr u pt ro ut i ne , an d r esu me s ex ecution fr om

the instruction following SLEEP. The contents of the Register File and SRAM are unal-

tered when the device wakes up from sleep. If a Reset occurs during sleep mode, the

MCU wakes up and executes from the Reset Vector.

Figure 18 on p age 33 pr e sen ts the d iff er ent clo ck s yst e ms in t he A T meg a16 2, an d the ir

distribution. The figure is helpful in selecting an appropriate sleep mode.

MCU Control Register –

MCUCR

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the

SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is

the prog ra mm er’s pu rp ose, it is rec omm end ed to write the Slee p Enable (SE ) bit to one

just before the exe cu tio n of the S LE EP in str u cti on a nd t o c lea r it i mme di atel y a fter wa k-

ing up.

• Bit 4 – SM1: Sleep Mode Select Bit 1

The Sle ep Mode Selec t bits s elect b etween th e five avail able s leep mod es a s show n in

Table 16.

MCU Control and Status

• Bit 5 – SM2: Sleep Mode Select Bit 2

The Sle ep Mode Selec t bits s elect b etween th e five avail able s leep mod es a s show n in

Table 16.

Bit 76543210

SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

JTD –SM2JTRF WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

42 ATmega162(V/U/L) 2513C–AVR–09/02

Extended MCU Control

• Bit 7 – SM0: Sleep Mode Select Bit 0

The Sle ep Mode Selec t bits s elect b etween th e five avail able s leep mod es a s show n in

Table 16.

Note: 1. Standby mode and Extended Standby mode are only available with external crystals

or resonators.

Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter

Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator,

Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as

internal ones like the Timer Overflow and USART Transmit Complete interrupts. If

wake-up from the Analog Comparator interrupt is not required, the Analog Comparator

can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-

tus Register – ACSR. This will reduce power consumption in Idle mode.

Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the external Oscillator is stopped, while the external

inte rrupts and the Watchdog continue operatin g (if enab led). Only an Externa l Reset, a

Watchdog Reset, a Br own-out Reset, an External Level Interrupt on INT0 or INT1, an

external interrupt on INT2, or a pin change interrupt can wake up the MCU. This sleep

mode ba sically halts all gen erated cloc ks, allo wing opera tion of asyn chronou s modules

only.

Note tha t if a level trig gered inter rupt is used fo r wake-up from Power-dow n mode, the

changed level must be held for some time to wake up the MCU. Refer to “External Inter-

rupts” on page 82 for details.

When wak ing up fro m Power-d own mode, there is a delay from the wa ke-up co nditio n

occurs until the wake-up becomes effective. This allows the clock to restart and become

stable after having been stopped. The wake-up period is defined by the same CKSEL

Fus es that de fine th e Rese t Tim e-out pe riod , as de scrib ed in “Cl ock Source s” on pa ge

34.

Bit 76543210

SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 16. Sleep Mode Sele ct

SM2 SM1 SM0 Sleep Mode

000Idle

0 0 1 Reserved

0 1 0 Power-down

0 1 1 Power-save

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Standby(1)

1 1 1 Extended Standby(1)

ATmega162(V/U/L)

2513C–AVR–09/02

Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter

Power-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,

Timer/Counter2 will run during sleep. The device can wake up from either Timer Over-

flow or Output Compare event from Timer/Counter2 if the corresponding

Time r/Counte r2 inte rrupt en able bi ts are se t in TIMS K, and the Global Interru pt Enab le

bit in SREG is set.

If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is rec-

ommende d instead of Po wer-save mo de because the c ontents of th e registers in the

Asynchr onous Ti mer should be co nsidered u ndefined after wake- up in Po wer-save

mode if AS2 is 0.

This sleep mode basically halts all clocks except clkASY, allowing operation only of asyn-

chronous modules, including Timer/Counter 2 if clocked asynchronously.

Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to

Power-down with the exception that the main Oscillator is kept running. From Standby

mode, the device wakes up in six clock cycles.

Extended Standby Mode When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is

identical to Power-save mode with the exception that the main Oscillator is kept running.

From Extended Standby mode, the device wakes up in six clock cycles.

Notes: 1. External Crysta l or res onator selected as clock source

2. If AS2 bit in ASSR is set

3. For INT1 and INT0, only level interrupt

Table 17. Active Clock domains and Wake up sources in the different sleep modes

Active Clock domains Oscillators Wa ke-up Sources

Sleep Mode clkCPU clkFLASH clkIO clkASY

Main Cl ock

Source Enabled Timer Osc

Enabled

INT2

INT1

INT0

and Pin Change Timer2

SPM/

EEPROM

Ready Other

I/O

Idle X X X X(2) XXXX

Power-down X(3)

Power-save X(2) X(2) X(3) X(2)

Standby(1) XX

(3)

Extended Standby(1) X(2) XX

(2) X(3) X(2)

44 ATmega162(V/U/L) 2513C–AVR–09/02

Minimizing Power

Consumption There are se veral is su es to c ons i der w hen tr ying to mi ni mi ze the p ower co nsu mption i n

an AVR c ontro lled sy stem. I n general , slee p modes sh ould be used as much as p ossi-

ble, and the sleep mode should be selected so that as few as possible of the device’s

functions are operating. All functions not needed should be disabled. In particular, the

following modules may need special consideration when trying to achieve the lowest

possible power consumption.

Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not needed. In

the other sleep m odes, the Analog Comp arator is automatic ally disa bled. Howev er, if

the Analog Comparator is set up to use the Internal Voltage Reference as input, the

Analog Com parato r should be disabl ed in all sle ep modes . Otherwis e, the Inter nal Vo lt-

age Reference will be enabled, independent of sleep mode. Refer to “Analog

Comparator” on page 192 for details on how to configure the Analog Comparator.

Brown-out Detector If the Brown- out Detect o r is not n eed ed i n the app li ca tio n, th is mod ul e sh oul d b e turned

off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in

all sleep modes , and hence, always consume power. In the deeper sleep mod es, this

will contr ibute sig nificant ly to the total current consu mption. Re fer to “Bro wn-out Dete c-

tion” on page 48 for details on how to configure the Brown-out Detector.

Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detector

or the Analog Comparator. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming

power. When turned on again, the user must allow the reference to start up before the

output is used. If t he refe rence is kept on in sleep mode, th e output c an be us ed im me-

diately. Refer to “Internal Voltage Reference” on page 50 for details on the start-up time.

Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off.

If the Watc hdog Timer is e nabled, it wil l be enabled in all sleep mo des, and hence,

always consume power. In the deeper sleep modes, this will contribute significantly to

the total current consumption. Refer to “Watchdog Timer” on page 50 for details on how

to configure the Watchdog Timer.

Port Pins When enter in g a sl ee p mod e, al l port pi ns shoul d be co nfi gur ed to us e min im um po wer.

The mos t impo rtant thi ng is to ensur e that n o pins drive resistiv e loa ds. In slee p modes

where the I/O clock (clk I/O) is stopped, the input buffers of the dev ice will be disabl ed.

This ensures that no power is consumed by the input logic when not needed. In some

cases, the input logic is needed for detecting wake-up conditions, and it will then be

enable d. Refer to the section “D igital Input E nable and Sl eep Modes” on page 65 for

details on which pins are enabled. If the input buffer is enabled and the input signal is

left floating or have an analog signal level close to VCC/2, the input buffer will use exces-

sive p ower.

On-chip Debug System If the On-chip Debug System is enabled by the OCDEN Fuse, and the chip enter sleep

mode , the main cloc k source r emains enab led, and hen ce, th is will cont ribute si gnifi-

cantly to the total current consumption.

There are three alternative ways to disable the OCD system:

• Disable OCDEN Fuse

• Disable JTAGEN Fuse

• Write one to the JTD bit in MCUCSR.

ATmega162(V/U/L)

2513C–AVR–09/02

System Control and

Reset

Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts exe-

cution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP

– Absolute Jump – instruction to the reset handling routine. If the program never

enabl es an interru pt source , the Interru pt Vectors are not use d, and regul ar program

code can be pl ac ed at thes e lo ca tio ns . Th is is als o th e c ase if the Reset Ve ctor is in th e

Application section while the Interrupt Vectors are in the Boot section or vice versa. The

circuit diagram in Figure 21 shows the Reset Logic. Table 18 defines the electrical

par ameters of the reset circuitry.

The I/O po rts of th e AVR are i mmedia tely res et to thei r init ial st ate when a res et sourc e

goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the

Interna l Reset. This all ows the power to reach a st able level be fore normal oper ation

starts. The Time-out period of the delay counter is defined by the user through the

CKSEL Fuse s. The different selections for the delay period are presented in “Clock

Sources” on page 34.

Reset Sources The ATmega162 has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (VPOT).

• External Reset. The MCU is reset when a low level is present on the RESET pin f or

longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and

the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the

Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled. The

device is guaranteed to operate at maximum frequency for the VCC voltage down to

VBOT. VBOT must be set to the corresponding minimum voltage of the device (i.e.,

minimum VBOT for ATmega162V is 1.8V).

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset

1149.1 (JTAG) Boundary-scan” on page 201 for details.

46 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 21. Reset Logic

Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT

(falling)

Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-

tion level is defined in Table 18. The POR is activated whenever VCC is below the

detectio n level . The PO R circuit ca n be used to trigger the Start- up Rese t, as wel l as to

detect a failure in supply voltage.

A Power-on Re set (POR) circuit ensures that the device is Reset from Power-on.

Reaching the Power-on Reset threshold voltage invokes the delay counter, which deter-

mines how long the device is kept in RESET after VCC rise. The RESET signal is

activated again, without any delay, when VCC decreases below the detection level.

Table 18. Reset Characteristics

Symbol Parameter Condition Min. Typ. Max. Units

VPOT

Power-on Reset Threshold Voltage

(rising) 1.2 V

Power-on Reset Threshold Voltage

(falling)(1) 1.1 V

VRST RESET Pin Threshold Voltage 0.2 0.85 VCC

tRST Minimum pulse width on RESET Pin 50 ns

tBOD Minimum lo w voltage period for

Brown-out detection. 2µs

MCU Control and Status

BODLEVEL [ 2..0]

Delay Counters

CKSEL[3:0]

CK TIMEOUT

WDRF

BORF

EXTRF

PORF

DATA BUS

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

JTRF

JTAG Reset

Watchdog

Oscillator

SUT[1:0]

Watchdog

Timer

RESET Reset Circuit

Brown-out

Reset Circuit

Power-on

Reset Circuit

COUNTER RESET

INTERNAL RESET

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 22. MCU Start-up, RESET Tied to VCC.

Figure 23. MCU Start-up, RESET Extended Externally

Extern al Rese t An External Reset is generated by a low level on the RESET pin. Reset pulses longer

than the min imum pulse width ( see Table 18) will gen erate a Reset, even if the cl ock is

not ru nning. Shorter pulses are not guarant eed to ge nerat e a Reset . When th e applie d

signal reaches the Reset Threshold Voltage – VRST on its positive edge, the delay

counter starts the MCU after the Time-out period tTOUT has expired.

Figure 24. External Reset During Operation

RESET

TIME-OUT

INTERNAL

RESET

tTOUT

VPOT

VRST

RESET

TIME-OUT

INTERNAL

RESET

tTOUT

VPOT

VRST

48 ATmega162(V/U/L) 2513C–AVR–09/02

Brown-out Detection ATmega162 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC

leve l during operation by comparing it to a fixed trig ger level. The t rigger le vel for the

BOD can be selec ted by the BODLEVE L Fuses. The trigge r level has a hyst eresis to

ensure spike free Brown-o ut Detection. The hys teresis on the det ection level sh ould be

interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.

Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For

devices where this is the case, the device is tested down to VCC = VBOT during the

productio n tes t. T his gua ran tee s th at a Brown-out Reset will o cc our b efo re V CC d rops

to a voltage where correct operation of the microcontroller is no longer guarateed.

This test is performed using BODLEVEL = 110 for ATmega162V, BODLEVEL = 101

for ATmega162L, and BODLEVEL = 100 for ATmega162.

2. BODLEVEL = 011 for ATmega162U. Otherwise reserved.

When the BOD is enabled and VCC decreases to a value below the trigger level (VBOT- in

Figure 25), the Brown-out Reset is immediately activated. When VCC increases above

the trigger level (VBOT+ in Figure 25), the delay counter starts the MCU after the Time-

out period tTOUT has expired.

The BOD c ir cuit wil l o nl y d etect a drop in V CC i f the v olta ge sta ys be low the trigg er le ve l

for longer than tBOD given in Table 18.

Table 19. BODLEVEL Fuse Coding

BODLEVEL Fuses [2:0] Min. VBOT(1) Typ. VBOT Max. VBOT Units

111 BOD Disabled

110 1.8

101 2.7

100 4.3

011(2) 2.3

010

Reserved001

000

Table 20. Brown-out Hysteresis

Symbol Parameter Min. Typ. Max. Units

VHYST Brown-out Detector hysteresis 50 mV

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 25. Brown-out Reset During Operation

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period

tTOUT. Refer to page 50 for details on operation of the Watchdog Timer.

Figure 26. Watchdog Reset During Operation

MCU Control and Status

caused an MCU Reset.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused b y a logic one in th e JTAG Reset Register

selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or

by writing a logic zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

VCC

RESET

TIME-OUT

INTERNAL

RESET

VBOT- VBOT+

tTOUT

Bit 76543210

JTD –SM2 JTRF WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 See Bit Description

50 ATmega162(V/U/L) 2513C–AVR–09/02

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a P ower-on Rese t occurs . The bit is reset onl y by wri ting a lo gic ze ro to

the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and

then Reset the MCUCSR as early as possible in the program. If the register is cleared

before another reset occurs, the source of the Reset can be found by examining the

Reset Flags.

Internal Voltage

Reference ATmega162 features an internal bandgap reference. This reference is used for Brown-

out Detection, and it can be used as an input to the Analog Comparator.

Voltage Reference Enable

Signals and Start-up Time The voltage reference has a st ar t-u p time that m ay in fluence t he w ay it sh oul d b e u se d.

The start-up time is given in Table 21. To save power, the reference is not always turned

on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL Fuses).

2. When the bandgap reference is connected to the Analog Comparator (by setting

the ACBG bit in ACSR).

Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always

allow the reference to start up before the output from the Analog Comparator is used. To

reduce power consumption in Power-down mode, the user can avoid the two conditions

above to ensure that the reference is turned off before entering Power-down mode.

Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at

1 MHz. This is the typical frequency at VCC = 5V. See characterization data for typical

values at oth er VCC lev els. B y con trol ling th e W atchd og Ti mer pr escal er, the Wa tchdo g

Reset interval can be adjusted as shown in Table 23 on page 52. The WDR – Watchdog

Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when

it is di sabled and when a Chip Reset o ccurs . Eight di fferen t clock cycle p eriod s can be

selected to determine the reset period. If the reset period expires without another

Watchd og Reset, the AT mega16 2 resets and ex ecutes fro m the Reset Vec tor. For tim-

ing details on the Watchdog Reset, refer to page 52.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out

period, 3 different safety levels are selected by the Fuses M161C and WDTON as

Table 21. Internal Voltage Reference Characteristics

Symbol Parameter Min. Typ. Max. Units

VBG Bandgap reference voltage 1.1 V

tBG Bandgap reference start-up time 40 70 µs

IBG Bandgap reference current

consumption 10 µA

ATmega162(V/U/L)

2513C–AVR–09/02

shown in Table 22. Safety level 0 corresponds to the setting in ATmega161. There is no

restric tion on enablin g the WDT in any of the safety le vels. Refer to “Timed Sequ ences

for Changing the Configuration of the Watchdog Timer” on page 54 for details.

Figure 27. Watchdog Timer

Watchdog Timer Control

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATmega162 and will always read as zero.

• Bit 4 – WDCE: Watchdog Change Enable

This bit mus t be set when the WDE bit is written to logi c zer o. O therwi se , the W atc hdo g

will not be disabl ed. Once written to one, hardware will clear this bit after four c lock

cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In

Safety Levels 1 and 2, this bit must also be set when changing the prescaler bits. See

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 54.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is

written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared

Ta b l e 2 2 . WDT Configuration as a Function of the Fuse Settings of M161C and

WDTON.

M161C WDTON Safety

Level

WDT

Initial

State How to Disable

the WDT

How to

Change Tim e-

out

Unprogrammed Unprogrammed 1 Disabled Timed sequence Timed

sequence

Unprogrammed Prog rammed 2 Enabled Alway s enabled Timed

sequence

Programmed Unprogrammed 0 Disabled Timed sequence No restriction

Programmed Programmed 2 Enabled Always enabled Timed

sequence

WATCHDOG

OSCILLATOR

Bit 76543210

– – – WDCE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

52 ATmega162(V/U/L) 2513C–AVR–09/02

if the WDCE bit has lo gic le vel one . To disabl e an enabl ed Watc hdog Time r, the foll ow-

ing procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be

written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the

Watchdog.

In safety lev el 2, it is not possible to dis able the Watch dog Timer, even with the algo-

rithm desc ribed above. See “Timed Sequence s for Chan ging the Con figuration of the

Watchdog Timer” on page 54.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

Timeout Periods are shown in Table 23.

Table 23. Wat chd og Timer Pr esca le Sel ec t

WDP2 WDP1 WDP0 Number of WDT

Oscillator Cy cle s Typical Time-out

at VCC = 3.0V Typical Time-out

at VCC = 5.0V

0 0 0 16K (16,384) 17 ms 16 ms

0 0 1 32K (32,768) 34 ms 33 ms

0 1 0 65K (65,536) 69 ms 65 ms

0 1 1 128K (131,072) 0.14 s 0.13 s

1 0 0 256K (262,144) 0.27 s 0.26 s

1 0 1 512K (524,288) 0.55 s 0.52 s

1 1 0 1,024K (1,048,576) 1.1 s 1.0 s

1 1 1 2,048K (2,097,152) 2.2 s 2.1 s

ATmega162(V/U/L)

2513C–AVR–09/02

The foll owing co de exam ple show s one asse mbly and one C func tion for tur ning off the

WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts

globally) so that no interrupts will occur during execution of these functions.

Assembly Code Examp le

WDT_off:

; Write logical one to WDCE and WDE

ldi r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example

void WDT_off(void)

{

/* Write logical one to WDCE and WDE */

WDTCR = (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

54 ATmega162(V/U/L) 2513C–AVR–09/02

Timed Sequences for

Changing the

Configuration of the

Watchdog Timer

The sequence for changing configuration differs slightly between the three safety levels.

Separate procedures are described for each level.

Safety Level 0 This mode is compatible with the Watchdog operation found in ATmega161. The Watch-

dog Timer is initia lly disab led, but ca n be ena bled by writing the WD E bit to one witho ut

any restriction. The Time-out period can be changed at any time without restriction. To

disable an enabled Watchdog Timer, the procedure described on page 51 (WDE bit

description) must be followed.

Safety Level 1 In thi s mod e, th e W atchdog Time r is i nit ial ly disabled, bu t c an be e nab led by wr iting the

WDE bit to one wi thou t a ny r est ric tion . A ti me d se q uence is n eede d when c hang in g th e

Watchdo g Time-out p eriod or disab ling an ena bled Watch dog Timer. To disable a n

enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following proce-

dure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be

written to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and

WDP bits as desired, but with the WDCE bit cleared.

Safety Level 2 In thi s mo de, the Watchd og T imer i s al ways en abled, and t he WD E bit will alwa ys rea d

as one. A tim ed s equ enc e is nee ded w hen chan gi ng the Wat chd og T ime- ou t per iod. T o

change the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the

WDE always is set, the WDE must be written to one to start the timed sequence.

2. Within the next four clock cycles, in the same operation, write the WDP bits as

desired, but with the WDCE bit cleared. The value written to the WDE bit is

irrelevant.

ATmega162(V/U/L)

2513C–AVR–09/02

Interrupts This section describes the specifics of the interrupt handling as performed in

ATmega1 62. For a general explanati on of the AVR interr upt handling, refer to “Reset

and Interrupt Handling” on page 12. Table 24 shows the interrupt table when the com-

patibility fuse (M161C) is unprogrammed, while Table 25 shows the interrupt table when

M161C Fuse is programmed. All assembly code examples in this sections are using the

interrupt table when the M161C Fuse is unprogrammed.

Interrupt Vectors in

ATmega162 Table 24. Reset and Interrupt Vectors if M161C is unprogrammed

Vect or No. Program

Address(2) Source Interrupt Definition

1 0x000(1) RESET External Pin, Power-on Reset, Brown-out

Reset, Watchdog Reset, and JTAG AVR

Reset

2 0x002 INT0 External Interrupt Request 0

3 0x004 INT1 External Interrupt Request 1

4 0x006 INT2 External Interrupt Request 2

5 0x008 PCINT0 Pin Change Interrupt Request 0

6 0x00A PCINT1 Pin Change Interrupt Request 1

7 0x00C TIMER3 CAPT Timer/Counter3 Capture Event

8 0x00E TIMER3 COMPA Timer/Counter3 Compare Match A

9 0x010 TIMER3 COMPB Timer/Counter3 Compare Match B

10 0x012 TIMER3 OVF Timer/Counter3 Overflow

11 0x014 TIMER2 COMP Timer/Counter2 Compare Match

12 0x016 TIMER2 OVF Timer/Counter2 Overflow

13 0x018 TIMER1 CAPT Timer/Counter1 Capture Event

14 0x01A TIMER1 COMPA Timer/Counter1 Compare Match A

15 0x01C TIMER1 COMPB Timer/Counter1 Compare Match B

16 0x01E TIMER1 OVF Timer/Counter1 Overflow

17 0x020 TIMER0 COMP Timer/Counter0 Compare Match

18 0x022 TIMER0 OVF Timer/Counter0 Overflow

19 0x024 SPI, STC Serial Transfer Complete

20 0x026 USART0, RXC USART0, Rx Complete

21 0x028 USART1, RXC USART1, Rx Complete

22 0x02A USART0, UDRE USART0 Data Register Empty

23 0x02C USART1, UDRE USART1 Data Register Empty

24 0x02 E USART0, TXC USART0, Tx Complete

25 0x030 USA RT1, TXC USART1, Tx Complete

26 0x032 EE_RDY EEPROM Ready

27 0x034 ANA_COMP Analog Comparator

28 0x036 SPM_RDY Store Program Memory Ready

56 ATmega162(V/U/L) 2513C–AVR–09/02

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader

address at reset, see “Boot Loader Support – Read-While-Write Self-programming”

on page 214.

2. When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of the

Boot Flash section. The address of each Interrupt Vector will then be the address in

this table added to the start address of the Boot Flash section.

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader

address at reset, see “Boot Loader Support – Read-While-Write Self-programming”

on page 214.

2. When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of the

Boot Flash section. The address of each Interrupt Vector will then be the address in

this table added to the start address of the Boot Flash section.

Table 25. Reset and Interrupt Vectors if M161C is programmed

Vect or No. Program

Address(2) Source Interrupt Definition

1 0x000(1) RESET External Pin, Power-on Reset, Brown-out

Reset, Watchdog Reset, and JTAG AVR

Reset

2 0x002 INT0 External Interrupt Request 0

3 0x004 INT1 External Interrupt Request 1

4 0x006 INT2 External Interrupt Request 2

5 0x008 TIMER2 COMP Timer/Counter2 Compare Match

6 0x00A TIMER2 OVF Timer/Counter2 Overflow

7 0x00C TIMER1 CAPT Timer/Counter1 Capture Event

8 0x00E TIMER1 COMPA Timer/Counter1 Compare Match A

9 0x010 TIMER1 COMPB Timer/Counter1 Compare Match B

10 0x012 TIMER1 OVF Timer/Counter1 Overflow

11 0x014 TIMER0 COMP Timer/Counter0 Compare Match

12 0x016 TIMER0 OVF Timer/Counter0 Overflow

13 0x018 SPI, STC Serial Transfer Complete

14 0x01A USART0, RXC USART0, Rx Complete

15 0x01C USART1, RXC USART1, Rx Complete

16 0x01E USART0, UDRE USART0 Data Register Empty

17 0x020 USART1, UDRE USART1 Data Register Empty

18 0x022 USART0, TXC USART0, Tx Complete

19 0x024 USART1, TXC USART1, Tx Complete

20 0x026 EE_RDY EEPROM Ready

21 0x028 ANA_COMP Analog Comparator

22 0x02A SPM_RDY Store Program Memory Ready

ATmega162(V/U/L)

2513C–AVR–09/02

Table 26 shows Rese t and Interr upt Vect ors place ment for the various c ombinat ions of

BOOTRST an d IVSEL s ettings. If the p rogram ne ver enables an interrupt source, the

Interrupt Vectors are not used, and regular prog ram code can be placed at these loca-

tions. This is also the case if the Reset Vector is in the Application section while the

Interrupt Vectors are in the Boot section or vice versa.

Note: 1. The Boot Reset Address is shown in Tabl e 94 on page 226. For the BOOTRST Fuse

“1” means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector

Addresses in ATmega162 is:

Address Labels Code Comments

0x000 jmp RESET ; Reset Handler

0x002 jmp EXT_INT0 ; IRQ0 Handler

0x004 jmp EXT_INT1 ; IRQ1 Handler

0x006 jmp EXT_INT2 ; IRQ2 Handler

0x008 jmp PCINT0 ; PCINT0 Handler

0x00A jmp PCINT1 ; PCINT1 Handler

0x00C jmp TIM3_CAPT ; Timer3 Capture Handler

0x00E jmp TIM3_COMPA ; Timer3 CompareA Handler

0x010 jmp TIM3_COMPB ; Timer3 CompareB Handler

0x012 jmp TIM3_OVF ; Timer3 Overflow Handler

0x014 jmp TIM2_COMP ; Timer2 Compare Handler

0x016 jmp TIM2_OVF ; Timer2 Overflow Handler

0x018 jmp TIM1_CAPT ; Timer1 Capture Handler

0x01A jmp TIM1_COMPA ; Timer1 CompareA Handler

0x01C jmp TIM1_COMPB ; Timer1 CompareB Handler

0x01E jmp TIM1_OVF ; Timer1 Overflow Handler

0x020 jmp TIM0_COMP ; Timer0 Compare Handler

0x022 jmp TIM0_OVF ; Timer0 Overflow Handler

0x024 jmp SPI_STC ; SPI Transfer Complete Handler

0x026 jmp USART0_RXC ; USART0 RX Complete Handler

0x028 jmp USART1_RXC ; USART1 RX Complete Handler

0x02A jmp USART0_UDRE ; UDR0 Empty Handler

0x02C jmp USART1_UDRE ; UDR1 Empty Handler

0x02E jmp USART0_TXC ; USART0 TX Complete Handler

0x030 jmp USART1_TXC ; USART1 TX Complete Handler

0x032 jmp EE_RDY ; EEPROM Ready Handler

0x034 jmp ANA_COMP ; Analog Comparator Handler

0x036 jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x038 RESET: ldi r16,high(RAMEND) ; Main program start

0x039 out SPH,r16 ; Set stack pointer to top of RAM

Table 26. Reset and Interrupt Vectors Placement(1)

BOOTRST IVSEL Reset address Interrupt Vectors Start Address

1 0 0x0000 0x0002

1 1 0x0000 Boot Reset Address + 0x0002

0 0 Boot Reset Address 0x0002

0 1 Boot Reset Address Boot Reset Address + 0x0002

58 ATmega162(V/U/L) 2513C–AVR–09/02

0x03A ldi r16,low(RAMEND)

0x03B out SPL,r16

0x03C sei ; Enable interrupts

0x03D <instr> xxx

... ... ...

When the BO OTRST F use is unp rogr ammed, th e boot secti on size se t to 2K byte s and

the IVSE L bit in t he GICR Reg ister is set before an y interrupt s are enabl ed, the mos t

typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

0x000 RESET: ldi r16,high(RAMEND) ; Main program start

0x001 out SPH,r16 ; Set stack pointer to top of RAM

0x002 ldi r16,low(RAMEND)

0x003 out SPL,r16

0x004 sei ; Enable interrupts

0x005 <instr> xxx

;

.org 0x1C02

0x1C02 jmp EXT_INT0 ; IRQ0 Handler

0x1C04 jmp EXT_INT1 ; IRQ1 Handler

... .... .. ;

0x1C36 jmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the boot section size set to 2K bytes, the

most typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

.org 0x002

0x002 jmp EXT_INT0 ; IRQ0 Handler

0x004 jmp EXT_INT1 ; IRQ1 Handler

... .... .. ;

0x036 jmp SPM_RDY ; Store Program Memory Ready Handler

;

.org 0x1C00

0x1C00 RESET: ldi r16,high(RAMEND) ; Main program start

0x1C01 out SPH,r16 ; Set stack pointer to top of RAM

0x1C02 ldi r16,low(RAMEND)

0x1C03 out SPL,r16

0x1C04 sei ; Enable interrupts

0x1C05 <instr> xxx

ATmega162(V/U/L)

2513C–AVR–09/02

When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes and the

IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical

and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

.org 0x1C00

0x1C00 jmp RESET ; Reset handler

0x1C02 jmp EXT_INT0 ; IRQ0 Handler

0x1C04 jmp EXT_INT1 ; IRQ1 Handler

... .... .. ;

0x1C36 jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x1C38 RESET: ldi r16,high(RAMEND) ; Main program start

0x1C39 out SPH,r16 ; Set stack pointer to top of RAM

0x1C3A ldi r16,low(RAMEND)

0x1C3B out SPL,r16

0x1C3C sei ; Enable interrupts

0x1C3D <instr> xxx

Moving Interrupts Between

Application and Boot Space The Gen eral Interrupt Cont rol Register c ontrols the placem ent of the Interr upt Vector

table.

General Interrupt Control

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVS EL bi t i s cl eared ( zero ), the Inte rrup t V ect ors are plac ed at t he s tart of th e

Flash mem ory. W hen thi s bit is set (on e), th e Inter rupt Vec tors ar e moved to the begin-

ning of the Boot Load er se ct ion of t he F l ash. T he ac tua l ad dres s of th e s tar t of the Bo ot

Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader

Support – Rea d-Wh ile-Wri te Se lf-prog ramm ing” on page 214 fo r de tails. To a void uni n-

tentio nal changes of Interrup t Vector tab les, a sp ecial wri te procedu re must be fo llowed

to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interr upts wil l automa tically be disabl ed whil e this se quence is execu ted. Inte rrupts are

disable d i n the cycl e IVCE i s set, and t hey r em ain di sa bl ed u nti l a fter t he i ns truc tion fol-

lowing the write to IV SEL. If IV SEL is not written, interrupts remain disabled for four

cycles. The I-bit in the Status Register is unaffected by the automatic disabling.

Note: If Interrupt Vectors are plac ed in the Boot Loader sec tion an d Boot Lock bit BLB0 2 is pro-

grammed, interrupts are disabled while executing from the Application section. If

Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro-

gramed, interrupts are disabled while executing from the Boot Loader section. Refer to

the section “Boot Loader Support – Read-While-Write Self-programming” on page 214

for details on B oot Loc k bit s.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit mu st be written to logi c one to enable chan ge of the IVSEL bit. IVC E is

cleared by hardware four cycles after it is written or when IVSEL is written. Setting the

Bit 76543210

INT1 INT0 INT2 PCIE1 PCIE0 – IVSEL IVCE GICR

Read/Write R/W R/W R/W R/W R/W R R/W R/W

Initial Value00000000

60 ATmega162(V/U/L) 2513C–AVR–09/02

IVCE bi t will d isabl e in terrupts , as ex plai ned in t he IVSEL d escri ption above . See Code

Example below.

Assembly Code Examp le

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE)

out GICR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL)

out GICR, r16

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of Interrupt Vectors */

GICR = (1<<IVCE);

/* Move interrupts to Boot Flash section */

GICR = (1<<IVSEL);

}

ATmega162(V/U/L)

2513C–AVR–09/02

I/O-Ports

Introduction All AVR ports have true Read-Modify- Write functionality when used as gener al digital

I/O ports. Th is mea ns that the direc tio n of one por t pin can be cha nge d with out un inten-

tionally c hanging the directi on of any other pi n with the SBI and CBI instructi ons. The

same applies when changing drive value (if configured as output) or enabling/disablin g

of pull-up resistors (if configured as input). Each output buffer has symmetrical drive

characteristics with both high sink and source capability. The pin driver is strong enough

to dri ve LE D di spla ys d irectl y. A ll p ort pins have indi vidu ally s elec tab le p ull-up res isto rs

with a suppl y-voltage in variant resis tance. All I/O pi ns have protection diodes to both

VCC and Ground as indicated in Figure 28. Refer to “Electrical Characteristics” on page

261 for a complete list of parameters.

Figure 28. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case

“x” re presen ts the nu mberin g letter for th e port, and a lowe r case “ n” repre sents the bit

number. H owever, when u sing the r egister or bit de fines in a progr am, th e precis e for m

must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally

as PORTxn. The physical I/O Registers and bit locations are listed in “Register Descrip-

tion for I/O-Ports” on page 80.

Three I /O memory address lo cations ar e allocate d for each port, one each for the Data

Port Inpu t Pins I/O locat ion is re ad only , while the Da ta Regis ter an d the Data Directio n

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on

page 62. Most port pins are multiplexed with alternate functions for the peripheral fea-

tures on the device. How each alternate function interferes with the port pin is described

in “Alternate Port Functions” on page 66. Refer to the individual module sections for a

full description of the alternate functions.

Note that enabling the alternate function of some of the port pins does not affect the use

of the other pins in the port as general digital I/O.

Cpin

Logic

Rpu

See figure

"General Digital I/O" for

details

Pxn

62 ATmega162(V/U/L) 2513C–AVR–09/02

Ports as General Digital

I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows a

functional description of one I/O-port pin, here generically called Pxn.

Figure 29. General Digital I/O(1)

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,

SLEEP, and PUD are comm on to all ports.

Configuring the Pin Each po rt pin consists of three registe r bits: DDxn, PORTx n, and PINxn. As s hown in

“Register Description fo r I/O-Po rts” on page 80, the DDxn bits are accessed at the

DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at

the PINx I/O address.

The DDxn bit i n the DDRx Register selects the d irection of thi s pin. If DDxn is written

logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-

ured as an input pin.

If PO RTxn i s writ ten lo gic o ne whe n the pin is config ured as an i nput p in, th e pul l-up

resistor is activ ated. To switch the pull-up resistor off, PORTxn has to be written logic

zero or the pin has to be configured as an output pin. The port pins are tri-stated when a

reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is

driven high (on e). If PORTx n is writte n logic ze ro when the pi n is confi gured as an out-

put pin, the port pin is driven low (zero).

When swit ching between tr i-state ({DDxn , PORTxn } = 0b00) and output hi gh ({DDxn,

PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =

0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up

clk

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clkI/O: I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BUS

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

ATmega162(V/U/L)

2513C–AVR–09/02

enabled s tate is fu lly ac c epta bl e, as a high- imp eda nt en vi ronment will not notice the dif-

ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in

the SFIOR Register can be set to disable all pull-ups in all ports.

Switc hing be tween in put with pull-u p and outp ut low ge nerat es the sa me probl em. Th e

user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state

({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 27 summarizes the control signals for the pin value.

Reading the Pin Value Independe nt of the setti ng of Data Dire ction bit DDx n, the por t pin can be rea d through

the PINxn Register bit. As shown in Figure 29, the PINxn Register bit and the preceding

latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near th e edge of th e interna l clock , but it al so intro duces a delay. F igure

30 shows a timing diagram of the synchron ization when reading an externally applied

pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min

respectively.

Figure 30. Synchronization when Reading an Externally Applied Pin Value

Table 27. Port Pin Configurations

DDxn PORTxn PUD

(in SFIOR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled

low.

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min

64 ATmega162(V/U/L) 2513C–AVR–09/02

Consider the clock peri od starting shor tly after the fi rst f alling e dge of the system clock .

The latch is closed when the clo ck is low, and goes trans parent when the cloc k is high,

as indicated by the shaded region of the “SYNC LATCH” signal . The signal value is

latched when the system clock goes low. It is clocked into the PINxn Register at the suc-

ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single

signal transition on the pin will be delayed between ½ and 1½ system clock period

depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as

indicated in Figure 31. The out instruction sets the “SYNC LATCH” signal at the positive

edge of the clock. In this case, the delay tpd through the synchronizer is one system

clock period.

Figure 31. Synchronization when Reading a Software Assigned Pin Value

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

ATmega162(V/U/L)

2513C–AVR–09/02

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and

define the port pins from 4 to 7 as inp ut wi th pul l-up s assigned to port pi ns 6 and 7 . The

result ing p in va lues are read back again, but a s pr evio usly di scu ssed, a nop instruction

is included to be able to read back the value recently assigned to some of the pins.

Note: 1. For the assembly program, two temporary registers are used to minimize the time

from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,

defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enable a nd Sleep

Modes As shown in F igure 29, the digi tal inpu t sig nal can be clampe d to g round at th e inp ut of

the sch mitt-trigge r. The sign al denoted SLEEP i n the figu re, is s et by the MCU Sleep

Controller in Power-down mode, Power-save mode, Standb y mode, and Extende d

Standby mode to avoid high power consumption if some input signals are left floating, or

have an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as External Interrupt pins. If the External

Interru pt Request i s not enabled, SLEEP is act ive also for the se pins. SLE EP is also

overridden by various other alternate functions as described in “Alt ernate Port Func-

tions” on page 66.

If a logi c hi gh level (“one ”) is presen t on an Async hron ous Ext ernal In terrupt pin config-

ured as “In terru pt on Risin g Edge, Fall ing Ed ge, or Any Logic Change on Pin” whi le the

external i nterrupt is not enable d, the corre sponding Ex ternal Interr upt Flag wi ll be set

when resu mi ng from the above ment ion ed s lee p mo des , as the c lam pi ng in thes e slee p

modes produces the requested logic change.

Assembly Code Examp le(1)

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

C Code Example(1)

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

66 ATmega162(V/U/L) 2513C–AVR–09/02

Unconnecte d pins If some pins are unused , it is recomm ended to ensur e that these p ins have a defin ed

level. Even thou gh most of the digital inputs are disabled in the de ep sleep modes as

describe d ab ove, fl oa tin g i nputs sho uld be av oided to r ed uc e c urre nt c on su mpti on in al l

other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal

pullup. In this case, the pullup will be disabled during reset. If low power consumption

during reset is important, it is recommended to use an external pullup or pulldown. Con-

nect ing unuse d pins dir ectly to VCC or GND is no t reco mm ended , sinc e thi s may ca use

excessive currents if the pin is accidentally configured as an output.

Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure

32 show s how th e port pin c ontrol si gnals from the si mplif ied Figu re 29 ca n be overrid -

den by alternate functions. The overriding signals may not be present in all port pins, but

the figure serves as a generic description applicable to all port pins in the AVR micro-

controlle r fami ly.

Figure 32. Alternate Port Functions(1)

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

clk

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

SET

CLR

DIxn

AIOxn

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

DIxn: DIGITAL INPUT PIN n ON PORTx

AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

RESET

CLR

PINxn

PORTxn

DDxn

DATA BUS

DIEOVxn

SLEEP

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

SLEEP: SLEEP CONTROL

Pxn

I/O

ATmega162(V/U/L)

2513C–AVR–09/02

Table 2 8 summariz es the functio n of the overriding s ignals. T he pin and por t indexes

from Fi gure 32 are not sho wn i n the su ccee ding ta bles. The over riding signa ls are g en-

erated internally in the modules having the alternate function.

The following subsections shortly describe the alternate functions for each port, and

relate the overriding signals to the alternate function. Refer to the alternate function

description for further details.

Table 28. Generic Description of Overriding Signals for Alternate Functions.

Signal Name Full Name Description

PUOE Pull-up Override

Enable If this signal is set, the pull -up enable is controlled by the

PUOV signal. If this signal is cleared, the pull-up is

enabled when {DDxn, PORTxn, PUD} = 0b010.

PUOV Pull-up Override

Value If PUOE is set, the pull-up is enabled/disabled when

PUOV is set/cleared, regardless of the setting of the

DDxn, PORTxn, and PUD Register bits.

DDOE Data Di rection

Override Enable If this signal is set, the Output Driver Enable is controlled

by the DDOV signal. If this signal is cleared, the Output

driver is enabl ed by the DDxn Register bit.

DDOV Data Di rection

Override Value If DDOE is set, the Output Driver is enabled/disabled

when DDOV is set/cleared , regardless of the setting of the

DDxn Register bit.

PVOE Port Value

Override Enable If this signal is set and the Output Driver is enabled, the

port value is controlled by the PVOV signal. If PVOE is

cleared , and the Output Drive r is enabled , the port V alue is

controlled by the PORTxn Register bit.

PVOV Port Value

Override Value If PVOE is set, the port va lue is set to PVOV, regardless of

the setting of the PORTxn Register bi t.

DIEOE Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is cont rolled by the

DIEOV signal. If this signal is cleared, the Digital Input

Enable is det erm ine d by MCU sta te (N orm al Mo de , Sleep

Modes).

DIEOV Digital Input

Enable Override

Value

If DIEOE is s et, the D igi tal Inp ut is en abl ed/d is abl ed w hen

DIEOV is set/cleared, regardless of the MCU state

(Normal Mode, Sleep Modes).

DI Digital Input This is the Digi tal Input to alte rnate functions . In the figure,

the signal is connected to the output of the schmitt trigger

but before the synchronizer. Unless the Digital Input is

used as a clock source, the module with the alternate

function will use its own synchronizer.

AIO Analog

Input/output This is the Anal og Inpu t/outpu t to/from altern ate func tions.

The signal is connected directly to the pad, and can be

used bi-directi onally.

68 ATmega162(V/U/L) 2513C–AVR–09/02

Special Function IO Register –

SFIOR

• Bit 2 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn

and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).

See “Configuring the Pin” on page 62 for more details about this feature.

Alternate Functions of Port A Port A has an alte rnate func tion a s the ad dress l ow byte and da ta lines f or the E xterna l

Memory Interface and as Pin Change Interrupt.

Table 30 and Table 31 relate the alternate functions of Port A to the overriding signals

shown in Figure 32 on page 66.

Bit 7 6 5 4 3 2 1 0

TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 29. Port A Pins Alternate Functions

Port Pin Alternate Function

PA7 AD7 (External memory interface address and data bit 7)

PCINT7 (Pin Change INTerrupt 7)

PA6 AD6 (External memory interface address and data bit 6)

PCINT6 (Pin Change INTerrupt 6)

PA5 AD5 (External memory interface address and data bit 5)

PCINT5 (Pin Change INTerrupt 5)

PA4 AD4 (External memory interface address and data bit 4)

PCINT4 (Pin Change INTerrupt 4)

PA3 AD3 (External memory interface address and data bit 3)

PCINT3 (Pin Change INTerrupt 3)

PA2 AD2 (External memory interface address and data bit 2)

PCINT2 (Pin Change INTerrupt 2)

PA1 AD1 (External memory interface address and data bit 1)

PCINT1 (Pin Change INTerrupt 1)

PA0 AD0 (External memory interface address and data bit 0)

PCINT0 (Pin Change INTerrupt 0)

ATmega162(V/U/L)

2513C–AVR–09/02

Notes: 1. ADA is short for ADdress Active and repre sents the time whe n addres s is outp ut. See

“External Memory Interface” on page 24.

2. PCINTn is Pin Change Interrupt Enable bit n.

3. PCINTn is Pin Change Interrupt input n.

Notes: 1. PCINT is Pin Change Interrupt Enable bit n.

2. PCINT is Pin Change Interrupt input n.

Table 30. Overriding Signals for Alternate Functions in PA7..PA4

Signal

Name PA7/AD7/

PCINT7 PA6/AD6/PCINT6 PA5/AD5/PCINT5 PA4/AD4/PCINT4

PUOE SRE SRE SRE SRE

PUOV ~(WR + ADA(1)) •

PORTA7 ~(WR + ADA) •

PORTA6 ~(WR + ADA) •

PORTA5 ~(WR + ADA) •

PORTA4

DDOE SRE SRE SRE SRE

DDOV WR + ADA WR + ADA WR + ADA WR + ADA

PVOE SRE SRE SRE SRE

PVOV if (ADA) then

else D7 OUTPUT

• WR

if (ADA) then

else D6 OU T P U T

• WR

if (ADA) then

else D5 OUTPUT

• WR

if (ADA) then

else D4 OUTPUT

• WR

DIEOE(2

)PCIE0 • PCINT7 PCIE0 • PCINT6 PCIE0 • PCINT5 PCIE0 • PCINT4

DIEOV1111

DI(3) D7 INPUT/

PCINT7 D6 INPUT/

PCINT6 D5 INPUT/

PCINT5 D4 INPUT/

PCINT4

AIO––––

Table 31. Overriding Signals for Alternate Functions in PA3..PA0

Signal

Name PA3/AD3/

PCINT3 PA2/AD2/

PCINT2 PA1/AD1/

PCINT1 PA0/AD0/

PCINT0

PUOE SRE SRE SRE SRE

PUOV ~(WR + ADA) •

PORTA3 ~(WR + ADA) •

PORTA2 ~(WR + ADA) •

PORTA1 ~(WR + ADA) •

PORTA0

DDOE SRE SRE SRE SRE

DDOV WR + ADA WR + ADA W R + ADA WR + ADA

PVOE SRE SRE SRE SRE

PVOV if (ADA) then

else D3 OUTPUT

• WR

if (ADA) then

else D2 OUTPUT

• WR

if (ADA) then

else D1 OUTPUT

• WR

if (ADA) then

else D0 OUTPUT

• WR

DIEOE(1) PCIE0 • PCINT3 PCIE0 • PCINT2 PCIE0 • PCINT1 PCIE0 • PCINT0

DIEOV1111

DI(2) D3 INPUT

/PCINT3 D2 INPUT

/PCINT2 D1 INPUT

/PCINT1 D0 INPUT

/PCINT0

AIO––––

70 ATmega162(V/U/L) 2513C–AVR–09/02

Alternate Functions Of Port B The Port B pins with alternate functions are shown in Table 32.

The alternate pin configuration is as follows:

• SCK – Port B, Bit 7

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is

enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7.

When th e SPI is enabled a s a Maste r, the data d irection of this pin is cont rolled by

DDB7. When the pin is forced by the SPI to be an input, the pull-up can still be con-

trolled by the PORTB7 bit.

• MISO – Port B, Bit 6

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is

enabled as a Master, this pin is configured as an input regardless of the setting of

DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by

DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be con-

trolled by the PORTB6 bit.

• MOSI – Port B, Bit 5

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is

enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5.

When th e SPI is enabled a s a Maste r, the data d irection of this pin is cont rolled by

DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be con-

trolled by the PORTB5 bit.

•SS

/OC3B – Port B, Bit 4

SS: Slav e Se lec t in put. W hen the SP I is en abled as a sl av e, thi s pin is con fig ured as an

input regardless of the setting of DDB4. As a Slave, the SPI is activated when this pin is

driven low. When the SPI is enabled as a Ma ster, the data direction of this pin is con-

trolled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still be

controlled by the PORTB4 bit.

Table 32. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7 SCK (SPI Bus Serial Clock)

PB6 MISO (SPI Bus Master Input/Slave Output)

PB5 MOSI (SPI Bus Master Output/Slave Input)

PB4 SS (SPI Slave Select Input)

OC3B (Timer/Counter3 Output Compare Match Output)

PB3 AIN1 (Analog Com para tor Negative Input )

TXD1 (USART1 Output Pin)

PB2 AIN0 (Analog Com para tor Posi tive Inpu t)

RXD1 (USART1 Input Pin)

PB1 T1 (Timer/Counter1 External Counter Input)

OC2 (Timer/Counter2 Output Compare Match Output)

PB0 T0 (Timer/Counter0 External Counter Input)

OC0 (Timer/Counter0 Output Compare Match Output)

clkI/O (Divided Syst em Cloc k)

ATmega162(V/U/L)

2513C–AVR–09/02

OC3B, Output Compare Match B output: The PB4 pin can serve as an external output

for the Timer/Counter3 Output Compare B. The pin has to be configured as an output

(DDB4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM

mode timer function.

• AIN1/TXD1 – Port B, Bit 3

AIN1, An alo g Comp arator Negative in put. Co nfigure the po rt p in as i nput wi th the inter-

nal pull-up switched off to avoid the digital port function from interfering with the function

of the Analog Comparator.

TXD1 , Transmi t Data (Dat a outp ut pin for USART1 ). When th e USART 1 Transm itter is

enabled, this pin is configured as an output regardless of the value of DDB3.

• AIN0/RXD1 – Port B, Bit 2

AIN0, Analog Comparator Positive Input. Configure the port pin as input with the internal

pull-u p switched off to av oid the digit al port functio n from inter fering with the function of

the Analog Comparator.

RXD1, Receive Data (Data input pin for USART1). When the USART1 Receiver is

enabled this pin is configured as an input regardles s of the valu e of DDB2. Wh en the

USART1 forces this pin to be an input, the pull-up can still be controlled by the PORTB2

bit.

• T1/OC2 – Port B, Bit 1

T1, Timer/Counter1 Counter Source.

OC2, Output comp are match output: The PB 1 pin can ser ve as an external output for

the Timer/Counter2 compare match. The PB1 pin has to be configured as an output

(DDB1 s et (on e) ) to s erve thi s func ti on. The O C2 pi n i s als o th e ou tpu t pi n fo r the P W M

mode timer function.

• T0/OC0 – Port B, Bit 0

T0, Timer/Counter0 counter source.

OC0, Output Compare Match output: The PB0 pin can serve as an external output for

the Timer/Counter0 Compare Match. The PB0 pin has to be configured as an output

(DDB0 s et (on e) ) to s erve thi s func ti on. The O C0 pi n i s als o th e ou tpu t pi n fo r the P W M

mode timer function.

clkI/O, Divided Sys tem Clock: The divided system clock can be output on the PB0 pin.

The divided system clock will be output if the CKOUT Fuse is programmed, regardless

of the PORTB0 and DDB0 settings. It will also be output during reset.

Table 33 and Table 34 relate the alternate functions of Port B to the overriding signals

shown in F igur e 32 o n pa ge 66. S PI M STR INPUT and S PI S LAVE O UTPU T con st itu te

the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE

INPUT.

72 ATmega162(V/U/L) 2513C–AVR–09/02

Notes: 1. CKOUT is one if the CKOUT Fuse is programmed.

2. clkI/O is the divided system clock.

Table 33. Overriding Signals for Alternate Functions in PB7..PB4

Signal

Name PB7/SCK PB6/MISO PB5/MOSI PB4/SS/OC3B

PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

PUOV PORTB7 •

PUD PORTB6 • PUD PORTB5 • PUD PORTB4 •

PUD

DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

DDOV 0 0 0 0

PVOE SPE • MSTR SPE • MSTR SPE • MSTR OC3B

ENABLE

PVOV SCK OUTPUT SPI SLAVE

OUTPUT SPI MSTR

OUTPUT OC3B

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI SCK INPUT SPI MSTR INPUT SPI SLAVE INPUT SPI SS

AIO – – – –

Table 34. Overriding Signals for Alternate Functions in PB3..PB0

Signal Name PB3/AIN1/TXD1 PB2/AIN0/RXD1 PB1/T1/OC2 PB0/T0/OC0

PUOE TXEN1 RXEN1 0 0

PUOV 0 PORTB2• PUD 0 0

DDOE TXEN1 RXEN1 0 CKOUT(1)

DDOV 1 0 0 1

PVOE TXEN1 0 OC2 ENABLE CKOUT + OC0

ENABLE

PVOV TXD1 0 OC2 if (CKOUT) then

clkI/O(2)

else OC0

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI – RXD1 T1 INPUT T0 INPUT

AIO AIN1 INPUT AIN0 INPUT – –

ATmega162(V/U/L)

2513C–AVR–09/02

Alternate Functions of Port C The Port C p ins with al terna te functi ons are shown in T able 35. If the JTAG interfa ce is

enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be acti-

vated even if a reset occurs.

• A15/TDI/PCINT15 – Port C, Bit 7

A15, External memory interface address bit 15.

TDI, JTAG Test Data In: Serial input data to be shifted into the Instruction Register or

Data Register (scan chains). When the JTAG interface is enabled, this pin can not be

used as an I/O pin.

PCINT15: The pin can also serve as a pin change interrupt.

• A14/TDO/PCINT14 – Port C, Bit 6

A14, External memory interface address bit 14.

TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Regis-

ter. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

PCINT14: The pin can also serve as a pin change interrupt.

Table 35. Port C Pins Alternate Functions

Port Pin Alternate Function

PC7 A15 (External memory interface address bit 15)

TDI (JTAG Test Data Input)

PCINT15 (Pin Change INTerrupt 15)

PC6 A14 (External memory interface address bit 14)

TDO (JTAG Test Data Output)

PCINT14 (Pin Change INTerrupt 14)

PC5 A13 (External memory interface address bit 13)

TMS (JTAG Test Mode Select)

PCINT13 (Pin Change INTerrupt 13)

PC4 A12 (External memory interface address bit 12)

TCK (JTAG Test Clock)

PCINT12 (Pin Change INTerrupt 12)

PC3 A11 (External memory interface address bit 11)

PCINT11 (Pin Change INTerrupt 11)

PC2 A10 (External memory interface address bit 10)

PCINT10 (Pin Change INTerrupt 10)

PC1 A9 (External memory interface address bit 9)

PCINT9 (Pin Change INTerrupt 9)

PC0 A8 (External memory interface address bit 8)

PCINT8 (Pin Change INTerrupt 8)

74 ATmega162(V/U/L) 2513C–AVR–09/02

• A13/TMS/PCINT13 – Port C, Bit 5

A13, External memory interface address bit 13.

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller

state ma chine . When the J TAG i nterf ace is enable d, this pin can not be used as an I/O

pin.

PCINT13: The pin can also serve as a pin change interrupt.

• A12/TCK/PCINT12 – Port C, Bit 4

A12, External memory interface address bit 12.

TCK, J TAG Tes t Clock: JTAG op eratio n is sync hronou s to TCK. When th e JTAG in ter-

face is enabled, this pin can not be used as an I/O pin.

PCINT12: The pin can also serve as a pin change interrupt.

• A11/PCINT11 – Port C, Bit 3

A11, External memory interface address bit 11.

PCINT11: The pin can also serve as a pin change interrupt.

• A10/PCINT10 – Port C, Bit 2

A10, External memory interface address bit 10.

PCINT11: The pin can also serve as a pin change interrupt.

• A9/PCINT9 – Port C, Bit 1

A9, External memory interface address bit 9.

PCINT9: The pin can also serve as a pin change interrupt.

• A8/PCINT8 – Port C, Bit 0

A8, External memory interface address bit 8.

PCINT8: The pin can also serve as a pin change interrupt.

Table 36 and Table 37 relate the alternate functions of Port C to the overriding signals

shown in Figure 32 on page 66.

ATmega162(V/U/L)

2513C–AVR–09/02

Notes: 1. PCINTn is Pin Change Interrupt Enable bit n.

2. PCINTn is Pin Change Interrupt input n.

Notes: 1. PCINTn is Pin Change Interrupt Enable bit n.

2. PCINTn is Pin Change Interrupt input n.

Table 36. Overriding Signals for Alternate Functions in PC7..PC4

Signal Name PC7/A15/TDI

/PCINT15 PC6/A14/TDO

/PCINT14 PC5/A13/TMS

/PCINT13 PC4/A12/TCK

/PCINT12

PUOE (XMM < 1) •

SRE + JTAGEN (XMM < 2) •

SRE +JTAGEN (XMM < 3) •

SRE + JTAGEN (XMM < 4) •

SRE + JTAGEN

PUOV JTAGEN 0 JTAGEN JTAGEN

DDOE SRE • (XMM<1)

+ JTAGEN SRE • (XMM<2)

+ JTAGEN SRE • (XMM<3)

+ JTAGEN SRE • (XMM<4)

+ JTAGEN

DDOV JTAGEN JTAGEN +

JTAGEN •

(SHIFT_IR |

SHIFT_DR)

JTAGEN JTAGEN

PVOE SRE • (XMM<1) SRE • (XMM<2)

+ JTAGEN SRE • (XMM<3) SRE • (XMM<4)

PVOV A15 if (JTAGEN) then

TDO

else A14

A13 A12

DIEOE(1) JTAGEN |

PCIE1 •

PCINT15

JTAGEN |

PCIE1 •

PCINT14

JTAGEN |

PCIE1 •

PCINT13

JTAGEN |

PCIE1 •

PCINT12

DIEOV 1 1 1 1

DI(2) PCINT15 PCINT14 PCINT13 PCINT12

AIO TDI – TMS TCK

Table 37. Overriding Signals for Alternate Functions in PC3..PC0

Signal Name PC3/A11/

PCINT11 PC2/A10/

PCINT10 PC1/A9/PCINT9 PC0/A8/PCINT8

PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)

PUOV0000

DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)

DDOV1111

PVOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM <7) SRE • (XMM<7)

PVOV A11 A10 A9 A8

DIEOE(1) PCIE1 •

PCINT11 PCIE1 •

PCINT10 PCIE1 • PCINT9 PCIE1 • PCINT8

DIEOV1111

DI(2) PCINT11 PCINT10 PCINT9 PCINT8

AIO––––

76 ATmega162(V/U/L) 2513C–AVR–09/02

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 38.

The alternate pin configuration is as follows:

•RD

– Port D, Bit 7

RD is the external data memory read control strobe.

•W

R – Port D, Bit 6

WR is the external data memory write control strobe.

• TOSC2/OC1A – Port D, Bit 5

TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asyn-

chronous clocking of Timer/Counter2, pin PD5 is disconnected from the port, and

becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator

is connected to this pin, and the pin can not be used as an I/O pin.

OC1A, Output Compare Match A output: T he PD5 pin can serve as an external output

for the Timer/Counter1 Output Compare A. The pin has to be configured as an output

(DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the

PWM mode timer function.

Table 38. Port D Pins Alternate Functions

Port Pin Alternate Function

PD7 RD (Read strobe to external memory)

PD6 WR (Write strobe to external memory)

PD5 T OSC2 (Timer Oscillator Pin 2)

OC1A (Timer/Counter1 Output Compare A Match Output)

PD4 T OSC1 (Timer Oscillator Pin 1)

XCK0 (USART0 External Clock Input/Output)

OC3A (Timer/Counter3 Output Compare A Match Output)

PD3 INT1 (External Interrupt 1 Input)

ICP3 (Timer/Counter3 Input Capture Pin)

PD2 INT0 (External Interrupt 0 Input)

XCK1 (USART1 External Clock Input/Output)

PD1 TXD0 (USART0 Output Pin)

PD0 RXD0 (USAR T0 Inp ut Pin)

ATmega162(V/U/L)

2513C–AVR–09/02

• TOSC1/XCK0/OC3A – Port D, Bit 4

TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asyn-

chronous clocking of Timer/Counter2, pin PD4 is disconnected from the port, and

beco mes the input of the inverting Osci llator Ampl ifier. In thi s mode, a cryst al Oscillator

is connected to this pin, and the pin can not be used as an I/O pin.

XCK0 , USAR T0 E xter nal Cl ock: T he D ata Dir ecti on Re giste r (DDD 4) c ontro ls whe ther

the clock is output (DDD4 set (one)) or input (DDD4 cleared (zero)). The XCK0 pin is

active only when USART0 operates in Synchronous mode.

OC3A, Output Compare Match A output: T he PD4 pin can serve as an external output

for the Timer/Counter1 Output Compare A. The pin has to be configured as an output

(DDD4 set (one)) to serve this function. The OC4A pin is also the output pin for the

PWM mode timer function.

• INT1/ICP3 – Port D, Bit 3

INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt

source.

ICP3, Input Capture Pin: The PD3 pin can act as an input capture pin for

Timer/Counter3.

• INT0/XCK1 – Port D, Bit 2

INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt

source.

XCK1 , USAR T1 E xter nal Cl ock: T he D ata Dir ecti on Re giste r (DDD 2) c ontro ls whe ther

the clock is output (DDD2 set (one)) or input (DDD2 cleared (zero)). The XCK1 pin is

active only when USART1 operates in Synchronous mode.

• TXD0 – Port D, Bit 1

TXD0 , Transmi t Data (Dat a outp ut pin for USART0 ). When th e USART 0 Transm itter is

enabled, this pin is configured as an output regardless of the value of DDD1.

78 ATmega162(V/U/L) 2513C–AVR–09/02

• RXD0 – Port D, Bit 0

RXD0, Receive Data (Data input pin for USART0). When the USART0 Receiver is

enabled this pin is configured as an input regardless of the value of DDD0. When

USART0 forces this pin to be an input, the pull-up can still be controlled by the PORTD0

bit.

Table 39 and Table 40 relate the alternate functions of Port D to the overriding signals

shown in Figure 32 on page 66.

Table 39. Overriding Signals for Alternate Functions PD7..PD4

Signal Name PD7/RD PD6/WR PD5/TOSC2/OC1A PD4/TOSC1/XCK0/OC3A

PUOE SRE SRE AS2 AS2

PUOV 0 0 0 0

DDOE SRE SRE AS2 AS2

DDOV 1 1 0 0

PVOE SRE SRE OC1A ENABLE XCK0 OUTPUT ENABLE |

OC3A ENABLE

PVOV RD WR OC1A if (XCK0 OUTPUT

ENABLE) then

XCK0 OUTPUT

elseOC3A

DIEOE 0 0 AS2 AS2

DIEOV 0 0 0 0

DI – – – XCK0 INPUT

AIO – – T /C2 OSC OUTPUT T/C2 OSC INPUT

Table 40. Overriding Signals for Alternate Functions in PD3..PD0

Signal Name PD3/INT1 PD2/INT0/XCK1 PD1/TXD0 PD0/RXD0

PUOE 0 0 TXEN0 RXEN0

PUOV 0 0 0 PORTD0 • PUD

DDOE 0 0 TXEN0 RXEN0

DDOV 0 0 1 0

PVOE 0 XCK1 OUTPUT ENABLE TXEN0 0

PVOV 0 XCK1 TXD0 0

DIEOE INT1 ENABLE INT0 ENABLE 0 0

DIEOV 1 1 0 0

DI INT1 INPUT/

ICP1 INPUT INT0 INPUT/XCK1 INPUT – RXD0

AIO – – – –

ATmega162(V/U/L)

2513C–AVR–09/02

Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 41.

The alternate pin configuration is as follows:

• OC1B – Port E, Bit 2

OC1B, Output Compare Match B output: The PE2 pin can serve as an external output

for the Timer/Counter1 Output Compare B. The pin has to be configured as an output

(DDE0 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM

mode timer function.

Table 42 relate the alternate functions of Port E to the overriding signals shown in Figure

32 on page 66.

•ALE – Port E, Bit 1

ALE is the external data memory Address Latch Enable signal.

• ICP1/INT2 – Port E, Bit 0

ICP1, Input Capture Pin: The PE0 pin can act as an input capture pin for

Timer/Counter1.

INT2, External Interrupt Source 2: The PE0 pin can serve as an external interrupt

source.

Table 41. Port E Pins Alternate Functions

Port Pin Alternate Function

PE2 OC1B (Timer/Counter1 Output CompareB Match Output)

PE1 ALE (Address Latch Enable to external memory)

PE0 ICP1 (Timer/Counter1 Input Capture Pin)

INT2 (External Interrupt 2 Input)

Table 42. Overriding Signals for Alternate Functions PE2..PE0

Signal Name PE2 PE1 PE0

PUOE 0 SRE 0

PUOV 0 0 0

DDOE 0 SRE 0

DDOV 0 1 0

PVOE OC1B ENABLE SRE 0

PVOV OC1B ALE 0

DIEOE 0 0 INT2 ENABLED

DIEOV 0 0 1

DI 0 0 INT2 INPUT/ ICP1 INPUT

AIO – – –

80 ATmega162(V/U/L) 2513C–AVR–09/02

I/O-Ports

Port A Data Register – PORTA

Port A Data Direction Register

– DDRA

Port A Input Pins Address –

PINA

Port B Data Register – PORTB

Port B Data Direction Register

– DDRB

Port B Input Pins Address –

PINB

Port C Data Register – PORTC

Port C Data Direction Register

– DDRC

Bit 76543210

PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

ATmega162(V/U/L)

2513C–AVR–09/02

Port C Input Pins Address –

PINC

Port D Data Register – PORTD

Port D Data Direction Register

– DDRD

Port D Input Pins Address –

PIND

Port E Data Register – PORTE

Port E Data Direction Register

– DDRE

Port E Input Pins Address –

PINE

Bit 76543210

PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

– – – – – PORTE2 PORTE1 PORTE0 PORTE

Read/Write R R R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

– – – – – DDE2 DDE1 DDE0 DDRE

Read/Write R R R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

–––––PINE2PINE1PINE0PINE

Read/WriteRRRRRRRR

Initial Value 0 0 0 0 0 N/A N/A N/A

82 ATmega162(V/U/L) 2513C–AVR–09/02

External Interrupts The External Interrupts are triggered by the INT0, INT1, INT2 pin, or any of the

PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2..0

or PCINT15..0 pins are configured as outputs. This feature provides a way of generating

a softwar e interr upt. Th e Externa l Interru pts can be trigge red by a fall ing or risi ng edge

or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in the

specificati on for the M CU Contro l Register – MCUCR and Extended M CU Control Reg-

ister – EMCUCR. When the external interrupt is enabled and is configured as level

triggered (only INT0/INT1), the interrupt will trigger as long as the pin is held low. The

pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change

interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK1 and

PCMSK0 Registers control which pins contribute to the pin change interrupts. Note that

recognition of falling or rising edge interrupts on INT0 and INT1 requires the presence of

an I/O clo ck, descr ibed in “Clock Syst ems and the ir Distri bution” on page 33. Low level

interrupts on INT0/INT1, the edge interrupt on INT2, and Pin change interrupts on

PCINT15..0 are detected asynchronously. This implies that these interrupts can be used

for waking the par t also from s leep modes oth er than Idl e mode. The I/O clock is halte d

in all sleep modes except Idle mode.

Note t hat if a level trig gered inter rupt is used for wak e-up f rom P ower- down mode, the

changed level must be held for some time to wake up the MCU. This makes the MCU

less se nsitiv e to noise. The changed le vel is s ampled twi ce by the Wat chdog Osc illator

clock. The period of the Watchdog Osci llator is 1 µs (nominal) at 5.0V and 25°C. The

frequency of the Watchdog Oscillator is voltage dependent as shown in “Electrical Char-

acteristics” on page 261. The MCU will wake up if the input has the required level during

this sampling or if it is held until the end of the start-up time. The start-up time is defined

by the SUT Fus es as des c ribed in “ Sys tem Clo ck and Clo ck O pti ons” on pa ge 3 3. If th e

level is sampled twice by the Watchdog Oscillator clock but disappears before the end

of the start-up time, the MCU will still wake up, but no interrupt will be generated. The

required level must be held long enough for the MCU to complete the wake up to trigger

the level interrupt.

MCU Control Register –

MCUCR The MCU Cont rol Register contains control bits for interrupt sense control and general

MCU functions.

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the

corresponding interrupt mask in the GICR are set. The level and edges on the external

INT1 pin that activa te the inter rupt are defined i n T a ble 43. The valu e on the INT1 pin is

sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last

longer than one clock period will generate an interrupt. Shorter pulses are not guaran-

teed to generate an interrupt. If low level interrupt is selected, the low level must be held

until the completion of the currently executing instruction to generate an interrupt.

Bit 76543210

SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

ATmega162(V/U/L)

2513C–AVR–09/02

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The Exter nal In terrupt 0 is acti vated b y the e xternal pin INT0 if the SREG I-flag a nd the

corresponding interrupt mask are set. The level and edges on the external INT0 pin that

activate the interrupt are defined in Table 44. The value on the INT0 pin is sampled

before detec ting edge s. If edge or toggle inter rupt is selecte d, pulse s that last l onger

than one clock period will generate an i nterrupt. Shorter pulses are not g uaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until

the completion of the currently executing instruction to generate an interrupt.

Extended MCU Control

• Bit 0 – ISC2: Interrupt Sense Control 2

The asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG

I-bit and the corresponding interrupt mask in GICR are set. If ISC2 is cleared (zero), a

falling edge on INT2 activates the interrupt. If ISC2 is set (one), a rising edge on INT2

activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT2

wider than the minimum pulse width given in Table 45 will generate an interrupt. Shorter

pulses are not guaranteed to generate an interrupt. When changing the ISC2 bit, an

interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its

Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally,

the INT2 interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit

(INTF2) in the GIFR Register before the interrupt is re-enabled.

Table 43. Interrupt 1 Sense Control

ISC11 ISC10 Description

0 0 The low level of INT1 generates an interrupt request.

0 1 Any logical change on INT1 generates an interrupt request.

1 0 The falling edge of INT1 generates an interrupt request.

1 1 The rising edge of INT1 generates an inte rrupt request.

Table 44. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Any logical change on INT0 generates an interrupt request.

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an inte rrupt request.

Bit 76543210

SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 45. Asynchronous External Interrupt Characteristics

Symbol Parameter Condition Min. Typ. Max. Units

tINT Minimum pulse width for

asynchronous external interrupt 50 ns

84 ATmega162(V/U/L) 2513C–AVR–09/02

General Interrupt Control

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 ( ISC11 and

ISC10) in the MCU general Control Register (MCUCR) define whether the external

interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity

on the pin will cause an interrupt request even if INT1 is configured as an output. The

corresp ond ing i nterr up t o f E xter nal I nterr upt Re que st 1 is e xe cu ted from th e INT1 Inte r-

rupt Vecto r.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 ( ISC01 and

ISC00) in the MCU general Control Register (MCUCR) define whether the external

interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity

on the pin will cause an interrupt request even if INT0 is configured as an output. The

corresp ond ing i nterr up t o f E xter nal I nterr upt Re que st 0 is e xe cu ted from th e INT0 Inte r-

rupt Vecto r.

• Bit 5 – INT2: External Interrupt Request 2 Enable

When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is enabled. The Interrupt Sense Control2 bit (ISC2) in the

Extend ed MCU Control Regi ster (EMCUC R) define s whether the ext ernal interru pt is

activat ed on risi ng or falling ed ge of the INT2 pin. Activi ty on the pi n will caus e an inter-

rupt request even if INT2 is configured as an output. The c orresponding interrupt of

External Interrupt Request 2 is executed from the INT2 Interrupt Vector.

• Bit 4 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will

cause an inte rru pt. The cor res po ndi ng int erru pt of Pin Chang e Inter rupt Request is exe-

cuted from the PCI1 Interrupt V ector. PCINT15..8 pins are enabled individually by the

PCMS K1 Register.

• Bit 3 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

pin chang e interrupt 0 is ena ble d. Any chan ge on any en abl ed PCINT 7. .0 pin w ill ca us e

an interrupt. The corresponding interrupt of Pi n Change Interrupt Request is executed

from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0

Bit 76543210

INT1 INT0 INT2 PCIE1 PCIE0 –IVSEL IVCE GICR

Read/Write R/W R/W R/W R/W R/W R R/W R/W

Initial Value00000000

ATmega162(V/U/L)

2513C–AVR–09/02

General Interrupt Flag

• Bit 7 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF 1

becomes set (one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU

will jum p to the co rresponding Interrupt Ve ctor. The fl ag is clear ed when the interrupt

routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

This flag is always cleared when INT1 is configured as a level interrupt.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF 0

becomes set (one). If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU

will jum p to the co rresponding Interrupt Ve ctor. The fl ag is clear ed when the interrupt

routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

This flag is always cleared when INT0 is configured as a level interrupt.

• Bit 5 – INTF2: External Interrupt Flag 2

When an ev en t on the I NT 2 pi n trig ger s an inte rrupt reques t, INTF 2 b ec ome s s et (on e) .

If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alterna tiv ely, the flag can be c le ar ed b y writ ing a lo gic al one to i t. Note that when en te r-

ing some sleep modes with the INT2 interrupt disabled, the input buffer on this pin will

be disab led. This ma y cause a lo gic change i n interna l signal s which will se t the INTF2

flag. See “Digital Input Enable and Sleep Modes” on page 65 for more information.

• Bit 4 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1

becom es set (on e). If the I-b it in SREG and th e PCIE1 bi t in GICR are set (one), th e

MCU will j ump to th e c orr es pond in g Int erru pt V ect or. T he fla g is c le ared when the i nte r-

rupt rou tin e is ex ec ute d. A lte rnati ve ly, the fla g can be cleare d by wr iting a logical one to

it.

• Bit 3 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0

becom es set (on e). If the I-b it in SREG and th e PCIE0 bi t in GICR are set (one), th e

MCU will j ump to th e c orr es pond in g Int erru pt V ect or. T he fla g is c le ared when the i nte r-

rupt rou tin e is ex ec ute d. A lte rnati ve ly, the fla g can be cleare d by wr iting a logical one to

it.

Bit 76543210

INTF1 INTF0 INTF2 PCIF1 PCIF0 ––– GIFR

Read/Write R/W R/W R/W R/W R/W R R R

Initial Value00000000

86 ATmega162(V/U/L) 2513C–AVR–09/02

Pin Change Mask Register 1 –

PCMSK1

• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8

Each PCINT15..8 bit selects whether pin change interrupt is enabled on the correspond-

ing I/O pin. If PCINT15..8 is set and the PCIE1 bit in GICR is set, pin change interrupt is

enabled o n the c orresp ondin g I/O p in. If P CINT15..8 i s cl eared, pi n cha nge in terrupt o n

the corresponding I/O pin is disabled.

Pin Change Mask Register 0 –

PCMSK0

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each P CINT7.. 0 bit s elects whethe r pin chan ge int errupt i s en abled on the correspo nd-

ing I/O pin . If P CINT7. .0 is set and the P CIE0 b it i n GIC R is set, pin ch ang e int errupt is

enabled on the c orresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on

the corresponding I/O pin is disabled.

The mapping between I/O pins and PCINT bits can be found in Figure 1 on page 2. Note

that the Pin Change Mask Register are located in Extended I/O. Thus, the pin change

interrupts are not supported in ATmega161 compatibility mode.

Bit 76543210

PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT9 PCMSK1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

ATmega162(V/U/L)

2513C–AVR–09/02

8-bit Timer/Counter0

with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The

main featur es ar e:

•Single Channel Counter

•Clear Timer on Compare Match (Auto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Frequency Genera tor

•External Event Counter

•10-bit Clock Prescaler

•Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 33. For the

actual placement of I/O pins, refer to “Pinout ATmega162” on page 2. CPU accessible

I/O Regis ters , in cl ud ing I/O bi ts a nd I /O pin s, ar e shown in bold. The dev ic e-s pec i fic I/O

page 98.

Figure 33. 8-bit Timer/Counter Block Diagram

Registers The Timer/Coun ter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers.

Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer

Interrupt Flag Register ( TIFR). All int errupts are i ndividually m asked with the T imer

Inter rupt Mas k Registe r (TIMSK) . TIFR an d TIMSK ar e not show n in the fi gure sinc e

these registers are shared by other timer units.

The Timer/Counter can be clocked internally, via th e prescaler, or by an external clock

source on the T0 pin. The Clock Select logic block controls which clock source and edge

the Timer/Counter uses to increment ( or decrement) its value. The Timer/Counter is

Timer/Counter

DATA BUS

TCNTn

Waveform

Generation OCn

= 0

Control Logic

0xFF

BOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCRn

TCCRn

Clock Select

Edge

Detector

( From Prescaler )

clkTn

TOP

OCn

(Int.Req.)

88 ATmega162(V/U/L) 2513C–AVR–09/02

inactiv e when no c lock source is selected. The output from the c lock select l ogic is

referred to as the timer clock (clkT0).

The double buffered Output Compare Register (OCR0) is compared with the

Timer/Counter value at all times. The result of the compare can be used by the Wave-

form Generator to generate a PWM or variable frequency output on the Output Compare

pin (OC0). See “Output Compare Unit” on page 89. for details. The compare match

event will also set the Compare Flag (OCF0) which can be used to generate an output

compare interrupt request.

Definitions Many register and bit references in this section are written in general form. A lower case

“n” replaces the Timer/Counter number, in this case 0. However, when using the register

or bit def ines in a progr am, the precis e form must be use d i.e., TCNT 0 for accessing

Timer/Counter0 counter value and so on.

The definitions in Table 46 are also used extensively throughout the document.

Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock

source i s selec ted by the Clock S elect logic which is controlled b y the Clock Selec t

(CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details on

clock sources and prescaler, see “Timer/Counter0, Timer/Counter1, and

Timer/ Cou nter3 Pr es ca le rs” on page 102.

Table 46. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0x FF (MAX) or the value stor ed in the OCR0 Register. The

assignment is dependent on the mode of operation.

ATmega162(V/U/L)

2513C–AVR–09/02

Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.

Figure 34 shows a block diagram of the counter and its surroundings.

Figure 34. Counter Unit Block Diagram

Signal description (internal signals):

count Increment or decrement TCNT0 by 1.

direction Select between increment and decrement.

clear Clear TCNT0 (set all bit s to zero).

clkTnTimer/Counter clock, referred to as clkT0 in the following .

top Signalize that TCNT0 has reached maximum value.

bottom Signalize that TCNT0 has reached minimum value (zero).

Depen ding of the mode of oper ation us ed, the co unter is cl eared , incremen ted, or de c-

remented at each timer clock (clkT0). clkT0 can be generated from an external or internal

clock source, selected by the clock select bits (CS02:0). When no clock source is

selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed

by the CPU, regardless of whet her clkT0 is present or not. A CPU write overrides (has

priority over) all counter clear or count operations.

The cou nting sequenc e is determine d by the settin g of the WGM01 and WG M00 bits

located in t he Timer/Counter Control Register (TCCR0). There a re close connect ions

between how the counter behaves (counts) and how waveforms are generated on the

output Compare Output OC0. For more details about advanced counting sequences

and waveform generation, see “Modes of Operation” on page 92.

The Timer/Counter overflow (TOV0) flag is set according to the mode of operation

selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

Output Compare Unit T he 8-bi t com parat or cont inu ously com par e s TCNT0 with the Out put Com par e Reg ister

(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will

set the Ou tpu t Co mpa re F la g (OCF0 ) at the nex t tim er c lo ck c y cle. If e nab led (OCIE0 =

1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an out-

put compare interrupt. T he OCF0 flag is automati cally cleared when the interrupt is

executed. Alter natively, the OCF 0 flag can be clear ed by software by writing a logical

one to its I/O bit location. The waveform generator uses the match signal to generate an

output acc ording to oper ating mode set by the WGM01:0 bits and Com pare Output

mode (COM01:0) bits. The max and bottom signals are used by the waveform generator

for handling the special cases of the extreme values in some modes of operation (See

“Modes of Operation” on page 92.).

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

90 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 35 shows a block diagram of the output compare unit.

Figure 35. Output Compare Unit, Block Diagram

The OCR0 Register is double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation,

the double buffering is disabled. The double bu ffering synchr onizes the up date of the

OCR0 Compare Register to either top or bottom of the counting sequence. The synchro-

niza tion pre vents the occu rrenc e of odd- length, non-s ymme trical PW M puls es, th ereby

making the output glitch-free.

The OCR0 Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has a ccess to th e OCR0 Buffer Register, and if double

buffering is disabled the CPU will access the OCR0 directly.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC0) bit. Forcing compare

match will not set the OCF0 flag or reload/clear the Timer, but the OC0 pin will be

updated as if a real compare match had occurred (the COM01:0 bits settings define

whether the OC0 pin is set, cleared or toggled).

Compare Match Blocking by

TCNT0 Write All CP U write opera tions to the TCNT0 Regi ster will b lock any comp are match tha t

occur i n the nex t tim er cl ock c ycle, even when the timer is sto pped. This fe atu re all ows

OCR0 to be i nit ia lize d to the same v al ue as TCNT 0 with out trigg er ing an i nte rrup t whe n

the T imer/Counter clock is enabled.

OCFn (Int.Req.)

= (8-bit Comparator )

OCRn

OCn

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

ATmega162(V/U/L)

2513C–AVR–09/02

Using the Output Compare

Unit Since writing TCNT0 in any mode of operation will block all compar e matches for one

timer clock cycle, there are risks involved when changing TCNT0 when using the output

compare channel, independently of whether the Timer/Counter is running or not. If the

value written to TCNT0 equals the OCR0 value, the compare match will be missed,

resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value

equal to BOTTOM when the counter is downcounting.

The setup of the OC0 should be performed before setting the Data Direction Register for

the port pin to output. The easiest way of setting the OC0 value is to use the Force Out-

put C ompare (FOC 0) strobe bits in N ormal mod e. The OC0 Re gister kee ps its val ue

even when changing between Waveform Generation modes.

Be aware that the COM01:0 bits are not doubl e buffered together with the compare

value. Changing the COM01:0 bits will take effect immediately.

Compare Match Output

Unit The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera-

tor uses the COM 01:0 bits for defining the Output Compare (OC0) state at the next

compare match. Also, the COM01:0 bits control the OC0 pin output source. Figure 36

shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O

Regist ers, I/O bits, an d I/O pins in the fi gure are show n in bold. Only the parts of the

general I/O port contro l registers (DDR and PORT) that are affec ted by the COM01:0

bits are shown. When referring to the OC0 state, the reference is for the internal OC0

Figure 36. Compare Match Output Unit, Schematics

The general I/O port function is overridden by the Output Compare (OC0) from the

wavefo rm gener ator if ei ther of t he COM01: 0 bits are set. H owever, the OC0 pin direc-

tion (input or output) is still controlled by the Data Direction Register (DDR) for the port

pin. T he Data Dire ction Regi ster bi t for the O C0 p in ( DDR_ OC0) must be se t as o utput

befor e the OC 0 value is v isible on the pin . The por t overrid e funct ion is in depend ent of

the Waveform Generation mode.

PORT

DDR

OCn

Waveform

Generator

COMn1

COMn0

DATA BUS

FOCn

clkI/O

92 ATmega162(V/U/L) 2513C–AVR–09/02

The design of the output compare pin logic allows initialization of the OC0 state before

the output is enabled. Note that some COM01:0 bit settings are reserved for certain

modes of operation. See “8-bit Timer/Counter Register Description” on page 98.

Compare Output Mode and

Waveform Generation The Wavefor m Gener ator uses the COM01:0 bit s differen tly in Norma l, CTC, and PW M

modes. For all modes, setting the COM01:0 = 0 tells the Waveform Generator that no

action on the OC0 Regis ter is to be performed on the next compare match. For Com -

pare Output actions in the non-PWM modes refer to Table 48 on page 99. For fast PWM

mode, refer to T able 49 on page 99, and for phase c orrect PWM refer to Table 50 on

page 99.

A change of the CO M01 :0 bits state wi ll have effect at the fir st compare mat ch after the

bits are written. For non-PWM modes, the action can be forced to have immediate effect

by using the FOC0 strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, i s defi ned b y the com binati on of the Wave form Genera tion mode (WGM 01:0) an d

Compare Output mo de (COM01:0) bi ts. The Comp are Output mode bits do not affect

the countin g sequence, whil e the Waveform Gene ration mode bits do. The COM01 :0

bits control whe ther the PWM output generated sho uld be inver ted or not (inverte d or

non-inver te d P WM ). F or no n- PW M mod es the COM0 1:0 bits control whe ther t he o utp ut

should be set, cleared, or tog gled at a comp are match (See “ Compare Mat ch Output

Unit” on page 91.).

For detaile d tim ing inform ation refe r to Figure 40, F igure 41, F igure 42 and Figure 43 in

“Timer/Counter Timing Diagrams” on page 96.

Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the

counting direction is always up (incr ementing), and no counter clear is performed. The

counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then

restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag

(TOV0) wi ll be set in the same t imer clock cyc le as the T CNT0 becomes z ero. The

TOV0 flag in this case behaves like a ninth bit, except that it is only set, not cleared.

However, c omb ine d wi th the tim er over fl ow int erru pt t hat auto matically c lears t he TO V 0

flag, the timer resolution can be increased by s oftware. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The output compare unit can be used to generate inte rrupts at some given time. Using

the outp ut co mpa re to ge ner ate wa vefor ms in Normal mod e is not rec om men ded , si nc e

this will occupy too much of the CPU time.

Clear Timer on Compare

Match (CT C) Mo d e In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the

counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the

counter, hence also its resolution. This mode allows greater control of the compare

match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 37. The counter value

(TCNT0) increases until a compare match occurs between TCNT0 and OCR0, and then

counter (TCNT0) is cleared.

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 37. CT C Mode, Timing Dia gr am

An interrupt can be ge nerated each time the counter value reaches the TOP v alue by

using the OCF0 flag. If the interrupt is enabled, the interrupt handler routine can be used

for updating the TOP value. However, changing TOP to a value close to BOTTOM when

the counte r is running with none or a low presc aler value mu st be done with car e since

the CTC mode d oes not have the double buffering feature. If the new value written to

OCR0 is lo wer than the c urrent value of T CNT0, the counter will miss the compare

match. The counter will then have to count to its maximum value (0xFF) and wrap

around starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC0 output can be set to toggle its

logical level on each compare match by setting the Compare Output mode bits to toggle

btmode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data

direct ion fo r the pin is set to ou tput. T he w avefor m ge nerate d will have a max imum fre-

quency of fOC0 = fclk_I/O/2 when OCR0 i s set to ze ro (0x00 ). The w avefor m freq uenc y is

defined by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mo de of op er ati on, the T OV0 f lag is s et in the sam e timer c l ock c y cl e

that the counter counts from MAX to 0x00.

Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high fre-

quency PWM waveform generation option. The fast P WM differs from the other PWM

option by its single-slope operation. The counter counts from BOTTOM to MAX then

restarts from BOTTOM. In non- inverting Compa re Output mode, the Ou tput Compare

(OC0) is cleared on the compare match between TCNT0 and OCR0, and set at BOT-

TOM. In inverting Compare Output mode, the output is set on compare match and

cleared at BOTTOM. Due to the single-slope operat ion, the operating frequency of the

fast PWM mode can be twice as high as the phase correct PWM mode that use dual-

slope operation. This high frequency makes the fast PWM mode well suited for power

regulation, rectification, and DAC applic ations. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX

value. The counter is then cleared at the following timer clock cycle. The timing diagram

for the fast PWM mode is shown in Figure 38. The TCNT0 value is in the timing diagram

shown as a histogram for illustrating the single-slope operation. The diagram includes

TCNTn

OCn

(Toggle)

OCn Interrupt Flag Set

1 4

Period 2 3

(COMn1:0 = 1)

fOCn fclk_I/O

2N1OCRn+()⋅⋅

-----------------------------------------------=

94 ATmega162(V/U/L) 2513C–AVR–09/02

non-inver ted and in vert ed PWM ou tputs. The s mall ho rizontal line mar ks on the T CNT0

slopes represent compare matches between OCR0 and TCNT0.

Figure 38. Fast PWM Mode, Timing Diagram

The Ti mer/ Counter Ove rflo w Flag (TO V0) i s set ea ch t ime t he coun ter reache s MAX. I f

the interrup t is enab led, the in terrupt ha ndler routine c an be used for updating the com-

pare value.

In fast PWM mode , the c omp are uni t al lows gen erati on of PWM wavefor m s on the O C0

pin. Setting the COM01:0 bits to two will produce a non-inverted PWM and an inverted

PWM output can be gener ated by sett ing the CO M01:0 to three ( See Tabl e 49 on page

99). T he actu al OC0 valu e will only be visible on the po rt pin if the data di rec tion for the

port pin is set as output. Th e PWM waveform is generated by setting (or clearing) the

OC0 Register at the compare match between OCR0 and TCNT0, and clearing (or set-

ting) the OC0 Register at the timer clock cycle the counter is clear ed (changes from

MAX to BOTTOM) .

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0 Register represents special cases when generating a

PWM waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the

output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal

to MAX will result in a constantly high or low output (depending on the polarity of the out-

put set by the COM01:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OC0 to toggle its logical level on each compare match (COM01:0 = 1). The

waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0 is

set to zer o. This feature is simila r to the OC0 toggle in CTC mode, except the dou ble

buffer feature of the output compare unit is enabled in the fast PWM mode.

TCNTn

OCRn Update ans

TOVn Interrupt Flag Set

Period 2 3

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

4 5 6 7

fOCnPWM fclk_I/O

N256⋅

------------------=

ATmega162(V/U/L)

2513C–AVR–09/02

Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-

slope operation. The counter counts r epeatedly from BOTTOM to MAX and then from

MAX to BOTTO M. In non-in verti ng Com pare O utpu t mod e, the Ou tput C ompare (OC0)

is clea red on the compare matc h bet ween TCN T 0 and OCR0 while upcou nti ng, a nd s et

on the compare match while downcounting. In inverting Output Compare mode, the

operation is inverted. The dual-slope operation has lower maximum operation frequency

than sing le slope operati on. However, due to the sy mmetric fea ture of the dual-slop e

PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phas e correct PWM mo de is fixed to ei ght bits. In pha se

correct PW M mode the counter is inc rement ed until the counter value matc hes MAX.

When the counter reaches MAX, it changes the count direction. The TCNT0 value will

be equal to MAX for one timer clock cycle. The timing diagram for the phase correct

PWM mode is shown on Figure 39. The TCNT0 value is in the timing diagram shown as

a histo gram for i llustr ating the d ual-sl ope o peratio n. T he di agram i nclu des non -inver ted

and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes repre-

sent compare matc he s betwe en OCR 0 and TCNT0 .

Figure 39. Phase Correct PWM Mode, Timing Diagram

The Tim er/Counte r Overflo w Flag (TOV0 ) is s et each time th e counte r reache s BOT-

TOM. The interrupt flag can be us ed to generate an interrupt each time the counter

reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on

the OC0 pin. Setting the COM01:0 bits to two will produce a non-inverted PWM. An

invert ed PWM output c an be g enerat ed by sett ing the C OM01: 0 to thr ee (See T able 5 0

on page 99). The actual OC0 value will only be visible on the port pin if the data direction

for the port pin is set as output. The PWM waveform is generated by clearing (or setting)

the OC0 Register at the compa re match between O CR0 and T CNT0 when th e count er

increments, and setting (or clearing) the OC0 Register at compare match between

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

1 2 3

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

96 ATmega162(V/U/L) 2513C–AVR–09/02

OCR0 and TCNT 0 when the counter d ecrements . The PWM frequency for th e output

when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The ex treme val ues for the OCR0 Regi ster rep resent sp ecial ca ses whe n generati ng a

PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to

BOTTO M, the o utput wi ll be con tinuous ly low a nd if s et equa l to MA X the ou tput wil l be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

Timer/Counter Ti ming

Diagrams The Timer/Count er is a synch ronous desig n and the timer clock (clk T0) is therefore

shown a s a clock enable s ignal in th e follo wing fig ures. Th e figures inclu de inform atio n

on when interru pt flag s are set . Figu re 40 cont ains t iming data for ba sic Time r/Coun ter

operation. The figure shows the count s equence close to the MAX v alue in all m odes

other than phase correct PWM mode.

Figure 40. Timer/Counter Timing Diagram, no Prescaling

Figure 41 shows the same timing data, but with the prescaler enabled.

Figure 41. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 42 shows the setting of OCF0 in all modes except CTC mode.

fOCnPCPWM fclk_I/O

N510⋅

------------------=

clk

(clkI/O/1)

TOVn

clk

I/O

TCNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

TCNTn

MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 42. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8)

Figure 43 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.

Figure 43. Timer/Counter Timi ng Dia gram, Cl ear Timer on Com par e Mat ch Mode, with

Prescaler (fclk_I/O/8)

OCFn

OCRn

TCNTn

OCRn Value

OCRn - 1 OCRn OCRn + 1 OCRn + 2

clk

I/O

clk

(clkI/O/8)

OCFn

OCRn

TCNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

98 ATmega162(V/U/L) 2513C–AVR–09/02

8-bit Timer/Counter

Ti mer/Counter Control

• Bit 7 – FOC0: Force Output Compare

The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However,

for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is

written when operating in PWM mode . When writing a logica l one to the FOC0 bit, an

immed iate co mpare matc h is forced on the Wave form G eneratio n unit. Th e OC0 outp ut

is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented

as a strobe. Therefore it i s the value present in the COM01:0 bits that determines the

effect of the forced compare.

A FOC 0 strobe wil l not gene rate any interrupt, n or will it clear the ti mer in CTC mode

using OCR0 as TOP.

The FOC0 bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the cou nting sequence of the co unter, the source for the maximum

(TOP) counter value, and what type of waveform generation to be used. Modes of oper-

atio n supported by the Timer /Counter unit are: Nor mal mode , Clear Tim er on Compar e

match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table

47 and “Modes of Ope ra tio n” on page 92.

Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-

initions. However, the functionality and location of these bits are compatible with

previous versions of the timer.

• Bit 5:4 – COM01:0: Compare Match Output Mode

These bits control the output compare pin (OC0) behavior. If one or both of the

COM01 :0 b its are set , the O C0 ou tput ov erride s t he n orm al p ort f unc tion alit y of the I/O

pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-

sponding to the OC0 pin must be set in order to enable the output driver.

Bit 76543210

FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0

Read/Write W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 47. Waveform Generation Mode Bit Description(1)

Mode WGM01

(CTC0) WGM00

(PWM0) Timer/Counter Mode

of Operation TOP Update of

OCR0 at TO V0 Flag

Set on

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xF F T O P BOTTOM

2 1 0 CTC OCR0 Immediate MAX

31 1Fast PWM 0xFFTOPMAX

ATmega162(V/U/L)

2513C–AVR–09/02

When O C0 is conn ected to the pin, the function of the CO M01:0 bi ts depends on the

WGM01:0 bit setting. Table 48 shows the COM01:0 bit functionality when the WGM01:0

bits are set to a Normal or CTC mode (non-PWM).

Table 49 shows the COM01:0 bit fu nctionality when the WGM0 1:0 bits are set to fast

PWM mode.

Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the

compare m atch is ign ored, bu t the s et or clear i s done at T OP. See “Fast PW M Mode”

on page 93 for more details.

Table 50 sho ws the COM 01:0 bi t fu nc tio nal ity wh en the W GM01:0 bi ts are se t to phase

correct PW M mode .

Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the

compare match is ignored, but the set or clear is done at TOP. See “Phase Correct

PWM Mode” on page 95 for more details.

Table 48. Compare Output Mode, non-PWM Mode

COM01 COM00 Description

0 0 Normal port operation, OC0 disconnected.

0 1 Toggle OC0 on compare match.

1 0 Clear OC0 on compare match.

1 1 Set OC0 on compar e matc h.

Table 49. Compare Output Mode, fast PWM Mode(1)

COM01 COM00 Description

0 0 Normal port operation, OC0 disconnected.

01Reserved

1 0 Clear OC0 on compare match, set OC0 at TOP.

1 1 Set OC0 on compare match, clear OC0 at TOP.

Table 50. Compare Output Mode, Phase Correct PWM Mode(1)

COM01 COM00 Description

0 0 Normal port operation, OC0 disconnected.

01Reserved

1 0 Clear OC0 on compare match when up-counting. Set OC0 on

compare match when downcounting.

1 1 Set OC0 on compare match when up-counting. Clear OC0 on

compare match when downcounting.

100 ATmega162(V/U/L) 2513C–AVR–09/02

• Bit 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

If external pin modes are used for the Timer/Counter 0, transitions on the T0 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the counti ng.

Timer/Counter Register –

TCNT0

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8 -bit counter. Writing to the T CNT0 Register blocks (removes )

the compare match on the following timer cl ock. Modifying the counter (TCNT0) while

the counter is running, introduces a risk of missing a compare match between TCNT0

and the OCR0 Register.

Output Compare Register –

OCR0

The Output Compare Register contains an 8-bit value that is continuously compared

with the counter value (TCNT0). A match can be used to generate an output compare

interrupt, or to generate a waveform output on the OC0 pin.

Timer/Counter Interrupt Mask

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if

an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the

Timer/Counter Interrupt Flag Register – TIFR.

Table 51. Clock Select Bit Description

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped).

001

clkI/O/(No prescaling)

010

clkI/O/8 (From prescaler)

011

clkI/O/64 (From prescaler)

100

clkI/O/256 (From prescaler)

101

clkI/O/1024 (From prescaler)

1 1 0 External clock source on T0 pin. Clock on falling edge.

1 1 1 External clock source on T0 pin. Clock on rising edge.

Bit 76543210

TCNT0[7:0] TCNT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

OCR0[7:0] OCR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

101

ATmega162(V/U/L)

2513C–AVR–09/02

• Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is

executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in

the Timer/Counter Interrupt Flag Register – TIFR.

Timer/Counter Interrupt Flag

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 i s set (one) whe n an over flow occu rs in Timer /Count er0. TOV0 i s cleare d

by har dware when execut ing the c orresp onding in terru pt handl ing vect or. Alter nativel y,

TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0

(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the

Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is

set when Timer/Counter0 changes counting direction at 0x00.

• Bit 0 – OCF0: Output Compare Flag 0

The OC F0 bi t is set (o ne) wh en a comp are ma tch occ urs be tween the Time r/Co unter0

and the data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when

executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by

writing a logic one to the fl ag. When the I-bit in SREG, OC IE0 (Timer/Counter0 Com -

pare ma tch Interr upt Enable ), and O CF0 are set (one), the Timer /Counter 0 Compare

Match Interrupt is executed .

Bit 76543210

TOV1 OCF1A OCF1B OCF2 ICF1 TOV2 TOV0 OCF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

102 ATmega162(V/U/L) 2513C–AVR–09/02

Timer/Counter0,

Timer /Counter1, and

Timer/Counter3

Prescalers

Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler mod-

ule, but the Timer/Counters can have different prescaler settings. The description below

applies to Timer/Counter3, Timer/Counter1, and Timer/Counter0.

Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =

1). This pr ovides the fa stest operati on, wi th a maxim um Tim er/Co unter c lock freq uen cy

equal to system clock frequency (fCLK_I/O). Alterna tively , one of fou r taps fr om the pre s-

caler can be use d as a clock source. The pr escaled clock has a frequency of either

fCLK_I/O/8, fCLK_I/O/64 , fCLK_I/O/256, or fCLK_I/O/1024. In addition, Timer/Counter3 has the

option of choosing fCLK_I/O/16 and fCLK_I/O/32.

Prescaler Reset The prescaler is free running, i.e., operates independently of the clock select logic of the

Timer/Counter, and it is shared by Timer/Counter3, Timer/Counter1, and

Timer/Counter0. Since the prescaler is not affected by the Timer/Counter’s clock select,

the st ate o f the pr es ca ler wi ll ha ve imp li ca tio ns for situa t io ns where a pr es c ale d c lock is

used. One examp le of prescaling artifacts occurs when th e Timer is enabled and

clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from

when th e Timer is enabl ed to th e first count occu rs can be from 1 to N+1 sy stem cl ock

cycles, where N equals the prescaler divisor (8, 64, 256, or 1024, additional selections

for Timer/Counter3: 32 and 64).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program

execution. However, care must be taken if the other Timer/Counter that shares the

same prescaler also uses prescaling. A Prescaler Reset will affect the prescaler pe riod

for all Timer/Counters it is connected to.

Extern al Clock So urc e An external clock source applied to the Tn/T0 pin can be used as Timer/Counter clock

(clkT1/clkT0) for Timer/Count er1 and Timer /Counter0. Th e Tn/T0 pin is samp led once

every s ys tem c loc k cyc le b y th e pin sy nchron iza tion lo gic. The s ync hroniz ed ( sam pled)

signal is then pa ssed through the edge detector. Figure 44 shows a functional equiva-

lent block diagram of the Tn/T0 synchronization and edge detector logic. The registers

are clocked at the positive edge of the internal system clock (clkI/O). The latch is trans-

parent in the high period of the internal system clock.

The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or neg-

ative (CSn2:0 = 6) edge it detects.

Figure 44. Tn/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system

clock cycles from an edge has been applied to the Tn/T0 pin to the counter is updated.

Enablin g a nd d is abl in g o f th e c lo ck i npu t mu st be don e when Tn/T 0 h as bee n st ab le for

at least one system c lock cycle , otherwise i t is a risk that a false Timer/Cou nter clock

pulse is generated.

Tn_sync

(To Clock

Select Logic)

Edge DetectorSynchronization

DQDQ

clkI/O

103

ATmega162(V/U/L)

2513C–AVR–09/02

Each half period of the external clock applied must be longer than one system clock

cycle to ensure correct sampling. The external clock must be guaranteed to have less

than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since

the edge detector use s sampling , the maximum fr equency of a n external clo ck it can

detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-

ation of t he sys tem cl oc k freq uenc y and d uty cycl e c aused by Oscillator sour ce (cr yst al,

resonator, and capacitors) tolerances, it is recommended that maximum frequency of an

external clock source is less than fclk_I/O/2.5.

An external clock source can not be prescaled.

Figure 45. Prescaler for Timer/Co unter0, Timer/Counter1, and Timer/Counter3(1)

Note: 1. The synchronization logic on the input pins (Tn/T0) is shown in Figure 44.

Special Function IO Register –

SFIOR

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing t he TSM bit to one activates th e Timer/Counter Synchronization mode. In this

mode, the value that is written to the PSR2 and PSR310 bits is kept, hence keeping the

corresponding prescaler reset signals asserted. This ensures that the corresponding

Timer/Counters are halted and can be configured to the same value without the risk of

one of them ad vancing dur ing configur ation. When the TSM bit is writte n to zero, the

PSR2 and PSR310 bits are cleared by hardware, and the Timer/Counters start counting

simultaneously.

• Bit 0 – PSR310: Prescaler Reset Timer/Counter3, Timer/Counter1, and

Timer/Counter0

When thi s bit is one, the Timer /Counter3, Ti mer/Counter 1, and Timer/Coun ter0 pres-

caler wil l be reset. This b it is normally c leared immediately by hardware, excep t if the

TSM bit is set. No te that Timer/Counter 3, Timer/Counter1, and Timer/Counter0 share

the same prescaler and a reset of this prescaler will affect all three timers.

PSR321

Clear

clk

TIMER/COUNTER1 CLOCK SOURCE

CS10

CS11

CS12

clk

TIMER/COUNTER1 CLOCK SOURCE

CS00

CS01

CS02

clk

TIMER/COUNTER3 CLOCK SOURCE

CS30

CS31

CS32

10-BIT T/C PRESCALER

CK/8

CK/64

CK/256

CK/1024

CK/16

CK/32

Bit 7 6 5 4 3 2 1 0

TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

104 ATmega162(V/U/L) 2513C–AVR–09/02

16-bit Timer/Counter

(Timer/Counter1 and

Timer/Counter3)

The 16-bit Timer/Counter unit allows accurate program execution timing (event man-

agement), wave generation, and signal timing measurement. The main features are:

•True 16-bit Design (i.e., allows 16-bit PWM)

•Two Independent Output Compare Units

•Double Buffered Output Compare Registers

•One Input Capture Unit

•Input Capture Noise Canceler

•Clear Timer on Compare Match (Auto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Variable PWM Period

•Frequency Genera tor

•External Event Counter

•Eight Independent Interrupt Sources (TOV1, OCF1A, OCF1B, ICF1, TOV3, OCF3A,

OCF3B, and ICF3)

Restriction in

ATmega161

Compatibility Mode

Note that in ATmega161 compatibility mode, only one 16-bits Timer/Counter is available

(Timer/Counter1).

Overview Most register and bit refer en ce s in th is se ct ion are writ ten i n ge ner al for m. A l ower c ase

“n” repl aces the Time r/ Coun ter nu mber, and a l ower cas e “x ” re pla ce s t he Out put Com-

pare unit channel. However, when using the register or bit defines in a program, the

precise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value and

so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 46. For the

actual placement of I/O pins, refer to “Pinout ATmega162” on page 2. CPU accessible

I/O Regis ters , in cl ud ing I/O bi ts a nd I /O pin s, ar e shown in bold. The dev ic e-s pec i fic I/O

on page 126.

105

ATmega162(V/U/L)

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Figure 46. 16-bit Timer/Counter Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Table 32 on page 70, and Table 38 on page 76 for

Timer/Counter1 pin placement and description.

Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B), and Input Capture

acces sing the 16- bit reg isters . These pro cedures are descr ibed in the section “Access -

ing 16-bit Register s” on page 107 . The Timer/Counter Control Regi sters (TCCRnA/B)

are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated

to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR)

and Extended Timer Interrupt Flag Register (ETIFR). All interrupts are individually

masked with the Timer Interrupt Mask Register (TIMSK) and Extended Timer Interrupt

Mask Register (ETIMSK). (E)TIFR and (E)TIMSK are not shown in the figure since

these registers are shared by othe r Time r uni ts.

The Timer/Counter can be clocked internally, via th e prescaler, or by an external clock

source on the T1 pin. The Clock Select logic block controls which clock source and edge

the Timer/Counter uses to increment ( or decrement) its value. The Timer/Counter is

inactive when no clock source is selected. The output from the Clock Select logic is

referred to as the Timer Clock (clkTn).

The double buffered Output Compare Registers (OCRnA/B) are compared with the

Timer/Counter value at all time. The result of the compare can be used by the waveform

gener ator to g enerate a P WM or vari able fr equency output on the Outp ut Compare pin

Clock Select

Timer/Counter

DATABUS

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clk

106 ATmega162(V/U/L) 2513C–AVR–09/02

(OCnA /B). See “Out put Compare Un its” on pag e 113. The compa re match eve nt will

also s et th e Comp are Match Flag (OC FnA/B) whi ch can be us ed t o gene rate an ou tput

compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external

(edge trig ger ed ) e vent on ei ther th e Inp ut Ca pture pin (ICPn ) o r on the An alo g Compar-

ator pins (See “Analog Comparator” on page 192.) The input capture unit includes a

digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or max imum Timer /Counter value, c an in some mo des of operati on be

defined by either the OCRnA Register, th e ICRn Register, or by a set of fixed values .

When usi ng OCRnA as TOP valu e in a PWM mode, the OCR nA Register can no t be

used for gen erating a PWM outp ut. However, the TOP value will in this case be double

buffered allowing the TOP value to be changed in run time. If a fixed TOP value is

required, the ICRn Register can be used as an alternative, freeing the OCRnA to be

used as PWM output.

Definitions The following definitions are used extensively throughout the section:

Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the

16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier

version regarding:

• All 16-bit Timer/Counter related I/O Register address locations, including Timer

Interrupt Registers.

• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt

Registers.

• Interrupt Vectors.

The fol lowing co ntr ol bi ts have c ha nge d na me, but hav e sam e fu nc tio nal ity a nd re g ister

location:

• PWMn0 is changed to WGMn0.

• PWMn1 is changed to WGMn1.

• CTCn is changed to WGMn2.

The following bits are added to the 16-bit Timer/Counter Control Registers:

• FOCnA and FOCnB are added to TCCRnA.

• WGMn3 is added to TCCRnB.

The 16-bit Timer/Counter has improvements that will affect the compatibility in some

special cases.

Table 52. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

MAX The co unter reache s its MAXimum when it becomes 0xFFFF (decimal

65535).

TOP The counter reaches the TOP when it becomes equal to the highest

value i n the co unt seq uence. The TOP v alue c an be assi gned to be on e

of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in

the OCRnA or ICRn Register. The assignment is dependent of the mode

of operation.

107

ATmega162(V/U/L)

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Access ing 16-bit

Registers The TCNTn, OCRnA/B , and ICRn are 16 -b it regi s ter s th at ca n be acc es se d by the AV R

CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or

write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the

high by te o f th e 1 6- bi t ac ces s. T he sa me Temp or ar y Reg ister i s sh ared between al l 16-

bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or

write operation. W hen the low byte of a 16-bit registe r is written by the CPU, the high

byte stored in the temporary register, and the low byte written are both copied into the

16-bit regi ster in the sam e clock c ycle. Wh en the low by te of a 16- bit reg ister is read by

the CPU, th e high byte of the 16-bi t register i s copied into the tempora ry registe r in the

same cloc k cyc le as the low byte is re ad.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the

OCRnA/B 16-bit registers does not involve using the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read,

the low byte must be read before the high byte.

The foll owing cod e exam ple s show how t o acce ss th e 16-bi t Timer Register s assu min g

that no interrupts updates the temporary register. The same principle can be used

directly for acce ssing the OCRnA/B an d ICRn Registe rs. No te that when using “C ”, the

compiler handles the 16-bit access.

Note: 1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “S TS” combine d with “SBRS”, “SBRC”, “SBR ”, and

“CBR”.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

It is imp ortant to no tic e t hat a cc es sing 16- bit r egi st ers a re ato mic op erati ons . If an i nte r-

rupt occur s betw een the two instruc tions access ing th e 16-bit r egister , and the interru pt

code updates the temporary register by accessing the same or any other of the 16-bit

Timer Register s, then the r esult of the access outs ide the int errupt wi ll be corru pted.

Assembly Code Examp les(1)

...

; Set TCNTn to 0x01FF

ldi r17,0x01

ldi r16,0xFF

out TCNTnH,r17

out TCNTnL,r16

; Read TCNTn into r17:r16

in r16,TCNTnL

in r17,TCNTnH

...

C Code Examples(1)

unsigned int i;

...

/* Set TCNTn to 0x01FF */

TCNTn = 0x1FF;

/* Read TCNTn into i */

i = TCNTn;

...

108 ATmega162(V/U/L) 2513C–AVR–09/02

Therefor e, whe n both the ma in c ode and th e int er rupt c ode u pdat e the te mporary regi s-

ter, the main code must disable the interrupts during the 16-bit access.

The foll owing code exam ples show ho w to do an atom ic read of the TCNT n Register

contents. Reading any of the OCRnA/B or ICRn Registers can be done by using the

same principle.

Note: 1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “S TS” combine d with “SBRS”, “SBRC”, “SBR ”, and

“CBR”.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

Assembly Code Examp le(1)

TIM16_ReadTCNTn:

; Save Global Interrupt Flag

in r18,SREG

; Disable interrupts

cli

; Read TCNTn into r17:r16

in r16,TCNTnL

in r17,TCNTnH

; Restore Global Interrupt Flag

out SREG,r18

ret

C Code Example(1)

unsigned int TIM16_ReadTCNTn( void )

{

unsigned char sreg;

unsigned int i;

/* Save Global Interrupt Flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNTn into i */

i = TCNTn;

/* Restore Global Interrupt Flag */

SREG = sreg;

return i;

}

109

ATmega162(V/U/L)

2513C–AVR–09/02

The following co de examples show how to do an atomic write of the TCNT n Register

contents. Wr iting any of the OCRnA/B or ICRn Registe rs can be done by using th e

same principle.

Note: 1. The example code assumes that the part specific header file is included.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,

and “SBI” instructions must be replaced with instructions that allow access to

extended I/O. Typically “LDS” and “S TS” combine d with “SBRS”, “SBRC”, “SBR ”, and

“CBR”.

The assembly code example requires that the r17:r16 register pair contains the value to

be written to TCNTn.

Reusing the Temporary High

Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers

written, then the high byte only needs to be written once. However, note that the same

rule of atomic oper ati on descr ib ed prev iou sl y also appl ie s in th is cas e.

Assembly Code Examp le(1)

TIM16_WriteTCNTn:

; Save Global Interrupt Flag

in r18,SREG

; Disable interrupts

cli

; Set TCNTn to r17:r16

out TCNTnH,r17

out TCNTnL,r16

; Restore Global Interrupt Flag

out SREG,r18

ret

C Code Example(1)

void TIM16_WriteTCNTn( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save Global Interrupt Flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNTn to i */

TCNTn = i;

/* Restore Global Interrupt Flag */

SREG = sreg;

}

110 ATmega162(V/U/L) 2513C–AVR–09/02

Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the clock select logic which is controlled by the Clock Select

(CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details on

clock sources and prescaler, see “Timer/Counter0, Timer/Counter1, and

Timer/ Cou nter3 Pr es ca le rs” on page 102.

Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional

counter unit. Figure 47 shows a block diagram of the counter and its surroundings.

Figure 47. Counter Unit Block Diagram

Signal description (internal signals):

Count Increment or decrement TCNTn by 1.

Direction Select between increment and decrement.

Clear Clear TCNTn (set all bit s to zero).

clkTnTimer/Counter clock.

TOP Signalize that TCNTn has reached maximum value.

BOTTOM Signalize that TCNTn has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High

(TCNTnH) contai ning the upper ei ght bits of the counter, and Coun ter Low (TCNTnL)

containing the lower eight bits. The TCNTnH Register can only be indirectly accessed

by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU

accesses the high byte temporary register (TEMP). The temporary register is updated

with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the

temporary register value when TCNTnL is written. This allows the CPU to read or write

the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is impor-

tant to not ice that ther e are speci al cases of writ ing to the TCN Tn Regist er whe n the

counter is counting that will gi ve unpr edic table res ults. T he spec ial c ases are de scr ibed

in the sections where they are of importance.

Depending on th e m ode of op er ati on used, the counter i s clea re d, incr em ente d, or de c-

remented at each Timer Clo ck (clkTn). The clkTn can be generated from an external or

internal clock source, selected by the Clock Select bits (CSn2:0). When no clock source

is selected (CSn2:0 = 0) the Timer is stopped. However, the TCNTn value can be

accessed by the CPU, independent of whether clkTn is present or not. A CPU write over-

rides (has priority over) all counter clear or count operations.

The coun ting sequen ce is det ermin ed by the se tting of the Waveform Generation mode

bits (W GM n3:0) l ocat ed in the Ti mer/Cou nter Cont rol Re gisters A and B (TCCRnA and

TCCRnB). There are close connections between how the counter behaves (counts) and

TEMP (8-bit)

DATA BUS

(8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit) Control Logic

Count

Clear

Direction

TOVn

(Int.Req.)

Clock Select

TOP BOTTOM

Edge

Detector

( From Prescaler )

clk

111

ATmega162(V/U/L)

2513C–AVR–09/02

how wave form s ar e gen erated on the Out put Co mpare outp uts OCn x. For mor e de tails

about advanced counting sequences and waveform generation, see “Modes of Opera-

tion” on page 116.

The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation

selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

Input Capture Unit The Timer/Counter incorporates an input capture unit that can capt ure external events

and give them a time-stamp indicating time of occurrence. The external signal indicating

an event, or multiple events, can be applied via the ICPn pin or alternatively, via the

Analog Comparator unit. The time-stamps can then be used to calcul ate frequency,

duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be

used for creating a log of the events.

The input capture unit is illustrated by the block diagram shown in Figure 48. The ele-

ments of the blo ck d iagram th at are no t dir ectly a part o f the i nput captu re un it are gray

shaded. The small “n” in register and bit names indicates the Timer/Counter number.

Figure 48. Input Capture Unit Block Diagram(1)

Note: 1. The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not

Timer/Counter3.

When a change of the logic level (an event) occurs on the Input Capture pin (ICPn),

alternatively on the Analo g Com parat or ou tput (ACO), and this change confirms to the

setting of the edge detector, a capture will be triggered. When a capture is triggered, the

16-bit val ue o f the co unte r (TCNTn ) is writte n to t he In put Capture Regis ter (ICRn ). The

Inpu t C ap t ur e F l a g (ICFn) is set at the same system clock as the TCNTn value is copied

into IC Rn Register. If enabled (T ICIEn = 1), the input c apture flag generates an input

capture interru pt. The ICF n flag is automati cally c leared when the i nterrup t is ex ecuted.

Alter nativel y the ICFn flag can be clear ed by softw are by writin g a logica l one to it s I/O

bit location.

ICFn (Int.Req.)

Analog

Comparator

WRITE ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

ICPn

Edge

Detector

TEMP (8-bit)

DATA BUS

(8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

ACIC* ICNC ICES

ACO*

112 ATmega162(V/U/L) 2513C–AVR–09/02

Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the

low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high

byte is copied into the high byte temporary register (TEMP). When the CPU reads the

ICRnH I/O location it will access the TEMP Register.

The ICRn Register can only be written when using a Waveform Generation mode that

utilizes the ICRn Register for defining the counter’s TOP value. In these cases the

Waveform G eneratio n mode (WG Mn3:0) b its m ust be set b efore the TOP valu e ca n be

written to the ICRn Register. When writing the ICRn Register the high byte must be writ-

ten to the ICRnH I/O location before the low byte is written to ICRnL.

For more infor mation on how to access the 16-bit regi sters refer to “Acce ssing 16-bi t

Registers” on page 107.

Input Capture Trigger Source The main trigger source for the input capture unit is the Input Capture pin (ICPn).

Timer/Counter1 can alternatively use the Analog Comparator output as trigger source

for th e inpu t captur e uni t. The A nalog Compa rator is sele cted a s trig ger sou rce by set-

ting the Analog Comparator Input Capture (ACIC) bit in the Analog Compar ator Control

and Status Register (ACSR). Be aware that changing trigger source can trigger a cap-

ture. The Input Capture Flag must therefore be cleared after the change.

Both t he In put C aptur e p in (IC Pn) and the An alog Comp arator ou tput (A CO) inpu ts are

sampled using the same technique as for the Tn pin (Figure 44 on page 102). The edge

detector is also ide ntical . Howeve r, when the no ise ca ncele r is enable d, additi onal lo gic

is inserted before the edge detector, which increases t he delay by four system clock

cycles. Note that the input of the no ise canceler and edge detector is always enabled

unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to

define TOP.

An input capture can be triggered by software by controlling the port of the ICPn pin.

Noise Canceler The Noi se Canc eler i mprov es n ois e imm uni ty by us i ng a s imp le di git al fil tering schem e.

The Noise Canceler input is monitored over four samples, and all four must be equal for

changing the output that in turn is used by the edge detector.

The Nois e Can ce ler is ena ble d by se ttin g the In put Capture Nois e Can celer (ICNCn ) bit

in Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler intro-

duces additional four system clock cycles of delay from a change applied to the input, to

the update of the ICRn Register. The noise canceler uses the system clock and is there-

fore not affected by the prescaler.

Using the Input Capture Unit The main challenge when using the input capture unit is to assign enough processor

capacity for handling the incoming events. The time between two events is critical. If the

processor has not read the captured value in the ICRn Register before the next event

occur s, the ICRn wil l be ov erwritt en with a new v alue. In this cas e the r esult of th e cap-

ture will be incorrect.

When using the input capture interrupt, the ICRn Register should be read as early in the

interrupt handler routine as possible. Even though the input capture interrupt has rela-

tively high pri ority, the maxi mum int errupt r espon se tim e is depen dent on t he ma ximu m

number of clock cycles it takes to handle any of the other interrupt requests.

Using the input capture unit in any mode of operation when the TOP value (resolution) is

actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed

after each captur e. Changi ng the edg e sens ing mus t be done as early as po ssible after

the ICRn Register has been read. Afte r a change of the ed ge, the Input Capture Flag

113

ATmega162(V/U/L)

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(ICFn) must be cleared by software (writing a logical one to the I/O bit location). For

measurin g frequency onl y, the clearing of the ICFn flag is not required (if an interrupt

handler is used).

Output Compare Units The 16-bit com parat or con tinuou sly com pares TCNTn with the O utput Compare Regis-

ter (OCRnx). If TCNT equals OCRnx the compar ator signals a match. A match will set

the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx =

1), the Out put Co mpa re Flag ge ner at es an outp ut comp ar e int er rupt. T he OCFn x flag is

automatically cleared when the interrupt is executed. Alternatively the OCFnx flag can

be cleared by software by writing a logical one to its I/O bit location. The Waveform Gen-

erator uses the matc h signal t o generate an ou tput acco rding to operating mo de set by

the Waveform Generation mode (WGMn3:0) bits and Compare Output mode

(COMnx1:0) bits. Th e TO P and BOT TO M s ignal s are u se d b y t he W av efo rm G ene ra tor

for handling the special cases of the extreme values in some modes of operation (See

“Modes of Operation” on page 116.)

A special feature of output c ompare unit A al lows it to define th e Timer/Coun ter TOP

value (i.e., co unter resoluti on). In a ddition to th e counter resolution , the TOP value

defines the period time for waveforms generated by the Waveform Generator.

Figure 49 sh ows a bl ock di agr am o f the outp ut co mpa re un it. T he s mal l “n” i n t he r egi s-

ter and bit names indicates the device number (n = n for Timer/Counter n), and the “x”

indicates output compare unit (A/B). The elements of the block diagram that are not

directly a part of the output compare unit are gray shaded.

Figure 49. Output Compare Unit, Block Diagram

The OCRnx Register is double buffered when using any of the twelve Pulse Width Mod-

ulation (P WM) modes. For the normal and Clear Timer on Compare (CTC) modes of

operation, the double buffering is disabled. The double buffering synchronizes the

update of the OCRnx Compare Register to either TOP or BOTTOM of the counting

OCFnx (Int.Req.)

(16-bit Comparator )

OCRnx Buffer (16-bit Register)

OCRnxH Buf. (8-bit)

OCnx

TEMP (8-bit)

DATA BUS

(8-bit)

OCRnxL Buf. (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

COMnx1:0WGMn3:0

OCRnx (16-bit Register)

OCRnxH (8-bit) OCRnxL (8-bit)

Waveform Generator

TOP

BOTTOM

114 ATmega162(V/U/L) 2513C–AVR–09/02

sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical

PWM pulse s, ther eb y mak ing the output glitch- fr ee.

The OCRnx Regis ter acce ss may seem complex , but this is not cas e. When the double

buffering is enabled, the CPU has access to the OCRnx Buff er Register, and if double

buffering is disabled the CPU will access the OCRnx directly. The content of the OCR1x

(Buffer or Compare) Register is only changed by a write operation (the Timer/Counter

does not update this register automatically as the TCNT1 and ICR1 Register). Therefore

OCR1x is not read via the high byte temporary register (TEMP). However, it is a good

practice to read the low byte first as when accessing other 16-bit registers. Writing the

OCRnx Regi st ers must be d one v ia th e TE MP R egi st er s ince th e compare of all 16 bits

is done continuously. The high byte (OCRnxH) has to be written first. When the high

byte I/O locati on is written by the CPU, the TEMP Reg ister will be upd ated by the valu e

written. Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte

will be copied into the upper eight bits of either the OCRnx buffer or OCRnx Compare

For more information of how to access the 16-bit registers refer to “Accessing 16-bit

Registers” on page 107.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing compare

match will not set the OCFnx flag or reload/clear the timer, but the OCnx pin will be

updated as if a real compare match had occurred (the COMn1:0 bits settings define

whether the OCnx pin is set, cleared or toggled).

Compare Match Blocking by

TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be

initialized to the same value as TCNTn without triggering an interrupt when the

Timer/Counter clock is enabled.

Using the Output Compare

Unit Since writing TCNTn in any mode of operation will block all compar e matches for one

timer clock cycle, there are risks involved when changing TCNTn when using any of the

output co mpare channel s, independ ent of wheth er the Time r/Coun ter is runnin g or not.

If the value written to TCNTn equals the OCRnx value, the compare match will be

missed , result ing in incor rect wave form gene ration. Do n ot write the TCNTn equa l to

TOP in PW M mode s with v ariable TOP v alues . The comp are ma tch for the TOP wil l be

ignored and the counter will contin ue to 0xFFFF. Similarl y, do not write the TCNTn value

equal to BOTTOM when the counter is downcounting.

The setup of the OCnx should be performed before setting the Data Direction Register

for the port pin to ou tput. The easiest way of se ttin g the OCnx value i s to use the Forc e

Output Compare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its

value even when changing between Waveform Generation modes.

Be aware that the COMnx1:0 bits are not double buffered together with the compare

value. Changing the COMnx1:0 bits will take effect immediately.

115

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Compare Match Output

Unit The Compare Output mode (COMnx1:0) bits have two functions. The waveform genera-

tor uses the COMnx1:0 bits for defining the output compare (OCnx) state at the next

comp are ma tch. Sec ondly th e COMn x1:0 b its cont rol th e OCnx pi n outpu t sourc e. Fig-

ure 50 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting.

The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of

the general I/O port control registers (DDR and PORT) that are affected by the

COMnx1: 0 bits are sho wn. When referring t o the OCnx state , the refer ence is for the

internal OCnx Register, not the OCnx pin. If a System Reset occur, the OCnx Register is

reset to “0 ”.

Figure 50. Compare Match Output Unit, Schematic

The gen eral I/O por t function is overridden by the output c ompare (OCnx) from the

Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin

direc tion (input or output) is stil l controll ed by the Data D irecti on Reg ister (DDR) for the

port pi n. The Da ta Direct ion Regi ster b it for the O Cnx pin (DD R_OC nx) must be set as

output before the OCnx value is visible on the pin. The port override function is generally

independent of the Waveform Generation mode, but there are some exceptions. Refer

to Table 53, Table 54 and Table 55 for details.

The des ign of th e ou tpu t co mpa re pi n lo gic al lo ws initi ali za tio n of the OC n x state befor e

the output is enab led. N ote that s ome COMnx1 :0 bit s ettings a re reserve d for cer tain

modes of operation. See “16-bit Timer/Counter Register Description” on page 126.

The COMnx1:0 bits have no effect on the input capture unit.

PORT

DDR

OCnx

Waveform

Generator

COMnx1

COMnx0

DATA BUS

FOCnx

clkI/O

116 ATmega162(V/U/L) 2513C–AVR–09/02

Compare Output Mode and

Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM

modes. For a ll m odes, sett ing the C OMn x1 :0 = 0 tel ls the Wa veform Ge nerato r th at no

action on the OCnx Register is to be performed on the next compare match. For Com-

pare Output actions in the non-PWM modes refer to Table 53 on page 126. For fast

PWM mode refe r to Table 54 on page 127, and for pha se correct and phase and fre-

quency correct PWM refer to Table 55 on page 127.

A change of the COMnx1:0 bits state will have effect at the first compare match after the

bits are written. For non-PWM modes, the action can be forced to have immediate effect

by using the FOCnx strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, i s defi ned b y the com bination of th e Wave form Genera tion mode (WG Mn3:0) and

Compare Output mode (COMnx1:0) bits. The Compare O utput mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0

bits control whe ther the PWM output generated sho uld be inver ted or not (inverte d or

non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the out-

put sho uld be s et, clear ed or togg le at a co mpar e match (See “Com pare Match Out put

Unit” on page 115.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 124.

Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the

counting direction is always up (incr ementing), and no counter clear is performed. The

counter simp ly o ve rruns when it pa sses its maxi mum 16 -bit value (MAX = 0xFFFF) and

then res tarts from the B OTTO M (0x 0000 ) . In norm al operatio n th e Timer/Counter Over-

flow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero.

The TOVn flag in this case behaves like a 17th bit, except that it is only set, not cleared.

However, c omb ine d wi th the tim er over fl ow int erru pt t hat auto matically c lears t he TO V n

flag, the timer resolution can be increased by s oftware. There are no special cases to

consider in the normal mode, a new counter value can be written anytime.

The inp ut cap ture uni t is e asy to us e in Normal m ode. Howeve r, obser ve that t he m axi-

mum interval between the external events must not exceed the resolution of the counter.

If the inte rval betw een even ts are too long, the timer overflow interrupt or the presc aler

must be used to extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

Clear Timer on Compare

Match (CT C) Mo d e In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn

cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0

= 4) or the ICRn ( WGMn3:0 = 12). The OCRnA or ICRn define the top value for the

counter, hence also its resolution. This mode allows greater control of the compare

match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 51. The counter value

(TCNTn) i nc reas es un til a c om pare mat ch oc cur s wit h e ither O CRn A or ICR n, and the n

counter (TCNTn) is cleared.

117

ATmega162(V/U/L)

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Figure 51. CT C Mode, Timing Dia gr am

An interrupt can be generated at each time the counter value reaches the TOP value by

either using the OCFn A or ICFn flag according to the regis ter used to define the TOP

value. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. Howeve r, changing the TOP to a value c lose to BOTTOM when the

counter is r unnin g wit h n one o r a lo w p resca ler va lue m ust be done with c are s ince the

CTC mode does not have the double buffering feature. If the new value written to

OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the com-

pare match. The counter will then have to count to its maximum value (0xFFFF) and

wrap around starting at 0x000 0 before the compa re match can occur. In ma ny cases

this feature i s not desi rabl e. An alte rn ative will then be to us e the fas t PW M mo de usin g

OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double

buffered.

For ge nera ting a wa vefor m out put i n CTC mod e, th e OC nA o utput can be set to togg le

its logical level on each compare match by setting the Compare Output mode bits to tog-

gle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the

data direction for the pin is set to output (DDR_OCnA = 1). The waveform generated will

have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000).

The waveform frequency is defined by the following equation:

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). For

Timer/Counter3 also prescaler factors 16 and 32 are available.

As for the Normal mo de of op er ati on, the T OVn f lag is s et in the sam e timer c l ock c y cl e

that the counter counts from MAX to 0x0000.

TCNTn

OCnA

(Toggle)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 4

Period

2 3

(COMnA1:0 = 1)

OCnA fclk_I/O

2N1OCRnA+()⋅⋅

---------------------------------------------------=

118 ATmega162(V/U/L) 2513C–AVR–09/02

Fast PWM Mode The fast Pulse Width Modulation or fas t PWM m ode (WG Mn3: 0 = 5,6, 7,14, or 15) pro -

vides a high frequenc y PWM waveform ge neration optio n. The fast P WM differs from

the other PWM options by its single-slope operation. The counter counts from BOTTOM

to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output

Compare (OCnx) is set on the compare match between TCNTn and OCRnx, and

cleared at TOP. In inverting Compare Output mode output is cleared on compare match

and set at TOP. Due to the single-slope operation, the operating frequency of the fast

PWM mode can be twice as high as the phase correct and phase and frequency correct

PWM modes that us e dual-slope operation. This high frequency make s the fast PWM

mode well suited for power regulation, rectification, and DA C applications. High fre-

quency allows physically small sized external components (coils, capacitors), hence

reduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either

ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to

0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM

resolution in bits can be calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in

ICRn (W GMn3:0 = 14), or the value i n OCRnA (WGMn3:0 = 15 ). The cou nter is then

cleare d at the followin g tim er cloc k cycle . The timing diagra m for the fast PW M mode is

shown in Figure 52. The figure shows fast PWM mode when OCRnA or ICRn is used to

define TOP. The TCNTn value is in the timing diagram shown as a histogram for illus-

trating the single-slope operation. The diagram includes non-inverted and inverted PWM

outputs. The small horizontal line marks on the TCNTn slopes represent compare

matches between OCRnx and TCNT n. The OCnx interrupt fla g will be set when a com-

pare match occurs.

Figure 52. Fast PWM Mode, Timing Diagram

The Timer /Counte r Overflo w Flag (TOV n) is set ea ch time the co unter rea ches TO P. In

addition the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when

RFPWM TOP 1+()log 2()log

-----------------------------------=

TCNTn

OCRnx/TOP Update and

TOVn Interrupt Flag Set and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 7

Period

2 3 4 5 6 8

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

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ATmega162(V/U/L)

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either OCRnA or ICRn is used for defi ning the TO P value. If one of th e interrupts ar e

enabled, the interrupt handler routine can be used for updating the TOP and compare

values.

When changing the TOP value the program must ens ure that the new TOP value is

higher or equal to the value of all of the compare registers. If the TOP value is lower

than any of the compare registers, a compare match will never occur between the

TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are

masked to zero when any of the OCRnx Registers are written.

The procedure for updating ICRn differs from updating OCRnA when used for defining

the TOP v alue. The ICRn Register i s not double buffer ed. This mea ns that if ICRn is

changed to a low value when the counte r is runni ng with none or a low presca ler valu e,

there is a risk that the ne w ICRn va lu e writte n is lower tha n the c urre nt va lue of TCNT n.

The result will then be that the counter will miss the compare match at the TOP value.

The counter will then have to co unt to the MA X value (0xFFFF) and wrap around start-

ing at 0x0000 before the compare match can occur. The OCRnA Register however, is

double buffered. This feature allows the OCRnA I/O location to be written anytime.

When the OCRn A I/O loc ation is writ ten the value wr itten will b e put into the OCRnA

Buffer Register. The OCRnA Compare Register will then be updated with the value in

the buff er re gister at the nex t ti mer c loc k cy c le t he TCNT n matche s T O P. The up dat e is

done at the same timer clock cycle as the TCNTn is cleared and the TOVn flag is set.

Using the IC Rn Register for defining TOP works well when using fixed TOP values. By

using ICRn, the OCRnA Register is free to be used for generating a PWM output on

OCnA. Howev er, if the base PW M frequenc y is activel y chang ed (by changin g the TOP

value ), using the OCRnA as TOP is clea rly a be tter cho ice due to its do uble buff er

feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the

OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an

inverted PWM output can be generated by setti ng the COMnx1:0 to three (See Table

on page 127). The actual OCnx value will only be visible on the port pin if the data direc-

tion for t he port pin is set as outpu t (DDR_OCnx). The PWM waveform is gene rated by

setting (or clearing) the OCn x Register at the compare match between OCRnx and

TCNTn, and cl eari ng (or se tting) the OCnx Regi ster at the timer cl ock cycle the counter

is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For

Timer/Counter3 also prescaler factors 16 and 32 are available.

The extrem e values for the OC Rnx Registe r represents s pecial ca ses when gene rating

a PWM wave form ou tput in th e fast PW M mode. If the OCRn x is s et equal to BOTT OM

(0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the

OCRnx equal to TOP will result in a constant high or low output (depending on the polar-

ity of the output set by the COMnx1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). The

waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is

set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the

double buffer feature of the output compare unit is enabled in the fast PWM mode.

OCnxPWM fclk_I/O

N1TOP+()⋅

-----------------------------------=

120 ATmega162(V/U/L) 2513C–AVR–09/02

Phase Correct PWM Mode The phase correct Pulse Width Modulation or pha se c or rect PWM mo de ( WGM n3 : 0 = 1 ,

2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation

option . The phase correct P WM mode is, l ike the phas e and freq uency corr ect PWM

mode, based on a dual-slope operation. The counter counts repe atedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output

mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn

and OCRn x while upcountin g, and set on the compare ma tch while downcount ing. In

inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the

symmetric feature of the dual-slope PWM modes, these modes are preferred for motor

control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or

defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or

OCRnA set to 0x0003), and the maximum resol ution is 16-bit (ICRn or OCRnA set to

MAX). The PWM resolution in bits can be calculated by using the following equation:

In phase correct PWM mode the counter is incremented until the counter value matches

either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the

value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter

has then reached the TOP and changes the count direction. T he TCNTn value will be

equa l to TOP for one tim er clo ck cy cl e. The t iming diag ram for the phas e c orre ct PW M

mode is shown on Figure 53. The figure shows phase correct PWM mode when OCRnA

or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a

histogram for illustrating the dual-slope operation. The diagram inc ludes non-inv erted

and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre-

sent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set

when a compare match occurs.

Figure 53. Phase Correct PWM Mode, Timing Diagram

The Tim er/Counte r Overflo w Flag (TOVn ) is s et each time th e counte r reache s BOT-

TOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or

RPCPWM TOP 1+()log 2()log

-----------------------------------=

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

121

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ICFn flag is set accordingly at the same timer clock cycle as the OCRnx Registers are

updated with the double buffer value (at TOP). The interrupt flags can be used to gener-

ate an interrupt each time the count er reaches the TOP or BOTTO M value.

When changing the TOP value the program must ens ure that the new TOP value is

higher or equal to the value of all of the compare registers. If the TOP value is lower

than any of the compare registers, a compare match will never occur between the

TCNTn an d the O CRnx. No te that w hen usi ng fixed TOP va lues, t he unus ed bits a re

masked to zero when any of the OCRnx Registers are written. As the third period shown

in Figu r e 53 il lu str at es, changing the T OP acti ve ly whi le the T ime r /Coun ter is r un nin g i n

the phas e cor rect mod e can re sult in an unsym metri cal outp ut. The reason fo r this can

be found in the time o f upd ate of the OCRn x Regis ter. S ince the O CRnx up date oc curs

at TOP, the PWM per io d s tarts and e nds at TO P. T h is imp li es that the l engt h of th e fal l-

ing slope is determined by the previous TOP value, while the length of the rising slope is

determined by the new TOP value. When these two values differ the two slopes of the

period will differ in length. The difference in length gives the unsymmetrical result on the

output.

It is recommended to use the phase and frequency correct mode instead of the phase

correct mode when changing the TOP value while the Timer/Counter is running. When

using a stati c TOP v alue there ar e prac tical ly no d ifferenc es be tween th e two m odes of

operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on

the OCnx pins. Settin g the CO Mnx1:0 bi ts to two will p roduce a non-inv erted P WM an d

an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table

55 on page 127). The actual OCnx value will only be visible on the port pin if the data

direction for the port pin is s et as output (DDR_OCnx). The PW M waveform is gener-

ated by setting (o r clearing) the OCnx Register at the compa re match be tween OCRn x

and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at

compare m atch between OCRn x and TCNT n when the coun ter d ecreme nts. Th e PWM

frequency for the output when using phase correct PWM can be calculated by the fol-

lowing equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For

Timer/Counter3 also prescaler factors 16 and 32 are available.

The extreme values for the OCRnx Register represent special cases when generating a

PWM wavefo rm output in the phase cor rect PWM mode. If the OCRnx is s et equal to

BOTTOM the output will be continuously low and if set equal to TOP the output will be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

Phase and Frequency Co rrect

PWM Mode The ph as e a nd frequency c orr ec t P ulse W id th Mod ula tio n, or p has e and fr eq uen cy co r-

rect PWM mode (WGMn3:0 = 8 or 9) provides a high r esolution phase and frequenc y

correct PWM waveform generation option. The phase and frequency correct PWM

mode is, like the phase correct PWM mode, based on a dual-slope operation. The

counter co unt s r ep eate dl y from B OTT OM ( 0x 00 00) to TOP an d th en f ro m TO P t o B OT-

TOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared

on the compare matc h between TCNTn and OCRnx while upcounting, and set on the

compare match while downcounting. In inverting Compare Output mode, the operation

is inver ted. T he dual -slope op erati on give s a lower ma ximum operat ion fre quenc y com-

fOCnxPCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

122 ATmega162(V/U/L) 2513C–AVR–09/02

pared to the si ngle-s lope op eration. Howeve r, due to the s ymmetr ic fea ture of the dua l-

slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct

PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register,

(see Figure 53 and Figure 54).

The PWM resolution for the phase and frequency correct PWM mode can be defined by

either IC Rn or OCRn A. T h e mi nimum resolu tion allo wed is 2- bit (I CRn o r OCR nA s et to

0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM

resolution in bits can be calculated using the following equation:

In phase and frequency correct PWM mode the counter is incremented until the counter

value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA

(WGMn3:0 = 9). The counter has then reached the TOP and changes the count direc-

tion. The TCNTn value will be equal to TOP for one timer clock cycle. The timing

diagram for the phase correct and frequency correct PWM mode is shown on Figure 54.

The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is

used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for

illustrating the dual-slope operation. The diagram includes no n-inverted and inverted

PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare

matches between OCRnx and TCNT n. The OCnx interrupt fla g will be set when a com-

pare match occurs.

Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the

OCRnx Registers are updated with the double buffer value (at BOTTOM). When either

OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag set when

TCNTn has reac hed TOP . The i nte rru pt fl ags c an th en b e us ed to ge nerate an interru pt

each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ens ure that the new TOP value is

higher or equal to the value of all of the compare registers. If the TOP value is lower

RPFCPWM TOP 1+()log 2()log

-----------------------------------=

OCRnx/TOP Update and

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

123

ATmega162(V/U/L)

2513C–AVR–09/02

than any of the compare registers, a compare match will never occur between the

TCNTn and the OCRnx.

As Figure 54 shows the output generated is, in contrast to the phase correct mode, sym-

metrical in all period s. Since the OCRnx Re giste rs are updated at BO TTOM, th e leng th

of the rising and the falling slopes will always be equal. This gives symmetrical output

pulses and is therefore frequency correct.

Using the IC Rn Register for defining TOP works well when using fixed TOP values. By

using ICRn, the OCRnA Register is free to be used for generating a PWM output on

OCnA. However , if the ba se PWM fr equenc y is acti vely ch anged by c hangin g the TOP

value, using the OCRnA as TOP is clearly a better choice due to its double buffer

feature.

In phase and frequency correct PWM mode, the comp are units allow generation of

PWM wa veforms o n the OCnx pins. Setti ng the COMn x1:0 bits to two will pr oduce a

non-inverted PWM and an inverted PWM output can be generated by setting the

COMnx1:0 to three (See Table 55 on page 127). The actual OCnx value will only be vis-

ible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The

PWM wave form i s generat ed by se tting (or cleari ng) the OCnx Regis ter at the comp are

match b etween OCRn x and TCN Tn when th e co unter i ncreme nts, and c learin g (or set-

ting) the OCnx Register at compare match between OCRnx and TCNTn when the

counter decr ements. The PWM frequency for the output when using phase and fre-

quency correct PWM can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). For

Timer/Counter3 also prescaler factors 16 and 32 are available.

The extrem e values for the OC Rnx Registe r represents s pecial ca ses when gene rating

a PWM waveform ou tput in the ph ase corr ect P WM mode . If the OCRn x i s set e qual to

BOTTOM the output will be continuously low and if set equal to TOP the output will be

set to hig h for non-in verted PWM mode . For inve rted PWM the output will have the

opposite logic values.

fOCnxPFCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

124 ATmega162(V/U/L) 2513C–AVR–09/02

Timer/Counter Ti ming

Diagrams The Timer/Count er is a synch ronous desig n and the timer clock (clk Tn) is therefore

shown a s a clock enable s ignal in th e follo wing fig ures. Th e figures inclu de inform atio n

on when interrupt flags are set, and when the OCRnx Register is updated with the

OCRnx buffer value (only for modes utilizing double buffering). Figure 55 shows a timing

diagram for the setting of OCFnx.

Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling

Figure 56 shows the same timing data, but with the prescaler enabled.

Figure 56. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)

Figure 57 shows the count sequence close to TOP in various modes. When using phase

and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The

timing diagrams wi ll be the sa me, but TOP should be re placed by BOT TOM, T OP-1 by

BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn flag at

BOTTOM.

clk

(clkI/O/1)

OCFnx

clk

I/O

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(clkI/O/8)

125

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 57. Timer/Counter Timing Diagram, no Prescaling

Figure 58 shows the same timing data, but with the prescaler enabled.

Figure 58. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

(clkI/O/1)

clk

I/O

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

126 ATmega162(V/U/L) 2513C–AVR–09/02

16-bit Timer/Counter

Timer/Counter1 Control

Timer/Counter3 Control

• Bit 7:6 – COMnA1:0: Compare Output Mode for channel A

• Bit 5:4 – COMnB1:0: Compare Output Mode for channel B

The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB

respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA

output overrides the normal port functionality of the I/O pin it is connected to. If one or

both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port

functionality of the I/O pin it is connected to. However, note that the Data Direction Reg-

ister (DDR) bit corresponding to the OCnA or OCnB pin must be set in order to enable

the output driver.

When the O CnA or O CnB is conne cted to the pin, the func tion of the C OMn x1:0 bit s is

dependent of th e W GMn3:0 bi ts setti ng. T ab le 53 shows the CO M nx1 :0 bi t fu nc tio nality

when the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).

Bit 76543210

COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 TCCR1A

Read/Write R/W R/W R/W R/W W W R/W R/W

Initial Value00000000

Bit 76543210

COM3A1 COM3A0 COM3B1 COM3B0 FOC3A FOC3B WGM31 WGM30 TCCR3A

Read/Write R/W R/W R/W R/W W W R/W R/W

Initial Value00000000

Table 53. Compare Output Mode, non-PWM

COMnA1/

COMnB1 COMnA0/

COMnB0 Description

0 0 Normal port operation, OCnA /OC nB discon nec te d.

0 1 Toggle OCnA/OCnB on com pa re mat ch.

1 0 Clear OCnA/OCnB on compare match (Set output to low level).

1 1 Set OCnA/OCnB on compare match (Set output to high level).

127

ATmega162(V/U/L)

2513C–AVR–09/02

Table 54 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the

fast PWM mode.

Note: 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is

set. In this case the compare match is ignored, but the set or clear is done at TOP.

See “Fast PWM Mode” on page 118. for more details.

Table 55 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the

phase correct or the phase and frequency correct, PWM mode.

Note: 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is

set. See “Phase Correct PWM Mode” on page 120. for more details.

• Bit 3 – FOCnA: Force Output Compare for channel A

• Bit 2 – FOCnB: Force Output Compare for channel B

The FOCnA/ FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM

mode. H owever , fo r ensur in g c om pati bili ty w ith futu re devi ces, these bits mu st be s et to

zero when TCCRnA is written when operating in a PWM mode. When writing a logical

one to the FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform

Generation unit. The OCnA/OCnB output is changed according to its COMnx1:0 bits

setting. Note that the F OCnA/FOCnB bits are implemented as st robes. Therefore it is

the value present in the COMnx1:0 bits that determine the effect of the forced compare.

A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear

Timer on Compare match (CTC) mode using OCRnA as TOP.

The FOCnA/FOCnB bits are always read as zero.

Table 54. Compare Output Mode, Fast PWM(1)

COMnA1/

COMnB1 COMnA0/

COMnB0 Description

0 0 Normal port operation, OCnA/OCnB disconnected.

0 1 WGMn3=0: Normal port operation, OCnA/OCnB disconnected.

WGMn3=1: Toggle OCnA on compare match, OCnB reserved.

1 0 Clear OCnA/OCnB on compare match, set OCnA/OCnB at TOP.

1 1 Set OCnA/OCnB on compare match, clear OCnA/OCnB at TOP.

Table 55 . Compare Output Mod e, Phase Correct and Pha se and Frequency Corr ect

PWM(1)

COMnA1/

COMnB1 COMnA0

COMnB0 Description

0 0 Normal port operation, OCnA/OCnB disconnected.

0 1 WGMn3=0: Normal port operation, OCnA/OCnB disconnected.

WGMn3=1: Toggle OCnA on compare match, OCnB reserved.

1 0 Clear OCnA/O CnB on compare match when up-counting. Set

OCnA/OCnB on compare match when downcounting.

1 1 Set OCnA/OCnB on compare match when up-counting. Clear

OCnA/OCnB on compare match when downcounting.

128 ATmega162(V/U/L) 2513C–AVR–09/02

• Bit 1:0 – WGMn1:0: Waveform Generation Mode

Combined wi th the WG Mn3:2 bits found i n the TCC RnB Regi ster, these bits control th e

counting sequence of the c ounter, the so urce for maxi mum (TOP) cou nter value, and

what type of waveform generation to be used, see Table 56. Modes of operation sup-

ported by th e Time r/Coun ter u ni t a re: Normal m ode ( coun ter ), Cl ea r Tim er o n Comp ar e

match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See

“Modes of Operation” on page 116.)

Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

Table 56. Waveform Generation Mode Bit Description(1)

Mode WGMn3 WGMn2

(CTCn) WGMn1

(PWMn1) WGMn0

(PWMn0) Timer/Counter Mode of Operation TOP Update of

OCRnx at TOVn Flag

Set on

0 0 0 0 0 Normal 0xFFFF Immediate MAX

1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM

2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM

3 0 0 1 1 PWM , Phas e Correct, 10-bit 0x 03FF TOP BOTTOM

4 0 1 0 0 CTC OCRnA Immediate MAX

5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP

6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP

7 0 1 1 1 Fast PWM, 10- bit 0x03FF TOP TOP

8 1 0 0 0 PWM, Phase and Frequency Correct ICRn BOTTOM BOTTOM

9 1 0 0 1 PWM, Phase and Frequency Correct OCRnA BOTTOM BOTTOM

10 1 0 1 0 PWM, Phase Correct ICRn TOP BOTTOM

11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM

12 1 1 0 0 CTC ICRn Immediate MAX

13 1 1 0 1 Reserved – – –

14 1 1 1 0 Fast PWM ICRn TOP TOP

15 1 1 1 1 Fast PWM OCRnA TOP TOP

129

ATmega162(V/U/L)

2513C–AVR–09/02

Timer/Counter1 Control

Timer/Counter3 Control

• Bit 7 – ICNCn: Input Capture Noise Canceler

Setting th is bi t (to on e) activ ates t he inpu t captur e noi se ca ncele r. Whe n the no ise can-

celer is activated, the input from the Input Capture pin (ICPn) is filtered. The filter

function requi res four succes sive equa l valu ed sam ples of the ICPn pi n for chang in g its

output. The input capture is therefore delayed by four Oscillator cycles when the noise

canceler is enabled.

• Bit 6 – ICESn: Input Captur e Edge Select

This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a cap-

ture event. When the ICES n bit is written to zero, a fal ling (negative) edge is used a s

trigger, and w hen the I CESn bi t is wr itten to o ne, a rising ( pos itive) e dge will tr igger the

capture.

When a c ap tur e is tr ig gered accor di ng to t he ICESn se ttin g, the co unte r va lue i s co pie d

into the Input Captur e Register (ICRn). T he event will als o set the Input Capture Flag

(ICFn), a nd this can be used to c ause an Inpu t Capture Interrupt , if this i nterrupt is

enabled.

When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in

the TCCRnA and the TCCRnB Registe r), the ICPn is dis connected and consequently

the input capture function is disabled.

• Bit 5 – Reserved Bit

This bit is re ser v ed for future use. For en su ri ng co mpa tib il ity wi th futu re de vi c es, th is bit

must be written to zero when TCCRnB is written.

• Bit 4:3 – WGMn3:2: Waveform Generation Mode

See TCCRnA Register description.

Bit 76543210

ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

130 ATmega162(V/U/L) 2513C–AVR–09/02

• Bit 2:0 – CSn2:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see

Figure 55 and Figure 56.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the counti ng. .

Table 57. Clock Select Bit Description Timer/Counter1

CS12 CS11 CS10 Description

0 0 0 No clock source. (Timer/Counter stopped).

001clk

I/O/1 (No prescal ing )

010clk

I/O/8 (From prescal er)

011clk

I/O/64 (From prescaler)

100clk

I/O/256 (From prescaler)

101clk

I/O/1024 (From presc al er)

1 1 0 External clock source on T1 pin. Clock on falling edge.

1 1 1 External clock source on T1 pin. Clock on rising edge.

Table 58. Clock Select Bit Description Timer/Counter3

CS32 CS31 CS30 Description

0 0 0 No clock source. (Timer/Counter stopped).

001clk

I/O / 1 (No prescaling)

010clk

I/O / 8 (From prescaler).

011clk

I/O / 64 (From prescaler).

100clk

I/O / 256 (From prescaler).

101clk

I/O / 1024 (From prescaler).

110clk

I/O / 16 (From prescaler).

111clk

I/O / 32 (From prescaler).

131

ATmega162(V/U/L)

2513C–AVR–09/02

Timer/Counter1 – TCNT1H and

TCNT1L

Timer/Counter3 – TCNT3H and

TCNT3L

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combine d TCNTn) give

direct ac cess, both for read and for writ e operations , to the Timer/ Counter unit 16 -bit

counter. To ensure that both the high and low bytes are read and written simultaneously

when the CP U ac ce ss es th ese r egi s ters, the access is pe rfor med us in g an 8- bit tempo-

rary hi gh byte r egiste r (TEMP) . This tem porar y regist er is sh ared by al l the other 16-bit

registers. See “Accessing 16-bit Registers” on page 107.

Modif ying the coun ter (TCNTn ) while the counter is running intr oduces a r isk of missin g

a compare match between TCNTn and one of the OCRnx Registers.

Writing to the TCNT n Register blocks ( remove s) the compare matc h on the followin g

timer clock for all compare units.

Output Compare Register 1 A

– OCR1AH and OCR1AL

Output Compare Register 1 B

– OCR1BH and OCR1BL

Output Compare Register 3 A

– OCR3AH and OCR3AL

Output Compare Register 3 B

– OCR3BH and OCR3BL

Bit 76543210

TCNT1[15:8] TCNT1H

TCNT1[7:0] TCNT1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

TCNT3[15:8] TCNT3H

TCNT3[7:0] TCNT3L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

OCR1A[15:8] OCR1AH

OCR1A[7:0] OCR1AL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

OCR1B[15:8] OCR1BH

OCR1B[7:0] OCR1BL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

OCR3A[15:8] OCR3AH

OCR3A[7:0] OCR3AL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

OCR3B[15:8] OCR3BH

OCR3B[7:0] OCR3BL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

132 ATmega162(V/U/L) 2513C–AVR–09/02

The Outp ut Com pare Regi sters cont ain a 16-bi t va lue th at is con tinuo usly compa red

with the counter value (TCNTn). A match can be used to generate an output compare

interrupt, or to generate a waveform output on the OCnx pin.

The Outp ut Compare Regist ers are 16-bi t in size. To ensu re that both the high and low

bytes are written simultaneously when the CPU writes to these registers, the access is

perf ormed using a n 8-bit t emp orary hi gh byt e regis ter (TE MP) . This te mpora ry reg ister

is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 107.

Input Capture Register 1 –

ICR1H and ICR1L

Input Capture Register 3 –

ICR3H and ICR3L

The Input Capture is updated with the counter (TCNTn) value each time an event occurs

on the IC Pn pin (or optio nally on the An alog Compara tor output for Timer /Counter1) .

The input capture can be used for defining the counter TOP value.

The Input Ca pture Regis ter is 16 -bit in si ze. To ens ure that bot h the high and low bytes

are read simultaneously when the CPU accesses these registers, the access is per-

formed using an 8-bit temporary high byte r egister (TEMP). This temporary register is

shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 107.

Timer/Counter Interrupt Mask

Note: 1. This register contains interrupt control bits for several Timer/Counters, but only

Timer1 bits are described in this section. The remaining bits are described in their

respective T imer sections.

• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is wri tte n to one, and the I-flag in t he Sta tus R egister is set (inte rrup ts glo-

bally enabled) , the Timer/Counter1 overflow interrupt is enabled. The corresponding

Interrupt V ec tor ( Se e “Inte rrup ts ” o n pa ge 5 5.) is e xecut ed wh en t he T OV 1 fl ag, l ocate d

in TIFR, is set.

• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is wri tte n to one, and the I-flag in t he Sta tus R egister is set (inte rrup ts glo-

bally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The

corresponding Interrup t Vector (See “Interrupts” on page 55.) is executed when the

OCF1A flag, located in TIFR, is set.

Bit 76543210

ICR1[15:8] ICR1H

ICR1[7:0] ICR1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

ICR3[15:8] ICR3H

ICR3[7:0] ICR3L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

133

ATmega162(V/U/L)

2513C–AVR–09/02

• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is wri tte n to one, and the I-flag in t he Sta tus R egister is set (inte rrup ts glo-

bally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The

corresponding Interrup t Vector (See “Interrupts” on page 55.) is executed when the

OCF1B flag, located in TIFR, is set.

• Bit 3 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is wri tte n to one, and the I-flag in t he Sta tus R egister is set (inte rrup ts glo-

bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The

corresponding Interrup t Vector (See “Interrupts” on page 55.) is executed when the

ICF1 flag, located in TIFR, is set.

Extended Timer/Counter

Interrupt Mask Register –

ETIMSK(1)

Note: 1. This register contains interrupt control bits for several Timer/Counters, but only

Timer3 bits are described in this section. The remaining bits are described in their

respective T imer sections.

• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable

When this bit is wri tte n to one, and the I-flag in t he Sta tus R egister is set (inte rrup ts glo-

bally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The

corresponding Interrup t Vector (See “Interrupts” on page 55.) is executed when the

ICF3 flag, located in TIFR, is set.

• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable

When this bit is wri tte n to one, and the I-flag in t he Sta tus R egister is set (inte rrup ts glo-

bally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The

corresponding Interrup t Vector (See “Interrupts” on page 55.) is executed when the

OCF3A flag, located in TIFR, is set.

• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable

When this bit is wri tte n to one, and the I-flag in t he Sta tus R egister is set (inte rrup ts glo-

bally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The

corresponding Interrup t Vector (See “Interrupts” on page 55.) is executed when the

OCF3B flag, located in TIFR, is set.

• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable

When this bit is wri tte n to one, and the I-flag in t he Sta tus R egister is set (inte rrup ts glo-

bally enabled) , the Timer/Counter3 overflow interrupt is enabled. The corresponding

Interrupt V ec tor ( Se e “Inte rrup ts ” o n pa ge 5 5.) is e xecut ed wh en t he T OV 3 fl ag, l ocate d

in TIFR, is set.

Bit 7 6 5 4 3 2 1 0

TICIE3 OCIE3A OCIE3B TOIE3 ––ETIMSK

Read/Write R R R/W R/W R/W R/W R R

Initial Value 0 0 0 0 0 0 0 0

134 ATmega162(V/U/L) 2513C–AVR–09/02

Timer/Counter Interrupt Flag

Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are

described in this section. The remaining bits are described in thei r respective Timer

sections.

• Bit 7 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC

modes, the TOV1 flag is set when the timer overflows. Refer to Table 56 on page 128

for the TOV1 flag behavior when using another WGMn3:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is

executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

• Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-

put Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is

executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-

put Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is

executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 3 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture

when the counter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alter-

natively, ICF1 can be cleared by writing a logic one to its bit location.

Bit 76543210

TOV1 OCF1A OC1FB OCF2 ICF1 TOV2 TOV0 OCF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

135

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Extended Timer/Counter

Interrupt Flag Register –

ETIFR(1)

Note: 1. This register contains flag bits for several Timer/Counters, but only Timer3 bits are

described in this section. The remaining bits are described in thei r respective Timer

sections.

• Bit 5 – ICF3: Timer/Counter3, Input Capture Flag

This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture

when the counter reaches the TOP value.

ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alter-

natively, ICF3 can be cleared by writing a logic one to its bit location.

• Bit 4 – OCF3A: Timer/Counter3, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Out-

put Compare Register A (OCR3A).

Note that a Forced Output Compare (FOC3A) strobe will not set the OCF3A flag.

OCF3A is automatically cleared when the Output Compare Match A Interrupt Vector is

executed. Alternatively, OCF3A can be cleared by writing a logic one to its bit location.

• Bit 3 – OCF3B: Timer/Counter3, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Out-

put Compare Register B (OCR3B).

Note that a Forced Output Compare (FOC3B) strobe will not set the OCF3B flag.

OCF3B is automatically cleared when the Output Compare Match B Interrupt Vector is

executed. Alternatively, OCF3B can be cleared by writing a logic one to its bit location.

• Bit 2 – TOV3: Timer/Counter3, Overflow Flag

The setting of this flag is dependent of the WGMn3:0 bi ts setting. In normal and CT C

modes, the TOV3 flag is set when the timer overflows. Refer to Table 56 on page 128

for the TOV3 flag behavior when using another WGMn3:0 bit setting.

TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is

executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit location.

Bit 76543210

ICF3 OCF3A OC3FB TOV3 –– ETIFR

Read/Write R R R/W R/W R/W R/W R R

Initial Value 0 0 0 0 0 0 0 0

136 ATmega162(V/U/L) 2513C–AVR–09/02

8-bit Timer/Counter2

with PWM and

Asynchronous

operation

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The

main featur es ar e:

•Single Channel Counter

•Clear Timer on Compare Match (Auto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Frequency Genera tor

•10-bit Clock Prescaler

•Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)

•Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 59. For the

actual placement of I/O pins, refer to “Pinout ATmega162” on page 2. CPU accessible

I/O Regis ters , in cl ud ing I/O bi ts a nd I /O pin s, ar e shown in bold. The dev ic e-s pec i fic I/O

page 147.

Figure 59. 8-bit Timer/Counter Block Diagram

Registers The Timer/Coun ter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers.

Interrupt request (shorten as Int.Req.) signals are all visible in the Timer In terrupt Flag

shared by other timer units.

Timer/Counter

DATABUS

TCNTn

Waveform

Generation OCn

= 0

Control Logic

= 0xFF

TOPBOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCn

(Int.Req.)

Synchronization Unit

OCRn

TCCRn

ASSRn

Status flags

clkI/O

clkASY

Synchronized Status flags

asynchronous mode

select (ASn)

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clkTn

clkI/O

137

ATmega162(V/U/L)

2513C–AVR–09/02

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously

clocked from the TOSC1/2 pins, as detai led later in this section. The asynchronous

operat ion is c ontrol led by the Asynchr onous S tatus Reg ister (ASSR). The Clock S elect

logic bl ock c ontr ols whic h c lock sou rce the Tim er/C oun ter u ses to in crem ent ( or d ecr e-

ment) its value. The Timer/Counter is in active when no clock source is selected. The

output from the clock select logic is referred to as the Timer Clock (clkT2).

The double buffered Output Compare Register (OCR2) is compared with the

Timer/Counter value at all times. The result of the compare can be used by the wave-

form generator to generate a PWM or variable frequency output on the Output Compare

Pin ( OC2). See “Output Co mpare Un it” on page 138 . for detai ls. The compare ma tch

event will also set the Compare Flag (OCF2) which can be used to generate an output

compare interrupt request.

Definitions Many register and bit references in this document are written in general form. A lower

case “n” replaces the Timer/Counter number, in this case 2. However, when us ing the

accessing Timer/Counter2 counter value and so on.

The definitions in Table 59 are also used extensively throughout the section.

Timer/Counter Clock

Sources The T imer /Co unte r c an be cl ocke d by an i nter na l syn ch ronous or an exte rn al async hro-

nous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O.

When the AS 2 bit i n the AS SR Regis te r is wr itte n to log ic one, the cl oc k sour c e is taken

from the Timer/Counte r Oscil lator c onnected to T OSC1 and TOS C2. For detai ls on

asynchronous operation, see “Asynchronous Status Register – ASSR” on page 150. For

details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 154.

Table 59. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0x FF (MAX) or the value stor ed in the OCR2 Register. The

assignment is dependent on the mode of operation.

138 ATmega162(V/U/L) 2513C–AVR–09/02

Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.

Figure 60 shows a block diagram of the counter and its surrounding environment.

Figure 60. Counter Unit Block Diagram

Signal description (internal signals):

count Increment or decrement TCNT2 by 1.

direction Selects between increment and decrement.

clear Clear TCNT2 (set all bit s to zero).

clkT2 Timer/Counter clock.

top Signalize s that TCNT2 has re ac hed max im um value .

bottom Signalize s that TCNT 2 has reac hed mi nim um va lue (zero ).

Depending on th e m ode of op er ati on used, the counter i s clea re d, incr em ente d, or de c-

remented at each timer clock (clkT2). clkT2 can be generated from an external or internal

clock source, selected by the Clock Select bits (CS22:0). When no clock source is

selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed

by the CPU, regardless of whet her clkT2 is present or not. A CPU write overrides (has

priority over) all counter clear or count operations.

The c ounting sequenc e is de termined by the setting of the W GM21 a nd WGM20 bits

located in t he Timer/Counter Control Register (TCCR2). There a re close connect ions

between how the counter behaves (counts) and how waveforms are generated on the

Output Compare output OC2. For more details about advanced counting sequences

and waveform generation, see “Modes of Operation” on page 141.

The Timer/Counter Overflow Flag (TOV2) is set acc ording to the mode of operation

sel ected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.

Output Compare Unit T he 8-bi t com parat or cont inu ously com par e s TCNT2 with the Out put Com par e Reg ister

(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will

set the Ou tpu t Co mpa re F la g (OCF2 ) at the nex t tim er c lo ck c y cle. If e nab led (OCIE2 =

1), the Output Compare Flag generates an output compare interrupt. The OCF2 flag is

automatically cleared when the interrupt is executed. Alternatively , the OCF2 flag can

be cleared by software by writing a logical one to its I/O bit location. The waveform gen-

erator uses the matc h signal t o generate an ou tput acco rding to operating mo de set by

the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom sig-

nals a re u sed by the w avefor m g enerator for hand ling the spe cial cases of the extr eme

values in some modes of operation (“Modes of Operation” on page 141).

Figure 61 shows a block diagram of the output compare unit.

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

topbottom

direction

clear

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clk

I/O

clk

139

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 61. Output Compare Unit, Block Diagram

The OCR2 Register is double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,

the double buffering is disabled. The double bu ffering synchr onizes the up date of the

OCR2 Compare Register to either top or bottom of the counting sequence. The synchro-

niza tion pre vents the occu rrenc e of odd- length, non-s ymme trical PW M puls es, th ereby

making the output glitch-free.

The OCR2 Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has a ccess to th e OCR2 Buffer Register, and if double

buffering is disabled the CPU will access the OCR2 directly.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC2) bit. Forcing compare

match will not set the OCF2 flag or reload/clear the timer, but the OC2 pin will be

updated as if a real compare match had occurred (the COM21:0 bits settings define

whether the OC2 pin is set, cleared or toggled).

Compare Match Blocking by

TCNT2 Write All CP U write opera tions to the TCNT2 Regi ster will b lock any comp are match tha t

occurs in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR2 to be i nit ia lize d to the same v al ue as TCNT2 without trigg er ing an i nte rrup t whe n

the T imer/Counter clock is enabled.

Using the Output Compare

Unit Since writing TCNT2 in any mode of operation will block all compar e matches for one

timer clock cycle, there are risks involved when changing TCNT2 when using the output

compare channel, independently of whether the Timer/Counter is running or not. If the

value written to TCNT2 equals the OCR2 value, the compare match will be missed,

OCFn (Int.Req.)

(8-bit Comparator )

OCRn

OCxy

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

140 ATmega162(V/U/L) 2513C–AVR–09/02

resulting in incorrect Waveform Generation. Similarly, do not write the TCNT2 value

equal to BOTTOM when the counter is downcounting.

The Setup of the OC2 should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC2 value is to use the Force

Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value

even when changing between Waveform Generation modes.

Be aware that the COM21:0 bits are not doubl e buffered together with the compare

value. Changing the COM21:0 bits will take effect immediately.

Compare Match Output

Unit The Com pare O utput mode ( COM 21:0) bi ts ha ve two functio ns. T he wa veform gener a-

tor uses the COM 21:0 bits for defining the Output Compare (OC2) state at the next

compare match. Also, the COM21:0 bits control the OC2 pin output source. Figure 62

shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O

Regist ers, I/O bits, an d I/O pins in the fi gure are show n in bold. Only the parts of the

general I/O port contro l registers (DDR and PORT) that are affec ted by the COM21:0

bits are shown. When referring to the OC2 state, the reference is for the internal OC2

Figure 62. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC2) from the

wavefo rm gener ator if ei ther of t he COM21: 0 bits are set. H owever, the OC2 pin direc-

tion (input or output) is still controlled by the Data Direction Register (DDR) for the port

pin. T he Data Dire ction Regi ster bi t for the O C2 p in ( DDR_ OC2) must be se t as o utput

befor e the OC 2 value is v isible on the pin . The por t overrid e funct ion is in depend ent of

the Waveform Generation mode.

PORT

DDR

OCn

Waveform

Generator

COMn1

COMn0

DATA BUS

FOCn

clk

I/O

141

ATmega162(V/U/L)

2513C–AVR–09/02

The des ign of the O u tput Com pare pin logi c al low s ini tia li za tio n o f th e OC 2 s tate bef or e

the output is enabled. Note that some COM21:0 bit settings are reserved for certain

modes of operation. See “8-bit Timer/Counter Register Description” on page 147.

Compare Output Mode and

Waveform Generation The Wavefor m Gener ator uses the COM21:0 bit s differen tly in Norma l, CTC, and PW M

modes. For all modes, setting the COM21:0 = 0 tells the Waveform Generator that no

action on the OC2 Register is to be performed on the next compare match. For compare

outpu t action s in the non -PWM mod es refer to Ta ble 61 on pa ge 148. For fast PWM

mode, r efer to Table 62 on page 148, and for phase correct PWM refer to Table 63 on

page 148.

A change of the CO M21 :0 bits state wi ll have effect at the fir st compare mat ch after the

bits are written. For non-PWM modes, the action can be forced to have immediate effect

by using the FOC2 strobe bits.

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, i s defi ned b y the com binati on of the Wave form Genera tion mode (WGM 21:0) an d

Compare Output mo de (COM21:0) bi ts. The Comp are Output mode bits do not affect

the countin g sequence, whil e the Waveform Gene ration mode bits do. The COM21 :0

bits control whe ther the PWM output generated sho uld be inver ted or not (inverte d or

non-inver te d P WM ). F or no n- PW M mod es the COM2 1:0 bits control whe ther t he o utp ut

should be set, cleared, or tog gled at a comp are match (See “ Compare Mat ch Output

Unit” on page 140.).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 145.

Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the

counting direction is always up (incr ementing), and no counter clear is performed. The

counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then

restarts from the bottom (0x00). In normal operati on the Timer/Counter Overflow Flag

(TOV2) wi ll be set in the same t imer clock cyc le as the T CNT2 becomes z ero. The

TOV2 flag in this case behaves like a ninth bit, except that it is only set, not cleared.

However, c omb ine d wi th the tim er over fl ow int erru pt t hat auto matically c lears t he TO V 2

flag, the timer resolution can be increased by s oftware. There are no special cases to

consider in the normal mode, a new counter value can be written anytime.

The Ou tput C omp ar e un it can be use d to g ene rate i nter rupts at so me g iv en tim e. Us in g

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

142 ATmega162(V/U/L) 2513C–AVR–09/02

Clear Timer on Compare

Match (CT C) Mo d e In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the

counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the

counter, hence also its resolution. This mode allows greater control of the compare

match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 63. The counter value

(TCNT2) increases until a compare match occurs between TCNT2 and OCR2, and then

counter (TCNT2) is cleared.

Figure 63. CT C Mode, Timing Dia gr am

An interrupt can be ge nerated each time the counter value reaches the TOP v alue by

using the OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be used

for updating the TOP value. However, changing the TOP to a value close to BOTTOM

when th e counte r is runnin g with non e or a l ow pr escale r va lue mu st be do ne with care

since the CTC mode does not have the double buffering feature. If the new value written

to OCR2 is lower than the current value of TCNT2, the counter will miss the compare

match. The counter will then have to count to its maximum value (0xFF) and wrap

around starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC2 output can be set to toggle its

logical level on each compare match by setting the Compare Output mode bits to toggle

mode (CO M21:0 = 1) . The OC2 value wil l not be visibl e on the port pin unles s the data

direct ion fo r the pin is set to ou tput. T he w avefor m ge nerate d will have a max imum fre-

quency of fOC2 = fclk_I/O/2 when OCR2 i s set to ze ro (0x00 ). The w avefor m freq uenc y is

defined by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

As for the Normal mode o f oper ation , the TOV2 flag is set in the same timer clock cycle

that the counter counts from MAX to 0x00.

TCNTn

OCn

(Toggle)

OCn Interrupt Flag Set

1 4

Period 2 3

(COMn1:0 = 1)

fOCn fclk_I/O

2N1OCRn+()⋅⋅

-----------------------------------------------=

143

ATmega162(V/U/L)

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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 1) provides a high fre-

quency PWM waveform generation option. The fast P WM differs from the other PWM

option by its single-slope operation. The counter counts from BOTTOM to MAX then

restarts from BOTTOM. In non- inverting Compa re Output mode, the Ou tput Compare

(OC2) is cleared on the compare match between TCNT2 and OCR2, and set at BOT-

TOM. In inverting Compare Output mode, the output is set on compare match and

cleared at BOTTOM. Due to the single-slope operat ion, the operating frequency of the

fast PWM mode ca n be twic e as high as the phase correc t PWM mod e that uses dual-

slope operation. This high frequency makes the fast PWM mode well suited for power

regulation, rectification, and DAC applic ations. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX

value. The counter is then cleared at the following timer clock cycle. The timing diagram

for the fast PWM mode is shown in Figure 64. The TCNT2 value is in the timing diagram

shown as a histogram for illustrating the single-slope operation. The diagram includes

non-inver ted and in vert ed PWM ou tputs. The s mall ho rizontal line mar ks on the T CNT2

slopes represent compare matches between OCR2 and TCNT2.

Figure 64. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time th e counter reaches MAX. If

the interrup t is enab led, the in terrupt ha ndler routine c an be used for updating the com-

pare value.

In fast PWM mode , the c omp are uni t al lows gen erati on of PWM wavefor m s on the O C2

pin. Setting the COM21:0 bits to two will produce a non-inverted PWM and an inverted

PWM output can be gener ated by sett ing the CO M21:0 to three ( See Tabl e 62 on page

148). The actual OC2 value will only be visible on the port pin if the data direction for the

port pin is set as output. Th e PWM waveform is generated by setting (or clearing) the

OC2 Register at the compare match between OCR2 and TCNT2, and clearing (or set-

ting) the OC2 Register at the timer clock cycle the counter is clear ed (changes from

MAX to BOTTOM) .

TCNTn

OCRn Update and

TOVn Interrupt Flag Set

Period 2 3

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

4 5 6 7

144 ATmega162(V/U/L) 2513C–AVR–09/02

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The ex treme val ues for the OCR2 Regi ster rep resent sp ecial ca ses whe n generati ng a

PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the

output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal

to MAX will result in a constantly high or low output (depending on the polarity of the out-

put set by the COM21:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved

by setting OC2 to toggle its logical level on each compare match (COM21:0 = 1). The

waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2 is set

to zero. This fea ture is simil ar to the OC2 to ggl e in CTC mo de, ex c ept the doub le bu ffer

feature of t he Output Compare unit is enabled in t he fast PWM mode.

Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 3) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-

slope operation. The counter counts r epeatedly from BOTTOM to MAX and then from

MAX to BOTTO M. In non-in verti ng Com pare O utpu t mod e, the Ou tput C ompare (OC2)

is clea red on the compare matc h bet ween TCN T 2 and OCR2 while upcou nti ng, a nd s et

on the compare match while downcounting. In inverting output compare mode, the oper-

ation is inverted. The dual-slope operation has lower maximum operation frequency

than sing le slope operati on. However, due to the sy mmetric fea ture of the dual-slop e

PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phas e correct PWM mo de is fixed to ei ght bits. In pha se

correct PW M mode the counter is inc rement ed until the counter value matc hes MAX.

When the counter reaches MAX, it changes the count direction. The TCNT2 value will

be equal to MAX for one timer clock cycle. The timing diagram for the phase correct

PWM mode is shown on Figure 65. The TCNT2 value is in the timing diagram shown as

a histo gram for i llustr ating the d ual-sl ope o peratio n. T he di agram i nclu des non -inver ted

and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes repre-

sent compare matc he s betwe en OCR 2 and TCNT2 .

Figure 65. Phase Correct PWM Mode, Timing Diagram

fOCnPWM fclk_I/O

N256⋅

------------------=

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

1 2 3

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

145

ATmega162(V/U/L)

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The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT-

TOM. The interrupt flag can be us ed to generate an interrupt each time the counter

reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on

the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM. An

invert ed PWM output c an be g enerat ed by sett ing the C OM21: 0 to thr ee (See T able 6 3

on page 148). Th e a ct ual OC2 va lue wi ll on ly be visib le on the po rt pin i f th e data di rec-

tion for the port pin i s set as output. The P WM waveform is generated by cleari ng (or

setting) the OC2 Register at the compare match between OCR2 and TCNT2 when the

counter increments, and setting (or clearing) the OC2 Register at compare match

between OCR2 and TCNT 2 when the co unter de crement s. The P WM frequen cy for the

output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The ex treme val ues for the OCR2 Regi ster rep resent sp ecial ca ses whe n generati ng a

PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to

BOTTO M, the o utput wi ll be con tinuous ly low a nd if s et equa l to MA X the ou tput wil l be

continuously high for non-inverted PWM mode. For inverted PWM the output will have

the opposite logic values.

Timer/Counter Ti ming

Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock

(clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should

be replaced by the Timer/Count er Oscillator clock. The figures inc lude information on

when interrupt flags are set. Figure 66 contains timing data for basic Timer/Counter

operation. The figure shows the count s equence close to the MAX v alue in all m odes

other than phase correct PWM mode.

Figure 66. Timer/Counter Timing Diagram, no Prescaling

Figure 67 shows the same timing data, but with the prescaler enabled.

fOCnPCPWM fclk_I/O

N510⋅

------------------=

clk

(clkI/O/1)

TOVn

clk

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

146 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 67. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 68 shows the setting of OCF2 in all modes except CTC mode.

Figure 68. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)

Figure 69 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.

Figure 69. Timer/Counter Timi ng Dia gram, Cl ear Timer on Com par e Mat ch mode, with

Prescaler (fclk_I/O/8)

TOVn

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

OCFn

OCRn

TCNTn

OCRn Value

OCRn - 1 OCRn OCRn + 1 OCRn + 2

clk

I/O

clk

(clkI/O/8)

OCFn

OCRn

TCNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

147

ATmega162(V/U/L)

2513C–AVR–09/02

8-bit Timer/Counter

Ti mer/Counter Control

• Bit 7 – FOC2: Force Output Compare

The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for

ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is

written when operating in PWM mode . When writing a logica l one to the FOC2 bit, an

immed iate co mpare matc h is forced on the Wave form G eneratio n unit. Th e OC2 outp ut

is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented

as a strobe. Therefore it i s the value present in the COM21:0 bits that determines the

effect of the forced compare.

A FOC 2 strobe wil l not gene rate any interrupt, n or will it clear the ti mer in CTC mode

using OCR2 as TOP.

The FOC2 bit is always read as zero.

• Bit 6, 3 – WGM21:0: Waveform Generation Mode

These bits control the cou nting sequence of the co unter, the source for the maximum

(TOP) counter value, and what type of waveform generation to be used. Modes of oper-

atio n supported by the Timer /Counter unit are: Nor mal mode , Clear Tim er on Compar e

match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table

60 and “Mode s of Ope ra tio n” on page 141.

Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-

initions. However, the functionality and location of these bits are compatible with

previous versions of the timer.

Bit 76543210

FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 TCCR2

Read/Write W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 60. Waveform Generation Mode Bit Description(1)

Mode WGM21

(CTC2) WGM20

(PWM2) Timer/Counter Mode

of Operation TOP Update of

OCR2 at TO V2 Fl ag

Set on

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xF F T OP BOTTOM

2 1 0 CTC OCR2 Immediate MAX

31 1Fast PWM 0xFFTOPMAX

148 ATmega162(V/U/L) 2513C–AVR–09/02

• Bit 5:4 – COM21:0: Compare Match Output Mode

These bits control the Output Compare pin (OC2) behavior. If one or both of the

COM21 :0 b its are set , the O C2 ou tput ov erride s t he n orm al p ort f unc tion alit y of the I/O

pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-

sponding to OC2 pin must be set in order to enable the output driver.

When O C2 is conn ected to the pin, the function of the CO M21:0 bi ts depends on the

WGM21:0 bit setting. Table 61 shows the COM21:0 bit functionality when the WGM21:0

bits are set to a normal or CTC mode (non-PWM).

Table 62 shows the COM21:0 bit fu nctionality when the WGM2 1:0 bits are set to fast

PWM mode.

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the

compare m atch is ign ored, bu t the s et or clear i s done at T OP. See “Fast PW M Mode”

on page 143 for more details.

Table 63 sho ws the COM 21:0 bi t fu nc tio nal ity wh en the W GM21:0 bi ts are se t to phase

correct PW M mode .

Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the

compare match is ignored, but the set or clear is done at TOP. See “Phase Correct

PWM Mode” on page 144 for more details.

Table 61. Compare Output Mode, non-PWM Mode

COM21 COM20 Description

0 0 Normal port operation, OC2 disconnected.

0 1 Toggle OC2 on compare match.

1 0 Clear OC2 on compa re matc h.

1 1 Set OC2 on compare match.

Table 62. Compare Output Mode, Fast PWM Mode(1)

COM21 COM20 Description

0 0 Normal port operation, OC2 disconnected.

01Reserved

1 0 Clear OC2 on compare match, set OC2 at TOP.

1 1 Set OC2 on compare match, clear OC2 at TOP.

Table 63. Compare Output Mode, Phase Correct PWM Mode(1)

COM21 COM20 Description

0 0 Normal port operation, OC2 disconnected.

01Reserved

1 0 Clear OC2 on compare match when up-counting. Set OC2 on compare

match w hen down co unt ing .

1 1 Set OC2 on compare match when up-counting. Clear OC2 on compare

match w hen down co unt ing .

149

ATmega162(V/U/L)

2513C–AVR–09/02

• Bit 2:0 – CS22:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see

Table 64.

Timer/Counter Register –

TCNT2

The Timer/Counter Register gives direct access, both for read and write operations, to

the Timer/Counter unit 8 -bit counter. Writing to the T CNT2 Register blocks (removes )

the compare match on the following timer cl ock. Modifying the counter (TCNT2) while

the counter is running, introduces a risk of missing a compare match between TCNT2

and the OCR2 Register.

Output Compare Register –

OCR2

The Output Compare Register contains an 8-bit value that is continuously compared

with the counter value (TCNT2). A match can be used to generate an output compare

interrupt, or to generate a waveform output on the OC2 pin.

Table 64. Clock Select Bit Description

CS22 CS21 CS20 Description

0 0 0 No clock source (Timer/Counter stopped).

001clk

T2S/(No prescaling)

010clk

T2S/8 (From prescaler)

011clk

T2S/32 (From prescaler)

100clk

T2S/64 (From prescaler)

101clk

T2S/128 (From prescaler)

110clk

T2S/256 (From prescaler)

111clk

T2S/1024 (From prescaler)

Bit 76543210

TCNT2[7:0] TCNT2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

OCR2[7:0] OCR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

150 ATmega162(V/U/L) 2513C–AVR–09/02

Asynchronous operation

of the Timer/Counter

Asynchronous Status

• Bit 3 – AS2: Asynchronous Timer/Counter2

When AS 2 is w ritten to zer o, T imer /Coun ter 2 is c lo cked fr om th e I /O c lock , c lkI/O. When

AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to

the Time r Osci llato r 1 (TOSC 1) pin . Wh en the va lue of A S2 is change d, the co ntents of

TCNT2, OCR2, and TCCR2 might be corrupted.

• Bit 2 – TCN2UB: Timer/Counter2 Update Busy

When Timer /Cou nter 2 op erates as ync hron ous l y and TCNT2 is writte n, this bit beco mes

set. When TCNT2 has been updated from the tempor ary storage register, this bit is

cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be

updated with a new value.

• Bit 1 – OCR2UB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes

set. When OCR2 has been updated from the temporary storage register, this bit is

cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be

updated with a new value.

• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes

set. When TCCR2 has been updated from the tempor ary storage register, this bit is

cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be

updated with a new value.

If a write is performed to any of the three Timer/Counter2 Registers while its update

busy flag is set, the updated value might get corrupted and cause an unintentional inter-

rupt to occur.

The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading

TCNT2, the actua l timer value is read. When re ading OCR2 or TCCR2, the va lu e in the

temporary storage register is read.

Bit 76543 2 1 0

–––– AS2 TCN2UB OCR2UB TCR2UB ASSR

Read/Write R R R R R/W R R R

Initial Value 0 0 0 0 0 0 0 0

151

ATmega162(V/U/L)

2513C–AVR–09/02

Asynchronous Operation of

Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken.

• W arning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Ti mer Registers TCNT2, OCR2, and TCCR2 might be

corrupted. A safe procedure for switching clock source is:

1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.

2. Select clock source by setting AS2 as appropriate.

3. Write new values to TCNT2, OCR2, and TCCR2.

4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and

TCR2UB.

5. Clear the Timer/Counter2 interrupt flags.

6. Enable interrupts, if needed.

• The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an

external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation.

The CPU main clock frequency must be more than four times the Oscillator

frequency.

• When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is

transferred to a temporary register, and latched after two positive edges on TOSC1.

The user should not write a new value before the contents of the temporary register

have been transferred to its destination. Each of the three mentioned registers have

their individual temporary register , which means that e.g., writing to TCNT2 does not

disturb an OCR2 write in progress. To detect that a transfer to the destination

implemented.

• When entering Power-save or Extended Standby mode after having written to

TCNT2, OCR2, or TCCR2, the user must wait until the written register has been

updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will

enter sleep mode before the changes are effective. This is particularly important if

the Output Compare2 interrupt is used to wake up the device, since the output

compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is

not finished, and the MCU enters sleep mode before the OCR2UB bit returns to

zero, the device will never receive a compare match interrupt, and the MCU will not

wake up.

• If Timer/Counter2 is used to wake the device up from Power-save or Extended

Standby mode, precautions must be taken if the user wants to re-enter one of these

modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between

wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will

not occur, and the device will fail to wake up. If the user is in doubt whether the time

before re-entering Power-save or Extended Standby mode is sufficient, the

following algorithm can be used to ensure that one TOSC1 cycle has elapsed:

1. Write a value to TCCR2, TCNT2, or OCR2.

2. Wait until the corresponding Update Busy flag in ASSR returns to zero.

3. Enter Power-save or Extended Standby mode.

• When the asynchronous operation is selected, the 32.768 kHz Oscillator for

Timer/Counter2 is always running, except in Power-down and Standby modes.

After a Power-up Reset or wake-up from Power-down or Standby mode, the user

should be aware of the fact that this Oscillator might take as long as one second to

stabilize. The user is advised to wait for at least one second before using

Timer/Counter2 after Power-up or wake-up from Power-down or Standby mode.

The contents of all Timer/Counter2 Registers must be considered lost after a wake-

up from Power-down or Standby mode due to unstable clock signal upon start-up,

152 ATmega162(V/U/L) 2513C–AVR–09/02

no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1

pin.

• Description of wake up from Power-save or Extended Standby mode when the

Timer is clocked asynchronously: When the interrupt condition is met, the wake up

process is started on the following cycle of the timer clock, that is, the Timer is

always advanced by at least one before the processor can read the counter value.

After wake-up, the MCU is halted for four cycles, it executes the interrupt routine,

and resumes execution from the instruction following SLEEP.

• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an

incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading

TCNT2 must be done through a register synchronized to the internal I/O clock

domain. Synchronization takes place for every rising TOSC1 edge. When waking up

from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will

read as the previous value (before entering sleep) until the next rising TOSC1 edge.

The phase of the TOSC clock after waking up from Power-save mode is essentially

unpredictable, as it depends on the wake-up time. The recommended procedure for

reading TCNT2 is thus as follows:

1. Write any value to either of the registers OCR2 or TCCR2.

2. W ait for the corresponding Update Busy Flag to be cleared.

3. Read TCNT2.

• During asynchronous operation, the synchronization of the interrupt flags for the

Asynchronous Timer takes three processor cycles plus one timer cycle. The Timer

is therefore advanced by at least one before the processor can read the T imer value

causing the setting of the interrupt flag. The output compare pin is changed on the

Timer clock and is not synchronized to the processor clock.

Timer/Counter Interrupt Mask

• Bit 4 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is

executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in

the Timer/Counter Interrupt Flag Register – TIFR.

• Bit 2 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE 2 bit is writt en to one and the I-bi t in the Statu s Regis ter is set (one) , the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if

an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the

Timer/Counter Interrupt Flag Register – TIFR.

Bit 76543210

TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

153

ATmega162(V/U/L)

2513C–AVR–09/02

Timer/Counter Interrupt Flag

• Bit 4 – OCF2: Output Compare Flag 2

The OC F2 bi t is set (o ne) wh en a comp are ma tch occ urs be tween the Time r/Co unter2

and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when

executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by

writing a logic one to the fl ag. When the I-bit in SREG, OC IE2 (Timer/Counter2 Com -

pare Ma tch Interr upt Enable ), and O CF2 are set (one), the Timer /Counter 2 Compare

Match Interrupt is executed .

• Bit 2 – TOV2: Timer/Counter2 Overflow Flag

The TOV 2 bit is set (one) whe n an over flow occu rs in Timer /Count er2. TOV2 i s cleare d

by har dware when execut ing the c orresp onding in terru pt handl ing vect or. Alter nativel y,

TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2

(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the

Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/ Cou nter2 change s co unti ng dir ect ion a t 0x00 .

Bit 76543210

TOV1 OCF1A OC1FB OCF2 ICF1 TOV2 TOV0 OCF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

154 ATmega162(V/U/L) 2513C–AVR–09/02

Timer/Counter Prescaler Figure 70. Prescaler for Timer/Counter2

The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to

the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asyn-

chrono usly clock ed from the TOS C1 pi n. T his en abl es use of T imer/ Coun ter2 as a Rea l

Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from

Port D. A c rys tal can then be c onn ected be tween the TO SC1 an d T OSC2 pi ns to s erv e

as an indep endent clo ck source for Timer/Count er2. The Osci llator is opti mized for us e

with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not

recommended.

For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,

clkT2S/128, c lkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be

select ed. Setting the PS R2 bit in SFIOR res ets the prescale r. This allow s the user to

operate with a predictable prescaler.

Special Function IO Register –

SFIOR

• Bit 1 – PSR2: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally

cleared imm ediate ly by ha rdware. If this bit is written when Tim er/Counter 2 is opera ting

in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit

will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7

– TSM: Timer/Counter Synchronization Mode” on page 103 for a description of the

Timer/Counter Synchronization mode.

10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

clkI/O clkT2S

TOSC1

AS2

CS20

CS21

CS22

clkT2S

/64

clkT2S

/128

clkT2S

/1024

clkT2S

/256

clkT2S

/32

PSR2

Clear

clkT2

Bit 7 6 5 4 3 2 1 0

TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Val-

ue 00000000

155

ATmega162(V/U/L)

2513C–AVR–09/02

Serial Peripheral

Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between t he ATmega162 a nd pe ri phe ra l de vi ce s or betw een s ev er al A VR dev ices . T h e

ATmega162 SPI includes the following features:

•Full-duplex, Three-wire Synchronous Data Transfer

•Master or Slave Operation

•LSB First or MSB First Data Transfer

•Seven Programmable Bit Rates

•End of Transmission Interrupt Flag

•Wr ite Collis ion Flag Pro tec tion

•Wake-up from Idle Mode

•Double Speed (CK/2) Master SPI Mode

Figure 71. SPI Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, and Table 32 on page 70 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 72.

The system consists of two Shift Registers, and a Master clock generator. The SPI Mas-

ter initiates the communication cycle when pulling low the Slave Select SS pi n of the

desired Slave. Master and Slave prepare the data to be sent in th eir respective Shift

change d ata. Data is alway s shifted from Master to Sl av e o n th e Ma st er Ou t – Slav e I n,

MOSI, lin e, and fr om Slave t o Master o n the Mas ter In – Slave O ut, MISO, li ne. After

each data packet, the Master will synchronize the Slave by pulling high the Slave Select,

SS, line.

SPI2X

DIVIDER

/2/4/8/16/32/64/128

156 ATmega162(V/U/L) 2513C–AVR–09/02

When configured as a Master, the SPI interface has no automatic control of the SS line .

This must be hand led by user softwa re before com munication ca n start. When this is

done, writing a byte to the SPI Data Register starts the SPI clock generator, and the

hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener-

ator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt Enable bit

(SPIE) in the SPCR Regist er is set, an interrup t is reque sted. The Mas ter may cont inue

to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high

the Slave Select, SS line. The last i ncoming by te will be k ept in the b uffer register for

later use.

When c onfi gured a s a S l ave , t he SP I i nte rfac e wi ll rem ai n s l eeping wi th MIS O tri- s tate d

as long as the SS pin is driven high. In this state, software may update the contents of

the SPI Data Register, SPDR, but the data will not be s hifted out by incoming clock

pulses on the SCK pin until the SS pin is driven low. As one byte has been completely

shifted, the end of transmis sio n fl ag, SP IF is set. If the S PI in terru pt e nab le bi t, S PIE, i n

the SPCR Regi ster is set, an interrupt is requested. T he Slave may continue to p lace

new data to be sent into SPDR before reading the incoming data. The last incoming byte

will be kept in the buffer register for later use.

Figure 72. SPI Master-slave Interconnection

The system is single buffered in the transmit direction and double buffered in the receive

direction. This means that bytes to be transmitted cannot be written to the SPI Data

received character must be read from the SPI Data Register before the next character

has been completely shifted in. Otherwise, the first byte is lost.

In SPI S lave mode, the c ontro l log ic will samp le the inco ming signa l of t he SCK pin. To

ensure correct sampling of the clock signal, the frequency of the SPI clock should never

exceed f osc/4.

When the SPI is enabled, the data direction of the MOSI, MISO , SCK, and SS pins is

overridd en acco rding t o Table 65. Fo r more detail s on autom atic port ov erride s, refer to

“Alternate Port Functions” on page 66.

Note: 1. See “Alternate Functions Of Port B” on page 70 for a detailed description of how to

define the direction of the user defined SPI pins.

Table 65. SPI Pin Overrides(1)

Pin Direction, Master SPI Direction, Slave SPI

MOSI User Defined Inpu t

MISO Input User Defined

SCK User Defined Input

SS User Defined Input

MSB MASTER LSB

8-BIT SHIFT REGISTER

MSB SLAVE LSB

8-BIT SHIFT REGISTER

MISO

MOSI

SPI

CLOCK GENERATOR SCK

MISO

MOSI

SCK

VCC

SHIFT

ENABLE

157

ATmega162(V/U/L)

2513C–AVR–09/02

The following code examples show how to initialize the SPI as a Master and how to per-

form a simple transmission. DDR_SPI in the examples must be replaced by the actual

Data Direction Register controlling the SP I pins. DD_MOSI, DD_MISO, and DD_SCK

must be repl aced by the ac tual data di rection bits for these pins. E.g ., if MOSI is pla ced

on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.

Note: 1. The example code assumes that the part specific header file is included.

Assembly Code Examp le(1)

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

sbis SPSR,SPIF

rjmp Wait_Transmit

ret

C Code Example(1)

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

}

158 ATmega162(V/U/L) 2513C–AVR–09/02

The following code examples show how to initialize the SPI as a slave and how to per-

form a simple reception.

Note: 1. The example code assumes that the part specific header file is included.

Assembly Code Examp le(1)

SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in r16,SPDR

ret

C Code Example(1)

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return data register */

return SPDR;

}

159

ATmega162(V/U/L)

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SS Pin Functionality

Slave Mod e When the SP I is c on fig ur ed as a sla ve , th e S lav e Selec t ( S S) pi n i s alway s inp ut. W he n

SS is held low, the SPI is activated, and MISO becomes an output if configured so by

the user. All ot her pins are inputs. When SS is dri ven hi gh, al l pins are input s, an d the

SPI is passive, which means that it will not receive incoming data. Note that the SPI

logic will be reset once the SS pin is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter syn-

chronous with the master clock generator. When the SS pin i s d ri ven high , t he S PI S la ve

will immediately reset the send and receive logic, and drop any partially received data in

the Shift Register.

Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine

the direction of the SS pin .

If SS is configured as an output, the pin is a general output pin which does not affect the

SPI system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If

the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master

with the SS pin defined as an i nput, the S PI syste m interpre ts this as another M aster

selecting the SPI as a slave And starting to send data to it. To avoid bus contention, the

SPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a

result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in

SREG is set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a

possibility that SS is driven low, the interrupt should always check that the MSTR bit is

still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to

re-enable SPI Master mode.

SPI Control Register – SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set

and the if the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit i s written to one, the SPI is enabled . This bit must be set to enable

any SPI operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

Bit 76543210

SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

160 ATmega162(V/U/L) 2513C–AVR–09/02

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written

logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will

be cleared , and SP IF in SPSR will becom e set. T he user will t hen have to set MSTR to

re-enable SPI Master mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is writte n to one, SCK is high when idle. When CPOL is written to zero,

SCK is low when idle. Refer to Figure 73 and Figure 74 for an example. The CPOL func-

tionality is summarized below:

• Bit 2 – CPHA: Clock Phase

The se ttin gs of the Clo ck P hase bi t ( CPH A) de ter mi ne if data i s sam pl ed on t he l ea ding

(first) or tra iling (last) edge of SCK. Refer to Figure 73 and F igure 74 for an example.

The CPHA functionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These tw o bits control the SCK rate of th e device confi gured as a Master . SPR1 an d

SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator

Clock frequency fosc is shown in the following table:

Table 66. CPOL Functionality

CPOL Leading Edge Trailing Edge

0 Rising Falling

1 Falling Rising

Table 67. CPHA Functionality

CPHA Leading Edge Trailing Edge

0 Sample Setup

1Setup Sample

Table 68. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency

000fosc/4

001

fosc/16

010

fosc/64

011

fosc/128

100

fosc/2

101

fosc/8

110

fosc/32

111

fosc/64

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SPI Status Register – SPSR

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE

in SPCR is set and global interrupts are enabled. If SS is an input and is driven low

when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hard-

ware when ex ecuting the corre sponding interrupt handling vector. A lternatively, the

SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing

the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.

The WCO L bit (and the SPIF bit ) are cleared by fi rst reading the SPI Sta tus Register

with WCOL set, and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATmega162 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written lo gic on e the SP I speed (SCK Frequen cy) wil l be dou bled whe n

the SPI is in Master mode (see Table 68). This means that the minimum SCK period will

be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran-

teed to work at fosc/4 or lower.

The SPI interface on the ATmega162 is also used for program memory and EEPROM

downloading or uploading. See page 242 for SPI serial programming and verification.

SPI Data Register – SPDR

The SPI Data Register is a read/write register used for data transfer between the Regis-

ter File and the SPI Shift Register. Writing to the register initiates data transmission.

Reading the register causes the Shift Register receive buffer to be read.

Bit 76543210

SPIF WCOL – – – – – SPI2X SPSR

Read/WriteRRRRRRRR/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

MSB LSB SPDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value X X X X X X X X Undefined

162 ATmega162(V/U/L) 2513C–AVR–09/02

Data Modes There are four combinations of SCK phase and polarity with respect to serial data,

which are determined by control bits CPHA and CPOL. The SPI data transfer formats

are shown in Figure 73 and F igure 74. D ata bits are shi fted out and la tched in on oppo-

site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is

clearly seen by summarizing Table 66 and Table 67, as done below:

Figure 73. SPI Transfer Format with CPHA = 0

Figure 74. SPI Transfer Format with CPHA = 1

Table 69. CPOL and CPHA Function ali ty

Leading Edge Trailing Edge SPI Mode

CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0

CPOL=0, CPHA=1 Setup (Rising) Samp le (Falling) 1

CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2

CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3

Bit 1

Bit 6 LSB

MSB

SCK (CPOL = 0)

mode 0

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 2

MSB

LSB Bit 6

Bit 1 Bit 5

Bit 2 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5

MSB first (DORD = 0)

LSB first (DORD = 1)

SCK (CPOL = 0)

mode 1

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 3

MSB

LSB Bit 6

Bit 1 Bit 5

Bit 2 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6 LSB

MSB

MSB first (DORD = 0)

LSB first (DORD = 1)

163

ATmega162(V/U/L)

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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART) is a highly flexible serial communication device. The main features are:

•Full Duplex Operation (Independent Serial Receive and Transmit Registers)

•Asynchronous or Synchronous Operation

•Master or Slave Clocked Synchronous Operation

•High Resolution Baud Rate Generator

•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

•Odd or Even Parity Generation and Parity Check Supported by Hardware

•Data OverRun Detection

•Framing Error Detection

•Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

•Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

•Multi-proce sso r Comm unic ation Mode

•Double Speed Asynchronous Communication Mode

Dual USART The ATm ega162 has two USA RTs, USART0 and USAR T1. The fu nctional ity for bo th

USARTs is described below.

USART0 and USART1 have different I/O Registers as shown in “Register Summary” on

page 272 . Note that in ATmega161 compatibility mode, the double buffering of the

USART Receive Register is disabled. For details, see “AVR USART vs. AVR UART –

Compatibi lity” on pa ge 165. Note also that the sha red UBRRH I Registe r in ATmega16 1

has been split into two seperate registers, UBRR0H and UBRR1H, in ATmega162.

A simplified block diagram of the USART Transmitter is shown in Figure 75. CPU acces-

sible I/O Registers and I/O pins are shown in bold.

164 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 75. USART Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Tabl e 34 on page 72, Table 39 on page 78, and Table

40 on page 78 for USART pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART

(listed from the top): Clock Generator, Transmitter and Receiver. Control registers are

shared by all units. The Clock Generation logic consists of synchronization logic for

externa l clo ck i npu t us ed by sync hr on ous s la ve ope ratio n, a nd the baud rate generator .

The XCK (Transfer Clock) pin is only used by synchronous transfer mode. The Trans-

mitter consists of a single write buffer, a serial Shift Register, parity generator and

control l ogi c fo r han dli ng differ e nt s eri al fr am e fo rmats . The write bu ffer a llows a conti n-

uous transfer of data without any delay between frames. The Receiver is the most

complex par t of the USA RT modu le du e to it s c loc k and da ta re co ve ry uni ts . The re co v-

ery units are used for asynchronous data reception. In addition to the recovery units, the

Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDR). The receiver supports the same frame formats as the Transmitter,

and can detect Frame Error, Data OverRun and Parity Errors.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA UCSRB UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

DATABUS

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

165

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AVR USART vs. AVR UART –

Compatibility The USART is fully compatible with the AVR UART regarding:

• Bit locations inside all USART Register s

• Baud Rate Generation

• Transmitter Ope r ation

• Transmit Buffer Functionality

• Receiver Operation

However, the receive buffering has two improvements that will affect the compatibility in

some special cases:

• A second buffer register has been added. The two buffer registers operate as a

circular FIFO buffer. Therefore the UDR must only be read once for each incoming

data! More important is the fact that the error flags (FE and DOR) and the ninth data

bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits

must always be read before the UDR Register is read. Otherwise the error status

will be lost since the buffer state is lost.

• The Receiver Shift Register can now act as a third buffer level. This is done by

allowing the received data to remain in the serial Shift Register (see Figure 75) if the

buffer registers are full, until a new start bit is detected. The USART is therefore

more resistant to Data OverRun (DOR) error conditions.

The fol lowing co ntr ol bi ts have c ha nge d na me, but hav e sam e fu nc tio nal ity a nd re g ister

location:

• CHR9 is changed to UCSZ2.

• OR is changed to DOR.

Clock Generation The Clock Gene ration logi c ge nerat es th e bas e cl ock fo r th e Tran smit ter a nd Rec eiv er.

The USART supports four modes of clock operation: Normal asynchronous, Double

Speed as ynchr onous, Maste r synchr onous and Slave synch ronous mode. The UMSE L

bit in USART Control and Status Register C (UCSRC) selects between asynchronous

and synchronous operation. Double Speed (asynchronous mode only) is controlled by

the U2X found in the UCSRA Regi ster. When using synchronous mode (UMSEL = 1),

the Data Direction Regi ster for the XCK pin (DDR_XCK) controls whether the clock

source is internal (Master mode) or external (Slave mode). The XCK pin is only active

when using synchronous mode.

Figure 76 shows a block diagram of the clock generation logic.

Figure 76. Clock Generation Logic, Block Diagram

Prescaling

Down-Counter / 2

UBRR

/ 4 / 2

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK rxclk

Edge

Detector

UCPOL

166 ATmega162(V/U/L) 2513C–AVR–09/02

Signal des cr i ption:

txclk Transmitter clock. (Internal Signal)

rxclk Receiver base clock. (Internal Signal)

xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.

xcko Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc XTAL pin frequency (System Clock).

Internal Clock Generation –

The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master

modes of operation. The description in this section refers to Figure 76.

The USART Baud Rate Register (UBRR) and the down-counter connected to it function

as a programmable prescaler or baud rate generator. The down-counter, running at sys-

tem clock (fosc ), is loaded with the UBRR value each time the counter has counted

down to zero or when the UBRRL Register is written. A clock is generated each time the

counter reaches zero. This clock is the baud rate generator clock output (=

fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or

16 depending on mode. The baud rate generator output is used directly by the receiver’s

clock and data recovery units. However, the recovery units use a state machine that

uses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X and

DDR_XCK bits.

Table 70 contai ns equation s for cal culating the baud rate (in bits pe r second) and for

calculati ng the UBRR value for each mode of operation using an i nternally gene rated

clock source.

Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).

BAUD Baud rate (in bits per second, bps)

fOSC System Oscillator clock frequency

UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)

Some exam ples of UBR R values for some system cloc k frequ encie s are found in T able

78 (see page 188).

Table 70. Equations for Calculating Baud Rate Register Setting

Operating Mod e Equation for Calcula ting

Baud Rate(1) Equation for Calculating

UBRR Value

Asynchronous Normal Mode

(U2X = 0)

Asynchronous Double Speed

Mode (U2X = 1)

Synchronous Master Mode

BAUD fOSC

16 UBRR 1+()

---------------------------------------= UBRR fOSC

16BAUD

------------------------1–=

BAUD fOSC

8UBRR 1+()

-----------------------------------=UBRR fOSC

8BAUD

-------------------- 1–=

BAUD fOSC

2UBRR 1+()

-----------------------------------=UBRR fOSC

2BAUD

-------------------- 1–=

167

ATmega162(V/U/L)

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Double Speed Operation

(U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only

has e ffect for the asy nchro nous ope ration . Set t his b it to zer o w hen u sin g sy nch ronous

operation.

Settin g this bit w ill red uce the di visor of the baud r ate divide r from 1 6 to 8, eff ectively

doubli ng the t ransfer rate for asynchro nous co mmunicat ion. Note howeve r that th e

Receiver will in this case only use half the number of samples (reduced from 16 to 8) for

data sam pl ing an d c l oc k reco very, and the r efore a more ac cu ra te bau d r ate s ett ing an d

system clock are required when this mode is used. For the Transmitter, there are no

downsides.

Exte rn al Clo ck External clocking is used by the synchronous slave modes of operation. The description

in this section refers to Figure 76 for details.

Externa l c lock inp ut f rom the XCK pin is s amp led by a syn chron iza tion regi ster to mini-

mize the chance of meta-stabilit y. The output from the synchronization register must

then pass through an edge detector before it can be used by the Transmitter and

Receiver. This process introduces a two CPU clock period delay and therefore the max-

imum external XCK clock frequency is limited by the following equation:

Note that f osc depe nds o n th e sta bilit y of th e sy stem cloc k so urce . It is therefo re r ecom-

mended to add some margin to avoid possible loss of data due to frequency variations.

Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock

input (Slave) or clock output (Mas ter). The dependency between the clock edges and

data sampling or data change is the same. The basic principle is that data input (on

RxD) is sampled at the opp osite XCK clock edge of th e edge the data output (TxD) is

changed.

Figure 77. Synchronous Mode XCK Timing.

The UCPOL bit UCRS C selects which XCK c lock edge is used for data sampling and

which is used for data change. As Figure 77 shows, when UCPOL is zero the data will

be ch anged at rising XCK edg e and sam pled at fallin g XCK ed ge. If UC POL is set , the

data will be changed at falling XCK edge and sampled at rising XCK edge.

XCK fOSC

-----------

RxD / TxD

XCK

RxD / TxD

XCK

UCPOL = 0

UCPOL = 1

Sample

168 ATmega162(V/U/L) 2513C–AVR–09/02

Frame Formats A serial frame is def ined to be on e charact er of data bits with synchr oniz ation bits (start

and st op bits ), and o ption ally a parity bit for e rror c hecki ng. Th e USAR T acce pts al l 30

combinations of the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the next

data bits , up to a total of nine , are succeed ing, ending wit h the most signi ficant bit. If

enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-

plete frame is transmitted, it can be directly followed by a new frame, or the

communication line can be set to an idle (high) state. Figure 78 illustrates the possible

combinations of the frame formats. Bits inside brackets are optional.

Figure 78. Frame Formats

St Start bit, always low.

(n) Data bits (0 to 8).

PParity bit. Can be odd or even.

Sp Stop bit, always high.

IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be

high.

The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in

UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that

changin g the s etti ng of a ny o f t hes e bi ts wi ll cor rupt all o ngoi ng c om mun ic ati on for both

the Receive r and Trans mit ter .

The USA RT Character S i Ze ( UCS Z2:0) b its s el ect the num ber o f data bit s in the fram e.

The USART Pa rity mode (UPM1: 0) bits enab le and se t the typ e of parity bi t. The sele c-

tion between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The

receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected

in the cases where the first stop bit is zero.

Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is

used, the result of the exclusive or is inverted. The relation between the parity bit and

data bits is as follows::

Peven Parity bit using even parity

Podd Parity bit using odd parity

dnData bit n of the character

10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)

FRAME

Peven dn1–…d3d2d1d00

Podd

⊕⊕⊕⊕⊕⊕

dn1–…d3d2d1d01⊕⊕⊕⊕⊕⊕

169

ATmega162(V/U/L)

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If used, the parity bit is located between the last data bit and first stop bit of a serial

frame.

USART Initialization The USART has to be initialized before any communication can take place. The initial-

ization pr ocess normally consists of s etting the baud rate, s etting frame format a nd

enabling the Transmitter or the Receiver depending on the usage. For interrupt dr iven

USART operation, the Global Interrupt Flag should be cleared (and interrupts globally

disabled) when doing the initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that

there are no ongoing tra nsmissio ns during the per iod the regis ters are cha nged. The

TXC flag can be used to check that the Transmitter has completed all transfers, and the

RXC flag can be used to check that there are no unread data in the receive buffer. Note

that the T XC fl ag must be clea red befor e eac h trans missio n (befor e UDR is written ) if it

is used for this purpose.

The following simple USART initialization code examples show one assembly and one

C function that are equal in functionality. The examples assume asynchronous opera-

tion using polling (no interrupts enabled) and a fixed frame format. The baud rate is

given as a function parameter. For the assembly code, the baud rate parameter is

assumed to be stored in the r17:r16 registers. When the function writ es to the UCSRC

and UCSRC.

Note: 1. The example code assumes that the part specific header file is included.

More advanced initialization routines can be made that include frame format as parame-

ters, disable interrupts and so on. However, many applications use a fixed setting of the

Assembly Code Examp le(1)

USART_Init:

; Set baud rate

out UBRRH, r17

out UBRRL, r16

; Enable receiver and transmitter

ldi r16, (1<<RXEN)|(1<<TXEN)

out UCSRB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0)

out UCSRC,r16

ret

C Code Example(1)

void USART_Init( unsigned int baud )

{

/* Set baud rate */

UBRRH = (unsigned char)(baud>>8);

UBRRL = (unsigned char)baud;

/* Enable receiver and transmitter */

UCSRB = (1<<RXEN)|(1<<TXEN);

/* Set frame format: 8data, 2stop bit */

UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0);

}

170 ATmega162(V/U/L) 2513C–AVR–09/02

baud and control registers, and for these types of applications the initialization code can

be placed directly in the main routine, or be combined with initialization code for other

I/O modules.

Data Transmission – The

USART Trans mitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN ) bit in the

UCSRB Register. When the Transmitter is enabled, the normal port operation of the

TxD pin is overridden by the USART and gi ven the function as the transmitter’s serial

output. The baud rate, mode of operati on and frame for mat mus t be set up once bef ore

doing any transmissions. If synchronous operation is used, the clock on the XCK pin will

be overridden and used as transmission clock.

Sending Frames with 5 to 8

Data Bit A data transmission is initiated by loading the transmit buffer with the data to be trans-

mitted . The CPU can loa d the transmit b uffer by writi ng to the UDR I/O lo cation. The

buffered data in t he transmit buffer wi ll be move d to t he Shift Regi ster whe n the Shift

in idle sta te (no ong oing tra nsmiss ion) o r immedia tely aft er the las t stop bi t of the previ-

ous frame is transmitted. When the Shift Register is loaded with new data, it will transfer

one complete frame at the rate given by the baud register, U2X bit or by XCK depending

on mode of operation.

The fo llowing code exa mples show a si mple USART trans mit function bas ed on poll ing

of the Data Register Empty (UDRE) flag. When using frames with less than eight bits,

the most significant bits written to the UDR are ignored. The USART has to be initialized

before the function can be used. For the assembly code, the data to be sent is assumed

to be stored in Register R16

Note: 1. The example code assumes that the part specific header file is included.

The function simply waits for the transmit buffer to be empty by checking the UDRE flag,

before loa ding it wi th new data to be trans mitte d. If the Data Regi ster Empt y inter rupt is

utilized, the interrupt routine writes the data into the buffer.

Assembly Code Examp le(1)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example(1)

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Put data into buffer, sends the data */

UDR = data;

}

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Sending Frames with 9 Data

Bit If 9-bit c haract ers are us ed (UCSZ = 7), the ninth bit mus t be writte n to the TXB8 bit in

UCSRB before the low byte of the character is written to UDR. The following code

exampl es show a transmit fu nction that handles 9 -bit chara cters. For the assemb ly

code, the data to be sent is assumed to be stored in Registers R17:R16.

Note: 1. These tra nsm it functions ar e w ritten to be gener al f unc tio ns . They can be op timiz ed i f

the contents of the UCSRB is static. For example, only the TXB8 bit of the UCSRB

The ninth bit can be used for indicating an address frame when using multi processor

communication mode or for other protocol handling as for example synchronization.

Transmit ter Fl ags and

Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register

Empty (UDRE) an d Transmit Comp lete (TXC). Both flags can be used for generatin g

interrupts.

The Data Re gister Empty (UDRE) flag indi cates whethe r the transmit bu ffer is ready to

receive new data. This bit is set when the transmit buffer is empty, and cleared when the

transmit buffer contains data to be transmitted that has not yet been moved into the Shift

the UCSRA Register.

When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one,

the USART Data Register Empty Interrupt will be executed as long as UDRE is set (pro-

vided that global interrupts are enabled). UDRE is cleared by writing UDR. Whe n

interrupt-driven data transmission is used, the Data Register Empty Interrupt routine

must eithe r write new data to UDR in order t o clear UDRE o r dis able the Data Register

Assembly Code Examp le(1)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB8

cbi UCSRB,TXB8

sbrc r17,0

sbi UCSRB,TXB8

; Put LSB data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example(1)

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Copy 9th bit to TXB8 */

UCSRB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDR = data;

}

172 ATmega162(V/U/L) 2513C–AVR–09/02

Empty Interrupt, otherwise a new interrupt will occur once the interrupt routine

terminates.

The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit

Shift Register has been shifted out and there are no new data currently present in the

transmit buffer. The TXC flag bit is automatically cleared when a transmit complete inter-

rupt is ex ecuted , or it c an be cl eared by writi ng a one t o its b it locati on. Th e TXC fla g is

useful in half-duplex commu nication inte rfaces (like the RS-485 standard ), where a

transmitting application must enter Receive mode and free the communication bus

immediately after completing the transmission.

When the T ransmi t Compete Interrupt Enable (TXCIE) b it in UCSR B is set, th e USART

Transmit Complete Interrupt will be executed when the TXC flag becomes set (provided

that globa l interrup ts are enabled) . When the transm it complete inte rrupt is used, the

interrupt handling routine does not have to clear the TXC flag, this is done automatically

when the interrupt is executed.

Parity Generator The Parity Generator calculates the parity bit for the serial frame data. When parity bit is

enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last

data bit and the first stop bit of the frame that is sent.

Disabling the Transmitter The disabling of the Transmitter (setting the TXEN to zero) will not become effective

until o ngoing an d pendin g transm issions a re comple ted, i.e., when t he Transmi t Shift

abled, the Transmitter will no longer override the TxD pin.

Data Reception – The

USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the

UCSRB Re gister to on e. When th e receiv er is enab led, the normal pin operation of the

RxD pin is overridden by the USART and given the function as the receiver’s serial

input. The baud rate, mode of operation and frame format must be set up once before

any serial reception can be done. If synchronous operation is used, the clock on the

XCK pin will be used as transfer clock.

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Receiving Frames with 5 to 8

Data Bits The Re ceiv er st arts data r ecep tion whe n it detec ts a v alid star t bit. E ach bit that follows

the star t bit will be s ampled at the bau d rate or XCK cloc k, and shif ted int o the Re ceiv e

Shift Register u ntil the first stop bi t of a frame is receiv ed. A second s top bit will be

ignored by the Receiver. When the first stop bit is received, i.e., a complete serial frame

is present i n the Re cei ve Shi ft Reg is ter, the con tents of the Shift Regi s ter will be mo ve d

into the receive buffer. The receive buffer can then be read by reading the UDR I/O

location.

The following code example shows a simple USART receive function based on polling

of the Re ceive C omplete ( RXC) flag. When us ing fra mes with le ss than eight bi ts the

most signi fican t bi ts of the data read from the UDR w ill b e ma sked to ze ro. The USAR T

has to be initialized before the function can be used.

Note: 1. The example code assumes that the part specific header file is included.

The fu nction simply waits for dat a to be present i n the r eceive b uffer by chec king th e

RXC flag, before reading the buffer and returning the value.

Assembly Code Examp le(1)

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get and return received data from buffer

in r16, UDR

ret

C Code Example(1)

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get and return received data from buffer */

return UDR;

}

174 ATmega162(V/U/L) 2513C–AVR–09/02

Receiving Frames with 9 Data

Bits If 9-bit characters are us ed (UCSZ=7) the ninth bit mu st be read from the RXB 8 bit in

UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and

UPE status flags as well. Read status from UCSRA, then data from UDR. Reading the

UDR I/O location will chang e the state of the receiv e buffer FIFO and consequ ently the

TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change.

The fol lowing code example show s a simple USAR T r eceive functi on that handl es bo th

nine bit charac ter s and the stat us bits .

Note: 1. The example code assumes that the part specific header file is included.

Assembly Code Examp le(1)

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in r18, UCSRA

in r17, UCSRB

in r16, UDR

; If error, return -1

andi r18,(1<<FE)|(1<<DOR)|(1<<UPE)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example(1)

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSRA;

resh = UCSRB;

resl = UDR;

/* If error, return -1 */

if ( status & (1<<FE)|(1<<DOR)|(1<<UPE) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

175

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The receiv e function e xample reads all the I/O Registers in to the Register Fi le before

any computation is done. This gives an optimal receive buffer utilization since the buffer

location read will be free to accept new data as early as possible.

Receive Com pete Flag and

Interrupt The USART Receiver has one flag that indicates the receiver state.

The Receive Complete (RXC) flag indicates if th ere are unread dat a present in the

receive buffer. This flag is one when unread data exist in the receive buffer, and zero

when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver

is dis ab led (RX EN = 0) , t he re ce iv e b uffe r wi ll be fl us hed an d c on se que ntly the RXC bi t

will becom e zero.

When the Recei ve Comple te Interr upt Enabl e (RXCIE ) in UCSRB is set, the USA RT

Receive Complete Inte rrupt will be e xecuted as long as th e RXC flag is set (provide d

that global interrupts are enabled). When interrupt-driven data reception is used, the

receive complete routine must read the received data from UDR in order to clear the

RXC flag, otherwise a new interrupt will occur once the interrupt routine terminates.

Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and

Parity Error (UPE). All can be accessed by reading UCSRA. Common for the error flags

is that they are l ocate d in the rec eive b uffer togeth er with the frame for whi ch they ind i-

cate the error status. Due to the buffering of the error flags, the UCSRA must be read

before the receiv e buffer (UDR), since reading th e UDR I/O locatio n changes the bu ffer

read loc ation . Anoth er equali ty for the err or flags is tha t they can not be a ltere d by soft-

ware do ing a write to the flag location . However, all flag s must be se t to zero when the

UCSRA is written for upward com patibility of future USART implementations. None of

the error flags can generate interrupts.

The Fram e Error (FE) flag indicates t he state of the first st op bit of the ne xt readable

frame stored in the receive buffer. The FE flag is z ero when the stop bit was correctly

read (as one), and the FE flag will be one when the stop bit was incorrect (zero). This

flag ca n be used for detecting ou t-of-syn c conditi ons, detect ing break conditio ns and

protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRC

since the receiver ignores all, except for the first, stop bits. For compatibility with future

devices, always set this bit to zero when writing to UCSRA.

The Data O verRu n (D OR ) flag in di cat es data l os s du e to a rece iv er buff er full con di tio n.

A Data OverRun occurs when the receive buffer is full (two characters), it is a new char-

acter waiting in the Receive Shift Register, and a new start bit is detected. If the DOR

flag is set there was one or more serial frame lost between the frame last read from

UDR, and the next frame read from UDR. For compatibility with future devices, alw ays

write this bit to zero when writing to UCSRA. The DOR flag is c leared when the frame

received was successfully moved from the Shift Register to the receive buffer.

The Parity Error (UPE) flag indicates that the next frame in the receive buffer had a Par-

ity Error when received. If parity check is not enabl ed the UPE bit will alway s be read

zero. Fo r compatib ility with fu ture devic es, always se t this bit to zero w hen writin g to

UCSRA. Fo r more deta il s see “Pa ri ty Bi t Calc ul ation” on page 168 and “ Pari ty Ch ec ke r”

on page 176.

176 ATmega162(V/U/L) 2513C–AVR–09/02

Parity Checker The Parity Checker is active when the high USART Parity Mode (UPM1) bit is set. Type

of parity check to b e performed (odd or even) is selected by the UPM0 bit. When

enabled, the Parity Checker calculates the parity of the data bits in incoming frames and

compares the result with the parity bit from the serial frame. The result of the check is

stored in the receive buffer together with the received data and stop bits. The Parity

Error (UPE) flag can then be read by software to check if the frame had a Parity Error.

The UPE bit is set if the next character that can be read from the receive buffer had a

parity error when received and the par ity checking was enabled at that point (UPM1 =

1). This bit is valid until the receive buffer (UDR) is read.

Disabling the Receiver In contra st to the Tran smitter, di sabling of the Re ceiver will be immediate . Data from

ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero)

the receiver will no longer override the normal function of the RxD port pin. The receiver

buffer FIFO will be flushed when the receiver is disabled. Remaining data in the buffer

will be lost

Flushing the Receive Buffer The rec eiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer

will be emptied of its contents. Unread data will be lo st. If the buffer has to be flushed

duri ng normal operati on, due to for insta nce an e rror cond ition, read the UD R I/O loca-

tion until the RXC flag is c leared. The following code example shows how to flus h the

receive buffer.

Note: 1. The example code assumes that the part specific header file is included.

Asynchronous Data

Reception The USART includes a clock recovery and a data recovery unit for handling asynchro-

nous data reception. The cloc k recovery lo gic is used for syn chronizin g the internally

generated baud rate clock to the incoming asynchronous serial frames at the RxD pin.

The data recovery logic samples and low pass filters each incoming bit, thereby improv-

ing the noise immunity of the receiver. The asynchronous reception operational range

depends on the accuracy of the in ternal baud rate clock, the rate of the incoming

frames, and the frame size in number of bits.

Asynchronous Clock

Recovery The cloc k recove ry logi c synchr onizes intern al clock to the incomi ng seri al frame s. Fig-

ure 79 illustrates the sampling process of the start bit of an incoming frame. The sample

rate is 16 tim es the baud rate for Nor mal mode, and 8 tim es the baud rate for Doubl e

Speed m ode. The horizon tal arrows illustrate the synchroni zation varia tion due to th e

sampl ing proce ss. Note th e larger time var iation whe n using th e double sp eed mode

Assembly Code Examp le(1)

USART_Flush:

sbis UCSRA, RXC

ret

in r16, UDR

rjmp USART_Flush

C Code Example(1)

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRA & (1<<RXC) ) dummy = UDR;

}

177

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(U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is

idle (i.e., no commu nication activi ty).

Figure 79. Start Bit Sampling

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD

line, the star t bit det ection sequence is initiated. Let samp le 1 deno te the firs t zero- s am-

ple as shown in the figure. The clock recovery logic then uses samples 8, 9 and 10 for

Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample

numbers inside b oxes on the figure ), to de cide if a valid s tart bi t is rece ived. If two or

more of these thr ee sam ples hav e logical high lev els (the major ity wins), the star t bit is

reje cted as a noise s pike and the rec eiver s tarts lo okin g for the nex t high to low- transi-

tion. If however, a valid start bit is detected, the clock recovery logic is synchronized and

the data recovery can begin. The synchronization process is repeated for each start bit.

Asynchronous Data Recovery Wh en the rece iver cloc k is sy nchronize d to the s tart bit, the data rec overy ca n begin.

The data recovery unit uses a state machine that has 16 states for each bit in Normal

mode and 8 states for each bit in Double Speed mode. Figure 80 shows the sampling of

the data bits and the parity bit. Each of the samples is given a number that is equal to

the state of the recovery unit.

Figure 80. Sampling of Data and Parity Bit

The decision of the logic level of the received bit is taken by doing a majority voting of

the logic value to the three samples in the center of the received bit. The center samples

are e mphas iz ed on the fig ure by havi ng t he s amp le nu mb er in side b oxe s. Th e ma jo rity

voting process is done as follows: If two or all three samples have high levels, the

received bit is regis tered to be a l ogic 1. If two or all th ree samp les h ave lo w leve ls, th e

received bit is registered to be a logic 0. This majority voting process acts as a low pass

filter for the incoming signal on the RxD pin. The recovery process is then repeated until

a complete frame is received. Including the first stop bit. Note that the receiver only uses

the first stop bit of a frame.

Figure 81 shows the sampling of the stop bit and the earliest possible beginning of the

start bit of the next frame.

12345678 9 10 11 12 13 14 15 16 12

STARTIDLE

BIT 0

1234 5 678120

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

12345678 9 10 11 12 13 14 15 16 1

BIT n

1234 5 6781

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

178 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 81. Stop Bit Sampling and Next Start Bit Sampling

The same majority voting is done to the stop bit as done for the other bits in the frame. If

the stop bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after

the last of the bits used for majority voting. For Normal Speed mode, the first low level

sample can be at point marked (A) in Figure 81. For Double Speed mode the first low

level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-

tion influences the operational range of the receiver.

Asynchronous Operational

Range The operational range of the receiver is dependent on the mismatch between the

receiv ed bit rate and th e inte rnally ge nerate d baud rate. If the Trans mitter is se nding

frames at too fast or too slow bit rates, or the internally generat ed baud rate of the

receiv er does not have a similar (see Tab le 71) base frequen cy, the rec eiver wil l not be

able to synchronize the frames to the start bit.

The following equations can be used to calculate the ratio of the incoming data rate and

internal receiver baud rate.

DSum of character size and parity size (D = 5 to 10 bit)

SSamples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

SFFirst sample number used for majority voting. SF = 8 for Normal Speed and

SF = 4 for Double Speed mode.

SMMiddle sample number used for majority voting. SM = 9 for Normal Speed and

SM = 5 for Double Speed mode.

Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to the

receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be

accepted in relation to the receiver baud rate.

Table 71 and Table 72 list the ma ximum receive r baud rat e error tha t can be tol erated.

Note that normal speed mode has higher toleration of baud rate variations.

12345678 9 10 0/1 0/1 0/1

STOP 1

1234 5 6 0/1

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

(A) (B) (C)

Rslow D1+()S

S1–DS⋅SF

-------------------------------------------= Rfast D2+()S

D1+()SS

-----------------------------------=

179

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The rec ommenda tions of the max imum rec eiver b aud rate error w as made under th e

assumption that the Receiver and Transmitter equally divides the maximum total error.

There are two pos sible s ources for the receiv ers baud r ate error. Th e receiv er’s syste m

clock ( XTAL) will alw ays h ave s ome mi nor ins tabil ity ov er the s upply vol tage rang e an d

the temp eratur e range. When using a c rys tal to gene r ate the sy st em c lock , thi s is r arely

a prob lem, bu t for a res onato r the sys tem clo ck may di ffer m ore than 2 % depe nding of

the resonators tolerance. The second source for the error is more controllable. The baud

rate generator can not always d o an exact division of the system frequency to get the

baud rate wanted. In this case an UBRR value that gives an acceptable low error can be

used if possibl e.

Multi-processor

Communication Mode Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil-

tering function of incoming frames received by the USART Receiver. Frames that do not

contain address infor mation will be ignored an d not put into the receive buffer. This

effecti vely re duces the numbe r of incomi ng fram es that ha s to be hand led by th e CPU,

in a system with multiple MCUs that communicate via the same serial bus. The Trans-

mitter is unaffected by the MPCM setting, but has to be used differently when it is a part

of a system utilizing the Multi-processor Communicat ion mode.

If the rec ei ver i s set up to re ce iv e fram es tha t co ntai n 5 to 8 data bits, t hen the f irst sto p

bit indicates if the frame contains data or address information. If the receiver is set up for

frames with nin e data bits , then the n inth b it (RXB 8) is used for id entify ing a ddress and

data fra mes. When the fra me type bit (the f irst stop or the ni nth bit) i s one, the frame

contains an address. When the frame type bit is zero the frame is a data frame.

Table 71. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2X = 0)

# (Data+Parity Bit) Rslow (%) Rfast (%) Max. Total Error (%) Recommended Max.

Receiver Error (%)

5 93.20 106.67 +6.67/-6.8% ± 3.0

6 94.12 105.79 +5.79/-5.88 ± 2.5

7 94.81 105.11 +5.11/-5.19 ± 2.0

8 95.36 104.58 +4.58/-4.54 ± 2.0

9 95.81 104.14 +4.14/-4.19 ± 1.5

10 96.17 103.78 +3.7 /-3.83 ± 1.5

Table 72. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2X = 1)

# (Data+Parity Bit) Rslow (%) Rfast (%) Max. Total Error (%) Recommended Max.

Receiver Error (%)

5 94.12 105.66 +5.66/-5.88 ± 2.5

6 94.92 104.92 +4.92/-5.08 ± 2.0

7 95.52 104.35 +4.35/-4.48 ± 1.5

8 96.00 103.90 +3.90/-4.00 ± 1.5

9 96.39 103.53 +3.53/-3.61 ± 1.5

10 96.70 103.23 +3.23/-3.30 ± 1.0

180 ATmega162(V/U/L) 2513C–AVR–09/02

The Mul ti-pr oc es sor Comm uni c atio n mo de e nab les s ever al s l ave MCUs to re ce iv e da ta

from a Master MCU. This is done by first decoding an address frame to find out which

MCU has been addressed. If a particular slave MCU has been addressed, it will receive

the following data frames as normal, while the other slave MCUs will ignore the received

frames until another address frame is received.

Using MPCM For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZ =

7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared when

a data frame (TXB = 0) is being transmitted. The slave MCUs must in this case be set to

use a 9-bit character frame format.

The following procedure should be used to exchange data in Multi-processor Communi-

cation mode:

1. All Slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA

is set).

2. The Master MCU sends an address frame, and all slaves receive and read this

frame. In the slave MCUs, the RXC flag in UCSRA will be set as normal.

3. Each Slave MCU reads the UDR Register and determines if it has been

selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next

address byte and keeps the MPCM setting.

4. The addressed MCU will receive all data frames until a new address frame is

received. The other Slave MCUs, which still have the MPCM bit set, will ignore

the data frames.

5. When the last data frame is received by the addressed MCU, the addressed

MCU sets the MPCM bit and waits for a new address frame from master. The

process then repeats from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since the

receiver mus t change between usi ng n and n+1 c haracter frame form ats. This makes

full-du ple x ope ra tio n d iffi c ult si nce the Tran sm itt e r an d Re ceiver us es th e s am e c ha ra c-

ter size setting. If 5 to 8 bit character frames are used, the Transmitter must be set to

use two stop bit (USBS = 1) since the first stop bit is used for indicating the frame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit.

The MPCM bi t sh ares the s am e I/O l oc ati on a s the T XC flag and thi s m ight ac ci de ntal ly

be cleared when using SBI or CBI instructions.

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Accessing UBRRH/

UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore

some special consideration must be taken when accessing this I/O location.

Write Access When doi ng a write ac cess of this I/O location, th e high bit of the value wr itten, the

USART Reg ister Se lect ( URSE L) bi t, co ntr ol s whic h one of the two regis ters that wi ll be

written. If URSEL is zero during a write operation, the UBRRH value will be updated. If

URSEL is one, the UCSRC setting will be updated.

The following code examples show how to access the two registers.

Note: 1. The example code assumes that the part specific header file is included.

As the cod e examp les illus trate, wri te acces ses of the tw o registe rs are rel atively unaf-

fected of the sharing of I/O location.

Assembly Code Examp les(1)

...

; Set UBRRH to 2

ldi r16,0x02

out UBRRH,r16

...

; Set the USBS and the UCSZ1 bit to one, and

; the remaining bits to zero.

ldi r16,(1<<URSEL)|(1<<USBS)|(1<<UCSZ1)

out UCSRC,r16

...

C Code Examples(1)

...

/* Set UBRRH to 2 */

UBRRH = 0x02;

...

/* Set the USBS and the UCSZ1 bit to one, and */

/* the remaining bits to zero. */

UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1);

...

182 ATmega162(V/U/L) 2513C–AVR–09/02

Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex opera-

tion. However, in most applications, it is rarely necessary to read any of these registers.

The read access is controlled by a timed sequence. Reading the I/O location once

returns the UBRRH Regis ter contents. If the register location was read in previ ous sys-

tem clock cycle, reading the register in the current clock cycle will return the UCSRC

content s. Note that the ti med seque nce for reading the UCSRC is an atomi c operation .

Interr upts m ust theref ore be c ontrol led (e.g. , by disa bling interrup ts glob ally) du ring the

read operation.

The following code example shows how to read the UCSRC Register contents.

Note: 1. The example code assumes that the part specific header file is included.

The assembly code example returns the UCSRC value in r16.

Reading the UBRRH contents is not an atomic operation and therefore it can be read as

an ordinary register, as long as the previous instruction did not access the register

location.

Assembly Code Examp le(1)

USART_ReadUCSRC:

; Read UCSRC

in r16,UBRRH

in r16,UCSRC

ret

C Code Example(1)

unsigned char USART_ReadUCSRC( void )

{

unsigned char ucsrc;

/* Read UCSRC */

ucsrc = UBRRH;

ucsrc = UCSRC;

return ucsrc;

}

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USART Register

Description

USART I/O Data Register –

UDR

The US ART Tran smit Da ta Buffer Registe r and US ART Rece ive Dat a Buffer Register s

share the same I/O address referred to as USART Data Register or UDR. The Transmit

Data Buffer Register (TXB) will be the destination for data written to the UDR Register

location. Reading the UDR Register location will return the contents of the Receive Data

Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter

and set to zero by the Receiver.

The transmit buffer can only be written when the UDRE flag in the UCSRA Register is

set. Data written to UDR when the UDRE flag is not set, will be ignored by the USART

Transmi tter. When data is wr itten t o the transm it buffe r, and the Transm it ter is enab led,

the Transmitter will load the data into the Transmit Shift Register when the Shift Register

is empty. Then the data will be serially transmitted on the TxD pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever

the receive buffer is accessed. Due to th is behavior of the receive buffer, do not use

read modify write instructions (SBI and CBI) on this location. Be careful when using bit

test instructions (SBIC and SBIS), since these also will change the state of the FIFO.

USART Control and Status

• Bit 7 – RXC: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the

receive bu ffer is empty (i.e. , does not co ntain any unread data ). If the receiver is dis-

abled, the receive buffer will be flushed and consequently the RXC bit will become zero.

The RXC flag can be used to generate a Receive Complete interrupt (see description of

the RXCIE bit).

• Bit 6 – TXC: USART Transmit Complete

This flag bit is set when the entire fr ame in the Trans mit Shi ft Regist er has been sh ifted

out and th ere are no new data curren tly prese nt in the transmi t buffer (UDR). The TX C

flag bit is automatically cleared when a transmit complete interrupt is executed, or it can

be cl eared by w riting a o ne to its bit locat ion. Th e TXC flag can gene rate a Tra nsmit

Complete interrupt (see description of the TXCIE bit).

• Bit 5 – UDRE: USART Data Register Empty

The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. If

UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE flag can

generate a Data Register Empty interrupt (see description of the UDRIE bit).

Bit 76543210

RXB[7:0] UDR (Read)

TXB[7:0] UDR (Write)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

RXC TXC UDRE FE DOR UPE U2X MPCM UCSRA

Read/Write R R/W R R R R R/W R/W

Initial Value 0 0 1 0 0 0 0 0

184 ATmega162(V/U/L) 2513C–AVR–09/02

UDRE is set after a Reset to indicate that the transmitter is ready.

• Bit 4 – FE: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when

received. I.e., when the first stop bit of the next character in the receive buffer is zero.

This bi t is val id unti l the rece ive bu ffer (UD R) is re ad. The FE bit i s zero when the sto p

bit of received data is one. Always set this bit to zero when writing to UCSRA.

• Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun condition is detected. A data overrun occurs when the

receive buffer is full (two characters), it is a new character waiting in the reCeive Shift

read. Always set this bit to zero when writing to UCSRA.

• Bit 2 – UPE: Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received

and the Pa rity Checkin g was e nabled at that p oint ( UPM1 = 1). Thi s bit is valid u ntil th e

receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

• Bit 1 – U2X: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using

synchronous operation.

Writi ng this bit to one will reduce the divi sor of th e baud rate divider from 16 to 8 effec-

tively doubling the transfer rate for asynchronous communication.

• Bit 0 – MPCM: Multi-processor Communication Mode

This bit en ables the Multi- pro cessor Com munic ation m ode. Wh en the M PCM bit is wr it-

ten to one, all th e inc oming frames rece ived by the USA RT rec eiver that do n ot con tain

addres s in formation wi ll b e ign or ed. Th e tran smitter is un affe cted by th e M PC M s etting.

For more detailed information see “Multi-processor Communication Mode” on page 179.

USART Control and Status

• Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete

interru pt will be gene rated only if th e RXCIE bit is writte n to one, the Globa l Interrupt

Flag in SREG is written to one and the RXC bit in UCSRA is set.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete

interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt

Flag in SREG is written to one and the TXC bit in UCSRA is set.

Bit 76543210

RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 UCSRB

Read/Write R/W R/W R/W R/W R/W R/W R R/W

Initial Value 0 0 0 0 0 0 0 0

185

ATmega162(V/U/L)

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• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable

Writing thi s bit to one enable s interrupt on the UDRE fla g. A Data Re giste r Empty inte r-

rupt will be ge nerat ed o nly i f the UDRI E bit i s writte n to one , the Glob al Inte rrup t Flag i n

SREG is written to one and the UDRE bit in UCSRA is set.

• Bit 4 – RXEN: Receiver Enable

Writing th is bit to one enables the USART Receiver. The Receiver will override normal

port operation for the RxD pin when enabled. Disabling the Receiver will flush the

receive buffer invalidating the FE, DOR and UPE Flags.

• Bit 3 – TXEN: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override nor-

mal port operation for the TxD pin when enabled. The disabling of the Transmitter

(writing TXEN to zero) will not become effective until ongoing and pending transmis-

sions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register

do not contain data to be transmitted. When disabled, the Transmitter will no longer

override the TxD port.

• Bit 2 – UCSZ2: Character Size

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits

(character size) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8: Receive Data Bit 8

RXB8 is the ninth data bit of the received character when operating with serial frames

with nine data bits. Must be read before reading the low bits from UDR.

• Bit 0 – TXB8: Transmit Data Bit 8

TXB8 is the 9th data bit in the character to be transmitted when operating with serial

frames with 9 data bits. Must be written before writing the low bits to UDR.

186 ATmega162(V/U/L) 2513C–AVR–09/02

USART Control and Status

Note: 1. The UCSRC Register shares the same I/O location as the UBRRH Register. See the

“Accessing UBRRH/ UCSRC Registers” on page 181 section which describes how to

access this register.

• Bit 7 – URSEL: Register Select

This bit selects between acces sing the UCSRC or the UBRRH Re gister. It is read as

one when reading UCSRC. The URSEL must be one when writing the UCSRC.

• Bit 6 – UMSEL: USART Mode Select

This bit selects between asynchronous and synchronous mode of operation.

• Bit 5:4 – UPM1:0: Parity Mode

These bits ena ble an d set type o f par ity gene ratio n and c heck. I f en abled, the tran smit-

ter will automatically generate and send the parity of the transmitted data bits within

each frame. The receiver will generate a parity value for the incoming data and compare

it to the UPM0 setting. If a mismatch is detected, the UPE flag in UCSRA will be set.

• Bit 3 – USBS: Stop Bit Select

This bit sel ects the number of stop bits to be inserted by the transmitter. The rece iver

ignores this setting.

Bit 76543210

URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 0 0 0 0 1 1 0

Table 73. UMSEL Bit Settings

UMSEL Mode

0 Asynchronous Operation

1 Synchronous Operation

Table 74. UPM Bits Settings

UPM1 UPM0 Parity Mode

0 0 Disabled

01Reserved

1 0 Enabled, Even Parity

1 1 Enabled, Odd Parity

Table 75. USBS Bit Settings

USBS Stop Bit(s)

01-bit

12-bit

187

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• Bit 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits com bined with th e UCSZ2 bit in UCSRB se ts the numb er of data bits

(Character Size) in a frame the receiver and transmitter use.

• Bit 0 – UCPOL: Clock Polarity

This bit i s used for sy nchronous mode onl y. Write this bi t to zero when asy nchronous

mode i s used. The UCPOL bi t sets t he rel ationshi p betwe en data output change and

data input sample, and the synchronous clock (XCK).

USART Baud Rate Registers –

UBRRL and UBRRH(1)

Note: 1. The UBRRH Register shares the same I/O location as the UCSRC Register. See the

“Accessing UBRRH/ UCSRC Registers” on page 181 section which describes how to

access this register.

• Bit 15 – URSEL: Register Select

This bit sel ects between acces sing the UBRRH or the UCS RC Register. It is read as

zero when reading UBRRH. The URSEL must be zero when writing the UBRRH.

• Bit 14:12 – Reserved Bits

These bits are reser ved for future use. For comp atibility with future devices, thes e bit

must be written to zero when UBRRH is written.

Table 76. UCSZ Bits Settings

UCSZ2 UCSZ1 UCSZ0 Character Size

0005-bit

0016-bit

0107-bit

0118-bit

100Reserved

101Reserved

110Reserved

1119-bit

Table 77. UCPOL Bit Settings

UCPOL Transmitted Data Changed

(Output of TxD Pin) Received Data Sampled

(Input on RxD Pin)

0 Rising XCK Edge Falling XCK Edge

1 Falling XCK Edge Rising XCK Edge

Bit 151413121110 9 8

URSEL – – – UBRR[11:8] UBRRH

UBRR[7:0] UBRRL

76543210

Read/Write R/W R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

00000000

188 ATmega162(V/U/L) 2513C–AVR–09/02

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit reg ister whi ch c onta ins th e US ART baud ra te. The UBRRH c onta ins th e

four most significant bits, and the UBRRL contains the eight least significant bits of the

USART baud ra te. Ongoing tr ansmissions by the trans mitter and receiver will be co r-

rupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of

the baud rate prescaler.

Examples of Baud Rate

Setting For standard crystal and resonator frequencies, the most commonly used baud rates for

asynchronous operation can be generated by using the UBRR settings in Table 78.

UBRR values which yield an actual baud r ate differing le ss than 0.5% f rom the target

baud rate, are bold in the table. Higher error ratings are acceptable, but the receiver will

have le ss noise resis tance when the err or ratings are high, esp ecially for large seri al

frames (see “Asynchronous Operational Range” on page 178). The error values are cal-

culated using the following equation:

Error[%] BaudRateClosest Match

BaudRate

--------------------------------------------------------1–





100%•=

Table 78. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

Baud

Rate

(bps)

fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2%

4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2%

9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%

14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1%

19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2%

28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5%

38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0%

57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5%

76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5%

115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5%

230.4k––––––00.0%––––

250k––––––––––00.0%

Max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps

1. UBRR = 0, Error = 0.0%

189

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Table 79. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%

4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%

9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0%

14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%

19.2k 110.0%230.0%120.2%250.2%230.0%470.0%

28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%

38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%

57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0%

76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0%

115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0%

230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0%

250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8%

0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8%

1M ––––––––––0-7.8%

Max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 Mbps 460.8 kbps 921.6 kbps

1. UBRR = 0, Error = 0.0%

190 ATmega162(V/U/L) 2513C–AVR–09/02

Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 8.0000 MHz fosc = 11.0592 MHz fosc = 14.7456 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%

4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%

9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%

14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%

19.2k 250.2%510.2%350.0%710.0%470.0%950.0%

28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%

38.4k 120.2%250.2%170.0%350.0%230.0%470.0%

57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%

76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0%

115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0%

230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0%

250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%

0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8%

1M – – 0 0.0% – – – – 0 -7.8% 1 -7.8%

Max. (1) 0.5 Mbps 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kbps 1.8432 Mbps

1. UBRR = 0, Error = 0.0%

191

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Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%

4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%

9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%

14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%

19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%

28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%

38.4k 250.2%510.2%290.0%590.0%32-1.4%640.2%

57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%

76.8k 120.2%250.2%140.0%290.0%151.7%32-1.4%

115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4%

230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4%

250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0%

0.5M10.0%30.0%––4-7.8%––40.0%

1M 00.0%10.0%––––––––

Max. (1) 1 Mbps 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps

1. UBRR = 0, Error = 0.0%

192 ATmega162(V/U/L) 2513C–AVR–09/02

Analog Comparator The Analog Co mparator compar es the input values on the positive pin AIN0 an d nega-

tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on

the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s

output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the

comparator can trigger a separate interrupt, exclusive to the Anal og Comparator. The

user ca n se lec t Inte rru pt tr igg erin g on c omp ar ator output rise, fa ll or toggl e. A bl oc k dia-

gram of the comparator and its surrounding logic is shown in Figure 82.

Figure 82. Analog Comp arator Block Diagra m (1)

Note: 1. Refer to Figure 1 on page 2 and Table 32 on page 70 for Analog Comparator pin

placement.

Analog Comparator Control

and Status Register – ACSR

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off.

This bit can be set at any time to turn off the Analog Comparator. This will reduce power

consumption in Active and Idle mode. When changing the ACD bit, the Analog Compar-

ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt

can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set , a fixed bandg ap re ferenc e vo lta ge re pla ce s the posi tiv e inp ut to the

Analog Comparator . Wh en this b it is c lea red, AIN0 is a pplied to the po si tiv e inp ut o f th e

Analog Comparator. See “Internal Voltage Reference” on page 50.

• Bit 5 – ACO: Analog Comparator Output

The o utput o f the A nalog Co mparato r is sy nchroniz ed and then d irectly c onnected to

ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit i s set by hardwar e when a compar ator output event trigge rs the in terrupt mod e

defined by ACIS1 and A CIS0. The A nalog Comparato r interrupt rout ine is ex ecuted if

ACBG

BANDGAP

REFERENCE

Bit 76543210

ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 N/A 0 0 0 0 0

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the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when execut-

ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a

logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana-

log Comparator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When writt en logic one, thi s bit enables the Input Captu re functio n in Timer/ Counter1 to

be triggered by the Analog Comparator. The comparator output is in this case directly

connec ted to the Inpu t Capture fron t-end lo gic, mak ing the compa rator util ize the noi se

canceler and edg e selec t features of the T imer/Co unter1 Inp ut Ca pture int errupt. W hen

written logic zero, no connection between the Analog Comparator and the Input Capture

function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-

rupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator inter-

rupt. The different settings are shown in Table 82.

When cha nging the ACIS1/A CIS0 bits, the Ana log Comparator Interrupt mus t be dis-

abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt

can occur when the bits are changed.

Table 82. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle.

01Reserved

1 0 Comparator Interrupt on Falling Output Edge.

1 1 Comparator Interrupt on Rising Output Edge.

194 ATmega162(V/U/L) 2513C–AVR–09/02

JTAG Interface and

On-chip Debug

System

Features •JTAG (IEEE std. 1149.1 Compliant) Interface

•Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard

•Debugger Access to:

– All Internal Peripheral Units

– Internal and External RAM

– The Internal Register File

– Program Counter

– EEPROM and Flash Memories

•Extensive On-chip Debug Support for Break Conditions, Including

– AVR Break Instruction

– Break on Change of Program Memory Flow

– Single Step Break

– Program Memory Breakpoints on Single Address or Address Range

– Data Memory Breakpoints on Single Address or Address Range

•Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•On-chip Debugging Supported by AVR Studio®

Overview The AVR IEEE std. 1149.1 compliant JTAG interface can be used for

• Testing PCBs by using the JTAG Boundary-scan capability.

• Programming the non-volatile memories, Fuses and Lock bits.

• On-chip debugging.

A brief description is given in the following sections. Detailed descriptions for Program-

ming via the J TAG interface, and using the Boundary-scan Chain c an be found in the

sectio ns “Program ming via the JTAG Interf ace” on page 247 and “IEE E 1149.1 (JT AG)

Boundary-scan” on page 201, respectivel y. The On-chip Debug support is considered

being private JTAG inst ructions, and distributed within ATM EL and to selected third

party vendors only.

Figure 83 shows a block diagram of the JTAG interface and the On-chip Debug system.

The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP

Controll er selec ts either the JTAG Ins tructi on Regis ter or one of se vera l Data Registe rs

as the scan chain (Shift Register) between the TDI – input and TDO – output. The

Instruction Register holds JTAG instructions controlling the behavior of a Data Register.

The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers

used for board- level testin g. The JTAG Progra mming Interfac e (actu ally consistin g of

several physical and virtual Data Registers) is used for serial programming via the JTAG

interfac e. The Internal Scan Chain and Break Poin t Scan Chai n are used for On-chi p

debugging only.

Test Access Port – TAP The JTAG interface is access ed through four of the AVR’s pins. In JTAG terminology,

these pins constitute the Test Access Port – TAP. These pins are:

• TMS: Test mode select. This pin is used for navigating through the TAP-controller

state machine.

• TCK: Test Clock. JTAG operation is synchronous to TCK.

• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data

• TDO: Test Data Out. Serial output data from Instruction register or Data Register.

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ATmega162(V/U/L)

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The IEE E std. 1149.1 also speci fies an optio nal TAP sig nal; TRST – Test ReSeT –

which is not provided.

When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins,

and the TAP controller is in reset. When programmed, the input TAP signals are inter-

nally pulled hig h and the JTAG is enabled fo r Boundar y-scan an d programm ing. The

device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is

monitored by the debugger to be able to detect External Reset sources. The debugger

can al so pu ll th e RES ET pi n lo w to r ese t th e w hol e sy stem, assumi ng on ly open c ol le c-

tors on the reset line are used in the application.

Figure 83. Block Diagram

TAP

CONTROLLER

TDI

TDO

TCK

TMS

FLASH

MEMORY

AVR CPU

DIGITAL

PERIPHERAL

UNITS

JTAG / AVR CORE

COMMUNICATION

INTERFACE

BREAKPOINT

UNIT FLOW CONTROL

UNIT

OCD STATUS

AND CONTROL

INTERNAL

SCAN

CHAIN

INSTRUCTION

BYPASS

JTAG PROGRAMMING

INTERFACE

Instruction

Address

Data

BREAKPOINT

SCAN CHAIN

ADDRESS

DECODER

ANALOG

PERIPHERIAL

UNITS

I/O PORT 0

I/O PORT n

BOUNDARY SCAN CHAIN

Analog inputs

Control & Clock lines

DEVICE BOUNDARY

196 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 84. TAP Controller State Diagram

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

011 1

197

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TAP Controller The TAP controller is a 16-state finite state machine that contr ols the operation of the

Boundary- scan circui try, JTAG progr amming circ uitry, or O n-chip Debug s ystem. The

state transitions depicted in Figure 84 depend on the signal present on TMS (shown

adjacent to each state transition) at the time of the rising edge at TCK. The initial state

after a Power-on Reset is Test-Logic-Reset.

As a definition in this document, the LSB is shifted in and out first for all Shift Registers.

Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG inter-

face is:

• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter

the Shift Instruction Register – Shift-IR state. While in this state, shift the four bits of

the JTAG instructions into the JTAG instruction register from the TDI input at the

rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in

order to remain in the Shift-IR state. The MSB of the instruction is shifted in when

this state is left by setting TMS high. While the instruction is shifted in from the TDI

pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction

selects a particular Data Register as path between TDI and TDO and controls the

circuitry surrounding the selected Data Register.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction

is latched onto the parallel output from the Shift Register path in the Update-IR

state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the

state machine.

• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the

Shift Data Register – Shift-DR state. While in this state, upload the selected data

from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state,

the TMS input must be held low during input of all bits except the MSB. The MSB of

the data is shifted in when this state is left by setting TMS high. While the Data

captured in the Capture-DR state is shifted out on the TDO pin.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected

data register has a latched parallel-output, the latching takes place in the Update-

DR sta te. The Exit -DR, Pause- DR, a nd Exit 2-DR states are on ly us ed for n aviga ting

the state machine.

As sh own in the state di agram, the Run-Test/Id le state need n ot be ent ered be tween

select ing JTAG ins tructi on and using Data Regi sters, and some JTAG in structions may

select c er tai n fun ction s to be per for me d in the Run -Te st/Idle, maki ng it uns uit abl e as an

Idle state.

Note: Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can

always be entered by holding TMS high for five TCK clock periods.

For de tailed info rmatio n on the JTAG speci fication, refer to th e literatur e listed i n “Bibl i-

ography” on page 200.

Using the Boundary-

scan Chain A compl ete des cri pti on of th e B oun dary -sc an cap abi li ti es are g iv en i n t he s ect ion “IE EE

1149.1 (JTAG) Boundary-scan” on page 201.

198 ATmega162(V/U/L) 2513C–AVR–09/02

Using the On-chip Debug

system As shown in Figure 83, the hardware support for On-chip Debugging consists mainly of

• A scan chain on the interface between the internal AVR CPU and the internal

peripheral units

• Break Point unit

• Communication interface between the CPU and JTAG system

All read or modify/wr ite operati ons need ed for implem enting the Deb ugger ar e done by

applying AVR instr uctions via the internal AV R CPU Scan Chain. The CPU s ends the

result to an I/O memory mapped location which is part of the communication interface

between the CPU and the JTAG system.

The Break Po in t un it im pl eme nts B rea k on Ch ange of p ro gram fl ow, Si ngl e Ste p B r eak,

two Program memory Break Points, and two Combined Break Points. Together, the four

Break Points can be configured as either:

• 4 single Program Memory Break Points

• 3 Single Program Memory Break Point + 1 single Data Memory Break Point

• 2 single Program Memory Break Points + 2 single Data Memory Break Points

• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask

(“range Break Point”)

• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask

(“range Break Point”)

A debugger, like the AVR Studio®, may however use one or more of these resources for

its internal purpose, leaving less flexibility to the end-user.

A list of the On-chip Debug specific JTAG instructions is given in “On-chip debug spe-

cific JTAG instructions” on page 199.

The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addi-

tion, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-

chip debug system to work. As a security feature, the On-chip debug system is disabled

when ei ther o f the LB1 or LB2 Loc k bits are set. Othe rwis e, the On- chip de bug sys tem

would have provided a backdoor into a secured device.

The AVR St udio enables the user to fully control execution of progr ams on an AVR

device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR

Instruc tio n Set Simu la tor . AVR Studi o supports source level execution of Assembl y pr o-

grams assembled with Atmel Corporation’s AVR Assembler and C programs compiled

with third party vendors’ compilers.

AVR Studio runs under Microsoft® Windows® 95/98/2000 and Microsoft Windows NT®.

For a full description of the AVR Studi o, please refer to the AVR Studio User Guide.

Only highlights are presented in this document.

All necess ary execution comma nds are available in AV R Studio, both on sour ce level

and on disassembly lev el. The user can execute the program, single step through the

code ei ther by tr acing into or steppi ng over fu nctions, step out of functi ons, pl ace the

cursor on a statement and execute until the statement is reached, stop the execution,

and reset the exec ution target. In addition, the us er can have an unlimited number of

code Break Points (using the BREAK instruction) and up to two data memory Break

Points, alternatively combined as a mask (range) Break Point.

199

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On-chip debug specific

JTAG instru ctions The On-chip debug support is considered being private JTAG instructions, and distrib-

uted with in ATMEL and to selected 3rd party vendors o nly. Instruction o pcodes are

listed for reference.

PRIVATE0; 0x8 Private JTAG instruction for accessing On-chip debug system.

PRIVATE1; 0x9 Private JTAG instruction for accessing On-chip debug system.

PRIVATE2; 0xA Private JTAG instruction for accessing On-chip debug system.

PRIVATE3; 0xB Private JTAG instruction for accessing On-chip debug system.

On-chip Debug Related

On-chip Debug Register –

OCDR

The OCDR Register provides a communication channel from the running program in the

microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing

to this location. At the same tim e, an internal fl ag; I/O Debug Regis ter Dirty – IDRD – is

set to i ndicate to the debug ger that th e regist er has been written. When the CP U re ads

the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the

IDRD bit. The debugger clears the IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In this case,

the OCDR Registe r can only be acces sed if the OC DEN Fuse is programm ed, and th e

debugg er enable s access to th e OCDR Registe r. In all other cases, th e standard I/O

location is accessed.

Refer to the debugger documentation for further information on how to use this register.

Using the JTAG

Programming

Capabilities

Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS,

TDI and TDO. These are the only pins that need to be controlled/observed to perform

JTAG programming (in addition to power pins). It is not required to apply 12V externally.

The JTA GEN Fuse m ust be program med and the JTD b it in th e MCUSR Re giste r must

be cleared to enable the JTAG Test Access Port.

The JTAG pr ogram mi ng cap abi li ty su ppo rts :

• Flash programming and verifying.

• EEPROM programming and verifying.

• Fuse progra mmi ng and ve rify ing .

• Lock bit programming and verifying.

The Lock bit secur ity is ex act ly as i n para llel progr am mi ng mo de. If the Loc k bits LB 1 or

LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a

chip erase. This is a security feature that ensures no backdoor exists for reading out the

content of a secured device.

The details on programming through the JTAG interface and programming specific

JTAG instructions are given in the section “Programming via the JTAG Interface” on

page 247.

Bit 7 6543210

MSB/IDRD LSB OCDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0 0000000

200 ATmega162(V/U/L) 2513C–AVR–09/02

Bibliography For more information about general Boundary-scan, the following literature can be

consulted:

• IEE E: IEEE Std 1149.1-19 90. IEE E Sta nda rd Test Ac ce ss Por t and Boun dary -sc an

Architecture, IEEE, 1993

• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-

Wesley, 1992

201

ATmega162(V/U/L)

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IEEE 1149.1 (JTAG)

Boundary-scan

Features •JTAG (IEEE std. 1149.1 Compliant) Interface

•Boundary-scan Capabilities According to the JTAG Standard

•Full Scan of all Port Functions as well as Analog Circuitry Having Off-chip Connections

•Supports the Optional IDCODE Instruction

•Additional Public AVR_RESET Instruction to Reset the AVR

System Overview T he Bo und ar y- sca n c ha in ha s the c apab il ity of driving a nd obs er ving the logic l eve ls o n

the digi tal I/ O pins , as wel l as the b oundary betwee n dig ital and an alog log ic fo r analo g

circuitry having Off-chip connections. At system level, all ICs having JTAG capabilities

are connected serially by the TDI/TDO signals to form a long Shift Register. An external

controlle r se ts up t he dev ices to drive v alues at the ir output pins , and ob serve t he inp ut

values rece ived from other devices . The co ntrol ler comp ares the r eceiv ed data wi th the

expecte d result . In this way, Bo undary- scan provid es a m echan ism fo r testin g inter con-

nections and integrity of components on Printed Circuits Boards by using th e four TAP

signals only.

The four IEEE 1149.1 de fined mandatory JTAG instructions IDCODE, BYPASS, SAM-

PLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction

AVR_RESET can be used for testing the Printed Circuit Boa rd. Initial scanning of the

Data Register path will show the ID-code of the device, since IDCODE is the default

JTAG instruction. It may be de sirable to have the AVR device in Reset during Test

mode. If not Reset, inputs to the device may be determined by the scan operations, and

the inte rnal software may be in an undetermined state when exiting the test mode.

Entering Reset, the outputs of any Port Pin will instantly enter the high impedance state,

making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be

issued to make the shortest po ssi ble sc an chain thr ough the device . The devi ce can be

set in the Reset state either by pulling the external RESET pin low, or issuing the

AVR_RESET instruction with appropriate setting of the Reset Data Register.

The EXTES T instruc tion is used for sampl ing exter nal pins and loa ding outp ut pins wi th

data. The data from the output latch will be driven out on the pins as soon as the

EXTEST i ns truc tio n i s lo ade d i nto the J TAG I R -R egister. The re fore, the S AMP LE /P RE-

LOAD should also be used for setting initial values to the scan ring, to avoid damaging

the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD

can also be used for taking a snapshot of the external pins during normal operation of

the part.

The JTAGE N Fuse m ust b e prog rammed and t he JTD bit in the I/O Regi ster MCUCS R

must be cleared to enable the JTAG Test Access Port.

When usi ng the J TAG i nterfa ce for Bou nda ry-scan , usin g a JT AG TCK cloc k frequen cy

higher than the internal chip frequency is possible. The chip clock is not required to run.

202 ATmega162(V/U/L) 2513C–AVR–09/02

Data Regist ers The data registers relevant for Boundary-scan operations are:

• Bypass Register

• Device Identification Register

• Reset Register

• Boundary-scan Chain

Bypass Register The Bypass Regi s ter c ons ists of a s ing le Shi ft R egi ste r sta ge. Wh en th e B yp as s R egi s-

ter is selected as path between TDI and TDO, the register is reset to 0 when leaving the

Capture- DR controller s tate. The Bypa ss Register can be u sed to shorten the s can

chain on a system when the other devices are to be tested.

Device Identi ficat ion Regist er Figure 85 shows the structure of the Device Identification Register.

Figure 85. The Format of the Device Identification Register

Version Version is a 4-bit number identifying the revision of the component. The relevant version

number is shown in Table 83.

Part Number The part number is a 16-bit code identifying the component. The JTAG Part Number for

ATmega162 is listed in Table 84.

Man uf actu rer ID The Man ufacture r ID is a 11-bit code identifyin g the manufactur er. The JTAG manufac-

turer ID for ATMEL is listed in Table 85.

Reset Register The Reset Register is a test data register used to reset the part. Since the AVR tri-states

Port Pins when reset, the Reset Register can also replace the function of the unimple-

mented optional JTAG instruction HIGHZ.

A high value in the Reset Register corresponds to pulling the external Reset low. The

part is reset as long as there is a high value pr esent in the Reset Register. Depending

on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out

Period (refer to “Clock Sources” on page 34) after releasing the Reset Register. The

MSB LSB

Bit 3128271211 1 0

Device ID Version Part Number Manufacturer ID 1

4 bits 16 bits 11 bits 1 bit

Table 83. JTAG Vers io n Numbers

Version JTAG Version number (Hex)

ATmega162 revision A 0x0

ATmega162 revision B 0x1

Table 84. AVR JTAG Part Numbe r

Part number JTAG Part Number (Hex)

ATmega162 0x9404

Table 85. Manufacturer ID

Manufacturer JTAG Man. ID (H ex)

ATMEL 0x01F

203

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2513C–AVR–09/02

output fro m this d ata regis ter is no t lat ched, so th e reset wi ll tak e place immed iately , as

shown in Figure 86.

Figure 86. Reset Register

Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on

the digi tal I/ O pins , as wel l as the b oundary betwee n dig ital and an alog log ic fo r analo g

circuitry having Off-chip connections.

See “Boundary-scan Chain” on page 205 for a complete description.

Boundary-scan Specific

JTAG Instru ctions The Instru ction Re giste r is 4-bit wi de, supp orting up to 16 inst ruction s. Lis ted belo w are

the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ

instru cti on i s not i mp lem ented, but a ll outp uts with tri-s tate ca pab il ity c an b e se t in hi gh-

impedant state by us ing the AVR_RESET ins truction, since the initia l state for all por t

pins is tri-state.

As a definition in this data sheet, the LSB is shifted in and out first for all Shift Registers.

The OP CODE fo r each in struc tion is shown behind th e instru ctio n name in hex for mat.

The text describes which Data Register is selected as path between TDI and TDO for

each instruc ti on.

EXTEST; 0x0 Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for

testing circuitry external to the AVR package. Fo r port-pins, Pull-up Disable, Output

Control, Output Data, and Input Data are all accessible in the scan chain. For analog cir-

cuits h av ing Off- ch ip co nnec ti ons, the inte rface bet ween the analo g an d th e di gi tal lo gic

is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is

driven out as soon as the JTAG IR-Register is loaded with the EXTEST instruction.

The active stat es ar e:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Internal Scan Chain is shifted by the TCK input.

• Update-DR: Data from the scan chain is applied to output pins.

From

TDI

ClockDR · AVR_RESET

TDO

From Other Internal and

External Reset Sources

Internal Reset

204 ATmega162(V/U/L) 2513C–AVR–09/02

IDCODE; 0x1 Optional JTAG instruction selecting the 32-bit ID-register as data register. The ID-Regis-

ter consists of a version number, a device number and the manufacturer code chosen

by JEDEC. This is the default instruction after Power-up.

The active stat es ar e:

• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan

Chain.

• Shift-DR: The IDCODE scan chain is shifted by the TCK input.

SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for preloading the output latches and taking a snapshot of

the input/output pins without affecting the system operation. However, the output latches

are not connected to the pins. The Boundary-scan Chain is selected as Data Register.

The active stat es ar e:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

• Update-DR: Data from the Boundary-scan chain is applied to the output latches.

However, the output latches are not connected to the pins.

AVR_RESET; 0xC The A VR specific public JTAG instruction for forcing the AVR d evice into the Reset

mode or releasing the JTAG Reset source. The TAP controller is not reset by this

instruction. The one bit Reset Register is selected as data register. Note that the r eset

will be active as long as ther e is a logic 'one' in the Reset Chain. The output from this

chain is not latched.

The active stat es ar e:

• Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; 0xF Mandatory JTAG instruction selecting the Bypass Register for data register.

The active stat es ar e:

• Capture-DR: Loads a logic “0” into the Bypass Register.

• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan Related

MCU Control and Status

and provides information on which reset source caused an MCU Reset.

• Bit 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.

If this b it is on e, t he J T AG int e rfac e i s disab le d. In order to a vo id uni nte nti ona l d isabl in g

or enabling of the JTAG interface, a timed sequence must be followed when changing

this bit: The application software must write this bit to the desired value twice within four

cycles to change its value.

Bit 76543210

JTD –SM2 JTRF WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R/W R R/W R/W R/W R/W R/ gnW

Initial Value 0 0 0 See Bit Description

205

ATmega162(V/U/L)

2513C–AVR–09/02

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused b y a logic one in th e JTAG Reset Register

selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or

by writing a logic zero to the flag.

Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on

the digi tal I/ O pins , as wel l as the b oundary betwee n dig ital and an alog log ic fo r analo g

circuitry having Off-chip connection.

Scanning the Digital Port Pins Figure 87 shows the Boundary-scan Cell for a bi-directional port pin with pull-up func-

tion. Th e c ell c ons is ts of a sta nda rd Bo und ar y-s ca n c ell for th e Pull-up E nab le – PUE x n

– function , and a bi-dir ectiona l pin ce ll that c ombine s the thr ee signals Outpu t Control –

OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.

The port and pin indexes are not used in the following description

The Boundary- scan logic is not i ncluded in the figures in the Data Sheet. Fi gure 88

shows a simple digi tal Port Pi n as descr ibed in the section “I/O -Ports ” on page 61. T he

Boundary-scan details from Figure 87 replaces the dashed box in Figure 88.

When no alternate port function is present, the Input Data – ID – corresponds to the

PINxn Register value (but ID has no synchronizer), Output Data corresponds to the

PORT Register, Output Control corresponds to the Data Direction – DD Register, and

the Pull-up Enabl e – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 88 to

make the scan chain read the actual pin value. For Analog function, there is a direct

connection from the external pin to the analog c ircuit, and a scan ch ain is inserted on

the interface between the digital logic and the analog circuitry.

206 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 87. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.

DQ DQ

1DQ DQ

Port Pin (PXn)

VccEXTESTTo Next CellShiftDR

Output Control (OC)

Pullup Enable (PUE)

Output Data (OD)

Input Data (ID)

From Last Cell UpdateDRClockDR

FF2 LD2

FF1 LD1

LD0FF0

207

ATmega162(V/U/L)

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Figure 88. General Port Pin Schematic Diagram

Scanning the RESET pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V active

high logic for high voltage parallel programming. An observe-only cell as shown in Fig-

ure 89 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.

Figure 89. Observe-only Cell

CLK

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

CLK : I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BUS

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

See Boundary-Scan Description

for Details!

PUExn

OCxn

ODxn

IDxn

PUExn: PULLUP ENABLE for pin Pxn

OCxn: OUTPUT CONTROL for pin Pxn

ODxn: OUTPUT DATA to pin Pxn

IDxn: INPUT DATA from pin Pxn

1DQ

From

Cell

ClockDR

ShiftDR

Cell

From System Pin To System Logic

FF1

208 ATmega162(V/U/L) 2513C–AVR–09/02

Scanning the Clock Pins T he AV R devi ces have m any clo ck op tions sele ctable by fu ses. T hese ar e: Inte rnal RC

Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low Frequency Crystal

Oscillator, and Ceramic Resonator.

Figu re 90 show s how each Oscill ator wi th exte rnal conn ectio n is sup ported in the scan

chain. Th e Enable s ignal is sup ported with a general Bou ndary-scan ce ll, while th e

Oscilla tor/clo ck ou tput is attac hed to a n obse rve-on ly c ell. I n addit ion to the mai n clock ,

the Timer Oscillator is scanned in the same way. The output from the internal RC Oscil-

lator is not scanned, as this Oscillator does not have external connections.

Figure 90. Boundary-scan Cells for Oscillators and Clock Options

Table 86 summaries the scan registers for the external clock pin XTAL1, oscillators with

XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.

Notes: 1. Do not enable more than one clock source as main clock at a time.

2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift

between the Internal Oscillator oscillatorand the JTAG TCK clock. If possible, scan-

ning an external clock is preferred.

3. The clock configuration is programmed by fuses. As a fuse is not changed run-time,

the clock configuration is considered fixed for a given application. The user is advised

to scan the same clock option as to be used in the final system. The enable signals

are supported in the scan chain because the system logic can disable clock options

in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not

provided. The INTCAP selection is not supported in the scan-chain, so the boundary

scan cha in can not make a XTAL Oscilla tor re qui rin g in tern al c ap ac itors to run unless

the fuses are correctly prog rammed.

Table 86. Scan Signals for the Oscillator(1)(2)(3)

Enable Signal Scanned Clock Line Clock Option

Scanned Clock

Line when Not

Used

EXTCLKEN EXTCLK (XTAL1) External Clock 0

OSCON OSCCK External Crystal

External Ceramic Resonator 0

OSC32EN OSC32CK Low Freq. External Crystal 0

TOSKO N TOSCK 32 kHz Timer Osc ill ator 0

1DQ

From

Cell

ClockDR

ShiftDR

Cell

To System Logic

FF1

1DQ DQ

From

Cell

ClockDR UpdateDR

ShiftDR

Cell EXTEST

From Digital Logic

XTAL1/TOSC1 XTAL2/TOSC2

Oscillator

ENABLE OUTPUT

209

ATmega162(V/U/L)

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Scanning the Analog

Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 91. The

Boundar y- sca n c ell from F igu re 92 i s attac he d to eac h o f thes e si gna ls . The s i gnal s ar e

described in Table 87.

The Co mpara tor need not be us ed for pu re conn ectivi ty test ing, sin ce all an alog in puts

are shared with a digital port pin as well.

Figure 91. Analog Comparator

Figure 92. General Boundary-scan Cell used for Signals for Comparator and ADC

ACBG

BANDGAP

REFERENCE

AC_IDLE

ACO

1DQ DQ

From

Cell

ClockDR UpdateDR

ShiftDR

Cell EXTEST

To Snalog Circuitry/

To Digital Logic

From Digital Logic/

From Analog Ciruitry

210 ATmega162(V/U/L) 2513C–AVR–09/02

ATmega162 Boundary-

scan Order Table 88 shows the Scan order between TDI and TDO when the Boundary-scan chain

is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit

scann ed out. The sc an order fol lows the pi nout order as far as possib le. Theref ore, the

bits of Port A a nd Port E is scanne d in th e opposit e bit ord er of the other po rts. Ex cep-

tions from the rules are the Scan chains for the analog circuits, which constitute the

most significant bits of the scan chain regardless of which physical pin they are con-

necte d to. In Figur e 87, PXn. Dat a correspon ds to FF0, PXn . Control cor respond s to

FF1, and PXn. Pullup_enable corresponds to FF2. Bit 4, 5, 6, and 7of Port C is not in the

scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

Table 87. Boundary-scan Signals for the Analog Comparator

Signal

Name

Direction as

seen from the

Comparator Description

Recommended

Input when Not

in Use

Output Values when

Recommended

Inputs are Used

AC_IDLE i npu t Tu rns off Analog

comparator

when true

1 Depends upon µC

code being executed

ACO output Analog

Comparator

Output

Will become

input to µC code

being executed

ACBG input Bandgap

Reference

enable

0 Depends upon µC

code being executed

Table 88. ATmega162 Boundary-scan Order

Bit Number Signal Name Module

105 AC_IDLE Comparator

104 ACO

103 ACBG

102 PB0.Data Port B

101 PB0.Control

100 PB0.Pullup_Enable

99 PB1.Data

98 PB1.Control

97 PB1.Pullup_Enable

96 PB2.Data

95 PB2.Control

94 PB2.Pullup_Enable

93 PB3.Data

92 PB3.Control

91 PB3.Pullup_Enable

90 PB4.Data

89 PB4.Control

88 PB4.Pullup_Enable

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87 PB5.Data Port B

86 PB5.Control

85 PB5.Pullup_Enable

84 PB6.Data

83 PB6.Control

82 PB6.Pullup_Enable

81 PB7.Data

80 PB7.Control

79 PB7.Pullup_Enable

78 RSTT Reset Logic

(Observe-only)

77 RSTHV

76 TOSC 32 kHz Timer Oscillator

75 TOSCON

74 PD0.Data Port D

73 PD0.Control

72 PD0.Pullup_Enable

71 PD1.Data

70 PD1.Control

69 PD1.Pullup_Enable

68 PD2.Data

67 PD2.Control

66 PD2.Pullup_Enable

65 PD3.Data

64 PD3.Control

63 PD3.Pullup_Enable

62 PD4.Data

61 PD4.Control

60 PD4.Pullup_Enable

59 PD5.Data Port D

58 PD5.Control

57 PD5.Pullup_Enable

56 PD6.Data

55 PD6.Control

54 PD6.Pullup_Enable

53 PD7.Data

52 PD7.Control

Table 88. ATmega162 Boundary-scan Order (Continued)

Bit Number Signal Name Module

212 ATmega162(V/U/L) 2513C–AVR–09/02

51 PD7.Pullup_Enable Port D

50 EXTCLKEN Enable signals for main

Clock/Oscillators

49 OSCON

48 OSC32EN

47 EXTCLK (XTAL1) Clock input and Oscillators

for the main clock (Observe-

only)

46 OSCCK

45 OSC32CK

44 PC0.Data Port C

43 PC0.Control

42 PC0.Pullup_Enable

41 PC1.Data

40 PC1.Control

39 PC1.Pullup_Enable

38 PC2.Data

37 PC2.Control

36 PC2.Pullup_Enable

35 PC3.Data

34 PC3.Control

33 PC3.Pullup_Enable

32 PE2.Data Port E

31 PE2.Control

30 PE2.Pullup_Enable

29 PE1.Data

28 PE1.Control

27 PE1.Pullup_Enable

26 PE0.Data

25 PE0.Control

24 PE0.Pullup_Enable

Table 88. ATmega162 Boundary-scan Order (Continued)

Bit Number Signal Name Module

213

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Note: 1. PRIVATE_SIGNAL1 should always be scanned in as zero.

Boundary-scan

Description Language

Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable

device s in a standa rd format us ed by autom ated test-g eneration software. T he order

and fu nctio n o f b its i n the Bound ar y-s ca n D ata Reg is ter a re inc lud ed in this de scr ip tio n.

A BSDL file for ATmega162 is available.

23 PA7.Data Port A

22 PA7.Control

21 PA7.Pullup_Enable

20 PA6.Data

19 PA6.Control

18 PA6.Pullup_Enable

17 PA5.Data

16 PA5.Control

15 PA5.Pullup_Enable

14 PA4.Data Port A

13 PA4.Control

12 PA4.Pullup_Enable

11 PA3.Data

10 PA3.Control

9 PA3.Pullup_Enable

8PA2.Data

7 PA2.Control

6 PA2.Pullup_Enable

5PA1.Data

4 PA1.Control

3 PA1.Pullup_Enable

2PA0.Data

1 PA0.Control

0 PA0.Pullup_Enable

Table 88. ATmega162 Boundary-scan Order (Continued)

Bit Number Signal Name Module

214 ATmega162(V/U/L) 2513C–AVR–09/02

Boot Loader Support

– Read-While-Write

Self-programming

The Boot Loader Support provides a real Read-While-Write Self-programming mecha-

nism for downloading and uploading program code by the MCU itself. This feature

allows flexible application software updates controlled by the MCU using a Flash-resi-

dent Boot Loader program. The Boot Lo ader program can use any available data

interface and associated protocol to r ead code a nd write (pro gram) that co de into the

Flash memory, or read the code from the program memory. The program code within

the Boot Loader section has the ca pability to writ e into the e ntire Fla sh, includ ing the

Boot Lo ader memory . The Boo t Loader can thus even modify itsel f, and it can also

erase itself from the code if the feature is not needed anymore. The size of the Boot

Loader memory is configurable with Fuses and the Boot Loader has two separate sets

of Boot Lock bits which can be set independently. This gives the user a unique flexibility

to select different levels of protection.

Features •Read-While-Write Self-programming

•Flexible Boot Memory Size

•High Security (Separate Boot Lock Bits for a Flexible Protection)

•Separate Fuse to Select Reset Vector

•Optimized Page(1) Size

•Code Efficient Algorithm

•Efficient Read-Modify-Write Support

Note: 1. A page is a section in the Flash consisting of several bytes (see Table 106 on page

233) used during programming. The page organization does not affect normal

operation.

Application and Boot

Loader Flash Sections T he Flash me mory is or ganized in t wo main sections, the Application section a nd the

Boot Loader section (see Figure 94). The size of the different sections is configured by

the BOO TSZ Fus es as sho wn in Tab le 94 on pag e 226 and Fi gure 94. These two s ec-

tions can have different level of protection since they have different sets of Lock bits.

Application Section The Application section is the section of the Flash that is used for storing the application

code. T he pr ot ect ion l ev el for the app li ca tio n s ec ti on ca n b e s el ec ted by t he App li ca tio n

Boot Lock bits (Boo t Lock bits 0 ), see Table 90 on page 2 17. The Applic ation secti on

can neve r sto re any Boot L oader co de sin ce the S PM in stru ction is di sable d when ex e-

cuted fro m the Application section.

BLS – Boot Loader Section While the Application section is used for storing the applicat ion code, the The Boot

Loader software must be located in the BLS since the SPM instruction can initiate a pro-

gramming when executing from the BLS only. The SPM instruction can access the

entire Flash , including the BLS itse lf. The protecti on level fo r the Boot Loader section

can be sele cted by the Boot Lo ader Lock bits (Boot Loc k bits 1), see Tabl e 91 on page

217.

Read-While-Write and No

Read-While-Write Flash

Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot

Loader software u pdate is depend ent on which ad dress that is being programmed. In

addition to the two sections that are configurable by the BOOTSZ Fuses as described

above, the Flash is also di vided into two fixed sections, the Read-While-Write (RWW)

section and the No Read-W hile-Write (NRWW) s ection. The limit between the RWW-

and NRWW se cti ons i s giv en in T abl e 95 on pag e 22 6 an d F i gure 9 4 on page 216. Th e

main difference between the two sections is:

• When erasing or writing a page located inside the RWW section, the NRWW section

can be read during the operation.

• When erasing or writing a page located inside the NRWW section, the CPU is halted

during the entire operation.

215

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Note that the user software can never read any code that is located inside the RWW

secti on during a Boot Loa der softwar e operation. The syntax “Rea d-While-W rite sec-

tion” refers to which section that is being programmed (erased or written), not which

section that actually is being read during a Boot Loader software update.

RWW – Read-While-Write

Section If a Boot Loader software update is progr amming a page inside the RWW section, it is

possible to read code from the Flash, but only code that is located in the NRWW s ec-

tion. Dur ing an ongo ing pro grammin g, the sof tware mu st ensur e that the RW W sectio n

never i s b eing r ead. If th e us er s oftware is trying to r ead code t ha t is l ocated insi de th e

RWW section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software

might end up in an unknown state. To avoid this, the interrupts should either be disabled

or mov ed to the Bo ot Loade r sect ion. Th e Boot Lo ader sec tion is al ways lo cated in th e

NRWW section . The RWW Se ction Busy bit (RWWSB) i n the Store Pr ogram Memory

Control Regi ster (SPMCR) will be r ead as logical one as lon g as the RWW se ction is

blocked for reading. After a programming is completed, the RWWSB must be cleared by

soft ware before r e adi ng co de lo cat e d in the R WW s ec ti o n. Se e “St o re Pro gr am Me m or y

Control Register – SPMCR” on page 218. for details on how to clear RWWSB.

NRWW – No Read-While-Write

Section T he code locate d in the NRW W secti on can be read when th e Boot Loader s oftwar e is

updating a page in th e RWW sec tion. W hen th e Boo t Loade r co de upd ates t he NRWW

section, the CPU is halted during the entire Page Erase or Page Write operation.

Figure 93. Read-While-Write vs. No Read-While-Write

Table 89. Read-While-Write Features

Which Section does the Z-

pointer Addres s During the

Programming?

Which Section Can be

Read During

Programming? Is the CPU

Halted?

Read-While-

Write

Supported?

RWW se cti on NRWW section No Yes

NRWW section None Yes No

Read-While-Write

(RWW) Section

No Read-While-Write

(NRWW) Section

Z-pointer

Addresses RWW

Section

Z-pointer

Addresses NRWW

Section

CPU is Halted

During the Operation

Code Located in

NRWW Section

Can be Read During

the Operation

216 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 94. Mem o ry Sect ions (1)

Note: 1. The parameters are given in Table 94 on page 226.

Boot Loader Lock Bits If no Boot Loade r c apa bili ty i s nee ded , the en tir e Fla sh is avai la bl e for appl ic ati on code.

The Boot Loader has two separate sets of Boot Lock bits which can be set indepen-

dently. This gives the user a unique flexibility to select different levels of protection.

The user can select:

• To protect the entire Flash from a software update by the MCU

• To protect only the Boot Loader Flash section from a software update by the MCU

• To protect only the Application Flash section from a software update by the MCU

• Allow software update in the entire Flash

See Table 90 and Table 91 for further details. The Boot Lock bits can be set in software

and in Serial or Parallel P rogramming mode, but they can be cleared b y a chip er ase

command only. The general Write Lock (Lock bit mode 2) does not control the program-

0x0000

Flashend

Program Memory

BOOTSZ = '11'

Application Flash Section

Boot Loader Flash Section Flashend

Program Memory

BOOTSZ = '10'

0x0000

Program Memory

BOOTSZ = '01' Program Memory

BOOTSZ = '00'

Application Flash Section

Boot Loader Flash Section

0x0000

Flashend

Application Flash Section

Flashend

End RWW

Start NRWW

Application flash Section

Boot Loader Flash Section

End RWW

Start NRWW End RWW

Start NRWW

0x0000

End RWW, End Application

Start NRWW, Start Boot Loader

Application Flash SectionApplication Flash Section

Application Flash Section

Read-While-Write SectionNo Read-While-Write Section Read-While-Write SectionNo Read-While-Write Section

Read While Write SectionNo Read While Write SectionRead-While-Write SectionNo Read-While-Write Section

End Application

Start Boot Loader

End Application

Start Boot Loader

End Application

Start Boot Loader

217

ATmega162(V/U/L)

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ming of the Flash memory by SPM instruction. Simil arly, the general Read/Write Lock

(Lock bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted.

Note: 1. “1” means unprog ram me d, “0” means programmed

Table 90. Boot Lock Bit0 Protection Modes (Application Section)(1)

BLB0 Mode BLB02 BLB01 Protection

111

No restrictions for SPM or LPM accessing the Application

section.

2 1 0 SPM is not allowed to write to the Application section.

300

SPM is not allo wed to write to the Applic ation s ection , and

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

401

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

Table 91. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1)

BLB1 Mode BLB12 BLB11 Protection

111

No restricti ons for SPM or LPM accessi ng the Boot Loader

section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

300

SPM is not allowed to write to the Boot Loader section,

and LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrupts

are disabl ed while exec uting from the Boot Loa der section .

401

LPM exec uti ng fr om the Ap plicatio n se cti on i s n ot al low e d

to read from the Boot Loader section. If Interrupt Vectors

are placed in the Application section, interrupts are

disabled while executing from the Boot Loader section.

218 ATmega162(V/U/L) 2513C–AVR–09/02

Entering the Boot Loader

Program En tering the Boo t Loader t akes pl ace by a jump o r call from the a pplica tion pr ogram.

This may be initiated by a trigger such as a command received via USART, or SPI inter-

face. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is

pointing t o the Boot Flash start address after a reset. I n this c ase, the B oot Loader is

started after a re set. Af ter the applic ation code i s loa ded, the p rogram can s tart exec ut-

ing the app lication co de. No te th at th e fus es c ann ot be ch anged by the MCU its elf . T his

means that once the Boot Reset Fuse is programmed, the Reset Vector will always

point t o the Bo ot L oader Rese t and the fuse can only be change d thr ough the Ser ial or

Parallel Programming interface.

Note: 1. “1” means unprog ram me d, “0” means programmed

Store Program Memory

Control Register – SPMCR The Store Program Memory Control Register contains the control bits needed to control

the Boot Loader operations.

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the

SPM r ead y i nterr upt will be enab led. Th e SP M r ead y In terru pt will be e xec uted as lon g

as the SPMEN bit in the SPMCR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-programming (Page Erase or Page Write) operation to the RWW section is

initiated, the RWWSB will be se t (one) by hardware. When the RWWSB bit is set, the

RWW sec tion can not be ac cesse d. The RWW SB b it will be clear ed if the RWW SRE bit

is wr itten to o ne after a Self-progr amming op eration is complete d. Alternat ively the

RWWSB bit will automatically be cleared if a page load operation is initiated.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega162 and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section

is bl ocked fo r readi ng (the RWWSB wi ll be set by hardware ). To re -enable the R WW

section, the user software must wait until the programming is completed (SPMEN will be

cleared). Then, if the RW WSRE bit is written to one at the same time as SPMEN, the

next SPM instruction within four clock cycles re-enables the RWW section. The RWW

section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write

(SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash

load operation will abort and the data loaded will be lost.

Table 92. Boot Reset Fuse(1)

BOOTRST Reset Addr ess

1 Reset Vector = Application Reset (address 0x0000).

0 Reset Vector = Boot Loader Reset (see Table 94 on page 226).

Bit 765 4 3210

SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

219

ATmega162(V/U/L)

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• Bit 3 – BLBSET: Boot Lock Bit Set

If thi s b it i s w ritten to one at the same t ime as S PME N, th e ne xt SPM i nstr ucti on w ithi n

four clock cycles sets B oot Lock bits, according to the data in R0. The data in R1 and

the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared

upon completion of the Lock bit set, or if no SPM instruction is executed within four clock

cycles.

An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR

pointer) into the destinati on register. See “Reading the Fuse and Lock Bits from Soft-

ware” on page 222 for details.

• Bit 2 – PGWRT: Page Write

If thi s b it i s w ritten to one at the same t ime as S PME N, th e ne xt SPM i nstr ucti on w ithi n

four clock cycles executes Page Write, with the data stored in the temporary buffer. The

page addr ess is ta ken from the high part of the Z -pointer. The data in R1 and R0 are

ignored . The PG WRT bit wi ll auto –clea r upon com pleti on of a Pa ge Write, or if no SPM

instruction is executed within four clock cycles. The CP U is halted during the entire

Page Write operation if the NRWW section is addressed.

• Bit 1 – PGER S: Page Erase

If thi s b it i s w ritten to one at the same t ime as S PME N, th e ne xt SPM i nstr ucti on w ithi n

four clock cy c le s execu tes Page Erase . The page add re ss is tak en from the high par t of

the Z-pointer . The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon

completion of a Page Erase, or if no SPM instruction is executed within four clock

cycles. The CPU is halted during the entire Page Write operation if the NRWW section is

addressed.

• Bit 0 – SPMEN : Store Program Memory Enable

This bi t enables the SPM i nstruction f or the nex t four cloc k cycles. If written to one

together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM

instruction will have a special meaning, see description above. If only SPMEN is written,

the follo wing S PM i nstruc tion wi ll s tore the va lue in R1:R0 in the tempo rary p age bu ffer

addre ssed by the Z -pointer . The L SB of the Z-po inter is igno red. The SP MEN bit wil l

auto-clear upon comple tion of an SPM instruction, or if no SPM instruction is executed

within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains

high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the

lower five bits will have no effect.

220 ATmega162(V/U/L) 2513C–AVR–09/02

Addressing the Flash

During Self-

programming

The Z-pointer is used to address the SPM commands.

Since the Flash is organized in pages (see Table 106 on page 233), the Program

Counter can be treated as having two different sections. One section, consisting of the

least significant b its, is addressing the words within a page, while the most s ignificant

bits are addressing the pages. This is shown in Figure 95. Note that the Page Erase and

Page Write operations are addressed independently. Therefore it is of major importance

that the Boo t Loader softwar e addresses the same page in both the Page Erase and

Page Write operation. Once a programming operation is initiated, the address is latched

and the Z-pointer can be used for other operations.

The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock

bits. The content of the Z-pointer is ignored and will have no effect on the operation. The

LPM instruction does also use the Z-pointer to store the address. Since this instruction

addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Figure 95. Addressing the Flash during SPM(1)

Note: 1. The different variables used in Figure 95 are listed in Table 96 on page 227.

Bit 151413121110 9 8

ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8

ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0

76543210

PROGRAM MEMORY

0115

Z - REGISTER

BIT

ZPAGEMSB

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

ZPCMSB

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0]:

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

221

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Self-programming the

Flash The program memory i s updated in a page by pag e fashion. Before programming a

page with the data stored in the temporary page buffer, the page must be erased. The

temporary page buffer is filled one word at a time using SPM and the buffer can be filled

either before the Page Erase command or between a Page Erase and a Page Write

operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the p age ne eds to be ch anged, t he rest of th e page must be s tore d (for

example in the temporary page buffer) before the erase, and the n be rewritten. When

using alternati ve 1, the Bo ot Loader provides an effectiv e Read-M odify-Wr ite featu re

which allo ws the user s oftware to first read the page, do the necessa ry changes, and

then write back the modified data. If alternative 2 is used, it is not possible to r ead the

old data wh il e lo adi ng s i nce the page is al r ead y e ra se d. The temp or ar y p age buf fer ca n

be accessed in a random sequence. It is essential that the page address used in both

the Page Er ase and Page Write operation is addressin g the same page . See “S imple

Assembly Code Example for a Boot Loader” on page 224 for an assembly code

example.

Performing Page Erase by

SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to

SPMCR and exe cu te SP M within four cl ock cy c les after writi ng SP MCR. The dat a in R1

and R0 is ignor ed. The page address must be written to PCPAGE in the Z-register.

Other bits in the Z-pointer will be ignored during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the Page

Erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

Filling the Temporary Buffer

(Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“000000 01” to SPMC R a nd ex ecute S PM within four cloc k c ycles after w riti ng SP MCR.

The conte nt of PCWORD in the Z-regi ster is used to add ress the data in the temporary

buffer. The temporary buffer will auto-erase after a Page Write oper ation or by writing

the RWWSRE bit in SPMCR. It is also erased after a System Reset. Note that it is not

possible to write more than one time to each address without erasing the temporary

buffer.

Performing a Page Wr it e To execute Page Write, set up the address in the Z-pointer, write “X0000101” to

SPMCR and exe cu te SP M within four cl ock cy c les after writi ng SP MCR. The dat a in R1

and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-

pointer must be written zero during this operation.

• Page Write to the RWW section: The NRWW section can be read during the Page

Write.

• Page Write to the NRWW section: The CPU is halted during the operation.

222 ATmega162(V/U/L) 2513C–AVR–09/02

Using the SPM Interrupt If the SPM interrupt is en abled, the SPM interrupt will generate a constant interrupt

when the SPMEN bit in SPMCR is cleared. This means that the interrupt can be used

instead of polling the SPMCR Register in software. When using the SPM interrupt, the

Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is

access ing the RWW section wh en it is blo cked for r eading. How to move the interru pts

is described in “Interrupts” on page 55.

Consideration while Updating

BLS Specia l car e must be t aken i f the us er allow s the B oot Load er se ction to b e update d by

leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can

corrupt th e en tir e B oot Loa der , an d fu rth er so ftwa re upd ates mi ght be i mpo ssi ble . If i t is

not nece ssary to change the Boot Loa der sof tware itsel f, it is recom mended to progra m

the Boot Lock bit11 to protect the Boot Loader software from any interna l softwa re

changes.

Prevent Reading the RWW

Section During Self-

programming

During Self-programming (either Page Erase or Page Write), the RWW section is

always blocked for reading. T he user software itself must prevent that this section is

addressed during the self programming operation. The RWWSB in the SPMCR will be

set as long as the RWW s ectio n is busy. During Self-p rogr amming th e Inte rrupt V ector

table s hould be m oved to the BLS as de scribe d in “Inte rrupts ” on page 55, or the inter-

rupts must be disabled. Before addressing the RWW section after the programming is

completed, the user software must clear the RWWSB by writing the RWWSRE. See

“Simple Assembly Code Example for a Boot Loader” on page 224 for an example.

Setting the Boot Loader Lock

Bits by SPM To set the Boot Loader Lock bits, write the d esired data to R0, write “ X0001001” to

SPMCR and execute SPM within four clock cycles after writing SPMCR. The only

accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot

Loader section from any software update by the MCU.

See Table 90 and Table 91 for how the different settings of the Boot Loader bits affect

the Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed

if an S PM in struction i s ex ec ut ed w ith in f our cyc le s af t er BL B SET an d SP ME N a re se t in

SPMCR. The Z-pointer is don’t care during this operation, but for future compatibility it is

recommended to load the Z -pointer with 0x0001 (same as used for reading the Lock

bits). For future compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1”

when writing th e Lock bits. When prog ramming the Lock bits the entire Flash can be

read during the operation.

EEPROM Write Prevents

Writing to SPMCR Note that an EEPROM write operation will bl ock all software programming to Flash.

Reading the Fuses and Lock bits from software will also be prevented during the

EEPROM write operation. It is recommended that the user checks the status bit (EEWE)

in the EECR Registe r and verifies that the bi t is cleared befo re writing to the SPMCR

Reading the Fuse and Lock

Bits from Softwar e It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,

load the Z -p ointer w ith 0x 000 1 a nd se t th e B LB SE T an d S P ME N bi ts in SPMCR. W he n

an LPM ins truction is ex ecuted withi n three CPU cycles afte r the BLBSET an d SPMEN

bits are set in SPMCR, th e va lue of the Lo ck bit s will be loaded in the des tinatio n regis-

ter. The BLBSET and SPMEN bits will auto-clear upon completion of r eading the Lock

bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is

Bit 76543210

R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1

223

ATmega162(V/U/L)

2513C–AVR–09/02

executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will

work as described in the Instruction set Manual.

The algorithm for reading th e Fuse Low byte is similar to the one desc ribed above for

reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and

set the BLBS ET and SPMEN bi ts in SPMCR. When an LP M instruction is ex ecuted

within thr ee cycles after the B LBSET a nd SPMEN b its are s et in the SP MCR, the v alue

of the Fuse Low byte (FLB) will be load ed in the destination regi ster as shown below.

Refer to Table 101 on page 230 for a detailed description and mapping of the Fuse Low

byte.

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM

instru ction i s exec uted with in three c ycles after the B LBSE T and SP MEN bi ts are s et in

the SPMCR, the value of the Fuse High byte (FHB) will be loaded in the destination reg-

ister as shown below. Refer to Table 99 on page 229 for detailed description and

mapping of the Fuse High byte.

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM

instru ction i s exec uted with in three c ycles after the B LBSE T and SP MEN bi ts are s et in

the SPMCR, the value of the Extended Fuse byte (EFB) will be loaded in the destination

regist er as shown b elow. Refer to Table 99 on pa ge 229 for deta iled desc ription and

mapping of the Extended Fuse byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that

are unprogrammed, will be read as one.

Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply volt-

age is too low for the CPU and the Flash to operate properly. These issues are the same

as for board lev el systems usin g the Flash, an d the sam e design solutions sh ould be

applied.

A Flash program corruption can be caused by two situations when the voltage is too low.

First, a regul ar write sequ ence to the Flas h requires a minimum volt age to operat e cor-

rectl y. Se condl y, th e CPU itse lf ca n execu te ins tr uctio ns inc orre ctly , if th e suppl y volt age

for executing instructions is too low.

Flash corruption can easily be avoided by following these design recommendations (one

is sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot

Loader Lock bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This can be done by enabling the internal Brown-out Detector (BOD) if

the operating voltage matches the detection level. If not, an external low VCC

Reset Protection circuit can be used. If a Reset occurs while a write operation is

in progress, the write operation will be completed provided that the power supply

voltage is sufficient.

Bit 76543210

Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1

Bit 76543210

Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Bit 76543210

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

Bit 76543210

Rd – – – EFB4 EFB3 EFB2 EFB1 –

224 ATmega162(V/U/L) 2513C–AVR–09/02

3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the SPMCR Register and thus the Flash from unintentional

writes.

Programming Time for Flash

When Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 93 shows the typical

programming time for Flash accesses from the CPU.

Simple Assembly Code

Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during self-programming (page erase and page write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not

; words

.org SMALLBOOTSTART

Write_page:

; page erase

ldi spmcrval, (1<<PGERS) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld r0, Y+

ld r1, Y+

ldi spmcrval, (1<<SPMEN)

call Do_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256

brne Wrloop

; execute page write

subi ZL, low(PAGESIZEB) ;restore pointer

sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; read back and check, optional

Table 93. SPM Programming Time

Symbol Min Programming Time Max Programming Time

Flash Write (Page Erase, Page W rite,

and Write Lock bits by SPM) 3.7ms 4.5ms

225

ATmega162(V/U/L)

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ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB) ;restore pointer

sbci YH, high(PAGESIZEB)

Rdloop:

lpm r0, Z+

ld r1, Y+

cpse r0, r1

jmp Error

sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256

brne Rdloop

; return to RWW section

; verify that RWW section is safe to read

Return:

in temp1, SPMCR

sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not

; ready yet

ret

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in temp1, SPMCR

sbrc temp1, SPMEN

rjmp Wait_spm

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEWE

rjmp Wait_ee

; SPM timed sequence

out SPMCR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

226 ATmega162(V/U/L) 2513C–AVR–09/02

ATmega162 Boot Loader

Parameters In Table 94 through Ta ble 96, the pa rameters used in the desc ription of th e self pro-

gramming are given.

Note: 1. The different BOOTSZ Fuse configurations are shown in Figure 94

Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on

page 215 and “RWW – Read-While-Write Section” on page 215

Table 94. Boot Size Configuration(1)

BOOTSZ1 BOOTSZ0 Boot

Size Pages

Application

Flash

Section

Boot

Loader

Flash

Section

End

Application

Section

Boot Reset

Address

(Start Boot

Loader

Section)

128

words 20x0000 -

0x1F7F 0x1F80 -

0x1FFF 0x1F7F 0x1F80

256

words 40x0000 -

0x1EFF 0x1F00 -

0x1FFF 0x1EFF 0x1F00

512

words 80x0000 -

0x1DFF 0x1E00 -

0x1FFF 0x1DFF 0x1E00

1024

words 16 0x0000 -

0x1BFF 0x1C00 -

0x1FFF 0x1BFF 0x1C00

Table 95. Read-While-Write Limit

Section Pages Address

Read-While -Write section (RWW) 112 0x0000 - 0x1BFF

No Read-While-Write section (NRWW) 16 0x1C00 - 0x1FFF

227

ATmega162(V/U/L)

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Note: 1. Z15:Z14: always igno red

Z0: should be zero for all SPM commands, byte select for the LPM instruction.

See “Addressing the Flash During Self-programming” on page 220 for details about

the use of Z-pointer during Self-programming.

Table 96 . Explanati on of Different Var iables Used i n Figur e 95 and the Ma pping to th e

Z-pointer(1)

Variable Corresponding

Z-value Description

PCMSB 12 Most significant bit in the Program Counter.

(The Program C ount er is 13 bits P C[12:0])

PAGEMSB 5 Most significant bit which is used to address

the word s withi n one p age (64 word s in a page

requires 6 bits PC [5:0]).

ZPCMSB Z13 Bit in Z-register that is mapped to PCMSB.

Because Z0 is not used, the ZPCMSB equals

PCMSB + 1.

ZPAGEMSB Z6 Bit in Z-register that is mapped to PCMSB.

Because Z0 is not used, the ZPAGEMSB

equals PAGEMSB + 1.

PCPAGE PC[12:6] Z13:Z7 Program Counter page address: Page select,

for Page E rase and Page Write

PCWORD PC[5:0] Z6:Z1 Program Counter word address: Word select,

for filli ng tempo rary buf fer (mu st be z ero during

Page Write operation)

228 ATmega162(V/U/L) 2513C–AVR–09/02

Memory

Programming

Program And Data

Memory Lock Bits The A Tmeg a162 pr ovides six Lock bi ts whic h can be left unprog ra mme d (“1” ) or can be

progra mmed (“0”) to obt ain the addit ional featu res listed in Table 98. The Loc k bits can

only be erased to “1” with the Chip Erase command.

Note: 1. “1” means unprog ram me d, “0” means programmed

Table 97. Lock Bit Byte(1)

Lock Bit Byte Bit no Description Default Value

7 – 1 (unprogrammed)

6 – 1 (unprogrammed)

BLB12 5 Boot Lock bit 1 (unprogrammed)

BLB11 4 Boot Lock bit 1 (unprogrammed)

BLB02 3 Boot Lock bit 1 (unprogrammed)

BLB01 2 Boot Lock bit 1 (unprogrammed)

LB2 1 Lock bit 1 (unprogrammed)

LB1 0 Lock bit 1 (unprogrammed)

Table 98. Lock Bit Protection Modes(1)(2)

Memory Lock Bits Protection Type

LB Mode LB2 LB1

1 1 1 No memory lock features enabled.

210

Further programming of the Flash and EEPROM is

disabled in Parallel and SPI/JTAG Serial Programming

mode. The Fuse bi ts are l ocked in both Se rial and Para llel

Programming mode(1).

300

Further programming and verifi cation of the Flash and

EEPROM is disabled in Parallel and SPI/JTAG Serial

Programm ing mode. Als o the Boot Lock bits and the Fuse

bits are locked in both Seria l and Parallel Pr ogramming

mode(1).

BLB0 Mode BLB02 BLB01

111

No restrictions for SPM or LPM accessing the Application

section.

2 1 0 SPM is not allowed to write to the Application section.

300

SPM is not allo wed to write to the Applic ation s ection , and

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

401

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

229

ATmega162(V/U/L)

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Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprog ram med, “0” mea ns prog ram me d

Fuse Bits T he ATmeg a162 has three Fuse bytes. Tabl e 100 and Table 101 describe briefly the

functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the

fuses are read as logical zero, “0”, if they are programmed.

Notes: 1. See “ATmega161 Compatibility Mode” on page 5 for details.

2. See Table 19 on page 48 for BODLEVEL Fuse de coding.

BLB1 Mode BLB12 BLB11

111

No restricti ons for SPM or LPM accessi ng the Boot Loader

section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

300

SPM is not allowed to write to the Boot Loader section,

and LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrupts

are disabl ed while exec uting from the Boot Loa der section .

401

LPM exec uti ng fr om the Ap plicatio n se cti on i s n ot al low e d

to read from the Boot Loader section. If Interrupt Vectors

are placed in the Application section, interrupts are

disabled while executing from the Boot Loader section.

Table 98. Lock Bit Protection Modes(1)(2) (Continued)

Memory Lock Bits Protection Type

Table 99. Extended Fuse Byte (1)(2)

Fuse Low Byte Bit no Description Default Value

–7– 1

–6– 1

–5– 1

M161C 4 ATmega161 co mpa tibility

mode 1 (unprogrammed)

BODLEVEL2(2) 3Brown-out Detector

trigger level 1 (unprogrammed)

BODLEVEL1(2) 2Brown-out Detector

trigger level 1 (unprogrammed)

BODLEVEL0(2) 1Brown-out Detector

trigger level 1 (unprogrammed)

–0– 1

230 ATmega162(V/U/L) 2513C–AVR–09/02

Notes: 1. The SPIEN Fuse is not accessible in SPI Serial Programming mode.

2. The default value of BOOTSZ1:0 results in maximum Boot Size. See Table 94 on

page 226 for details.

3. Never ship a product with the OCDEN Fuse programmed regardl ess of the setting of

Lock bits and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts

of the clock system to be running in all sleep modes. This may increase the power

consumption.

Notes: 1. The default value of SUT1:0 results in maximum start-up time for the default clock

source. See Table 12 on page 37 for details.

2. The default setting of CKSEL3:0 results in Internal RC Oscillator @ 8 MHz. See

Table 5 on page 34 for details.

3. T he CK OUT Fu se al l ow th e sy st e m cl oc k to b e o utp ut o n Po rt B 0 . Se e “ Cl oc k ou t put

buffer” on page 39 for details.

4. See “System Clock Pres caler” on page 39 for details.

The s tatus of th e Fuse bits is not affe cted by Chip E rase. Not e that th e Fuse bits ar e

locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the

Lock bits.

Table 100. Fuse High Byte

Fuse Low Byte Bit no Description Default Value

OCDEN(3) 7 Enable OCD 1 (unprogramm ed , OCD

disabled)

JTAGEN 6 Enable JTAG 0 (programmed, JTAG

enabled)

SPIEN(1) 5Enable Serial Program and Data

Downloading 0 (programmed, SPI prog.

enabled)

WDTON 4 Watchdog Timer always on 1 (unprogrammed)

EESAVE 3 EEPROM memory is preserved

through the Chip Erase 1 (unprogrammed,

EEPROM not preserved)

BOOTSZ1 2 Select Boot Size (see Table 94 for

details) 0 (program me d) (2)

BOOTSZ0 1 Select Boot Size (see Table 94 for

details) 0 (program me d) (2)

BOOTRST 0 Sel ect Reset Vector 1 (unp rogra mm ed )

Table 101. Fuse Low Byte

Fuse Low Byte Bit no Description Default value

CKDIV8(4) 7 Divide clock by 8 0 (programmed)

CKOUT(3) 6 Clock Output 1 (unprogrammed)

SUT1 5 Select start-up time 1 (unprogrammed)(1)

SUT0 4 Select start-up time 0 (programmed)(1)

CKSEL3 3 Select Clock source 0 (programmed)(2)

CKSEL2 2 Select Clock source 0 (programmed)(2)

CKSEL1 1 Select Clock source 1 (unprogrammed)(2)

CKSEL0 0 Select Clock source 0 (programmed)(2)

231

ATmega162(V/U/L)

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Latching of Fuses The Fuse values are latched when the device enters Programming mode and changes

of the Fuse values will have no effect until the part leaves Programming mode. This

does not apply to the EESAVE F use which will take effect once it is progr ammed. The

Fuses are also latched on Power-up in Normal mode.

Signature Bytes All Atmel microcontrollers have a 3-byte signature code which identifies the device. This

code ca n be r ead in bot h S er ia l a nd P aral le l m ode , al so whe n th e de vi c e i s loc k ed. Th e

three bytes reside in a separate address space.

For the ATmega162 the signature bytes are:

1. 0x000: 0x1E (indicates manufactured by Atmel).

2. 0x001: 0x94 (indicates 16KB Flash memory).

3. 0x002: 0x04 (indicates ATmega162 device when 0x001 is 0x94).

Calibration Byte The ATmega162 has a one-byte calibration value for the internal RC Oscillator. This

byte resides in the high byte of address 0x000 in the signature address space. During

Reset, this byte is automatically written into the OSCCAL Register to ensure correct fre-

quency of the calibrated RC Oscillator.

Parallel Programming

Parameters, Pin

Mapping, and

Commands

This section describes how to parallel program and verify Flash Program memory,

EEPROM Data memor y, Memory Lock bits, and Fuse bits in the ATmeg a162. Pulses

are assumed to be at least 250 ns unless otherwise noted.

Signal Names In this section, some pins of the ATmega162 are referenced by signal names describing

their functionality during parallel programming, see Figure 96 and Table 102. Pins not

described in the following table are referenced by pin names.

The XA1/XA0 pins determine th e action executed when the XTAL1 pin is given a posi-

tive pulse. The bit coding is shown in Table 104.

When pulsing WR or OE, the command loaded determines the action executed. The dif-

ferent Commands are shown in Table 105.

Figure 96. Parallel Pr ogr am mi ng

VCC

+5V

GND

XTAL1

PD1

PD2

PD3

PD4

PD5

PD6

PB7 - PB0 DATA

RESET

PD7

+12 V

BS1

XA0

XA1

RDY/BSY

PAGEL

PA0

BS2

232 ATmega162(V/U/L) 2513C–AVR–09/02

Table 102. Pin Name Mapping

Signal Name in

Programming Mode Pin Name I/O Function

RDY/BSY PD1 O 0: Device is bus y p rogram ming, 1 : Dev ice is ready

for new command

OE PD2 I Output Enable (Active low)

WR PD3 I Write P ulse (Active low)

BS1 PD4 I Byte Selec t 1 (“0” select s low byte, “1” sele cts high

byte)

XA0 PD5 I XTAL Action Bit 0

XA1 PD6 I XTAL Action Bit 1

PAGEL PD7 I Program Memory and EEPROM data Page Load

BS2 PA0 I Byte Select 2 (“0” sele cts low byte, “1” selects 2’ nd

high byte)

DATA PB7 - 0 I/O Bi-directional Data bus (Output when OE is low)

Table 103. Pin Values used to Enter Programming Mode

Pin Symbol Value

PAGEL Prog_enable[3] 0

XA1 Prog_enable[2] 0

XA0 Prog_enable[1] 0

BS1 Prog_enable[0] 0

Table 104. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0 0 Load Flash or EEPROM address (High or low address byte determined by BS1)

0 1 Load Data (High or Low data byte for Flash determined by BS1).

1 0 Load Command

1 1 No Action, Idle

233

ATmega162(V/U/L)

2513C–AVR–09/02

Parallel Programming

Enter Programming Mode The following algorithm puts the device in Parallel Programming mode:

1. Apply 4.5 - 5.5V between VCC and GND.

2. Set RESET to “0” and toggle XTAL1 at least six times.

3. Set the Prog_enable pins listed in Table 103 on page 232 to “0000” and wait at

least 100 ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns

after +12V has been applied to RESET, will cause the device to fail entering Pro-

gramming mode.

Considerations for Efficient

Programming The loaded command and address are retained in the device during programming. For

efficient programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory

locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless

the EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256-

word window in Flash or 256 byte EEPROM. This consideration also applies to

Signature bytes reading.

Table 105. Command Byte Bit Coding

Command Byte Command Executed

1000 0000 Chip Erase

0100 0000 Write Fuse Bits

0010 0000 Write Lock Bits

0001 0000 Write Flash

0001 0001 Write EEPROM

0000 1000 Read Signature Bytes and Calibration byte

0000 0100 Read Fuse and Lock Bits

0000 0010 Read Flash

0000 0011 Read EEPROM

Table 106. No. of Words in a Page and no. of Pages in the Flash

Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB

8K words (16K bytes) 64 words PC[5:0] 128 PC[12:6] 12

Table 107. No. of Words in a Page and no. of Pages in the EEPROM

EEPROM Size Page Size PCWORD No. of pages PCPAGE EEAMSB

512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8

234 ATmega162(V/U/L) 2513C–AVR–09/02

Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock

bits ar e not reset unti l t he pr ogram me mor y ha s bee n c om pl etel y er as ed. The Fuse b its

are not ch anged. A Chip Eras e must be perform ed before the Flash or EEPROM are

reprogrammed.

Note: 1. The EEPRPOM memory is preserved during chip erase if the EESAVE Fuse is

programmed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

Programming the Flash The Flash is organized in pages, see Table 106 on page 233. When programming the

Flash, the program data is latched into a page buffer. This allows one page of program

data to be programme d simulta neousl y. The follow ing proc edure desc ribes how to pr o-

gram the entire Flash memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This selects high data byte.

2. Give PAGEL a positive pulse. This latches the data bytes (See Figure 98 for sig-

nal wa veforms).

F. Repeat B through E until the entire buffer is filled or until all data within the page is

loaded.

235

ATmega162(V/U/L)

2513C–AVR–09/02

While the lower bits in the address are mapped to words within the page, the higher bits

addres s the pages within the FLASH. This is illustrated in F igure 97 on page 235 . Note

that if less than eight bits are required to address words in the page (pagesize < 256),

the most significant bi t(s) in the address lo w byte are used to address the page when

performing a Page Write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Give WR a negative pulse. This starts programming of the entire page of data.

RDY/BSYgoes low.

2. Wait until RDY/BSY goes high. (See Figure 98 for signal waveforms)

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write sig-

nals are reset.

Figure 97. Addressing the Flash which is Organized in Pages(1)

Note: 1. PCPAGE and PCWORD are listed in Table 106 on page 233.

PROGRAM MEMORY

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0]:

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

236 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 98. Pr og ra mming the Fl ash Wav efo rms

Note: “XX” is don’t care. The letters refer to the programming description above.

Programming the EEPROM The EEPROM is organized in pages, see Table 107 on page 233. When programming

the EEPROM, the program data is latched into a page buffer. This allows one page of

data to be programmed simultaneously. The programming algorithm for the EEPROM

data mem ory is as foll ows (refe r to “Programm ing the F lash” on pag e 234 for detai ls on

Command, Address and Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

5. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

1. Set BS to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page.

RDY/BSY goes low.

3. Wait until to RDY/BSY goes high before programming the next page

(See Figure 99 for signal waveforms).

RDY/BSY

RESET +12V

PAGEL

BS2

0x10 ADDR. LOW ADDR. HIGH

DATA

DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH

XA1

XA0

BS1

XTAL1

XX XX XX

ABCDEBCDEGH

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Figure 99. Pr og ra mmi ng the EE PROM Wa ve forms

Reading the Flash The algo rithm for re ading the Fl ash memory is as follow s (refer to “Prog ramming the

Flash” on page 234 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at

DATA.

5. Set BS to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the

Flash” on page 234 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at

DATA.

5. Set OE to “1”.

Programming the Fuse Low

Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming

the Flash” on page 234 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “0” and BS2 to “0”. This selects low data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

RDY/BSY

RESET +12V

PAGEL

BS2

0x11 ADDR. HIGH

DATA ADDR. LOW DATA ADDR. LOW DATA XX

XA1

XA0

BS1

XTAL1

AGBCEBCEL

238 ATmega162(V/U/L) 2513C–AVR–09/02

Programming the Fuse High

Bits The algorithm for programming the Fuse high bits is as follows (refer to “Programming

the Flash” on page 234 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

Programming the Extended

Fuse Bits The algo rithm for program ming th e Exten ded Fuse bits is as follow s (refer to “Pro gram-

ming the Flash” on page 234 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse

bit.

3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2 to “0”. This selects low data byte.

Figure 100. Pr ogramming the FUSES Waveforms

RDY/BSY

RESET +12V

PAGEL

0x40

DATA DATA XX

XA1

XA0

BS1

XTAL1

0x40 DATA XX

Write Fuse Low byte Write Fuse high byte

0x40 DATA XX

Write Extended Fuse byte

BS2

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Programming the Lock Bits The algori thm for programming the Lock bits is as follow s (refer to “Progr amming the

Flash” on page 234 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is pro-

grammed (LB1 and LB2 is programmed), it is not possible to program the Boot

Lock Bi ts by any exte rnal Pr ogr am mi ng mode .

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and Lock

Bits The algorithm for rea ding the Fuse and Lock bi ts is as follows (refer to “Programming

the Flash” on page 234 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can

now be read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can

now be read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1” and BS1 to “0”. The status of the Extended Fuse bits

can now be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be

read at DATA (“0” means programmed).

6. Set OE to “1”.

Figure 101. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

Reading the Signature B ytes The algorith m for reading the signature bytes is as follows (refer to “P rogramming the

Flash” on page 234 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at

DATA.

4. Set OE to “1”.

Lock Bits 0

BS2

Fuse High Byte

BS1

DATA

Fuse Low Byte 0

BS2

Extended Fuse Byte

240 ATmega162(V/U/L) 2513C–AVR–09/02

Reading the Calibration Byte The algorithm for reading the calibratio n byte is as follows (refer to “ Programming the

Flash” on page 234 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x 00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

Parallel Programming

Characteristics Figure 102. Parallel Programming Timing, Including some General Timing

Requirements

Figure 103. Parallel Programming Timing, Loading Sequence with Timing

Requirements(1)

Note: 1. The timing requirements shown in Figure 102 (i.e., tDVXH, tXHXL, an d tXLDX) als o apply

to loading operation.

Data & Contol

(DATA, XA0/1, BS1, BS2)

XTAL1

tXHXL

tWLWH

tDVXH tXLDX

tPLWL

tWLRH

RDY/BSY

PAGEL

tPHPL

tPLBX

tBVPH

tXLWL

tWLBX

tBVWL

WLRL

XTAL1

PAGEL

PLXH

XLXH

XLPH

ADDR0 (low byte) DATA (low byte) DATA (high byte) ADDR1 (low byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE) LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

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Figure 104. Parallel Prog ramming Timing , Rea ding S equence ( withi n the S ame Pa ge)

with Timing Requirements(1)

Note: 1. The timing requirements shown in Figure 102 (i.e., tDVXH, tXHXL, an d tXLDX) als o apply

to reading operation.

Table 108. Parallel Programming Characteristics, VCC = 5 V ± 10%

Symbol Parameter Min Typ Max Units

VPP Programming Enable Voltage 11.5 12.5 V

IPP Prog ramming Enable Current 250 µA

tDVXH Data and Control Valid before XTAL1 High 67 ns

tXLXH XTAL1 Low to XTAL1 High 200 ns

tXHXL XTAL1 Pulse Width High 150 ns

tXLDX Data and Control Hold after XTAL1 Low 67 ns

tXLWL XTAL1 Low to WR Low 0 ns

tXLPH XTAL1 Low to PAGEL high 0 ns

tPLXH PAGEL low to XTAL1 high 150 ns

tBVPH BS1 Valid befo re PAGEL High 67 ns

tPHPL PAGEL Pulse Width High 150 ns

tPLBX BS1 Hold after PAGEL Low 67 ns

tWLBX BS2/1 Hold after WR Low 67 ns

tPLWL PAGEL Low to WR Low 67 ns

tBVWL BS1 Valid to WR Low 67 ns

tWLWH WR Pulse Wi dth Low 150 ns

tWLRL WR Low to RDY/BSY Low 0 1 µs

tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms

tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 ms

tXLOL XTAL1 Low to OE Low 0 ns

XTAL1

ADDR0 (low byte) DATA (low byte) DATA (high byte) ADDR1 (low byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE) READ DATA

(HIGH BYTE) LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

242 ATmega162(V/U/L) 2513C–AVR–09/02

Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock

Bits commands.

2. tWLRH_CE is valid for the Chip Erase command.

Serial Downloading

SPI Serial Programming

Pin Mapping

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI

bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI

(input) an d MISO (output) . After RES ET is set low, the P rogram ming E nable i nstru ction

needs to be e xe cut ed firs t bef or e pro gr am/e rase op erati ons c an b e exec ut ed. NOTE , i n

Table 109 on page 242, the pin mapping for SPI programming is listed. Not all parts use

the SPI pins dedicated for the internal SPI interface.

Figure 105. SPI Serial Programming and Verify(1)

Note: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock

source to the XTAL1 pin.

When programming the EEPROM, an auto-erase c ycle is built into the sel f-timed pro-

gramming operation (in the Serial mode ONLY) and there is no need to first execute the

Chip E rase inst ruction. The Chip Era se operati on turns th e conten t of every m emory

location in both the Program and EEPROM arrays into 0xFF.

tBVDV BS1 Valid to DATA valid 0 250 ns

tOLDV OE Low to DATA Valid 250 ns

tOHDZ OE High to DATA Tr i-stated 250 ns

Table 108. Parallel Programming Characteristics, VCC = 5 V ± 10% (Continued)

Symbol Parameter Min Typ Max Units

Table 109. Pin Mapping SPI Serial Programming

Symbol Pins I/O Description

MOSI PB5 I Serial Data in

MISO PB6 O Serial Data out

SCK PB7 I Serial Clock

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

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Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high

periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

SPI Serial Programming

Algorithm When writing serial data to the ATmega162, data is clocked on the rising edge of SCK.

When reading data from the ATmega162, data is clocked on the fa lling edge of SCK.

See Figure 106.

To program and verify the ATmega162 in the SPI Serial Programming mode, the follow-

ing sequence is recommended (See four byte instruction formats in Table 111):

1. Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In

some systems, the programmer can not guarantee that SCK is held low during

Power-up. In this case, RESET must be given a positive pulse of at least two

CPU clock cycles duration after SCK has been set to “0”.

2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Pro-

gramming Enable serial instruction to pin MOSI.

3. The SPI Serial Programming instructions will not work if the communication is

out of synchronization. When in sync. the second byte (0x53), will echo back

when issuing the third byte of the Programming Enable instruction. Whether the

echo is correct or not, all four bytes of the instruction must be transmitted. If the

0x53 did not echo back, give RESET a positive pulse and issue a new Program-

ming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one

byte at a time by supplying the 6 LSB of the address and data together with the

Load Program Memory Page instruction. To ensure correct loading of the page,

the data low byte must be loaded before data high byte is applied for a given

address. The Program Memory Page is stored by loading the Write Program

Memory Page instruction with the 8 MSB of the address. If polling is not used,

the user must wait at leas t tWD_FLASH before issuing the next page. (See Table

110.) Accessing the SPI serial programming interface before the Flash write

operation completes can result in incorrect programming.

5. The EEPROM array can either be programmed one page at a time or it can be

programmed byte by byte.

For Page Programming, the following algorithm is used:

The EEPR OM memory page is load ed one byte at a time by supp lyin g the 2 LSB of

the address and data toge ther with the Load EEPROM Memory Pag e instructio n.

The EE PRO M M em o ry Pa ge i s s t or ed b y lo ad i ng th e Write EEPRO M M em o ry P a ge

instruction with the 8 MSB of the address. If polling is not used, the user must wait at

least tWD_EEPROM before is suing the ne xt page . (See Ta ble 100.) Acc essing the SPI

Serial Prog ramming interfac e before the EEP ROM write operation c ompletes can

result in incorrect programming.

Alteratively, the EEPROM can be programmed bytewise

The EEPROM array is programmed one byte at a time by supplying the address

and da ta to gethe r with th e Write EEPR OM in struc tion. An EEPR OM me mory lo ca-

tion is first automatically erased before new data is written. If polling is not used, the

user mu st wait a t least tWD_EEPROM before is suing th e next by te. (See Table 110 .) In

a chip erased device, no 0xFFs in the data file(s) need to be programmed.

244 ATmega162(V/U/L) 2513C–AVR–09/02

6. Any memory location can be verified by using the Read instruction which returns

the content at the selected address at serial output MISO.

7. At the end of the pro gr amm ing session, RES ET can be set high to commence

normal operation.

8. Power-off sequence (if needed):

Set RE SE T to “1”.

Turn VCC power off.

Data Polling Flash When a pa ge is being progr ammed into the Flash , reading an addres s location within

the page be in g progr am med will give the val ue 0x FF . At the time the devic e i s read y for

a new page, the programmed value will read correctly. This is used to determine when

the next page can be written. Note that the entire page is written simultaneously and any

address within the page can be used for polling. Data polling of the Flash will not work

for th e value 0xF F, so wh en progra mming th is value, the user will have to wa it for at

least tWD_FLASH bef ore p rogramm ing th e nex t page. As a chip erased devic e cont ains

0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be

skipped. See Table 110 for tWD_FLASH value .

Data Pol ling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the

address location being programmed will give the value 0xFF. At the time the device is

ready for a new byte, the programmed v alue will read correctly. T his is used to de ter-

mine when the next by te can be written. This will not work for the value 0xFF, but the

user should ha ve the fo llowin g in mind : As a chip erased device c ontain s 0xF F in all

locations, programming of addresses that are meant to contain 0xFF, can be skipped.

This does not apply if the EEPROM is re-programmed without chip erasing the device.

In this case, data polling c annot be used for the value 0xFF, and the user will have to

wait at least tWD_EEPROM before programming the next byte. See Table 110 for

tWD_EEPROM value.

Figure 106. SPI Serial Programming Waveforms

Table 110. Minimum Wait Delay before Writing the Next Flash or EEPROM Location

Symbol Minimum Wait Delay

tWD_FLASH 4.5 ms

tWD_EEPROM 9.0 ms

tWD_ERASE 9.0 ms

MSB

LSB

SERIAL CLOCK INPUT

(SCK)

SERIAL DATA INPUT

(MOSI)

(MISO)

SAMPLE

SERIAL DATA OUTPUT

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Table 111. SPI Serial Programming Instruction Set(1)

Instruction Instruction Format Operation

Byte 1 Byte 2 Byte 3 Byte4

Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming

after RESET goes low.

Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.

Read Program Memo ry 0010 H000 00aa aaaa bbbb bbbb oooo oooo Read H (hig h or low) data o from

Program memory at word address

a:b.

Load Program Memory

Page

0100 H000 00xx xxxx xxbb bbbb iiii iiii Write H (high or low) data i to

Program Memory page at word

address b. Data low byte must be

loaded before Data high byte is

applied within the sa me add res s.

Write Program Me mory

Page 0100 1100 00aa aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at

address a:b.

Read EEPROM Memory 1010 0000 00xx xxaa bbbb bbbb oooo oooo Read data o from EEPROM

memory at address a:b.

Write EEPROM Memory

(byte access) 1100 0000 00xx xxaa bbbb bbbb iiii iiii Write dat a i to EEPROM me mory

at address a:b.

Load EEPROM Memory

Page (page access)

1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory

page buffer. After data is loaded,

program EEPROM page.

Write EEPROM Memory

Page (page access) 1100 0010 00xx xxaa bbbb bb00 xxxx xxxx Write EEPROM page at address

a:b.

Read Lock Bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bi ts. “0” = p r og ram med,

“1” = unprogrammed. See Table

97 on page 228 for details.

Write Lo ck Bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to

program Lock bits. See Table 97

on page 228 for details.

Read Signature Byte 0011 0000 00xx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address

Write Fuse Bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram. See Table 101 on

page 230 for details.

Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to

unprogram. See Table 100 on

page 230 for details.

Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx xxxx xxii Set bits = “0” to program, “1” to

unprogram. See Table 99 on

page 229 for details.

Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed,

“1” = unprogrammed. See Table

101 on page 230 for details.

246 ATmega162(V/U/L) 2513C–AVR–09/02

Note: 1. a = address high bits, b = address low bits , H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care

Read Fuse High Bits

0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. “0” = pro-

grammed, “1” = unprogrammed.

See Table 100 on page 230 for

details.

Read Extended Fuse Bits

0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” =

pro-grammed, “1” =

unprogram m ed. See Table 99 on

page 229 for details.

Read Calibration Byte 0011 1000 00xx xxxx 0000 0000 oooo oooo Read Calibration Byte

Poll RDY/BSY

1111 0000 0000 0000 xxxx xxxx xxxx xxxoIf o = “1”, a programmi ng operati on

is still busy. Wait until this bit

returns to “0” before applying

another command.

Table 111. SPI Serial Programming Instruction Set(1) (Continued)

Instruction Instruction Format Operation

Byte 1 Byte 2 Byte 3 Byte4

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SPI Serial Programming

Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 264.

Programmi ng via the

JTAG In terface Pr ogramming through the JT AG interface requires control of the four JTA G specific

pins: TCK, TMS, TDI, and TDO. Control of the Reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The

device is default shipped with the Fuse programmed. In addition, the JTD bit in

MCUCSR mu st be cl ear ed . Al ternat iv ely , if the JT D bi t is set, the Extern al Re se t can be

forced low. Then, the JTD bit will be cleared after two chip clock s, and the JTAG pins

are available for programming. This provides a means of using the JTAG pins as normal

port pins in running mode while still a llowing In-System Programming v ia the JTAG

interface. Note that this technique can not be used when using the JTAG pins for

Boundar y-sca n or On -chip De bug. In t hese c ases th e JT AG pins must be dedi cated for

this purpo se .

As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific JTAG

Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG

instructions useful for Programming are listed below.

The OP CODE fo r each in struc tion is shown behind th e instru ctio n name in hex for mat.

The text describes which Data Register is selected as path between TDI and TDO for

each instruc ti on.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can

also be used as an idle state between JT AG sequences. The state machine sequence

for changing the instruction word is shown in Figure 107.

248 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 107. State machine sequence for changing the instruction word

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

011 1

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AVR_RESE T (0xC) The AVR s pecif ic public JTA G instr uctio n for sett ing the A VR device in the Reset mod e

or taking th e device out from t he Reset mode. The TAP con troller is not re set by this

instruction. The one bit Reset Register is selected as data register. Note that the r eset

will be active as long as there is a logic “one” in the Reset Chain. The output from this

chain is not latched.

The active stat es ar e:

• Shift-DR: The Reset Register is shifted by the TCK input.

PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port.

The 16- bit Prog rammi ng Ena ble Regi ster is sele cte d as data r egist er. The a ctiv e states

are the following:

• Shift-DR: The programming enable signature is shifted into the Data Register.

• Update-DR: The programming enable signature is compared to the correct value,

and Programming mode is entered if the signature is valid.

PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the

JTAG port. The 15-bit Programming Command Register is selected as data register.

The active states are the following:

• Capture-DR: The result of the previous command is loaded into the Data Register.

• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the

previous command and shifting in the new command.

• Update-DR: The programming command is applied to the Flash inputs.

• Run-Test/Idle: One clock cycle is generated, executing the applied command (not

always required, see Table 112 below).

PROG_PAGELOAD (0x6) The A VR spec ific p ublic JTA G ins tructio n to d irectly load the Flash data page via th e

JTAG port. The 1024 bit Virtual Flash Page Load Register is selected as register. This is

a virtual s ca n c hain wi th le ngt h equ al to the number of bits in o ne Fl as h pag e. In ter nally

the Shi ft Register is 8-bit. Unl ike most JTAG inst ructions, the U pdate- DR state is not

used to transfer data from the Shift Register. The data are automatically transferred to

the Flash page bu ffer byte-by-by te in the Shift-DR state by an intern al state machine.

This is the only active state:

• Shift-DR: Flash page data are shifted in from TDI by the TCK input, and

automatically loaded into the Flash page one byte at a time.

PROG_PAGEREAD (0x7) The AVR s pec if ic publ ic JT A G in stru ct ion to read one full Flas h da ta pag e vi a the J T AG

port. The 103 2 bit Virtual Flash Pa ge Read Regist er is selec ted as data regis ter. This is

a virtual scan chain with length equal to the number of bits in one Flash page plus eight.

Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR

state is no t u sed to tr ansfer d ata to the Shi ft Regi st er . The dat a are aut oma tical ly tr an s-

ferred from the Flash page buffer byte- by-byte in the Shift- DR state by an interna l state

machine. This is the only active state:

• Shift-DR: Flash data are automatically read one byte at a time and shifted out on

TDO by the TCK input. The TDI input is ignored.

Note: The JTAG instructions PROG_PAGELOAD and PROG_PAGEREAD can only be used if

the AVR devce is the first decive in JTAG scan chain. If the AVR cannot be the first

device in the scan chain, the byte-wise programming algorithm must be used.

250 ATmega162(V/U/L) 2513C–AVR–09/02

Data Registers The Data Registers are selected by the JTAG Instruction Registers described in section

“Programming Specific JTAG Instructions” on page 247. The Data Registers relevant for

programmi ng ope ra tio ns are:

• Reset Register

• Programming Enable Register.

• Programming Command Register.

• Virtual Flash Page Load Register.

• Virtual Flash Page Read Register.

Reset Register The Re set Regist er is a t est d ata r egiste r us ed t o rese t t he pa rt d uring prog rammin g. It

is required to reset the part before entering Programming mode.

A high value in the Reset Re gister corresp onds to pulling the ex ternal r eset low . The

part is reset as long as there is a high value pr esent in the Reset Register. Depending

on the fuse settings for the clock options, the part will remain reset for a Reset Time-out

period (refer to “Clock Sources” on page 34) after releasing the Reset Register. The out-

put fro m this data register is not latc hed, so the reset will ta ke place i mmediat ely, as

shown in Figure 86 on page 203.

Programming Enable Register The P rogramming Enabl e Register is a 16-bit register. The co ntents of this r egister is

compared to the programming enable signature, binary code 1010_0011_0111_0000.

When the conten ts of the register is equal to the programmi ng enable signature, pro-

gramming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset,

and should always be reset when leaving Programming mode.

Figure 108. Programming Enable Register

TDI

TDO

ClockDR & PROG_ENABLE

Programming Enable

0xA370

251

ATmega162(V/U/L)

2513C–AVR–09/02

Programming Command

ally shift in programming commands, and to serially shift out the result of the previous

command, if any. T he JTAG Programming Ins truction Set is shown i n Table 112. The

state sequence when shifting in the programming commands is illustrated in Figure 110.

Figure 109. Programming Command Register

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

252 ATmega162(V/U/L) 2513C–AVR–09/02

Table 112. JTAG Programming Instruction Set

Instruction TDI sequence TDO sequence Notes

1a. Chip eRase 0100011_10000000

0110001_10000000

0110011_10000000

xxxxxxx_xxxxxxxx

1b. Poll for Chip Erase complete 0110011_10000000 xxxxxox_xxxxxxxx (2)

2a. Enter Fl ash Write 0100011_00010000 xxxxxxx_xxxxxxxx

2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx

2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx

2f. Latch Data 0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

2g. Write Flash Page 0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

2h. Poll for Page Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2)

3a. Enter Fl ash Read 0100011_00000010 xxxxxxx_xxxxxxxx

3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

3d. Read Data Low and High Byte 0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

xxxxxxx_oooooooo low byte

high byte

4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx

4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx

4e. Latch Data 0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

4f. Write EEPROM Page 0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

(1)

4g. Poll for Page Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2)

5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx

5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)

5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

253

ATmega162(V/U/L)

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5d. Read Data Byte 0110011_bbbbbbbb

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

6a. E nter Fuse Write 0100011_01000000 xxxxxxx_xxxxxxxx

6b. Load Data Low Byte(6) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6c. Write Fuse Extended Byte 0111011_00000000

0111001_00000000

0111011_00000000

xxxxxxx_xxxxxxxx

(1)

6d. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2)

6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6f. Write Fuse High byte 0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

6g. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2)

6h. Load Data Low Byte(8) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3)

6i. Write Fuse Low Byte 0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

(1)

6j. Poll for Fuse Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2)

7a. E nter Lo ck Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx

7b. Load Data Byte(9) 0010011_11iiiiii xxxxxxx_xxxxxxxx (4)

7c. Write Lock Bits 0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

(1)

7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2)

8a. Enter Fu se/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx

8b. Read Fuse Extended Byte(6) 0111010_00000000

0111111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8c. Read Fuse High Byte(7) 0111110_00000000

0111111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8d. Read Fuse Low Byte(8) 0110010_00000000

0110011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8e. Read Lock Bits(9) 0110110_00000000

0110111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_xxoooooo (5)

Table 112. JTAG Programming Instruction Set (Continued)

Instruction TDI sequence TDO sequence Notes

254 ATmega162(V/U/L) 2513C–AVR–09/02

Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is

normally the case).

2. Repeat until o = “1”.

3. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse.

4. Set bits to “0” to program the corresponding lock bit, “1” to leave the Lock bit unchanged.

5. “0” = programmed, “1” = unprogrammed.

6. The bit mapping for Fuses Extended byte is listed in Table 99 on page 229.

7. The bit mapping for Fuses High byte is listed in Table 100 on page 230.

8. The bit mapping for Fuses Low byte is listed in Table 101 on page 230.

9. The bit mapping for Lock Bits byte is listed in Table 97 on page 228.

10.Address bits exceeding PCMSB and EEAMSB (Table 106 and Table 107) are don’t care

Note: a = address high bits

b = address low bits

H = 0 – Low byte, 1 – High Byte

o = data ou t

i = data in

x = don’t care

8f. Read Fuses and Lock Bits 0111010_00000000

0111110_00000000

0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

(5)

Fuse ext. byte

Fuse high byte

Fuse low byte

Lock bits

9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx

9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx

9c. Read Signature Byte 0110010_00000000

0110011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx

10b. Load Addres s Byte 00000 11_bbbbbbbb xxxxxxx_xxxxxxxx

10c. Read Calibration Byte 0110110_00000000

0110111_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

11a. Load No Operation Command 0100011_00000000

0110011_00000000 xxxxxxx_xxxxxxxx

xxxxxxx_xxxxxxxx

Table 112. JTAG Programming Instruction Set (Continued)

Instruction TDI sequence TDO sequence Notes

255

ATmega162(V/U/L)

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Figure 110. State Machine Sequence for Changing/Reading the Data Word

Virtual Flash Page Load

number of bits in one Flas h page. Inte rnally the Shift Registe r is 8-bit, and th e data are

automa tically tr ansferr ed to th e Flash page b uffer by te-by-by te. Shif t in al l inst ruction

words in the page, starting with the LSB of the first instruction in the page and ending

with the MSB of the last instruction in the page. This provides an efficient way to load the

entire Flash page buffer before executing Page Write.

Test-Logic-Reset

Run-Test/Idle

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-DR Scan

Capture-DR

011 1

256 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 111. Virtual Flash Page Load Register

Virtual Flash Page Read

number of bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the

data are automatically transferred from the Flash data page byte-by-byte. The first eight

cycles are used to transfer the first byte to the internal Shift Register, and the bits that

are shifted out during these right cycles should be ignored. Following this initialization,

data ar e shif ted o ut start ing with the LS B of the first i nstruc tion i n the pa ge and endin g

with the MSB of the last instruction in the page. This provides an efficient way to read

one full Flash page to verify programming.

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

STROBES

ADDRESS

State

Machine

257

ATmega162(V/U/L)

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Figure 112. Virtual Flash Page Read Register

Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 112.

Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift one in the Reset Register.

2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Pro-

gramming Enable Register.

Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS.

2. Disable all programming instructions by using no operation instruction 11a.

3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the Pro-

gramming Enable Register.

4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS.

2. Start Chip Erase using programming instruction 1a.

3. Poll for Chip Erase complete using programming instruction 1b, or wait for

tWLRH_CE (refer to Table 108 on page 241).

Programming the Flash 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load address high byte using programming instruction 2b.

4. Load address low byte using programming instruction 2c.

5. Load data using programming instructions 2d, 2e and 2f.

6. Repeat steps 4 and 5 for all instruction words in the page.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for

tWLRH_FLASH (refer to Table 108 on page 241).

TDI

TDO

Flash

EEPROM

Fuses

Lock Bits

STROBES

ADDRESS

State

Machine

258 ATmega162(V/U/L) 2513C–AVR–09/02

9. Repeat steps 3 to 7 until all data have been programmed.

A more efficient data transfer can be achieved using the PROG_PAGELOAD

instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load the page address using programming instructions 2b and 2c. PCWORD

(refer to Table 106 on page 233) is used to address within one page and must be

written as 0.

4. Enter JTAG instruction PROG_PAGELOAD.

5. Load the entire page by shifting in all instruction words in the page, starting with

the LSB of the first instruction in the page and ending with the MSB of the last

instruction in the page.

6. Enter JTAG instruction PROG_COMMANDS.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for

tWLRH_FLASH (refer to Table 108 on page 241).

9. Repeat steps 3 to 8 until all data have been programmed.

Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load address using programming instructions 3b and 3c.

4. Read data using programming instruction 3d.

5. Repeat steps 3 and 4 until all data have been read.

A more efficient data transfer can be achieved using the PROG_PAGEREAD

instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load the page address using programming instructions 3b and 3c. PCWORD

(refer to Table 106 on page 233) is used to address within one page and must be

written as 0.

4. Enter JTAG instruction PROG_PAGEREAD.

5. Read the entire page by shifting out all instruction words in the page, starting

with the LSB of the first instruction in the page and ending with the MSB of the

last instruction in the page. Remember that the first 8 bits shifted out should be

ignored.

6. Enter JTAG instruction PROG_COMMANDS.

7. Repeat steps 3 to 6 until all data have been read.

259

ATmega162(V/U/L)

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Programming the EEPROM 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM write using programming instruction 4a.

3. Load address high byte using programming instruction 4b.

4. Load address low byte using programming instruction 4c.

5. Load data using programming instructions 4d and 4e.

6. Repeat steps 4 and 5 for all data bytes in the page.

7. Write the data using programming instruction 4f.

8. Poll for EEPROM write complete using programming instruction 4g, or wait for

tWLRH (refer to Table 108 on page 241).

9. Repeat steps 3 to 8 until all data have been programmed.

Note: The PROG_PAGELOAD instruction can not be used when programming the EEPROM

Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM read using programming instruction 5a.

3. Load address using programming instructions 5b and 5c.

4. Read data using programming instruction 5d.

5. Repeat steps 3 and 4 until all data have been read.

Note: The PROG_PAGEREAD instruction can not be used when reading the EEPROM

Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse write using programming instruction 6a.

3. Load data low byte using programming instructions 6b. A bit value of “0” will pro-

gram the corresponding Fuse, a “1” will unprogram the Fuse.

4. Write Fuse extended byte using programming instruction 6c.

5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH

(refer to Table 108 on page 241).

6. Load data low byte using programming instructions 6e. A bit value of “0” will pro-

gram the corresponding Fuse, a “1” will unprogram the Fuse.

7. Write Fuse High byte using programming instruction 6f.

8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH

(refer to Table 108 on page 241).

9. Load data low byte using programming instructions 6h. A “0” will program the

Fuse, a “1” will unprogram the Fuse.

10. Write Fuse Low byte using programming instruction 6i.

11. Poll for Fuse write complete using programming instruction 6j, or wait for tWLRH

(refer to Table 108 on page 241).

Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Lock bit write using programming instruction 7a.

3. Load data using programming instructions 7b. A bit value of “0” will program the

corresponding Lock bit, a “1” will leave the Lock bit unchanged.

4. Write Lock bits using programming instruction 7c.

5. Poll for Lock bit write complete using programming instruction 7d, or wait for

tWLRH (refer to Table 108 on page 241).

260 ATmega162(V/U/L) 2513C–AVR–09/02

Reading the Fuses and Lock

Bits 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse/Lock bit read using programming instruction 8a.

3. To read all Fuses and Lock bits, use programming instruction 8f.

To only read Fuse Extended byte, use programming instruction 8b.

To only read Fuse High byte, use programming instruction 8c.

To only read Fuse Low byte, use programming instruction 8d.

To only read Lock bits, use programming instruction 8e.

Reading the Signature B ytes 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Signature byte read using programming instruction 9a.

3. Load address 0x00 using programming instruction 9b.

4. Read first signature byte using programming instruction 9c.

5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second

and third signature bytes, respectively.

Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Calibration byte read using programming instruction 10a.

3. Load address 0x00 using programming instruction 10b.

4. Read the calibration byte using programming instruction 10c.

261

ATmega162(V/U/L)

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Electrical Characteristics

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the d evic e. This is a stress rating only an d

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may af fect device

reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-1.0V to VCC+0.5V

Voltage on RESET with respect to Ground......-1.0V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ..................... ..... ...... ............... 40.0 mA

DC Current VCC and GND Pins................................ 200.0 mA

DC Characte ristics

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unl ess otherwise noted)

Symbol Parameter Condition Min. Typ. Max. Units

VIL Input Low Voltage Except XTAL1 pin -0.5 0.3 VCC(1) V

VIL1 Input Low Voltage XTAL1 pin, External

Clock Selected -0.5 0.1 VCC(1) V

VIH Input High Voltag e Except XTAL1 and

RESET pins 0.6 VCC(2) VCC + 0.5 V

VIH1 Input High Voltag e XTAL1 pin, External

Clock Selected 0.7 VCC(2) VCC + 0.5 V

VIH2 Input High Voltage RESET pin 0.9 VCC(2) VCC + 0.5 V

VOL Output Low Voltage(3)

(Ports A,B,C,D,E) IOL = 20 mA, VCC = 5V

IOL = 10 mA, VCC = 2.7V 0.7V

0.5V V

VOH Output High Voltage(4)

(Ports A,B,C,D,E) IOH = -20 mA, VCC = 5V

IOH = -10 mA, VCC = 2.7V 4.0

2.2 V

IIL Input Leakage

Current I/O Pin Vcc = 5.5V, pin low

(absolute value) 8µA

IIH Input Leakage

Current I/O Pin Vcc = 5.5V, pin high

(absolute value) 8µA

RRST Reset Pull-up Resistor 20 100 kΩ

Rpu I/O Pin Pull-up Resistor 20 100 kΩ

262 ATmega162(V/U/L) 2513C–AVR–09/02

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest value where the pin is guaranteed to be read as high

3. Although each I/O port can sink more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state

conditions (non-transient), the following must be observed:

PDIP Package:

1] The sum of all IOL, for all ports, should not exceed 300 mA.

2] The sum of all IOL, for port B0 - B7, D0 - D7, and XTAL2, should not exceed 150 mA.

3] The sum of all IOL, for ports A0 - A7, E0 - E2, C0 - C7, should not exceed 150 mA.

TQFP and MLF Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports B0 - B7, D0 - D7, and XTAL2, should not exceed 200 mA.

3] The sum of all IOL, for ports C0 - C7 and E1 - E2, should not exceed 200 mA.

4] The sum of all IOL, for ports A0 - A7 and E0, should no t exceed 200 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Althou gh eac h I /O port can source mo re th an the tes t c ond iti ons (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under stead y st at e

conditions (non-transient), the following must be observed:

PDIP Package:

1] The sum of all IOH, for all ports, should not exceed 300 mA.

2] The sum of all IOH, for port B0 - B7, D0 - D7, and XTAL2, should not exceed 150 mA.

3] The sum of all IOH, for ports A0 - A7, E0 - E2, C0 - C7, should not exceed 150 mA.

TQFP and MLF Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports B0 - B7, D0 - D7, and XTAL2, should not exceed 200 mA.

3] The sum of all IOH, for ports C0 - C7 and E1 - E2, should not exceed 200 mA.

4] The sum of all IOH, for ports A0 - A7 and E0, should not exceed 200 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

ICC

Power Supply Current

Active 4 MHz, VCC = 3V

(ATmega162L) 5mA

Active 8 MHz, VCC = 5V

(ATmega162) 15 mA

Idle 4 MHz, VCC = 3V

(ATmega162L) 2mA

Idle 8 MHz, VCC = 5V

(ATmega162) 7mA

Power-down mo de

WDT Enabled ,

VCC = 3.0V < 15 µA

WDT Disabl ed,

VCC = 3.0V < 1 µA

VACIO Analog Comparator

Input Offset Voltage VCC = 5V

Vin = VCC/2 40 mV

IACLK Analog Comparator

Input Leakage Current VCC = 5V

Vin = VCC/2 -50 50 nA

tACID Analog Comparator

Propagation Delay VCC = 2.7V

VCC = 4.0V 750

500 ns

DC Characteristics (Continued)

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unl ess otherwise noted)

Symbol Parameter Condition Min. Typ. Max. Units

263

ATmega162(V/U/L)

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External Clock Dr ive

Waveforms Figure 113. External Clock Drive Waveforms

External Clock Dr ive

Note: 1. R should be in the range 3 kΩ - 100 kΩ, and C sh ould be at least 20 pF. The C values

given in the table includes pin capacitanc e. This will vary with package type.

IL1

IH1

Table 113. External Clock Drive

Symbol Parameter

VCC = 1.8 - 3.6V VCC =2.7 - 5.5V VCC = 4.5 - 5.5V

UnitsMin. Max. Min. Max. Min. Max.

1/tCLCL

Oscillator

Frequency 0108016MHz

tCLCL Clock Period 1000 125 62.5 ns

tCHCX High Time 400 50 25 ns

tCLCX Low Time 400 50 25 ns

tCLCH Rise Time 2.0 1.6 0.5 µs

tCHCL Fall Time 2.0 1.6 0.5 µs

∆tCLCL

Change in

period from one

clock cy cl e to

the next

22 2%

Table 114. External RC Oscillator, Typical Frequencies(1)

R [kΩ]C [pF]f

100 70 TBD

31.5 20 TBD

6.5 20 TBD

264 ATmega162(V/U/L) 2513C–AVR–09/02

SPI Timing

Characteristics See Figure 114 and Figure 115 for details.

Figure 114. SPI Interface Timing Requirements (Master Mode)

Table 115. SPI Timing Parameters

Description Mode Min Typ Max

1 SCK period Master See Table 68

2 SCK high/low Master 50% duty cycle

3 Rise/Fall time Master TBD

4 Setup Master 10

5HoldMaster 10

6 Out to SCK Master 0.5 • tsck

7 SCK to out Master 10

8 SCK to out high Master 10

9 SS low to out Slave 15

10 SCK period Slave 4 • tck

11 SCK high/low Sla ve 2 • tck

12 Rise/Fall time Slave TBD

13 Setup Slave 10

14 Hold Slave tck

15 SCK to out Slave 15

16 SCK to SS high Slave 20

17 SS high to tri-state Slave 10

18 SS low to SCK Slave 2 • tck

MOSI

(Data Output)

SCK

(CPOL = 1)

MISO

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

345

265

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 115. SPI Interface Timing Requirements (Slave Mode)

MISO

(Data Output)

SCK

(CPOL = 1)

MOSI

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

11 11

1213 14

266 ATmega162(V/U/L) 2513C–AVR–09/02

External Data Memory Timing

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 116. External Data Memory Characteristics, 4.5 - 5.5 Volts, no Wait-state

Symbol Parameter

8 MHz Oscillator Va riable Oscillator

UnitMin Max Min Max

01/t

CLCL Os ci lla tor Freq uen cy 0.0 16 MHz

LHLL ALE Pulse Width 115 1.0tCLCL-10 ns

AVLL Address Valid A to ALE Low 57.5 0.5tCLCL-5(1) ns

3a tLLAX_ST

Address Hold After ALE Low,

write acces s 55 ns

3b tLLAX_LD

Address Hold after ALE Low,

read access 55 ns

AVLLC Address Valid C to ALE Low 57.5 0.5tCLCL-5(1) ns

AVRL Address Valid to RD Low 115 1.0tCLCL-10 ns

AVWL Address Valid to WR Low 115 1.0tCLCL-10 ns

LLWL ALE Low to WR Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) ns

LLRL ALE Low to RD Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) ns

DVRH Data Setup to RD High 40 40 ns

10 tRLDV Read Low to Data Valid 75 1.0tCLCL-50 ns

11 tRHDX Data Hold After RD High 0 0 ns

12 tRLRH RD Pulse Widt h 115 1 .0tCLCL-10 ns

13 tDVWL Data Setup to WR Low 42.5 0.5tCLCL-20(1) ns

14 tWHDX Data Hold After WR High 115 1.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 125 1.0tCLCL ns

16 tWLWH WR Pulse Width 115 1.0tCLCL-10 ns

Table 117. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state

Symbol Parameter

8 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

10 tRLDV Read Low to Data Valid 200 2.0tCLCL-50 ns

12 tRLRH RD P ulse Width 240 2.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 240 2.0tCLCL ns

16 tWLWH WR Pulse Width 240 2.0tCLCL-10 ns

267

ATmega162(V/U/L)

2513C–AVR–09/02

Table 118. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 ns

12 tRLRH RD P ulse Width 365 3.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 375 3.0tCLCL ns

16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns

Table 119. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 ns

12 tRLRH RD P ulse Width 365 3.0tCLCL-10 ns

14 tWHDX Data Hold After WR High 240 2.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 375 3.0tCLCL ns

16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns

Table 120. External Data Memory Characteristics, 2.7 - 5.5 Volts, no Wait-state

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

LHLL ALE Pulse Width 235 tCLCL-15 ns

AVLL Address Valid A to ALE Low 115 0.5tCLCL-10(1) ns

3a tLLAX_ST

Address Hold After ALE Low,

write access 55

3b tLLAX_LD

Address Hold after ALE Low,

read access 55

AVLLC Address Valid C to ALE Low 115 0.5tCLCL-10(1) ns

AVRL Address Valid to RD Low 235 1.0tCLCL-15 ns

AVWL Address Valid to WR Low 235 1.0tCLCL-15 ns

LLWL ALE Low to WR Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns

LLRL ALE Low to RD Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns

DVRH Data Setup to RD High 45 45 ns

10 tRLDV Read Low to Data Valid 190 1.0tCLCL-60 ns

11 tRHDX Data Hold After RD High 0 0 ns

268 ATmega162(V/U/L) 2513C–AVR–09/02

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

12 tRLRH RD P ulse Width 235 1.0tCLCL-15 ns

13 tDVWL Data Setup to WR Low 105 0.5tCLCL-20(1) ns

14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 250 1.0tCLCL ns

16 tWLWH WR Pulse Width 235 1.0tCLCL-15 ns

Table 120. External Data Memory Characteristics, 2.7 - 5.5 Volts, no Wait-state (Continued)

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

Table 121. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

10 tRLDV Read Low to Data Valid 440 2.0tCLCL-60 ns

12 tRLRH RD P ulse Width 485 2.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 500 2.0tCLCL ns

16 tWLWH WR Pulse Width 485 2.0tCLCL-15 ns

Table 122. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

10 tRLDV Read Low to Data Valid 690 3.0tCLCL-60 ns

12 tRLRH RD P ulse Width 735 3.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 750 3.0tCLCL ns

16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns

Table 123. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

10 tRLDV Read Low to Data Valid 690 3.0tCLCL-60 ns

12 tRLRH RD P ulse Width 735 3.0tCLCL-15 ns

14 tWHDX Data Hold After WR High 485 2.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 750 3.0tCLCL ns

16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns

269

ATmega162(V/U/L)

2513C–AVR–09/02

Figure 116. External Memory Timing (SRWn1 = 0, SRWn0 = 0

Figure 117. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) DataAddress

System Clock (CLKCPU)

8 12

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. addr.

DA7:0 Address Data

Prev. data XX

DA7:0 (XMBK = 0) DataAddress

System Clock (CLK

CPU

)

8 12

270 ATmega162(V/U/L) 2513C–AVR–09/02

Figure 118. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

Figure 119. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)

Note: 1. The ALE pulse in the last period (T4 - T7) is only present if the next instruction

accesses the RAM (internal or external).

ALE

T1 T2 T3

Write

Read

A15:8 Address

Prev. addr.

DA7:0 Address DataPrev. data XX

DA7:0 (XMBK = 0) Data

Address

System Clock (CLK

CPU

)

8 12

T4 T5

ALE

T1 T2 T3

Write

Read

A15:8

Address

Prev. addr.

DA7:0

Address DataPrev. data XX

DA7:0 (XMBK = 0)

Data

Address

System Clock (CLK

CPU

)

8 12

T4 T5 T6

271

ATmega162(V/U/L)

2513C–AVR–09/02

ATmega162 Typical

Characteristics –

Prelim inary Data

The following charts show typical behavior. T hese figures are not tested during manu-

facturing. All current consumption measurements are performed with all I/O pins

configured as inpu ts a nd with internal pul l-ups enabl ed. A sine wav e ge ner at or with rai l-

to-rail output is us ed as clock source. T he CKSEL Fuses are progr ammed to select

external clock.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: Operating voltage,

operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and

ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as

CL*VCC*f where CL = load c apac itance, VCC = o peratin g vol tage an d f = ave rage switc h-

ing frequency of I/O pin.

The parts ar e characte rized at freque ncies higher than test limi ts. Par ts are not guar an-

teed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog

Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif-

ferential current drawn by the Watchdog Timer.

272 ATmega162(V/U/L)  2513C–AVR–09/02
Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) Reserved – – – – – – – –
.. Reserved – – – – – – – –
(0x9E) Reserved – – – – – – – –
(0x9D) Reserved – – – – – – – –
(0x9C) Reserved – – – – – – – –
(0x9B) Reserved – – – – – – – –
(0x9A) Reserved – – – – – – – –
(0x99) Reserved – – – – – – – –
(0x98) Reserved – – – – – – – –
(0x97) Reserved – – – – – – – –
(0x96) Reserved – – – – – – – –
(0x95) Reserved – – – – – – – –
(0x94) Reserved – – – – – – – –
(0x93) Reserved – – – – – – – –
(0x92) Reserved – – – – – – – –
(0x91) Reserved – – – – – – – –
(0x90) Reserved – – – – – – – –
(0x8F) Reserved – – – – – – – –
(0x8E) Reserved – – – – – – – –
(0x8D) Reserved – – – – – – – –
(0x8C) Reserved – – – – – – – –
(0x8B) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 FOC3A FOC3B WGM31 WGM30 129
 (0x8A) TCCR3B ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 126
(0x89) TCNT3H Timer/Counter3 – Counter Register High Byte 131
 (0x88) TCNT3L Timer/Counter3 – Counter Register Low Byte 131
 (0x87) OCR3AH Timer/Counter3 – Output Compare Register A High Byte 131
(0x86) OCR3AL Timer/Counter3 – Output Compare Register A Low Byte 131
(0x85) OCR3BH Timer/Counter3 – Output Compare Register B High Byte 131
(0x84) OCR3BL Timer/Counter3 – Output Compare Register B Low Byte 131
(0x83) Reserved – – – – – – – –
(0x82) Reserved – – – – – – – –
(0x81) ICR3H Timer/Counter3 – Input Capture Register High Byte 132
(0x80) ICR3L Timer/Counter3 – Input Capture Register Low Byte 132
(0x7F) Reserved – – – – – – – –
(0x7E) Reserved – – – – – – – –
(0x7D) ETIMSK –– TICIE3 OCIE3A OCIE3B TOIE3 ––133
 (0x7C) ETIFR –– ICF3 OCF3A OCF3B TOV3 ––134
(0x7B) Reserved – – – – – – – –
(0x7A) Reserved – – – – – – – –
(0x79) Reserved – – – – – – – –
(0x78) Reserved – – – – – – – –
(0x77) Reserved – – – – – – – –
(0x76) Reserved – – – – – – – –
(0x75) Reserved – – – – – – – –
(0x74) Reserved – – – – – – – –
(0x73) Reserved – – – – – – – –
(0x72) Reserved – – – – – – – –
(0x71) Reserved – – – – – – – –
(0x70) Reserved – – – – – – – –
(0x6F) Reserved – – – – – – – –
(0x6E) Reserved – – – – – – – –
(0x6D) Reserved – – – – – – – –
(0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 86
(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 86
(0x6A) Reserved – – – – – – – –
(0x69) Reserved – – – – – – – –
(0x68) Reserved – – – – – – – –
(0x67) Reserved – – – – – – – –
(0x66) Reserved – – – – – – – –
(0x65) Reserved – – – – – – – –
(0x64) Reserved – – – – – – – –
(0x63) Reserved – – – – – – – –
(0x62) Reserved – – – – – – – –
(0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 39

273
ATmega162(V/U/L)
2513C–AVR–09/02
(0x60) Reserved – – – – – – – –
0x3F (0x5F) SREG I T H S V N Z C 8
0x3E ( 0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 11
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11
0x3C(2)(0x5C)(2) UBRR1H URSEL1 UBRR1[11:8] 187
UCSR1C URSEL1 UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 186
0x3B (0x5B) GICR INT1 INT0 INT2 PCIE1 PCIE0 – IVSEL IVCE 59, 84 
0x3A (0x5A) GIFR INTF1 INTF0 INTF2 PCIF1 PCIF0 – – –85
0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 100, 132, 152
0x38 (0x58) TIFR TOV1 OCF1A OCF1B OCF2 ICF1 TOV2 TOV0 OCF0 101, 134, 153
0x37 (0x57) SPMCR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 218
0x36 (0x56) EMCUCR SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 28,42,83
0x35 (0x55) M CUCR SRE SRW1 0 SE SM1 ISC11 ISC10 ISC01 ISC00 28,41,82
0x34 (0x54) MCUCSR JTD – SM2 JTRF WDRF BORF EXTRF PORF 41,49,204
0x33 (0x53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 98
0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) 100
0x31 (0x51) OCR0 Timer/Counter0 Output Compare Register 100
0x30 (0x50) SFIOR TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 30,68,103,154
0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 126
0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 129
0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 131
0x2C (0x4C) TCNT1L Timer/Counter1 – Counter  Register Low Byte 131
0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 131
0x2A (0x4A) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte 131
0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte 131
0x28 (0x48) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte 131
0x27 (0x47) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 147
0x26 (0x46) ASSR – – – – AS2 TCON2UB OCR2UB TCR2UB 150
0x25 (0x45) ICR1H Timer/Counter1 – Input Capture Register High Byte 132
0x24 (0x44) ICR1L Timer/Counter1 – Input Capture Register Low Byte 132
0x23 (0x43) TCNT2 Timer/Counter2 (8 Bits) 149
0x22 (0x42) OCR2 Timer/Counter2 Output Compare Register 149
0x21 (0x41) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 51
0x20(2) (0x40) (2) UBRR0H URSEL0 – – – UBRR0[11:8] 187
UCSR0C URSEL0 UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 186
0x1F (0x3F) EEARH – – – – – – – EEAR8 18
0x1E (0x3E) EEARL EEPROM Address Register Low Byte 18
0x1D (0x3D) EEDR EEPROM Data Register 19
0x1C (0x3C) EECR – – – – EERIE EEMWE EEWE EERE 19
0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 80
0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 80
0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 80
0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 80
0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 80
0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 80
0x15 (0x35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 80
0x14 (0x34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 80
0x13 (0x33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 81
0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 81
0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 81
0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 81
0x0F (0x2F) SPDR  SPI Data Register 161
0x0E (0x2E) SPSR SPIF WCOL – – – – –SPI2X 161
0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR 0 159
0x0C (0x2C) UDR0  USART0 I/O Data Register 183
0x0B (0x2B) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 183
0x0A (0x2A) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB8 0 184
0x09 (0x29) UBRR0L  USART0 Baud Rate Register Low Byte 187
0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 192
0x07 (0x27) PORTE – – – – – PORTE2 PORTE1 PORTE0 81
0x06 (0x26) DDRE – – – – – DDE2 DDE1 DDE0 81
0x05 (0x25) PINE – – – – – PINE2 PINE1 PINE0 81
0x04(1) (0x24) (1) OSCCAL Oscillator Calibration Register 37
OCDR On-chip Debug Register 199
0x03 (0x23) UDR1 USART1 I/O Data Register 183
0x02 (0x22) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 183
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

274 ATmega162(V/U/L) 2513C–AVR–09/02

Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this addres s. Refer to the debug-

ger specific documentation for details on how to use the OCDR Register.

2. Refer to the USART description for details on how to access UBRRH and UCSRC.

3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

4. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

0x01 (0x21) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 184

0x00 (0x20) UBRR1L USART1 Baud Rate Register Low Byte 187

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

275

ATmega162(V/U/L)

2513C–AVR–09/02

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh :Rdl ← Rdh:R dl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K S ubtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • KZ,N,V1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One ’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0x FF - K) Z,N, V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Mu ltiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Mu ltiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2

FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← k None 3

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← Z None 3

CALL k Direct Sub rou tine Call PC ← k None 4

RET Subroutine Return PC ← STAC K None 4

RETI Interrupt Return PC ← STAC K I 4

CPSE Rd,Rr Co mpare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

276 ATmega162(V/U/L) 2513C–AVR–09/02

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← K None 1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Sto re In d i re c t (X) ← Rr None 2

ST X +, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Sto re In d i re c t (Y) ← Rr Non e 2

ST Y +, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z) , Z ← Z+1 None 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← P None 1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd A rithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Fla g Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← T None 1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH S et Half Carry Flag in SREG H ← 1H1

Mnemonics Operands Description Operation Flags #Clocks

277

ATmega162(V/U/L)

2513C–AVR–09/02

CLH Clear Half Carry Flag in SREG H ← 0 H 1

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1

BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

278 ATmega162(V/U/L) 2513C–AVR–09/02

Ordering Information

Note: 1. This d evic e ca n al so be supplied in wafer form. Please conta ct y our loc al At me l sa les office for detail ed ordering information

and minimum quantities.

Speed (MHz) Power Supply Ordering Code Package Operation Range

1 1.8 - 3.6V ATmega162V-1AC

ATmega162V-1PC

ATmega162V-1MC

44A

40P6

44M1

Commercial

(0°C to 70°C)

8 2.4 - 4.0V ATmega162U-8AC

ATmega162U-8PC

ATmega162U-8MC

44A

40P6

44M1

Commercial

(0°C to 70°C)

8 2.7 - 5.5V ATmega162L-8AC

ATmega162L-8PC

ATmega162L-8MC

44A

40P6

44M1

Commercial

(0°C to 70°C)

ATmega162L-8AI

ATmega162L-8PI

ATmega162L-8MI

44A

40P6

44M1

Industrial

(-40°C to 85°C)

16 4.5 - 5.5V ATmega162-16AC

ATmega162-16PC

ATmega162-16MC

44A

40P6

44M1

Commercial

(0°C to 70°C)

ATmega162-16AI

ATmega162-16PI

ATmega162-16MI

44A

40P6

44M1

Industrial

(-40°C to 85°C)

Package Type

44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (MLF)

279

ATmega162(V/U/L)

2513C–AVR–09/02

Packaging Information

44A

1.20(0.047) MAX

10.10(0.394)

9.90(0.386) SQ

12.25(0.482)

11.75(0.462) SQ

0.75(0.030)

0.45(0.018) 0.15(0.006)

0.05(0.002)

0.20(0.008)

0.09(0.004) 0˚~7˚

0.80(0.0315) BSC

PIN 1 ID

0.45(0.018)

0.30(0.012)

PIN 1

*Controlling dimension: millimeter

44-lead, Thin (1.0mm) Plastic Quad Flat Package

(TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch.

Dimension in Millimeters and (Inches)*

JEDEC STANDARD MS-026 ACB

REV. A 04/11/2001

280 ATmega162(V/U/L) 2513C–AVR–09/02

40P6

52.71(2.075)

51.94(2.045) PIN

13.97(0.550)

13.46(0.530)

0.38(0.015)MIN

0.56(0.022)

0.38(0.015)

REF

15.88(0.625)

15.24(0.600)

1.65(0.065)

1.27(0.050)

17.78(0.700)MAX

0.38(0.015)

0.20(0.008)

2.54(0.100)BSC

3.56(0.140)

3.05(0.120)

SEATING

PLANE

4.83(0.190)MAX

48.26(1.900) REF

0º ~ 15º

40-lead, Plastic Dual Inline

Package (PDIP), 0.600" wide

Dimension in Millimeters and (Inches)*

JEDEC STANDARD MS-011 AC

*Controlling dimension: Inches

REV. A 04/11/2001

281

ATmega162(V/U/L)

2513C–AVR–09/02

44M1

2325 Orchard Parkway

San Jose, CA 95131 TITLE

44M1, 44-pad ,7 x 7 x 1.0 mm body, lead pitch 0.50mm

Micro lead frame package (MLF)

DRAWING NO. REV

08/29/01

44M1

SEATING PLANE

TOP VIEW

BOTTOM VIEW

SIDE VIEW

Marked pin#1 identifier

PIN #1 CORNER

(*Unit of Measure = mm)

COMMON DIMENSIONS

SYMBOL MIN NOM MAX NOTE

E2 5.00 5.20 5.40

L 0.35 0.55 0.75

5.00 5.20 5.40

0.80 0.90 1.00

0.00 0.02 0.05

0.18 0.23 0.30

0.25 REF

7.00 BSCD

E 7.00 BSC

e 0.50 BSC

NOTE 1. JEDEC STANDARD MO-220, Fig 1 (Saw Singulation), VKKD-1

282 ATmega162(V/U/L) 2513C–AVR–09/02

Data Sheet Change

Log for ATmega162 Please note that the referring page numbers in this section are referred to this docu-

ment. The referring revision in this section are referring to the document revision.

Changes from Rev.

2513A -0 5/ 02 to Re v.

2513B-09/02

1. Added information for ATmega162U.

Information about ATmega162U included in “Features” on page 1, Table 19,

“BODLEVEL Fuse Coding,” on page 48, and “Ordering Information” on page 278.

Changes from Rev.

2513B -0 9/ 02 to Re v.

2513C-09/02

1. Canged the Endurance on the Flash to 10,000 Write/Erase Cycles.

i
ATmega162(V/U/L)
2513C–AVR–09/02
Table of Contents Features.............. .... ..... ..... .............................................. ..... ..... .... .........  1
Pin Configurations................................................................................  2
Disclaimer............................................................................................................. 2
Overview........ ..... .... ........................ .... ..... ..... .........................................  3
Block Diagram ...................................................................................................... 3
ATmega161 and ATmega162 Compatibility......................................................... 4
Pin Descriptions.................................................................................................... 5
About Code Examples.......................................................................................... 6
AVR CPU Core ................. .... ..... ............................................................  7
Introduction........................................................................................................... 7
Architectural Overview.......................................................................................... 7
ALU – Arithmetic Logic Unit.................................................................................. 8
Status Register..................................................................................................... 8
General Purpose Register File ........................................................................... 10
Stack Pointer ...................................................................................................... 11
Instruction Execution Timing............................................................................... 12
Reset and Interrupt Handling.............................................................................. 12
AVR ATmega162 Memories...............................................................  15
In-System Reprogrammable Flash Program Memory........................................ 15
SRAM Data Memory........................................................................................... 16
EEPROM Data Memory...................................................................................... 18
I/O Memory......................................................................................................... 23
External Memory Interface.................................................................................. 24
XMEM Register Description................................................................................ 28
System Clock and Clock Options .....................................................  33
Clock Systems and their Distribution.................................................................. 33
Clock Sources..................................................................................................... 34
Default Clock Source.......................................................................................... 34
Crystal Oscillator................................................................................................. 34
Low-frequency Crystal Oscillator........................................................................ 36
Calibrated Inte rnal RC Osci ll ator ........................ ...... ....... ...... .................... ...... ... 37
External Cloc k. ....... ...... ....... ...... ...... ....... ................... ....... ...... ....... ...... ....... ...... ... 38
Clock output buffer.............................................................................................. 39
Timer/Counter Oscillator..................................................................................... 39
System Clock Prescaler...................................................................................... 39
Power Management and Sleep Modes..............................................  41
Idle Mode............................................................................................................ 42
Power-down Mode.............................................................................................. 42
Power-save Mode............................................................................................... 43
Standby Mod e........ ...... ....... ................... ...... ....... ...... ....... ...... ....... ...... ................ 43

ii ATmega162(V/U/L)  2513C–AVR–09/02
Extended Standby Mode .................................................................................... 43
Minimizing Power Consumption ......................................................................... 44
System Control and Reset.................................................................  45
Internal Voltage Reference................................................................................. 50
Watchdog Timer ................................................................................................. 50
Timed Sequences for Changing the Configuration of the Watchdog Timer ....... 54
Interrupts.............................................................................................  55
Interrupt Vectors in ATmega162......................................................................... 55
I/O-Ports ...............................................................................................  61
Introduction......................................................................................................... 61
Ports as General Digital I/O................................................................................ 62
Alternate Port Functions..................................................................................... 66
Register Description for I/O-Ports....................................................................... 80
External Interrupts..............................................................................  82
8-bit Timer/Counter0 with PWM.........................................................  87
Overview............................................................................................................. 87
Timer/Counter Clock Sources............................................................................. 88
Counter Unit........................................................................................................ 89
Output Compare Unit.......................................................................................... 89
Compare Match Output Unit............................................................................... 91
Modes of Operation............................................................................................ 92
Timer/Counter Timing Diagrams......................................................................... 96
8-bit Timer/Counter Register Description ........................................................... 98
Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers ....  
102
16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)........  104
Restriction in ATmega161 Compatibility Mode................................................. 104
Overview........................................................................................................... 104
Accessing 16-bit Registers............................................................................... 107
Timer/Counter Clock Sources........................................................................... 110
Counter Unit...................................................................................................... 110
Input Capture Unit............................................................................................. 111
Output Compare Units...................................................................................... 113
Compare Match Output Unit............................................................................. 115
Modes of Operation.......................................................................................... 116
Timer/Counter Timing Diagrams....................................................................... 124
16-bit Timer/Counter Register Description ....................................................... 126

iii
ATmega162(V/U/L)
2513C–AVR–09/02
8-bit Timer/Counter2 with PWM and Asynchronous operation....  136
Overview........................................................................................................... 136
Timer/Counter Clock Sources........................................................................... 137
Counter Unit...................................................................................................... 138
Output Compare Unit........................................................................................ 138
Compare Match Output Unit............................................................................. 140
Modes of Operation.......................................................................................... 141
Timer/Counter Timing Diagrams....................................................................... 145
8-bit Timer/Counter Register Description ......................................................... 147
Asynchronous operation of the Timer/Counter................................................. 150
Timer/Counter Prescaler................................................................................... 154
Serial Peripheral Interface – SPI...................................................... 155
SS Pin Functionality.......................................................................................... 159
Data Modes ...................................................................................................... 162
USART ........... ..... .... ..... ......................................................................  163
Dual USART..................................................................................................... 163
Clock Generation.............................................................................................. 165
Frame Formats ................................................................................................. 168
USART Initialization.......................................................................................... 169
Data Transmission – The USART Transmitter................................................. 170
Data Reception – The USART Receiver .......................................................... 172
Asynchronous Data Reception ......................................................................... 176
Multi-processor Communication Mode............................................................. 179
Accessing UBRRH/
UCSRC Registers ...................................................................................................... 181
USART Register Description............................................................................ 183
Examples of Baud Rate Setting........................................................................ 188
Analog Comparator......... .... ..... ....................... ..... ..... .... ..... ..............  192
JTAG Interface and On-chip Debug System.................................. 194
Features............................................................................................................ 194
Overview........................................................................................................... 194
Test Access Port – TAP.................................................................................... 194
TAP Controller.................................................................................................. 197
Using the Boundary-scan Chain....................................................................... 197
Using the On-chip Debug system..................................................................... 198
On-chip debug specific JTAG instructions........................................................ 199
On-chip Debug Related Register in I/O Memory.............................................. 199
Using the JTAG Programming Capabilities...................................................... 199
Bibliography...................................................................................................... 200

iv ATmega162(V/U/L)  2513C–AVR–09/02
IEEE 1149.1 (JTAG) Boundary-scan ............................................... 201
Features............................................................................................................ 201
System Overview.............................................................................................. 201
Data Registers.................................................................................................. 202
Boundary-scan Specific JTAG Instructions ...................................................... 203
Boundary-scan Chain....................................................................................... 205
ATmega162 Boundary-scan Order................................................................... 210
Boundary-scan Description Language Files..................................................... 213
Boot Loader Support – Read-While-Write Self-programming......  214
Features............................................................................................................ 214
Application and Boot Loader Flash Sections.................................................... 214
Read-While-Write and No Read-While-Write Flash Sections........................... 214
Boot Loader Lock Bits....................................................................................... 216
Entering the Boot Loader Program................................................................... 218
Addressing the Flash During Self-programming............................................... 220
Self-programming the Flash ............................................................................. 221
Memory Programming......................................................................  228
Program And Data Memory Lock Bits .............................................................. 228
Fuse Bits........................................................................................................... 229
Signature By tes .................. ................... ...... ....... ...... ....... ...... ....... ................... . 231
Calibration Byte ................................................................................................ 231
Parallel Programming Parameters, Pin Mapping, and Commands.................. 231
Parallel Programming....................................................................................... 233
Serial Downloading........................................................................................... 242
SPI Serial Programming Pin Mapping.............................................................. 242
Programming via the JTAG Interface ............................................................... 247
Electrical Characteristics.................................................................  261
External Clock Drive Waveforms...................................................................... 263
External Clock Drive......................................................................................... 263
SPI Timing Characteristics ............................................................................... 264
External Data Mem or y Timing ..................... ....... ................... ....... ...... ....... ...... . 266
ATmega162 Typical Characteristics – Preliminary Data............... 271
Register Summary............................................................................ 272
Instruction Set Summa ry......... ..... .............................................. ..... 275
Ordering Information........................................................................  278

ATmega162(V/U/L)

2513C–AVR–09/02

Packaging Information..................................................................... 279

44A ................................................................................................................... 279

40P6 ................................................................................................................. 280

44M1................................................................................................................. 281

Data Sheet Change Log for ATmega162 ........................................ 282

Changes from Rev. 2513A-05/02 to Rev. 2513B-09/02................................... 282

Changes from Rev. 2513B-09/02 to Rev. 2513C-09/02................................... 282

Table of Contents .................................................................................. i

vi ATmega162(V/U/L) 2513C–AVR–09/02

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2513C–AVR–09/02 0M

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