DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT125
Quad buffer/line driver; 3-state
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT125
FEATURES
•Output capability: bus driver
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT125 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled
by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a HIGH impedance OFF-state.
The “125” is identical to the “126” but has active LOW enable inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr= tf= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW):
PD= CPD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in V
∑(CL×VCC2×fo) = sum of outputs
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay nA to nY CL= 15 pF; VCC =5V 9 12 ns
C
Iinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per buffer notes 1 and 2 22 24 pF
December 1990 3
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT125
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 4, 10, 13 1OE to 4OE outputs enable inputs (active LOW)
2, 5, 9, 12 1A to 4A data inputs
3, 6, 8, 11 1Y to 4Y data outputs
7 GND ground (0 V)
14 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
(a) (b)
Fig.4 Functional diagram. Fig.5 Logic diagram (one buffer).
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
INPUTS OUTPUT
nOE nA nY
L
L
H
L
H
X
L
H
Z
December 1990 4
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT125
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL=50pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA to nY 30 100 125 150 ns 2.0 Fig.6
11 20 25 30 4.5
9 17 21 26 6.0
tPZH/ tPZL 3-state output enable time
nOE to nY 41 125 155 190 ns 2.0 Fig.7
15 25 31 38 4.5
12 21 26 32 6.0
tPHZ/ tPLZ 3-state output disable time
nOE to nY 41 125 155 190 ns 2.0 Fig.7
15 25 31 38 4.5
12 21 26 32 6.0
tTHL/ tTLH output transition time 14 60 75 90 ns 2.0 Fig.6
5 12 15 18 4.5
4 10 13 15 6.0
December 1990 5
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT125
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL=50pF
INPUT UNIT LOAD COEFFICIENT
nA, nOE 1.00
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA to nY 15 25 31 38 ns 4.5 Fig.6
tPZH/ tPZL 3-state output enable time
nOE to nY 15 28 35 42 ns 4.5 Fig.7
tPHZ/ tPLZ 3-state output disable time
nOE to nY 15 25 31 38 ns 4.5 Fig.7
tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6
December 1990 6
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT125
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : VM= 1.3 V; VI= GND to 3 V.
