TOSHIBA THLY64805 1FG-80,-80L,-10,-10L TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 8,388,608-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THLY648051FG is a 8,388,608-word by 64-bit synchronous dynamic RAM module consisting of four TC59SM716FT/FTL DRAMs on a printed circuit board. FEATURES @ 8,388,608-word by 64-bit organization @ Single power supply of 3.3V +0.3V @ Pipeline architecture -80 10 @ Auto-refresh and Self-refresh capability tcx Clock Cycle Time (CL = 2) 10ns 12ns e@ All inputs and outputs LVTTL-compatible tras Active-to-Precharge Command 48 ns 60 ns Period (min) e@ 4096 refresh cycles per 64ms tac Access Time from CLK(CL = 2) | 6ns 8ns @ Package: 144-pin small-outline DIMM tre Ref/Active-to-Ref/Active 68 ns 84 ns (gold contacts) Command Period (min) PIN ASSIGNMENT PIN NAMES FRONT s to All ress In BAO, 1 Bank Select In #S0 Chip Select /RAS Row Address Strobe mn WE E BO to 7 Disable / Write Mask BACK oe SIE O2 60 62 1440 SDA Serial Data/Address for PD PD VDD Power (+3.3 VSS Ground 1] VSS 2] VSS 49] DQ13 50] DQ45 97] DQ22 98] DQ54 3[DQ0 4[DQ32 51/DQ14 52] DQ46 99/DQ23 100] DQ55 5[DQi 6| DQ33 53| DQ15 54] DQ47 101| VDD 102| VDD 7[DQ2 8/DQ34 55| vss 56] VSS 103] A6 104| A7 3|DQ3 10] DQ35 57| NC 58] NC 105] AS 106| BAO 11| VDD 12] VDD 59| NC 60] NC 107| VSS 108| VSS 13] DQ4 14] DQ36 61| CLKO 62| CKE 109] A9 710] BAI 15|DQ5 16| DQ37 63| VDD 64| VDD 111[A10 712[A11 17] DQ6 18] DQ38 65| /RAS 66| (CAS 113] VDD 114] VDD 19| DQ7 20|DQ39 67| WE 68| NC 715| DQMB2 716| DQMB6 21| VSS 22| VSS 69] /CSO 70] NC 117| DQMB3 718] DQMB7 23| DQMBO 24] DQMB4 711 NC 72| NC 119] VSS 120| VSS 25| DQMB1 26| DQMB5 73| NC 74] NC 121| DQ24 122| DQ56 27| VDD 28| VDD 75| VSS 76| VSS 123] DQ25 124| DQS7 29[ AO 30/A3 77| NC 78] NC 125| DQ26 126| DQ58 31[Al 32|A4 79| NC 80| NC 127| DQ27 128| DQ59 33| A2 34| A5 $1| VDD 82| VDD 129] VDD 730| VDD 35| VSS 36] VSS 83| DQI6 84] DQ48 131| DQ28 132] DQ60 37| DQB 38] DQ40 85/DQI7 86] DQ49 133| DQ29 134| DQ61 39| DQ9 40|DQ41 87| DQi18 88| DQ50 735|DQ30 736| DQ62 41] DQ10 42] DQ42 89] DQ19 90] DQ51 137|DQ31 138| DQ63 43|DQ11 44] DQ43 91| vss 92| vss 139| vss 140| vss 45| VDD 46| VDD 93| DQ20 94] DQ52 141[SDA 142[ SCL 47|DQ12 48| DQ44 95] DQ21 96| DQ53 143] VDD 144] VDD 000707EBA2 @ TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices, or TOSHIBA Semiconductor Reliability Handbook etc.. @ The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (Unintended Usage). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION far any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 2000-07-14 1/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L Serial Presence Detect (Rev.1.2A) Byte ; ; -80 -10 Number Function Described Entry Value Entry Entry Value Entry 0 mio bytes Written into Serial Memory at Module 128bytes 80h 128bytes 80h 1 Total # bytes of SPD Memory Device 256bytes 08h 256bytes 08h 2 (PPM EDO. SDRAM) frome Appendix A SDRAM 04h SDRAM 04h 3 # Row Addresses on this Assembly RAO-RA11 0Ch RAO-RA11 0Ch 4 # Column Addresses on this Assembly CA0-CAB 09h CA0-CAB 09h 5 # Module Banks on this Assembly 1Bank Oth 1Bank Oth 6 Data Width of this Assembly... x64 40h x64 40h 7 ..Data Width Continuation x64 00h x64 00h 8 Voltage Interface Standard of this Assembly LVTTL Oth LVTTL Oth 9 epRam Cycle Time at Max. Supported CAS Latency (CL), CL = 3, 8.0ns 80h CL = 3, 10ns Aoh 10 SDRAM Access from Clock @ CL = X CL = 3, 6.0ns 60h CL = 3, 7.0ns 70h 11 DIMM Configuration Type (Non-parity, Parity, ECC) Non-Parity 00h Non-Parity 00h 12 Refresh Rate/Type 15.625 ysiselt 80h 15.625 ysiself 80h 13 SDRAM Width, Primary DRAM x16 10h x16 10h 14 Error Checking SDRAM Data Width N/A 00h N/A 00h 15 minimum Clock Delay, Back to Back Random Column 41CLK Oth 1CLK Oth 16 Burst Lengths Supported 1,2,4,8 Full page 8Fh 1,2,4,8 Full page 8Fh 17 # Banks on each SDRAM Device 4Bank 04h 4Bank 04h 18 CAS # Latencies Supported 2,3 06h 2,3 06h 19 Cs # Latency Oth Oth 20 WE # Latency Oth Oth 21 SDRAM Module Attributes 00h 00h 22 SDRAM Device Attributes: General OEh OEh 23 Minimum Clock Cycle Time at CL- X-1 CL = 2, 10 ns AOdh CL = 2, 12 ns coh 24 Maximum Data Access Time from Clock @ CL X-1 CL = 2, 6.0ns 60h CL = 2, 8.0ns 80h 25 Minimum Clock Cycle Time at CL X-2 00h 00h 26 Maximum Data Access Time from Clock @ CL X-2 00h 00h 27 Minimum Row Precharge Time 20 ns 14h 24ns 18h 28 Minimum Row Active to Row Active Delay 20 ns 14h 20 ns 14h 29 Minimum RAS to CAS Delay 20 ns 14h 24ns 18h 30 Minimum RAS Pulse Width 48 ns 30h 60 ns 3Ch 31 Madule/Bank Density 64 MB 10h 64 MB 10h 32 Command & Address signal Input Set-up Time 2ns 20h 2.5 ns 25h 33 Command & Address signal Input Hold Time Ins 10h Ins 10h 34 Data signal Input Set-up Time 2ns 20h 2.5 ns 25h 35 Data signal Input Hold Time Ins 10h Ins 10h 36-61 Superset Information (may be used in future) FFh FFh 62 SPD Revision Rev.1.2A 12h Rev.1.2A 12h 63 Checksum for bytes 0-62 1ED1h Dth 1F5Fh 5Fh Option Manufacturers JEDEC ID Code per JEP-106E Manufacturing Location Manufacturer's Part Number Revision Code Manufacturing Date Serial Number Manufacturer Data Reserved Reserved Intel Specification Intel Specification Intel Specification Intel Specification 2000-07-14 2/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L BLOCK DIAGRAM cs0O cs LDQgM@ Fo DQmB0 RAS RAS vor ee pao CAS CAS M1 vos /-e paz CKE CKE upom / Dame WE WE ves Lo ae CLK : : : AO to 11, BS0,1 W016 DO1s +1 CS LDQM FO DQMB2 W- RAS VO1 _? DQ16 CAS M2 vos -- pa23 CKE upqgm /-o pame3 WE vag F-? pa24 CLK : : : AO to 11,BS0,1 016 pQ3t Ss Lbom - DQmB4 CLKQ o fr cs RAS Wot - 0932 CAS M3 vos -- paQ39 CKE oo Uupqgm /_o Domes WE vQ9 F paao CLK ! : ! AO to 11,BS0,1 016 pQ47 Lt LDQM F DQMB6 Wit L_| pas vo1 - peas CAS M4 vos -- pass CKE upqgm /_o bome7 WE a9 F- pass CLK : : : AO to 11,BS0,1 O16 ba6? AO to 11, BAO, 1 Vpp @ M1to4 Vpp @ E2PROM V rc1 to 4 =C5 to 8 7c9 to 12 Vv. t C13 sso Mito4 E2PROM 10.0 10 pF 5 cLK1 owt scLojsc. F*PROM cpa} 4 cpa AO Al A2. WC I T T l 777 2000-07-14 3/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L ABSOLUTE MAXIMUM _ RATINGS SYMBOL ITEM RATING UNIT NOTES Vin Input Voltage -0.5 to Vpp + 0.3 Vv 1 Vout Output Valtage -0.5 to Vpp + 0.3 Vv 1 Vop Power Supply Voltage -0.5 to 46 Vv 1 Topr Operating Temperature 0 to 70 c 1 Tst Storage Temperature -55 to 125 C 1 Pp Power Dissipation 1.2 Ww 1 lout Short Circuit Output Current 50 mA 1 RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to 70C) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES Vopp Supply Voltage 3.0 3.3 3.6 Vv 2 Vin LVTTL Input High Voltage 2.0 - Vop + 0.3 V 2 VIL LVTTL Input Low Voltage -0.5 - 0.8 Vv 2 CAPACITANCE (Vpp = 3.3V,f = 1MHz, Ta = 0 to 70C) SYMBOL PARAMETER MIN MAX UNIT Cy Input Capacitance (AO to A11) - T.B.D. pF Cio Input Capacitance (RAS, CAS, WE) - T.B.D. pF C3 Input Capacitance (CLKO) - T.B.D. pF Cia Input Capacitance (C50) - T.B.D. pF Cs Input Capacitance (DQMBO to 7) - T.B.D. pF Cog /O Capacitance (DQO0 to DQ63) - T.B.D. pF 2000-07-14 4/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L DC CHARACTERISTICS (Vpp = 3.3V + 0.3V, Ta = 0 to 70C) -80 -10 SYMBOL ITEM UNIT | NOTES MIN MAX MIN MAX lec OPERATING CURRENT 1 . Active-Precharge Command . Cycling without Burst Operation 1-Bank Operation ~ 320 ~ 280 mA 3 lcc1B | (tex = tre min) STANDBY CURRENT lec2 (tee = min, CS = Vin, CKE = Vip - 160 - 140 nA ; Vinvi = Vin (min) / Vi, (max) CKE = Vi. Icc2p | Bank: Inactive State) (Power-down Mode) 7 4 ~ 4 STANDBY CURRENT lecas (CLK = Vi, CS = Vin, CKE = Vin - 40 - 40 aA Vint = Vin (min) /V\_ (max) CKE = Vi, lcc2zps_ | Bank: Inactive State) (Power-down Mode) 7 4 7 4 lec3 NO OPERATING CURRENT CKE = Vin - 180 - 160 (tex = min, CS = Viq (min) CKEZV mA 3 lcc3p_| Bank: Active State (2 Banks)) (Power-Down Mode) - 40 - 40 BURST OPERATING CURRENT leca ; . - 440 - 360 mA 3,4 (te, = min, CS = Vin (min) Read/Write Command Cycling) AUTO-REFRESH CURRENT lecs . . - 720 - 600 mA 3 (tex = min, Auto-Refresh Command Cycling) SELF-REFRESH CURRENT THLY648051FG-80, -10 - 4 - 4 cc6 | (self-Refresh Mode, CKE = 0.2V mA 3 (Self-Refresh Mode, CKE = 0.2V) [111 vago51FG-80L,-10L | 2.4 - 2.4 | INPUT LEAKAGE CURRENT ; 5 5 5 A (1) | (OV S Viv S Vpp, All Other Pins Not under Test = 0V) e OUTPUT LEAKAGE CURRENT 5 5 5 5 A Oth) (Dout Is Disabled, OV S Vout s Vpp) e OUTPUT LEVEL Vou 2.4 - 2.4 - Vv LVTTL Output H Level Voltage (loyt = -2mA) OUTPUT LEVEL Voi - 0.4 - 0.4 Vv LVTTL Output L Level Voltage (lout = 2 MA) 2000-07-14 5/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Vpp = 3.3V + 0.3V, Ta = 0 to 70C) SYMBOL PARAMETER oan 80 TAX aN 7 TAK UNIT | NOTES tre Ref/Active-Ref/Active Command Period 68 84 tras Active- Precharge Command Period 48 100000 60 100000 ns treo Active-Read/Write Command Delay Time 20 24 9 tec Read/Write(a) Read/Write(b) 1 1 cycle Command Period tre Precharge-Active Command Period 20 24 trrp Active(a)-Active(b) Command Period 20 20 twr Write Recovery Time CcL* = 2 10 12 CL* = 3 8 10 tek CLK Cycle Time CL* = 2 10 1000 12 1000 CL* = 3 8 1000 10 1000 tey CLK High Level Width 3 3 10 te CLK Low Level Width 3 3 tac Access Time from CLK cL* =2 6 CL* = 3 6 7 ton Output Data Hold Time 3 3 tuz Qutput Data High Impedance Time 3 8 3 10 ns 8 tiz Output Data Low Impedance Time 0 0 tsp Power-down Mode Entry Time 0 8 0 10 tr Transition Time of CLK (Rise and Fall) 0.5 10 0.5 10 tps Data-in Set-up Time 2 2.5 toy Data-in Hold Time 1 1 tas Address Set-up Time 2 2.5 tay Address Hold Time 1 1 teks CKE Set-up Time 2 2.5 tekH CKE Hold Time 1 1 tems Command Set-up Time 2 2.5 tem Command Hold Time 1 1 trer Refresh Time 64 64 ms trsc Made Register Set Cycle Time 16 20 ns 9 * CL is CAS latency. 2000-07-14 6/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L NOTES: 1. Conditions outside the limits listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltages are referenced to Vss. 3. These parameters depend on the cycle rate and their values are measured at the minimum cycle rate values tcx and trc. Input signals are changed once during tcx. 4, These parameters depend on the output loading. The specified values are obtained with the output open. 5. The power-up sequence is described in Note 11. 6. AC TEST CONDITIONS Reference Level of Output Signals 1AV/1.4V Output Load See the diagram for AC Test Load (B) below Input Signal Levels 2.4V/0.4V Transition Time (Rise and Fall) of Input Signals 2ns Reference Level _of Input Signals 1.4V 3.3V 1.4V > 2kO S500 Output oF- Output TL. 50 pF z 870.0 a al 50 pF AC TEST LOAD (A) AC TEST LOAD (B) 7. Transition times are measured between the Vjq and Vj, levels. Transition (rise and fall) of input signals has a fixed slope. 8. tyz defines the time at which the outputs go open circuit and are not reference levels. 9. These parameters depend on the number of clock cycles and depend on the operating frequency of the clock as follows: Number of clock cycles = Specified value of timing / Clock period (Round up fractions to a whole number. ) 2000-07-14 7/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L 10. 11. tcy is the pulse width of CLK measured from the positive edge to the negative edge and referenced to Vyiy (min). tcy, is the pulse width of CLK measured from the negative edge to the positive edge and referenced to Viz (max). Power-up Sequence Power-up must be performed in the following sequence. 1) Power must be applied to Vpp and VppQ (simultaneously) with all input signals heldin the NOP state. The CLK signal must be started at the same time as power is applied. 2) After power-up a pause of at least 200 seconds is required. Then, DQM and CKE must be held High (at the Vpp level) to ensure that the DQ output is high-impedance. 3) Both banks must be precharged. 4) The Mede Register Set command must be asserted to initialize the Mode register. 5) An Auto-Refresh operation must consist of at least eight Auto-Refresh cycles. The order in which 4) and 5) are performed is interchangeable. 2000-07-14 8/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L Mode Register Set Cycle CLK t TF MS tomy trsc us ZY tems temH A } tems tomy ~ ath tems | tcMH we Ye YZ tas tay |<<] A0toA11, Set Register Data BAO, 1 AO Al Burst Length A2 A3 | Addressing Mode A4 AS CAS Latency AG A7 | 0 | (Test Mode) A8& | 0 Reserved AI Write Mode A10} 0 BAO! 0 Reserved BA1] 0 a] > NR =/]/=/-|o|lolo|lo z =|/[o/o/]-|-|o/|o Next Command Burst L uential Interleave 1 1 2 4 8 Reserved Reserved A3 Addressing Mode 0 Sequential 1 Interleave CAS Lat Reserved Reserved 2 3 4 Single-Write Mode Burst Read and Burst Write Burst Read and Single Write 2000-07-14 9/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L TIMING DIAGRAMS Read Timing Read CAS Latency PN NF LS CLK j AO to All, BAO, 1 t tac tac _, tuz CAC tz ton ton. DQ0 to 63 VALID VALID R DATA-OUT DATA-OUT Read Command I } Burst Length 2000-07-14 10/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L Command Input Timing tex te. ton Vin la ww Lp NL gh NLL a tr tr tems. | tomy temH t te a" te tomH ms Vi te tomy ( tc tcmH We Yl) tas taH AO to A11, BAO, { Vii tes teKH teks} tcKH teks teKH CKE Yi \ \ \ 7 2000-07-14 11/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L Control Timing for Input Data (Word Mask) tomy tems} tcmy tems ocMeo to 7 tyr vy tos} ton tos} ton tps} toy tps tpy <_$<_\_| (SS) $< | VALID VALID VALID VALID DQO to 63 DATA-IN DATA-IN DATA-IN DATA-IN 4 pL (Clock Mask) CLK _* \ 4 P\ teKH teks | tcKH teks <> CKE \ i f tos} tpH tps | tpy tps} toy tps] tpy ed | ~<a |~<___>-| fe} <___>} ee |__| D00 3 OM VALID VALID V7 yy" VALID VN VALID 20 to Zq_DATAIN KZN DATA-IN AZ ZN __DATA-IN KZN DATA-iN KZN Control Timing for Output Data (Output Enable) tcMH tems} tcmH tems <> a DQMBO to 7 f - \ \ Lj i tac tac _, tuz | tou \ tou | ton _, VALID VALID DQO to 63 DATA-OUT DATA-OUT (Clock Mask) CLK f \_j tcKH teks | tekH teks <> 1 Y J fy CKE LK Li tac \ tac _| tac _| tac _| tou | tou ton toH VALID VALID DQO to 63 DATA-OUT VALID DATA-OUT DATA-OUT 2000-07-14 12/13TOSHIBA THLY64805 1FG-80,-80L,-10,-10L PACKAGE DIMENSIONS (THLY648051FG) Unit: mm FRONT 67.60 + 0.13 3.80 MAX ~ = = ~ 7 S > oOo oO OQ OQ Ho] tH N S| 3) 8 | = in q st I 3.30 + 0.13 23.20 4.60 1.00 + 0.10 2.00 + 0.13 63.60 REF BACK 3.70 + 0.13 | CONTACT DIMENSIONS @ THLY648051FG FRONT 2.55MIN 4.00 +0.10 FULL-R 0.60 + 0.05 | 1.50 + 0.10 <>! 2.50 Weight: g (typ) 4.60 Contacts: gold 2000-07-14 13/13