NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals Field-programmable microcontroller peripheral Key Features May, 1993 OQ Single Chip Programmable Peripheral for Microcontroller-based Applications Q 19 Individually Configurable I/O pins that can be used as: Microcontroller I/O port expansion Programmable Address Decoder (PAD) VO Latched address output Open drain or CMOS 1 Two Programmable Arrays (PAD A & PAD B) Total of 40 Product Terms and up to 16 Inputs and 24 Outputs Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging Logic replacement Q No Glue Microcontroller Chip-Set Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode 8-bit data bus width ALE and Reset polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS PSEN pin for 8051 users QC) Built-In Page Logic To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities Upto 16 pages bE D WB 6653924 0071870 &Tb MBSICS Preliminary specification PSD312 Ft t1963 512 Kbits of UV EPROM Configurable as 64K x 8 Divides into 8 equal mappable biocks for optimized mapping Block resolution is 8K x 8 120 ns EPROM access time, including input latches and PAD address decoding. 16 Kbit Static RAM Configurable as 2K x 8 120 ns SRAM access time, including input latches and PAD address decoding Address/Data Track Mode Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor CMiser-Bit Programmable option to further reduce power consumption Built-In Security Locks the PSD312 and PAD Decoding Configuration Available in a Choice of Packages 44 Pin PLCC and CLCC 52 Pin POFP Simple Menu-Driven Software: Configure the PSD312 on an IBM PC Pin and Function Compatible with the PSD31XNAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals Field-programmable microcontroller peripheral BLE D MM 6653924 0071871 732 MESIC3 Preliminary specification PSD312 Security Security Mode in the PSD3XX locks the software. In window packages, the mode is Mode contents of the PAD A, PAD B and all the erasable through UV full part erasure. In configuration bits. The EPROM, SRAM, the security mode, the PSD3XxX contents and I/O contents can be accessed only cannot be copied on a programmer. through the PAD. The Security Mode can be set by the MAPLE or Programming CMiser-Bit The CMiser-Bit provides a programmable In the default mode, or if the PSD3XxX< is option for power-sensitive applications that configured without programming the require further reduction in power CMiser-Bit (CMiser = 0), the device consumption. The CMiser-Bit (CMiser = 1) operates at specified speed and power in the Maple portion of the PSD3XX sytem rating as specified in the A.C. and D.C. development software can be used to Characteristics. reduce power consumption. The CMiser-Bit However, if the CMiser-Bit is programmed turns off the EPROM blocks in the PSD3XX . : : (CMiser = 1), the device consumes even whenever the EPROM is not accessed, . ; . lower current, and is reflected in the data thereby reducing the active current heet. Thi de h dder i consumed by the PSD3XX. sneet, (nis mode has an adder in propagation delay in T5, T6, and T7 parameters in the A.C. Characteristics, and should be added to compute worst-case timing requirements in the application. Absolute Symbo!| Parameter Condition Min | Max | Unit nevonst T Storage Temperature CERDIP = 65 + 150 c gs sv ge emp PLASTIC e5 | +125| C Voltage on any Pin With Respect to GND | -0.6 +7 Vv Programming . Vep Supply Voltage With Respect to GND | -0.6 +14 Vv Voc Supply Voltage With Respect to GND | -0.6 +7 Vv ESD Protection >2000 Vv NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. and functional operation of the device at theses or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. . Operating Vee Tolerance Range Range Temperature Vee ce -12 15 -20 Commercial 0 C to +70C +5V + 10% +10% | +10% Industrial 40 C to +80C +5V +10% | +10% Military 55 C to +125C +5V +10% Recommended Symbol Parameter Conditions Min | Typ | Max | Unit Conditions Veco Supply Voltage All Speeds 45 5 5.5 Vv Vin High-level Input Voltage | Voc =4.5Vto55V 2 Vv Vit Low-level Input Voltage Veco =45Vto5.5V 0 0.8 Vv May, 1993 96NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals blE D 6653924 OO7L47?e 679 MBSIC3 Preliminary specification Field-programmable microcontroller peripheral PSD312 DC CMiser = 1 Characteristics | symbol| Parameter _| Conditions Subtract: Min | Typ | Max| Min) Typ | Max | Unit lo. = 20 pA 0.01 | 0.1 Vv Vo. Output Low Veco =4.5V Voltage lo. = 8 MA Voc =4.5V 0.15 | 0.45 Vv lou = -20 WA 4.4 |449 Vv Vou Output High Veo = 4.5 V Voltage lon = -2 MA Veen 45V 2.4 | 3.9 v Voc Standby Comm't 50 | 100 pA Ispi Current (CMOS) : (Notes 2 and 4) ind/Mil 75 | 150 pA Comm'! (Note 6) 16 | 35 7 10 | mA Active Current Comm (CMOS) (No (Note 7) 28 | 50 7 10 | mA ere Internal Memory - Block Selected) asta 16 | 45 7 | 10 | ma (Notes 2and5) _|_(Note 6) Ind/Mil (Note 7) 28 | 60 7 10 | mA Comm (Note 6) 16 | 35 0 O | mA Active Current Comm't 28 | 50 o | o |ma loce (CMOS) (EPROM | (Note 7) Block Selected) Ind/Mil (Notes 2 and5) | (Note 6) 16 | 45 O | 0 | mA Ind/Mil (Note 7) 28 | 60 0 0 | mA Comm! (Note 6) 47 | 80 7 10 | mA Active Current Comm't 59 | 95 7 10 | mA loca (CMOS) (SRAM _ | (Note 7) Block Selected Ind/Mil (Notes 2 and 5) {Note 6) 47 | 100 7 10 | mA tInd/Mil (Note 7) 59 | 115 7 10 | mA { Input Leakage Vin =5.5V _ Lt Current or GND 4 7+0.14} 1 pA | Output Leakage Vout =5.5V | _. Lo Current or GND 10) #5 | 10 yA NOTES: 2. CMOS inputs: GND + 0.3 V or Voc + 0.3V. 3. TIL inputs: Vi < 0.8 V, Vin 2 2.0 V. 4. CSVA19 is high and the part is in a power-down configuration mode. 5. Add 3.0 mA/MHz for AC power component (power = AC + DC). 6. Ten (10) PAD product terms active. (Add 380 LA per product term, typical, or 480 pA per product term maximum 7. Forty-one (41) PAD product terms active. May, 1993 97NAPC/PHILIPS SEMICOND bLE D MM 6653924 0071873 505 MBSICS Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD312 AC Characteristics -90 12 15 -20 Symbol Parameter CMiser 3S 1) unit Min | Max | Min | Max | Min | Max| Min|Max| Add: T1 ALE or AS Pulse Width 20 30 40 50 0 ns T2 Address Set-up Time 5 9 12 15 0 ns T3 Address Hold Time 8 9 12 15 0 ns Leading Edge of Read T4 | to Data Active 0 0 0 0 0 ns T5 ALE Valid to Data Valid 100 130 160 200 10 ns T6 Address Valid to Data Valid 90 |. 120 150 200 10 ns T7 | CSI Active to Data Valid 100 130 160 200 15 ns Leading Edge of Read T8 to Data Valid 32 38 55 60 0 ns T9 Read Data Hold Time 0 0 0 0 0 ns T10 Trailing Edge of Read to Data High-Z 32 32 35 40 0 ns T11 Trailing Edge of ALE or AS to Leading Edge of Write 0 0 0 0 0 ns RD, &, PSEN, or DS T12 Pulse Width 40 45 60 75 0 ns Ti2A | WR Pulse Width 20 25 35 45 0 ns Trailing Edge of Write or T13 Read to Leading Edge 0 0 0 0 0 ns of ALE or AS Address Valid to Traiting T14 Edge of Write 90 120 150 200 0 ns CSI Active to Trailing Edge T15 of Write 100 130 160 200 0 ns T16 Write Data Set-up Time 20 25 30 40 0 ns T17 Write Data Hold Time 5 5 10 15 0 ns Port to Data Out Valid T18 Propagation Delay 30 30 35 45 0 ns T19 Port Input Hold Time 0 0 0 0 0 ns Trailing Edge of Write T20 | to Port Output Valid 40 40 50 60 0 ns T2q | ADior Control to CSOI 6 |25|6]30| 6 | 35] 5 | 45 0 ns Valid ADi or Control to CSOi T22 Invalid 5 25 5 30 4 35 4 45 0 ns May, 1993 98NAPC/PHILIPS SEMICOND bE D MM 6653924 OO7L874 441 MBSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD312 AC Characteristics (Cont.) -90 -12 15 20 | omiser <1 Symbol Parameter - - - - iser= 1) unit Min | Max | Min | Max | Min | Max| Min|Max| Add: Track Mode Address T23 Propagation Delay: 22 22 28 28 0 ns CSADOUT1 Already True Track Mode Address Propagation Delay: T23A CSADOUT1 Becomes 38 33 50 50 0 ns True During ALE or AS Track Mode Trailing Edge T24 of ALE or AS to Address 32 32 35 40 0 ns High-Z Track Mode Read T25 Propagation Delay 29 29 35 35 0 ns Track Mode Read T26 Hold Time 11 29 11 29 10 29 10 35 0 ns Track Mode Write Cycle, 727 Data Propagation Delay 20 20 30 30 o ns Track Mode Write T28 Cycle, Write to Data 8 30 8 30 7 40 7 55 0 ns Propagation Delay Hold Time of Port A T29 Valid During Write 2 2 2 2 0 ns CSOi Trailing Edge T30 | CSiActive to CSOi Active | 9 | 40 | 9 | 45 | 9 | 50] 8 | 60 0 ns CSI Inactive to CSOi 731 Inactive 9 40 9 45 9 50 8 60 0 ns Direct PAD Input as T32 Hold Time 10 10 12 15 0 ns 133 | R/W Active to E or DS Start | 20 20 30 40 0 ns 134 | Eor DS Endto RAW 20 20 30 40 0 ns T35 AS Inactive to E high 0 0 0 0 0 ns Address to Leading T36 Edge of Write 20 20 25 30 0 ns NOTES: 8. ADi = any address line. GSOi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port C (CS8-CS10). 10. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or RM, transparent PCO-PC2, ALE (or AS). 11. Control signals RD/E/DS or WR or RW. ar May, 1993 99NAPC/PHILIPS SEMICOND bLE D WM 66539924 0071875 3486 MBSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD312 Figure 1. Timing of 8-Bit Multiplexed Address/DataBus, CRRWR = 0 READ CYCLE WRITE CYCLE 32 CSVAI9 as CSI 15 32 STABLE INPUT STABLE INPUT 6 Direct (12) PAD Input Multiptexed (13) Inputs 10 14 AO/ADO- ATIAD7 ADDRESS A DATA VALID ADDRESS B 2 3 9 3 Active High ALE Active Low ALE RD/E/DS as RD BHE/PSEN as PSEN WA/Vpp or RW as WAR Any of PAO-PA7 as I/O Pin Any of PBO-PB7 as I/O Pin Any of PAO-PA7 Pins as Address Outputs ADDRESS A ADDRESS B See referenced notes on page 106. May, 1999 100NAPC/PHILIPS SEMICOND bB1E D MM 66535924 0071876 214 MBSIC3 Philips Semiconductors Microcontroller Peripherais Preliminary specification Field-programmable microcontroller peripheral PSD312 Figure 2. Timing of 8-Bit Multiplexed Address/DataBus, CRRWR = 1 READ CYCLE WRITE CYCLE 32 CSVA19 as CSI 15 32 i 12) p AD Int 2) STABLE INPUT STABLE INPUT Multiplexed (13) Inputs 10 14 AQ/ADO- - ATIAD? ADDRESS A DATA VALID ADDRESS B 2 3 9 3 Active High AS Active Low AS RD/E/DS as E RDvE/DS as DS WRWVpp or RW as R/W Any of PAO-PA7 as (/O Pin Any of PBO-PB7 as I/O Pin Any of PAO-PA7 Pins as Address Outputs ADDRESS A ADDRESS B See referenced notes on page 106. May, 1993 101NAPC/PHILIPS SEMICOND bLE D MB 6653924 0071877? 150 MBSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD312 Figure 3. Timing of 8-Bit Data, Non-Multiplexed Address/DataBus, CRRWR = 0 READ CYCLE WRITE CYCLE 32 CSI/A19 as CSI Direct (12) PAD Input STABLE INPUT STABLE INPUT 6 14 A0/ADO- A15/AD15 STABLE INPUT STABLE INPUT as A0-A15 32 Multiplexed (13) Inputs 10 PAO-PA7 DATA VALID 9 Active High ALE Active Low ALE ADVE/DS as AD WR/Vpp_or RAW as WR Any of PBO-PB7 as I/O Pin See referenced notes on page 106. May, 1993 102NAPC/PHILIPS SEMICOND blE D MM 66539e4 0071878 O57 MBSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD312 Figure 4. Timing of 8-Bit Data, Non-Multiplexed Address/DataBus, CRRWR = 1 READ CYCLE WRITE CYCLE 32 CSVAI9 as CSI i 12) PAD Inet STABLE INPUT STABLE INPUT 6 4 A0/ADO- AIS/AD15 STABLE INPUT STABLE INPUT as AO-A15 32 Muttiplexed (13) Inputs 10 PAO-PA7 DATA VALID 9 Active High ALE Active Low ALE RD/E/DS as E RDOVE/DS as DS WRVpp or RW as RAW Any of PBO-PB7 as V/O Pin See referenced notes on page 106. May, 1993 103NAPC/PHILIPS SEMICOND bLE D MM 6653924 0071879 Te3 MBSICS3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD312 Figure 5. Chip-Select Output Timing 30 31 csiaig ~ \ J as CSI 4 Direct PAD "?) y ee _X INPUT STABLE Multiplexed (18) f PAD Inputs x N 2, 3 ALE ~ (Multiplexed AT,\ Made Only) | orALE \ y (Multiplexed Vl A Mode Only) 21 22 a > -P- GSor (14.19) \ fy A See referenced notes on page 106. May, 1993 104NAPC/PHILIPS SEMICOND BLE D MB 6653924 0071480 745 MSTICS Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD312 Figure 6. Port A as ADO-AD7 Timing (Track Mode), CRRWR = 0 READ CYCLE WRITE CYCLE Direct PAD Input STABLE INPUT STABLE INPUT (12,15) 2 Multiplexed PAD Inputs STABLE INPUT STABLE INPUT (16,18) 2 3 26 3 AO/ADO- A7/AD7 ADDRESS DATA VALID ADDRESS ALE or ALE RDvE/DS as RD WR/Vpp oF RW as WR 24 PAO-PA7 ADR OUT DATA IN ADR OUT csoi (14,17) See referenced notes on page 106. May, 1993 105NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals bLE D M@@ 6653924 0071861 681 MESIC3 Preliminary specification Field-programmable microcontroller peripheral PSD312 Figure 11. Port A as ADO-AD7 Timing (Track Mode), CRRWR = 1 READ CYCLE WRITE CYCLE Direct PAD Input STABLE INPUT STABLE INPUT (12,15) Multiplexed PAD Inputs STABLE INPUT STABLE INPUT (16,18) 2 3 96 3 AOIADO- ADDRESS DATA VALID ADDRESS AS or AS RO/E/DS as E ROvE/DS as DS WAWVpp or RW as RW 24 PAO-PA7 DATA IN ADR OUT CSOi (14,17) Notes for 12. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, Timing RD/E, WR or RW, transparent PCO-PC2, ALE in non- multiplexed modes. 13. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS): Diagrams AO/ADO-A15/AD15, CSVA19 as ALE dependent A19, ALE dependent PCO-PC2. May, 1993 14, CSGi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port C (CS58-CS10). 15. CSADOUT1, which internally enables the address transfer to Port A, should be derived only from direct PAD input signals, otherwise the address propagation delay is slowed down. 16. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively, can be derived from any combination of direct PAD inputs and multiplexed PAD inputs. 17. The write operation signals are included in the CSOi expression. 18. Multiptexed PAD inputs: any of the following PAD AD inputs that are latched by the ALE (or AS) in the multiplexed modes: A11/AD11-A15/AD15, GSVA19 as ALE dependent A19, ALE dependent PCO-PC2. 19. CSOI product terms can include any of the PAD input signals except for reset and CSI. 106NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals b1E D MM 6653924 0071442 S18 MSIC3 Preliminary specification Field-programmable microcontroller peripheral PSD312 Pin _ Symbol Parameter Conditions | Typical?" | Max | Unit Capacitance Cin Capacitance (for input pins only) Vin=OV 4 6 pF Cout | Capacitance (for input/output pins) Vout = 0 V 8 12 pF Cypp | Capacitance (for WR/Vpp or RAW/Vpp) | Vpp =0 V 18 25 pF NOTES: 20. This paramter is only sampled and is not 100% tested. 21. Typical values are for Ty = 25C and nominal supply voltages. Figure 8. AC Testing Input/Output 30V Waveform x 4 C TEST POINT > 15V OV Figure 9. 2.01V AC Testing Load Circult 195.0 DEVICE UNDER TEST CG, = 30 pF (INCLUDING == SCOPE ANDJIG = CAPACITANCE) Erasure and To clear all locations of their programmed sources at 2537 A, exposure to fluorescent Programming contents, expose the device to ultra-violet light and sunlight eventually erases the May, 1993 light source. A dosage of 15 W second/cm? is required. This dosage can be obtained with exposure to a wavelength of 2537 A and intensity of 12000 p W/cm? for 15 to 20 minutes. The device should be about 1 inch from the source, and all filters should be removed from the UV light source prior to erasure. The PSD3XxX and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although the erasure times will be much longer than with UV 107 device. For maximum system reliability, these sources should be avoided. If used in such an environment, the package windows should be covered by an opaque substance. Upon delivery, or after each erasure, the PSD3XxX device has all bits in the PAD and EPRON in the 1 or high state. The config- uration bits are in the 0 or low state. The code, configuration, and PAD MAP data are loaded through the procedure of programming.NAPC/PHILIPS SEMICOND BLE D MM 6653924 00718863 454 MBSICI Philips Semiconductors Microcontroller Peripherals _ Preliminary specification Field-programmable microcontroller peripheral PSD312 Pin 44-Pin 52-Pin Assignments Pin Name PLEC/CLEC PQFP Package Package PSEN 1 46 WR/Vpp or R/(W 2 47 RESET 3 48 PB7 4 49 PB6 5 50 PBS 6 51 PB4 7 2 PB3 8 3 PB2 9 4 PB1 10 5 PBO 1 6 GND 12 7 ALE or AS 13 8 PA7 14 9 PAG 15 10 PA5 16 1 PA4 17 12 PA3 18 15 PA2 19 16 PAI 20 17 PAO 24 18 RD/E/DS 22 19 ADO/AD 23 20 AD1/A1 24 21 AD2/A2 25 22 ADS/A3 26 23 AD4/A4 27 24 ADS5/A5 28 25 AD6/AG 29 28 AD7/A7 30 29 A8 31 30 Ag 32 31 A10 33 32 GND 34 33 Att 35 34 A12 36 35 A13 37 36 A14 38 37 A15 39 38 PCO 40 Al PC1 41 42 PC2___ 42 43 A19/CSI 43 44 Voc 44 45 NOTE: 36. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect. May, 1993 108NAPC/PHILIPS SEMICOND BLE D MM 6653524 00714884 390 MBSICS Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD312 Package Information 2 6 _ - & Ig Figure 10. ras g2858 Drawing 4 gegSe fetes 44 Pin Ceramic PRR RRR Leaded Chip pps 7 PU sats Carrler (CLEC) PBS 8 ~ r] ; i 1) 38 Ai4 with Window pp? 9 3 ph 37 ais (Package Type L) PBI 10 1 N36 A12 PBO 11 cc 35 A11 GND 12 00 34 GND ALE orAS 13 Tj 33 A10 PA7 14 C77) 32 Ag PAG 15 cc") 31 As PAS 16 ge] 30 AD7Z/A7 PA4 17 rT] 20 ADG/AG 2SA2RRRRSRKRER 22229222232 (TOP VIEW) e228 a3 Figure 11. Drawing J2 5 44 Pin Plastic kj 3S B Leaded Chip ~ e228 o8a58 Carrier (PLCC geagee 2888 with Window eorourSases (Package Type J) iu i PB4 7 TU) 39 At5 PB3 8 oT) 39 A114 PB2 9 1] 37 A13 PB1 10 mc 36 Ai2 PBO 11 iN 35 Ait GND 12 "7 34 GND ALE or AS 13 "T] 33 A10 PAT 14 wg) 32 A9 PAG 15 (1) 34 AS PAS 16 C7 30 AD7/A7 PA4 17 oc") 29 ADG/AG 2SSRatRaRegS o g = Oo 2 orn ono ct 2 (TOP VIEW) Boe GS SAREE e@aadcaca May, 1993 109NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals bLE D MM 6653924 0071885 227 MBSIC3 Preliminary specification Field-programmable microcontroller peripheral PSD312 Figure 12. Drawing Q2 - 52 Pin POFP = (Package Type Q) bE * . & gBSS8ER sf958 Sasssesessseygss NODA OOOO OO / N\ OQ nc 1 C4 {139 NC Ppa 2 CO {38 AIS Pps 3 C4 (337 Al4 Pe2 4 Co ()36 A13 PB1 5 C4 35 A12 pBo 6 C4 [34 All enp 7 C3 [] 33 GND ALEor AS 8 [7] [132 A10 Pa7 9 [4 [731 Ao Pas 10 Cj [30 As Pas 11 Co [29 AD7/A7 Pas 12 CI [128 ADG/AG nc 13 [7 [127 NC \ / UUUUUUUUUUU UY TLEELSSeHRzRRK Peee eb es 355? @<<<acdc<e (TOP VIEW) May, 1993 140NAPC/PHILIPS SEMICOND blE D MM 6653924 00714846 163 MBSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD312 Ordering Overati Spd.| Package | Package| ~-PETa""9 | manufacturin Information Part Number (as) Type. Drawing Tempera | Procedure 7 ge PSD312-90 A 90 | 44-pin PLCC J2 Commercial Standard PSD312-90 KA 90 | 44-pin CLCC L4 Commercial Standard PSD312-12 A 120 | 44-pin PLCC J2 Commercial Standard PSD312-12 KA | 120 | 44-pin CLCC L4 Commercial Standard PSD312-12 B 120 | 52-pin PQFP Q2 Commercial Standard PSD312-15 A 150 | 44-pin PLCC J2 Commercial Standard PSD312-151A 150 | 44-pin PLCC J2 Industrial Standard PSD312-15 KA | 150 | 44-pin CLCC L4 Commercial Standard PSD312-151 KA | 150 | 44-pin CLCC L4 Industrial Standard PS$D312-15 B 150 | 52-pin PQFP Q2 Commercial Standard PS$D312-151 B 150 | 52-pin PQFP Q2 Industrial Standard PSD312-20 A 200 | 44-pin PLCC J2 Commercial Standard PSD312-201 A 200 | 44-pin PLCC J2 Industrial Standard PSD312-20 KA | 200 | 44-pin CLCC L4 Commercial Standard PSD312-201KA | 200 | 44-pin CLCC L4 industrial Standard PSD312-20 B 200 | 52-pin PQFP Q2 Commercial Standard PSD312-201 B 200 | 52-pin PQFP Q2 Industrial Standard May, 1993 11