1. General description
The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. It is defined in accordance with the
JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity
checking function in a compatible pinout. The JEDEC standard for SSTU32866 is pending
publication. The register is configurable (using configuration pins C0 and C1) to two
topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter configuration can be designated as
Register A or Register B on the DIMM.
The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN)
input, compares it with the data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW).
The convention is even parity, that is, valid parity is defined as an even number of ones
across the DIMM-independent data inputs combined with the parity input bit.
The SSTU32866 is packaged in a 96-ball, 6 ×16 grid, 0.8 mm ball pitch LFBGA package
(13.5 mm by 5.5 mm).
2. Features
■Configurable register supporting DDR2 Registered DIMM applications
■Configurable to 25-bit 1:1 mode or 14-bit 1:2 mode
■Controlled output impedance drivers enable optimal signal integrity and speed
■Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
■Supports up to 450 MHz clock frequency of operation
■Optimized pinout for high-density DDR2 module design
■Chip-selects minimize power consumption by gating data outputs from changing state
■Supports SSTL_18 data inputs
■Checks parity on the DIMM-independent data inputs
■Partial parity output and input allows cascading of two SSTU32866s for correct parity
error processing
■Differential clock (CK and CK) inputs
■Supports LVCMOS switching levels on the control and RESET inputs
■Single 1.8 V supply operation
■Available in 96-ball, 13.5 ×5.5 mm, 0.8 mm ball pitch LFBGA package
SSTU32866
1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity for DDR2 RDIMM applications
Rev. 02 — 11 November 2004 Product data sheet
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 2 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
3. Applications
■DDR2 registered DIMMs desiring parity checking functionality
4. Ordering information
Table 1: Ordering information
T
amb
=0
°
Cto+70
°
C.
Type number Solder process Package
Name Description Version
SSTU32866EC/G Pb-free (SnAgCu solder
ball compound) LFBGA96 plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5 ×5.5 ×1.05 mm SOT536-1
SSTU32866EC SnPb solder ball
compound LFBGA96 plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5 ×5.5 ×1.05 mm SOT536-1
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 3 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
5. Functional diagram
(1) Disabled in 1:1 configuration.
Fig 1. Functional diagram of SSTU32866; 1:2 Register A configuration with C0 = 0 and
C1 = 1 (positive logic)
002aaa649
1D
R
1D
R
1D
R
QCKEA
QCKEB (1)
QODTA
QODTB (1)
QCSA
QCSB (1)
C1
C1
C1
CSR
DCS
DODT
DCKE
D2 0
11D
R
Q2A
Q2B (1)
C1
to 10 other channels
(D3, D5, D6, D8 to D14)
CK
VREF
CK
RESET
SSTU32866
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 4 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
Fig 2. Parity logic diagram for 1:2 Register A configuration (positive logic); C0 = 0, C1 = 1
002aaa650
D
R
Q2A, Q3A,
Q5A, Q6A,
Q8A to Q14A
Q2B, Q3B,
Q5B, Q6B,
Q8B to Q14B
CLK
PAR_IN
D2, D3, D5, D6,
D8 to D14
CK
CK
RESET
LPS0
(internal node)
CE
VREF
PARITY
CHECK
C1
0
1
D
RCLK
D
RCLK
CE
D
RCLK
1
0
C0
R
CLK
D
RCLK
LPS1
(internal node)
0
1
2-BIT
COUNTER
QERR
PPO
D2, D3, D5, D6,
D8 to D14
D2, D3, D5, D6,
D8 to D14
11
11
11 11
11
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Product data sheet Rev. 02 — 11 November 2004 5 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration for LFBGA96
Fig 4. Ball mapping, 1:1 register (C0 = 0, C1 = 0)
002aab135
SSTU32866EC/G
SSTU32866EC
Transparent top view
TR
PN
ML
J
G
K
H
FE
DC
BA
246135
ball A1
index area
DCKE PPO VREF VDD QCKE d.n.u.
123456
D2 D15 GND GND Q2 Q15
A
B
D3 D16 VDD VDD Q3 Q16C
DODT GND GND QODT d.n.u.D
D5 D17 VDD VDD Q5 Q17E
D6 D18 GND GND Q6 Q18F
PAR_IN RESET VDD VDD C1 C0G
CK DCS GND GND QCS d.n.u.H
CK CSR VDD VDD n.c. n.c.J
D8 D19 GND GND Q8 Q19K
D9 D20 VDD VDD Q9 Q20L
D10 D21 GND GND Q10 Q21M
D11 D22 VDD VDD Q11 Q22N
D12 D23 GND GND Q12 Q23P
D13 D24 VDD VDD Q13 Q24R
D14 D25 VREF VDD Q14 Q25T
002aab108
QERR
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 6 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
Fig 5. Ball mapping, 1:2 Register A (C0 = 0, C1 = 1)
Fig 6. Ball mapping, 1:2 Register B (C0 = 1, C1 = 1)
DCKE PPO VREF VDD QCKEA QCKEB
123456
D2 d.n.u. GND GND Q2A Q2B
A
B
D3 d.n.u. VDD VDD Q3A Q3BC
DODT QERR GND GND QODTA QODTBD
D5 n.c. VDD VDD Q5A Q5BE
D6 n.c. GND GND Q6A Q6BF
PAR_IN RESET VDD VDD C1 C0G
CK DCS GND GND QCSAH
CK CSR VDD VDD n.c. n.c.J
D8 d.n.u. GND GND Q8A Q8BK
D9 d.n.u. VDD VDD Q9A Q9BL
D10 d.n.u. GND GND Q10A Q10BM
D11 d.n.u. VDD VDD Q11A Q11BN
D12 d.n.u. GND GND Q12A Q12BP
D13 d.n.u. VDD VDD Q13A Q13BR
D14 d.n.u. VREF VDD Q14A Q14BT
002aab109
QCSB
D1 PPO VREF VDD Q1A Q1B
123456
D2 d.n.u. GND GND Q2A Q2B
A
B
D3 d.n.u. VDD VDD Q3A Q3BC
D4 GND GND Q4A Q4BD
D5 d.n.u. VDD VDD Q5A Q5BE
D6 d.n.u. GND GND Q6A Q6BF
PAR_IN RESET VDD VDD C1 C0G
CK DCS GND GND QCSAH
CK CSR VDD VDD n.c. n.c.J
D8 d.n.u. GND GND Q8A Q8BK
D9 d.n.u. VDD VDD Q9A Q9BL
D10 d.n.u. GND GND Q10A Q10BM
DODT d.n.u. VDD VDD QODTA QODTBN
D12 d.n.u. GND GND Q12A Q12BP
D13 d.n.u. VDD VDD Q13A Q13BR
DCKE d.n.u. VREF VDD QCKEA QCKEBT
002aab110
QCSB
QERR
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 7 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
6.2 Pin description
Table 2: Pin description
Symbol Pin Type Description
GND B3, B4, D3, D4,
F3, F4, H3, H4,
K3, K4, M3, M4,
P3, P4
ground input ground
VDD A4, C3, C4, E3,
E4, G3, G4, J3,
J4, L3, L4, N3,
N4, R3, R4, T4
1.8 V nominal power supply voltage
VREF A3, T3 0.9 V nominal input reference voltage
CK H1 Differential input positive master clock input
CK J1 Differential input negative master clock input
C0 G6 LVCMOS inputs Configuration control inputs; Register A
or Register B and 1:1 mode or 1:2 mode
select.
C1 G5
RESET G2 LVCMOS input Asynchronous reset input. Resets
registers and disables VREF data and
clock.
CSR J2 SSTL_18 input Chip select inputs. Disables D1 to D25[2]
outputs switching when both inputs are
HIGH.
DCS H2
D1 to D25 [1] SSTL_18 input Data input. Clocked in on the crossing of
the rising edge od CK and the falling
edge of CK.
DODT [1] SSTL_18 input The outputs of this register bit will not be
suspended by the DCS and CSR control.
DCKE [1] SSTL_18 input The outputs of this register bit will not be
suspended by the DCS and CSR control.
PAR_IN G1 SSTL_18 input Parity input. Arrives one clock cycle after
the corresponding data input.
Q1 to Q25,
Q2A to Q14A,
Q1B to Q14B
[1] 1.8 V CMOS
outputs Data outputs that are suspended by the
DCS and CSR control.[3]
PPO A2 1.8 V CMOS
output Partial parity out. Indicates odd parity of
inputs D1 to D25[2].
QCS, QCSA,
QCSB [1] 1.8 V CMOS
output Data output that will not be suspended by
the DCS and CSR control.
QODT, QODTA,
QODTB [1] 1.8 V CMOS
output Data output that will not be suspended by
the DCS and CSR control.
QCKE, QCKEA,
QCKEB [1] 1.8 V CMOS
output Data output that will not be suspended by
the DCS and CSR control.
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 8 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
[1] Depends on configuration. Refer to Figure 4,Figure 5, and Figure 6 for ball number.
[2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3] Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
7. Functional description
The SSTU32866 is a 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity,
designed for 1.7 V to 1.9 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers
that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18
specifications. The error (QERR) output is 1.8 V open-drain driver.
The SSTU32866 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration for the 1:2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The SSTU32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN)
input, compares it with the data received on the DIMM-independent D-inputs and
indicates whether a parity error has occurred on its open-drain QERR pin (active-LOW).
The convention is even parity, i.e., valid parity is defined as an even number of ones
across the DIMM-independent data inputs combined with the parity input bit.
When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration,
parity is checked on the PAR_IN input which arrives one cycle after the input data to which
it applies. The partial-parity-out (PPO) and QERR signals are produced three cycles after
the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the
second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which
arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of
the first device. The PPO and QERR signals are produced on the second device three
clock cycles after the corresponding data inputs. The PPO output of the first register is
QERR D2 open-drain
output Output error bit. Generated one clock
cycle after the corresponding data output
n.c. [1] - Not connected. Ball present but no
internal connection to the die.
d.n.u. [1] - Do not use. Inputs are in
standby-equivalent mode and outputs
are driven LOW.
Table 2: Pin description
…continued
Symbol Pin Type Description
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 9 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
cascaded to the PAR_IN of the second register. The QERR output of the first register is
left floating and the valid error information is latched on the QERR output of the second
register.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock
cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT,
and CSR) are not included in the parity check computation.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all
outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic
HIGH or LOW level.
The device also supports low-power active operation by monitoring both system chip
select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states
when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn
and PPO outputs will function normally. The RESET input has priority over the DCS and
CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the
QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can
be hard-wired to ground, in which case, the set-up time requirement for DCS would be the
same as for the other Dn data inputs. To control the low-power mode with DCS only, then
the CSR input should be pulled up to VDD through a pull-up resistor.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the Qn outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTU32866 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 10 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
7.1 Function table
[1] Q0 is the previous state of the associated output.
[1] PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR.
[2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3] PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.
[4] This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for
two clock cycles or until RESET is driven LOW.
Table 3: Function table (each flip-flop)
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
↑
= LOW-to-HIGH transition;
↓
= HIGH-to-LOW transition
Inputs Outputs[1]
RESET DCS CSR CK CK Dn, DODTn,
DCKEn Qn QCS QODT,
QCKE
HL L ↑↓LLLL
HL L ↑↓HHLH
H L L L or H L or H X Q0Q0Q0
HL H ↑↓LLLL
HL H ↑↓HHLH
H L H L or H L or H X Q0Q0Q0
HH L ↑↓LLHL
HH L ↑↓HHHH
H H L L or H L or H X Q0Q0Q0
HH H ↑↓LQ
0HL
HH H ↑↓HQ
0HH
H H H L or H L or H X Q0Q0Q0
L X or floating X or floating X or floating X or floating X or floating L L L
Table 4: Parity and standby function table
L = LOW voltage level; H = HIGH voltage level; X = don’t care;
↑
= LOW-to-HIGH transition;
↓
= HIGH-to-LOW transition
Inputs Outputs[1]
RESET DCS CSR CK CK ∑of inputs = H
(D1 to D25) PAR_IN[2] PPO[3] QERR
HL X ↑↓ even L L H
HL X ↑↓ odd L H L
HL X ↑↓ even H H L
HL X ↑↓ odd H L H
HH L ↑↓even L L H
HH L ↑↓ odd L H L
HH L ↑↓even H H L
HH L ↑↓ odd H L H
HH H ↑↓ X X PPO0QERR0
H X X L or H L or H X X PPO0QERR0
L X or floating X or floating X or floating X or floating X or floating X or floating L H
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 11 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
8. Limiting values
[1] Stresses beyond those listed under ‘absolute maximum ratings’ may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under ‘recommended operating
conditions’ is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
[2] The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
[3] This value is limited to 2.5 V maximum.
9. Recommended operating conditions
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.5 +2.5 V
VIreceiver input voltage −0.5[2] +2.5[3] V
VOdriver output voltage −0.5[2] VDD + 0.5[3] V
IIK input clamp current VI< 0 V or VI>V
DD -−50 mA
IOK output clamp current VO< 0 V or VO>V
DD -±50 mA
IOcontinuous output current 0 V < VO< VDD -±50 mA
ICCC continuous current through
each VDD or GND pin -±100 mA
Tstg storage temperature −65 +150 °C
Vesd electrostatic discharge
voltage Human Body Model (HBM); 1.5 kΩ;
100 pF 2- kV
Machine Model (MM); 0 Ω; 200 pF 200 - V
Table 6: Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 1.7 - 1.9 V
VREF reference voltage 0.49 ×VDD 0.50 ×VDD 0.51 ×VDD V
VTT termination voltage VREF −40 mV VREF VREF +40mV V
VIinput voltage 0 - VDD V
VIH(AC) AC HIGH-level input voltage data (Dn),
CSR, and
PAR_IN inputs
VREF + 250 mV - - V
VIL(AC) AC LOW-level input voltage data (Dn),
CSR, and
PAR_IN inputs
--V
REF −250 mV V
VIH(DC) DC HIGH-level input voltage data (Dn),
CSR, and
PAR_IN inputs
VREF + 125 mV - - V
VIL(DC) DC LOW-level input voltage data (Dn),
CSR, and
PAR_IN inputs
--V
REF −125 mV V
VIH HIGH-level input voltage RESET, Cn [1] 0.65 ×VDD -- V
VIL LOW-level input voltage RESET, Cn [1] - - 0.35 ×VDD V
VICR common mode input voltage
range CK, CK [2] 0.675 - 1.125 V
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 12 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
[1] The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
[2] The differential inputs must not be floating, unless RESET is LOW.
10. Characteristics
VID differential input voltage CK, CK [2] 600 - - mV
IOH HIGH-level output current - - −8mA
IOL LOW-level output current - - 8 mA
Tamb operatingambienttemperature
in free air 0 - +70 °C
Table 6: Recommended operating conditions
…continued
Symbol Parameter Conditions Min Typ Max Unit
Table 7: Characteristics
At recommended operating conditions (see Table 6), unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output voltage IOH =−6 mA; VDD = 1.7 V 1.2 - - V
VOL LOW-level output voltage IOL = 6 mA; VDD = 1.7 V - - 0.5 V
IIinput current all inputs; VI=V
DD or GND;
VDD = 1.9 V --±5µA
IDD static standby current RESET = GND; IO= 0 mA;
VDD = 1.9 V - - 100 µA
static operating current RESET = VDD; IO= 0 mA;
VDD = 1.9 V; VI=V
IH(AC) or VIL(AC)
- - 40 mA
IDDD dynamicoperatingcurrent per MHz,
clock only RESET = VDD;
VI=V
IH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle.
IO= 0 mA; VDD = 1.8 V
-16-µA
dynamicoperatingcurrent per MHz,
per each data input, 1:1 mode RESET = VDD;
VI=V
IH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle. One
data input switching at half clock
frequency, 50 % duty cycle.
IO= 0 mA; VDD = 1.8 V
-11-µA
dynamicoperatingcurrent per MHz,
per each data input, 1:2 mode RESET = VDD;
VI=V
IH(AC) or VIL(AC); CK and CK
switching at 50 % duty cycle. One
data input switching at half clock
frequency, 50 % duty cycle.
IO= 0 mA; VDD = 1.8 V
-19-µA
Ciinput capacitance, data and CSR
inputs VI=V
REF ±250 mV; VDD = 1.8 V 2.5 - 3.5 pF
input capacitance,
CK and CK inputs VICR = 0.9 V; Vi(p-p) = 600 mV;
VDD = 1.8 V 2-3pF
input capacitance, RESET input VI=V
DD or GND; VDD = 1.8 V 3 - 4 pF
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 13 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
[1] This parameter is not necessarily production tested.
[2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken
HIGH.
[3] VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
[1] Includes 350 ps of test-load transmission line delay.
[2] This parameter is not necessarily production tested.
Table 8: Timing requirements
At recommended operating conditions (see Table 6), unless otherwise specified. See Figure 2.
Symbol Parameter Conditions Min Typ Max Unit
fclock clock frequency - - 450 MHz
tWpulse duration, CK, CK HIGH
or LOW 1--ns
tACT differential inputs active time [1] [2] --10ns
tINACT differential inputs inactive time [1] [3] --15ns
tsu set-up time DCS before CK↑, CK↓, CSR HIGH; CSR
before CK↑,CK↓, DCS HIGH 0.7 - - ns
DCS before CK↑, CK↓, CSR LOW 0.5 - - ns
DODT, DCKE and data (Dn) before CK↑,
CK↓0.5 - - ns
PAR_IN before CK↑,CK↓0.5 - - ns
thhold time DCS, DODT, DCKE and data (Dn) after
CK↑,CK↓0.5 - - ns
PAR_IN after CK↑,CK↓0.5 - - ns
Table 9: Switching characteristics
At recommended operating conditions (see Table 6), unless otherwise specified. See Section 11.1.
Symbol Parameter Conditions Min Typ Max Unit
fMAX maximum input clock frequency 450 - - MHz
tPDM propagation delay, single bit switching from CK↑ and CK↓ to Qn [1] 1.41 - 1.8 ns
tPD propagation delay from CK↑ and CK↓ to PPO 0.5 - 1.8 ns
tLH LOW-to-HIGH propagation delay from CK↑ and CK↓ to QERR 1.2 - 3 ns
tHL HIGH-to-LOW propagation delay from CK↑ and CK↓ to QERR 1 - 2.4 ns
tPDMSS propagation delay,
simultaneous switching from CK↑ and CK↓ to Qn [1] [2] - - 2.0 ns
tPHL HIGH-to-LOW propagation delay from RESET↓ to Qn↓--3ns
from RESET↓ to PPO↓--3ns
tPLH LOW-to-HIGH propagation delay from RESET↓ to QERR↑--3ns
Table 10: Data output edge rates
At recommended operating conditions (see Table 6), unless otherwise specified. See Section 11.2.
Symbol Parameter Conditions Min Typ Max Unit
dV/dt_r rising edge slew rate from 20 % to 80 % 1 - 4 V/ns
dV/dt_f falling edge slew rate from 80 % to 20 % 1 - 4 V/ns
dV/dt_∆absolute difference between dV/dt_r
and dV/dt_f from 20 % or 80 %
to 80 % or 20 % - - 1 V/ns
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Product data sheet Rev. 02 — 11 November 2004 14 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
10.1 Timing diagrams
Fig 7. Timing diagram for SSTU32866 used as a single device; C0 = 0, C1 = 0
RESET
DCS
CSR
CK
CK
D1
to
D25
Q1
to
Q25
PAR_IN
PPO
QERR
tsu th
m m + 1 m + 2 m + 3 m + 4
tPD
CK to Q
tsu th
tPD
CK to PPO
tPD
CK to QERR
002aaa655
tPD
CK to QERR
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 15 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
Fig 8. Timing diagram for the first SSTU32866 (1:2 Register A configuration) device used in pair; C0 = 0, C1 = 1
RESET
DCS
CSR
CK
CK
D1
to
D14
Q1
to
Q14
PAR_IN
PPO
QERR
(not used)
tsu th
m m + 1 m + 2 m + 3 m + 4
tPD
CK to Q
tsu th
tPD
CK to PPO
tPD
CK to QERR
002aaa656
tPD
CK to QERR
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 16 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
(1) PAR_IN is driven from PPO of the first SSTU32866 device.
Fig 9. Timing diagram for the second SSTU32866 (1:2 Register B configuration) device used in pair;
C0=1,C1=1
RESET
DCS
CSR
CK
CK
D1
to
D14
Q1
to
Q14
PAR_IN(1)
PPO
(not used)
QERR
tsu th
m m + 1 m + 2 m + 3 m + 4
tPD
CK to Q
tsu th
tPD
CK to PPO
tPD
CK to QERR
002aaa657
tPD
CK to QERR
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 17 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
11. Test information
11.1 Parameter measurement information for data output load circuit
VDD =1.8V±0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤10 MHz; Z0=50Ω; input slew rate = 1 V/ns ±20 %, unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
(1) CL includes probe and jig capacitance.
Fig 10. Load circuit, data output measurements
(1) IDD tested with clock and data inputs held at VDD or GND, and IO= 0 mA.
Fig 11. Voltage and current waveforms; inputs active and inactive times
VID = 600 mV
VIH =V
REF + 250 mV (AC voltage levels) for differential inputs. VIH =V
DD for LVCMOS inputs.
VIL =V
REF −250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 12. Voltage waveforms; pulse duration
RL = 100 Ω
RL = 1000 Ω
VDD
TL = 50 Ω
CK inputs CK
CK OUT
DUT
test point
002aaa371
test point
TL = 350 ps, 50 Ω
RL = 1000 Ω
CL = 30 pF(1)
LVCMOS
RESET
10 %
IDD(1)
tINACT
VDD
VDD/2
tACT
90 %
0 V
002aaa372
VDD/2
VICR VICR
VIH
VIL
input
tW
VID
002aaa373
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 18 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
VID = 600 mV
VREF =V
DD/2
VIH =V
REF + 250 mV (AC voltage levels) for differential inputs. VIH =V
DD for LVCMOS inputs.
VIL =V
REF −250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; set-up and hold times
tPLH and tPHL are the same as tPD.
Fig 14. Voltage waveforms; propagation delay times (clock to output)
tPLH and tPHL are the same as tPD.
VIH =V
REF + 250 mV (AC voltage levels) for differential inputs. VIH =V
DD for LVCMOS inputs.
VIL =V
REF −250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 15. Voltage waveforms; propagation delay times (reset to output)
tsu VIH
VIL
VID
th
CK
CK
input VREF VREF
VICR
002aaa374
VOH
VOL
output
tPLH
002aaa375
VTT
VICR VICR
tPHL
CK
CK Vi(p-p)
tPHL
002aaa376
LVCMOS
RESET
output VTT
VDD/2 VIH
VIL
VOH
VOL
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 19 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
11.2 Data output slew rate measurement information
VDD =1.8V±0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤10 MHz; Z0=50Ω; input slew rate = 1 V/ns ±20 %, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, HIGH-to-LOW slew measurement
Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, LOW-to-HIGH slew measurement
Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement
CL = 10 pF(1)
VDD
OUT
DUT
test point
RL = 50 Ω
002aaa377
VOH
VOL
output
80 %
20 %
dv_f
dt_f
002aaa378
CL = 10 pF(1)
OUT
DUT
test point
RL = 50 Ω
002aaa379
VOH
VOL
80 %
20 %
dv_r
dt_r
output
002aaa380
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 20 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
11.3 Error output load circuit and voltage measurement information
VDD =1.8V±0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤10 MHz; Z0=50Ω; input slew rate = 1 V/ns ±20 %, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Fig 20. Load circuit, error output measurements
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
RESET input.
Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
to clock inputs
CL = 10 pF(1)
VDD
OUT
DUT
test point
RL = 1 kΩ
002aaa500
VCC/2
tPLH
VCC
0 V
0.15 V
VOH
0 V
output
waveform 2
RESET
002aaa501
LVCMOS
VICR
tHL
VCC/2
VCC
VOL
timing
inputs
output
waveform 1
Vi(p-p)
VICR
002aaa502
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 21 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
11.4 Partial Parity Out load circuit and voltage measurement information
VDD =1.8V±0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤10 MHz; Z0=50Ω; input slew rate = 1 V/ns ±20 %, unless otherwise specified.
Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
clock inputs
VICR
tLH
VOH
0 V
timing
inputs
output
waveform 2
Vi(p-p)
VICR
0.15 V
002aaa503
(1) CL includes probe and jig capacitance.
Fig 24. Partial Parity Out load circuit
VTT =V
DD/2
tPLH and tPHL are the same as tPD.
Vi(p-p) = 600 mV
Fig 25. Partial Parity Out voltage waveforms; propagation delay times with respect to
clock inputs
CL = 5 pF(1)
OUT
DUT
test point
RL = 1 kΩ
002aaa654
VOH
VOL
output
tPLH
002aaa375
VTT
VICR VICR
tPHL
CK
CK Vi(p-p)
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 22 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
VTT =V
DD/2
tPLH and tPHL are the same as tPD.
VIH =V
REF + 250 mV (AC voltage levels) for differential inputs. VIH =V
DD for LVCMOS inputs.
VIL =V
REF −250 mV (AC voltage levels) for differential inputs. VIL =V
DD for LVCMOS inputs.
Fig 26. Partial Parity Out voltage waveforms; propagation delay times with respect to
RESET input
tPHL
002aaa376
LVCMOS
RESET
output VTT
VDD/2 VIH
VIL
VOH
VOL
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 23 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
12. Package outline
Fig 27. Package outline SOT536-1 (LFBGA96)
0.8
A1bA2
UNIT Dye
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
00-03-04
03-02-05
IEC JEDEC JEITA
mm 1.5 0.41
0.31 1.2
0.9 5.6
5.4
y1
13.6
13.4
0.51
0.41 0.1 0.2
e1
4
e2
12
DIMENSIONS (mm are the original dimensions)
SOT536-1
E
0.15
v
0.1
w
0 5 10 mm
scale
SOT536-1
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm
A
max.
AA2
A1
detail X
e
e
X
D
E
A
B
C
D
E
F
H
G
J
K
L
M
P
N
R
T
246135
BA
e2
e1
ball A1
index area
ball A1
index area
y
y1C
b
C
AC
CB
∅ vM
∅ wM
1/2 e
1/2 e
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 24 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our
Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 °Cto270°C depending on solder paste
material. The top-surface temperature of the packages should preferably be kept:
•below 225 °C (SnPb process) or below 245 °C (Pb-free process)
–for all BGA, HTSSON..T and SSOP..T packages
–for packages with a thickness ≥2.5 mm
–for packages with a thickness < 2.5 mm and a volume ≥350 mm3 so called
thick/large packages.
•below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
•Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
–larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 25 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
–smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
•For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
13.5 Package related soldering information
[1] For more detailed information on the BGA packages refer to the
(LF)BGA Application Note
(AN01026);
order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the
Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods
.
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217 °C±10 °C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
Table 11: Suitability of surface mount IC packages for wave and reflow soldering methods
Package[1] Soldering method
Wave Reflow[2]
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, VFBGA, XSON not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable[4] suitable
PLCC[5], SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended[5] [6] suitable
SSOP, TSSOP, VSO, VSSOP not recommended[7] suitable
CWQCCN..L[8], PMFP[9], WQCCN..L[8] not suitable not suitable
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 26 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.
[9] Hot bar soldering or manual soldering is suitable for PMFP packages.
14. Abbreviations
Table 12: Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Silicon
DDR Double Data Rate
DIMM Dual In-line Memory Module
JEDEC Joint Electron Device Engineering Council
LFBGA Low profile Fine-pitch Ball Grid Array
LVCMOS Low Voltage Complementary Metal Oxide Silicon
PPO Partial Parity Out
PRR Pulse Repetition Rate
RDIMM Registered Dual In-line Memory Module
SSTL Stub Series Terminated Logic
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 27 of 29
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
15. Revision history
Table 13: Revision history
Document ID Release date Data sheet status Change notice Doc. number Supersedes
SSTU32866_2 20041111 Product data sheet - 9397 750 14181 SSTU32866-01
Modifications: •The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
•Data sheet status upgraded to ‘Product data sheet’.
•(Old) Figure 1 and Figure 2 (logic diagrams) moved to Section 5 “Functional diagram”
•Section 6 “Pinning information”
–changed ‘NC’ to ‘n.c.’ and ‘DNU’ to ‘d.n.u.’
–added Figure 3 “Pin configuration for LFBGA96”
–added Figure 4,Figure 5, and Figure 6 (replacing old Tables 2, 3 and 4 “Ball mapping”)
–Table 2 “Pin description”: added (new) Table note [1] and its references at affected pins.;
added pin number column.
•Table 3 “Function table (each flip-flop)”: added Table note [1] and its reference at ‘Outputs’.
•Table 4 “Parity and standby function table”:
–added (new) Table note [1] and its reference at ‘Outputs’.
–Table note [4]: changed ‘This transition assumes ...’ to ‘This condition assumes ...’.
•Table 5 “Limiting values”:
–symbol Vi changed to VI; Symbol Vo changed to VO.
–symbols ESDHBM and ESDMM replaced with Vesd (added model types under “Conditions”)
•Table 6 “Recommended operating conditions”:
–changed column heading from ‘Nom’ to ‘Typ’
–changed VIH (for Data, CSR, and PAR_IN inputs) to VIH(AC) and VIH(DC); condition changed to
‘data inputs (Dn) ...’
–changed VIL (for Data, CSR, and PAR_IN inputs) to VIL(AC) and VIL(DC); condition changed to
‘data inputs (Dn)
–table note split into 2 notes; references added.
•merged sections “Static characteristics” and “Dynamic characteristics” into Section 10
“Characteristics”
•Table 7 “Characteristics”: changed IDDD Parameter from “dynamic operating current ...” to
“dynamic operating current per MHz ...”; change Unit from “µA/MHz” to “µA”.
•Table 8 “Timing requirements”:
–changed symbol fCLOCK to fclock
–changed symbol tSU to tsu
–changed symbol tH to th
•Figure 7 modified.
•Section 11.1 “Parameter measurement information for data output load circuit”: titles for
Figure 14 and Figure 15 modified.
•added Section 14.
SSTU32866-01 20040709 Objective data - 9397 750 12145 -
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
9397 750 14181 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 02 — 11 November 2004 28 of 29
16. Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
Level Data sheet status[1] Product status[2] [3] Definition
I Objective data Development This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 11 November 2004
Document number: 9397 750 14181
Published in The Netherlands
Philips Semiconductors SSTU32866
1.8 V DDR2 configurable registered buffer with parity
20. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 Functional description . . . . . . . . . . . . . . . . . . . 8
7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . 10
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
9 Recommended operating conditions. . . . . . . 11
10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 12
10.1 Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 14
11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 17
11.1 Parameter measurement information for
data output load circuit . . . . . . . . . . . . . . . . . . 17
11.2 Data output slew rate measurement
information . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.3 Error output load circuit and voltage
measurement information. . . . . . . . . . . . . . . . 20
11.4 Partial Parity Out load circuit and voltage
measurement information. . . . . . . . . . . . . . . . 21
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
13.1 Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
13.2 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 24
13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 24
13.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25
13.5 Package related soldering information . . . . . . 25
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 26
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
16 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 28
17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
18 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
19 Contact information . . . . . . . . . . . . . . . . . . . . 28
