100315SC - Fairchild Semiconductor

September 1991

Revised November 1999

100315 Low Skew Quad Clock Driver

100315

Low Skew Quad Clock Driver

General Description

The 100315 contains four low skew differential drivers,

designed for generation of multiple, minimum skew differ-

ential clocks from a single differential input. This device

also has the capability to select a secondary single-ended

clock source for use in lower frequency system level test-

ing. The 100315 is a 300 Series redesign of the 100115

clock driver .

Features

■Low output-to-output skew (≤50 ps)

■Differential inputs and outputs

■Secondary clock available for system level testing

■2000V ESD protection

■Voltage compensated operating range: −4.2V to −5.7V

Ordering Code:

Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the o rdering code.

Logic Diagram

Pin Descriptions

Note 1: TCLK and CLKSEL are single-ended inputs, with internal 50 kΩ

pull-down resistors.

Connection Diagram

Truth Table

L = LOW Voltage Level

H = HIGH Voltage Level

X = Don't Care

Order Number Package Number Package Descriptions

100315SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Pin Names Description

CLKIN, CLKIN Differential Clock Inputs

CLK1–4, CLK1–4Differential Clock Outputs

TCLK Test C lock Input (Note 1)

CLKSEL Clock Input Select (Not e 1)

CLKSEL CLKIN CLKIN TCLK CLKnCLKn

LLHXLH

LHLXHL

H X XLLH

HXXHHL

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100315

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: The “Absolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

Note 3: ESD te s ti ng c onforms t o M I L-STD-8 83, Meth od 3015.

DC Electrical Characteristi cs (Note 4)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C

Note 4: The specified limits represent the “worst case” value for the parameter. Since these “wor st ca se” value s normally occur at th e temperature extr emes,

additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.

AC Electrical Characteristi cs

VEE = −4.2V to −4.8, VCC = VCCA = GND

Note 5: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged d evice . The sp ecificatio ns appl y to an y output s swit ching in th e sam e direc tion eithe r HIGH- to-LOW (tOSHL), or LOW-to-H IGH (tOSLH), or in opp osite

direc ti ons both H L and LH (tOST). Parameters tOST and tPS guaranteed by design.

Storage Temperature −65°C to +150°C

Maximum Junction Temperature (TJ)+150°C

Case Temperature under Bias (TC)0°C to +85°C

VEE Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) VCC to +0.5V

Output Curren t (DC Output HIGH) −50 mA

Operating Range (Note 2) −5.7V to −4.2V

ESD (Not e 3) ≥2000V

Case Temperature (TC)0°C to +85°C

Supply Voltage ( VEE)−5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage −1025 −955 −870 mV VIN = VIH(Max) Loading with

VOL Output LOW Voltage −1830 −1705 −1620 or VIL(Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1035 mV VIN = VIH(Min) Loading with

VOLC Output LOW Voltage −1610 or VIL(Max) 50Ω to −2.0V

VIH Single-Ended Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs

VIL Single-Ended Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs

IIL Input LOW Current 0.50 µAV

IN = VIL(Min)

IIH Input HIGH Current

VIN = VIH(Max)

CLKIN, CLKIN 150 µA

TCLK 250 µA

CLKSEL 250 µA

VDIFF Input Voltage Differential 150 mV Required for Full Output Swing

VCM Common Mode Voltage VCC − 2V VCC − 0.5V V

ICBO Input Leakage Current −10 µAV

IN = VEE

IEE Power Supply Current −67 −35 mA

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

fMAX Maximum Clock Frequency 750 750 750 MHz

tPLH Propagation Delay CLKIN,

ns Figures 1, 3

tPHL CLKIN to CLK(1–4), CLK(1–4)

Differential 0.59 0.79 0.62 0.82 0.67 0.87

Single-Ended 0.59 0.99 0.62 1.02 0.67 1.07

tPLH Propagation Delay, TCLK 0.50 1.20 0.50 1.20 0.50 1.20 ns Figures 1, 2

tPHL to CLK(1–4), CLK(1–4)

tPLH Propagation Delay, CLKSEL 0.80 1.60 0.80 1.60 0.80 1.60 ns Figures 1, 2

tPHL to CLK(1–4), CLK(1–4)

tTLH Transition Time 0.30 0.80 0.30 0.80 0.30 0.80 ns Figures 1, 4

tTHL 20% to 80%, 80% to 20%

tOST Maximum Skew Opposite Edge

DIFF Output-to-Output Variation 50 50 50 ps (Note 5)

Data to Output Path

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100315

Test Circuit

Note:

Shown for testing CLKIN to CLK1 in the differ enti al mode.

L1, L2, L3 and L4 = equal leng th 50Ω impedance lines.

All unuse d inputs and outputs are loa ded with 50 Ω in paralle l wi th ≤3 pF to GND.

Scope should have 50Ω input terminator internally. FIGURE 1. AC Test Circuit

Switching Waveforms

FIGURE 2. Propagation Delay, TCLK, CLKSEL to Outputs

FIGURE 3. Propagation Delay, CLKIN/CLKIN to Outputs

FIGU RE 4. Transiti on Times

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100315 Low Skew Quad Clock Driver

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life supp or t devices o r syste ms a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A cr itical compon ent in any com ponen t of a life su pport

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.