DCD: DSPI: Serial Peripheral Interface - Lattice Semiconductor

All trademarks mentioned in this document http://www.DigitalCoreDesign.com

are trademarks of their respective owners. http://www.dcd.pl

Serial Peripheral Interface – Master/Slave

ver 1.23

OVERVIEW

The DSPI is a fully configurable SPI mas-

ter/slave device, which allows user to config-

ure polarity and phase of serial clock signal

SCK.

The DSPI allows the microcontroller to

communicate with serial peripheral devices. It

is also capable of interprocessor communica-

tions in a multi-master system. A serial clock

line (SCK) synchronizes shifting and sampling

of the information on the two independent se-

rial data lines. DSPI data are simultaneously

transmitted and received.

The DSPI is a technology independent de-

sign that can be implemented in a variety of

process technologies.

The DSPI system is flexible enough to in-

terface directly with numerous standard prod-

uct peripherals from several manufacturers.

The system can be configured as a master or

a slave device. Data rates as high as CLK/4.

Clock control logic allows a selection of clock

polarity and a choice of two fundamentally

different clocking protocols to accommodate

most available synchronous serial peripheral

devices. When the SPI is configured as a

master, software selects one of four different

bit rates for the serial clock.

The DSPI automatically drive selected by

SSCR (Slave Select Control Register) slave

select outputs (SS7O – SS0O), and address

SPI slave device to exchange serially shifted

data. Error-detection logic is included to sup-

port interprocessor communications. A write-

collision detector indicates when an attempt is

made to write data to the serial shift register

while a transfer is in progress. A multiple-

master mode-fault detector automatically dis-

ables DSPI output drivers if more than one

SPI devices simultaneously attempts to be-

come bus master.

DSPI is fully customizable, which means it

is delivered in the exact configuration to meet

users’ requirements. There is no need to pay

extra for not used f eatures and wasted silicon.

It includes fully automated testbench with

complete set of tests allowing easy package

validation at each stage of SoC design flow.

APPLICATIONS

● Embedded microprocessor boards

● Consumer and professional audio/video

● Home and automotive radio

● Digital multimeters

KEY FEATURES

● SPI Master

○ Master and Multi-master operations

○ 8 SPI slave select lines

○ System error detection

○ Mode fault error

○ Write collision error

○ Interrupt generation

○ Supports speeds up ¼ of syste m clock

All trademarks mentioned in this document http://www.DigitalCoreDesign.com

are trademarks of their respective owners. http://www.dcd.pl

○ Bit rates generated 1/4, 1/8, 1/ 16, 1/32 of

system clock.

○ Four transfer formats supported

○ Simple interface allows easy connection to

microcontrollers

● SPI Slave

○ Slave operation

○ System error detection

○ Interrupt generation

○ Supports speeds up ¼ of syste m clock

○ Simple interface allows easy connection to

microcontrollers

○ Four transfer formats supported

● Fully synthesizable, static synchronous

design with no internal tri-states

DELIVERABLES

Ø Source code:

¨ VHDL Source Code or/and

¨ VERILOG Source Code or/and

¨ Encrypted, or plain text EDIF netlist

Ø VHDL & VERILOG test bench environ-

ment

¨ Active-HDL automatic simulation macros

¨ ModelSim automatic simulation macros

¨ Tests with reference responses

Ø Technical documentation

¨ Installation notes

¨ HDL core specification

¨ Datasheet

Ø Synthesis scripts

Ø Example application

Ø Technical support

¨ IP Core implementation support

¨ 3 months maintenance

· Delivery the IP Core updates, minor and major

versions changes

· Delivery the documentation updates

· Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

● Single Design license for

○ VHDL, Verilog source code called HDL

Source

○ Encrypted, or plain text EDIF called Netlist

● One Year license for

○ Encrypted N et lis t only

● Unlimited Designs license for

○ HDL Source

○ Netlist

● Upgrade from

○ HDL Source to Netlist

○ Single Design to Unlimited Designs

All trademarks mentioned in this document http://www.DigitalCoreDesign.com

are trademarks of their respective owners. http://www.dcd.pl

SYMBOL

datai(7:0)

addr(7:0)

scki

mi

si

ss

clk

rst

datao(7:0)

cs

rd

we

ss7o

ss6o

ss5o

ss4o

ss3o

ss2o

ss1o

ss0o

scko

sckz

mo

so

int

PINS DESCRIPTION

PIN TYPE DESCRIPTION

clk input Global clock

rst input Global reset

datai(7:0) input Data bus input

addr(1:0) input Processor address lines

cs input Chip select

rd input Processor read strobe

we input Processor write strobe

scki input SPI clock input

mi input Master serial data input

si input Slave serial data input

ss input Slave select

datao(7:0) output Data bus output

int output Interrupt request

scko output SPI clock output

sckz output SPI clock output enable

mo output Master serial data output

so output Slave serial data output

ss7o-ss0o output Slave select outputs

BLOCK DIAGRAM

Shift register and Read Data Buffer – it is a

central element in the SPI system. The sys-

tem is single buffered in the transmit direction

and double buffered in the receive direction.

This fact means new data for transmission

cannot be written to the shifter until the previ-

ous transaction is complete; however, re-

ceived data is transferred into a parallel read

data buffer so the shifter is free to accept a

second serial character. As long as the first

character is read out of the read data buffer

before the next serial character is ready to be

transferred, no overrun condition will occur.

When an SPI transfer occurs, an 8-bit charac-

ter is shifted out on data pin while a different

8-bit character is simultaneously shifted in a

second data pin. Another way to view this

transfer is that an 8-bit shift register in the

master and another 8-bit shift register in the

slave are connected as a circular 16-bit shift

register. When a transfer occurs, this distrib-

uted shift register is shifted eight bit positions;

thus, the characters in the master and slave

are effectively exchanged.

8-Bit Shift Register

Read Data B uffer

MSB LSB

SPI Clock

Logic

Divider

¸4 - ¸512

SPI Contr ol Reg.

SPI Status Reg.

clk

SPR CPH

A

CPOL

SPI

Controller

mo

so mi

si

scko

scki

sckz

datao(7:0) ss

SS Control Reg.

ss7o

ss6o

ss5o

ss4o

ss3o

ss2o

ss1o

ss0o

datai(7:0)

addr

(

1:0

)

cs

we

rd int

Control Register may be read or written at

any time, is used to configure the DSPI Sys-

tem. This register controls the mode of trans-

mission (Master, Slave), polarity and phase of

SPI Clock and transmission speed.

Status Register (SPSR) is read only register

contains flags indicating the completion of

transfer or occurrence of system errors. All

flags are set automatically when the corre-

sponding event occur and cleared by software

sequence.

Slave Select Control Register configures

which slave select output should be driven

while SPI master transfer. Contents of SSCR

All trademarks mentioned in this document http://www.DigitalCoreDesign.com

are trademarks of their respective owners. http://www.dcd.pl

register is automatically assigned on SS7O-

SS0O pins when DSPI master transmission

starts.

SPI Clock Logic - Software can select any of

four combinations of serial clock (SCK) phase

and polarity using two bits in the SPI control

register (SPCR). The clock polarity is specified

by the CPOL control bit, which selects an ac-

tive high or active low clock and has no sig-

nificant effect on the transfer format. The clock

phase (CPHA) control bit selects one of two

fundamentally different transfer formats. The

clock phase and polarity should be identical

for the master SPI device and the communi-

cating slave device. In some cases, the phase

and polarity are changed between transfers to

allow a master device to communicate with

peripheral slaves having different require-

ments. The flexibility of the SPI system on the

DSPI allows direct interface to almost any

existing synchronous serial peripheral.

SPI Controller manages the Master/Slave

operation and controls the transmission. The

SPI Controller manages the transmission

speed and format (Phase and polarity). Con-

troller is also responsible for generating of

interrupt request and detection of transmission

errors.

PERFORMANCE

The following table gives a survey about the

Core area and performance in the LATTICE®

devices after Place & Route (all key features

have been included):

Device Speed

grade LUTs/PFUs Fmax

ispXPGA -5 150 / 40 163 MHz

ORCA 4 -3 134 / 26 66 MHz

ORCA 3 -7 132 / 26 52 MHz

Core performance in LATTICE® devices

Transfer Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity using two

bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit,

which selects an active high or active low clock and has no significant effect on the transfer format.

The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats.

The clock phase and polarity should be identical for the master SPI device and the communicating

slave device. In some cases, the phase and polarity are changed between transfers to allow a

master device to communicate with peripheral slaves having different requirements. The flexibility

of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial

peripheral.

6

5

4

3

2

21

1LSB

MSB

MSB LSB

12345678

SCK CYCLE#

SC K (CP O L =0 )

SC K (CP O L =1)

MOSI

MISO

SS

6

5

4

3

2

21

1LSB

MSB

MSB LSB

12345678

SCK CYCLE#

SC K (CPO L =0)

SCK (CPO L=1)

MOSI

MISO

SS

All trademarks mentioned in this document http://www.DigitalCoreDesign.com

are trademarks of their respective owners. http://www.dcd.pl

CONTACTS

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

e-mail: i

i

in

n

nf

f

fo

o

o@

@

@d

d

dc

c

cd

d

d.

.

.p

p

pl

l

tel. : +48 32 282 82 66

fax : +48 32 282 74 37

Field Office:

Texas Research Park

14815 Omicron Dr. suite 100

San Antonio, TX 78245,USA

e-mail: i

i

in

n

nf

f

fo

o

oU

U

US

S

S@

@

@d

d

dc

c

cd

d

d.

.

.p

p

pl

l

tel. : +1 210 422 8268

fax : +1 210 679 7511

Distributors:

MTC - Micro Tech Components GmbH

AM Reitweg 15

89407 Dillingen, GERMANY

e-mail : M

M

MT

T

TC

C

Ci

i

in

n

nf

f

fo

o

o@

@

@m

m

mt

t

tc

c

c.

.

.d

d

de

e

tel. : +49 9071 7945-0

fax : +49 9071 7945-20

Territory: Germany, Austria, Switzerland