Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
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DDR2 Unbuffered SDRAM MODULE
240pin Unbuffered Module based on 1Gb Q-die
64/72-bit Non-ECC/ECC
60FBGA & 84FBGA with Lead-Free and Halogen-Free
(RoHS compliant)
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
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Table of Contents
1.0 DDR2 Unbuffered DIMM Ordering Information ..........................................................................4
2.0 Features .........................................................................................................................................4
3.0 Address Configuration .................................................................................................................4
4.0 x64 DIMM Pin Configurations (Front side/Back side) ................................................................5
5.0 x72 DIMM Pin Configurations (Front side/Back side) ................................................................6
6.0 Pin Description ..............................................................................................................................6
7.0 Input/Output Function Description .............................................................................................7
8.0 Functional Block Diagram : .........................................................................................................8
8.1 1GB, 128Mx64 Module - M378T2863QZ(H)S ......................................................................................8
8.2 1GB, 128Mx72 ECC Module - M391T2863QZ(H)3 ................................................................................9
8.3 2GB, 256Mx64 Module - M378T5663QZ(H)3 .....................................................................................10
8.4 2GB, 256Mx72 ECC Module - M391T5663QZ(H)3 ..............................................................................11
8.5 512MB, 64Mx64 Module - M378T6464QZ(H)3 ...................................................................................12
9.0 Absolute Maximum DC Ratings .................................................................................................13
10.0 AC & DC Operating Conditions ...............................................................................................13
10.1 Recommended DC Operating Conditions (SSTL - 1.8) ....................................................................13
10.2 Operating Temperature Condition ................................................................................................14
10.3 Input DC Logic Level ..................................................................................................................14
10.4 Input AC Logic Level ..................................................................................................................14
10.5 AC Input Test Conditions ............................................................................................................14
11.0 IDD Specification Parameters Definition ................................................................................15
12.0 Operating Current Table : .........................................................................................................16
12.1 M378T2863QZ(H)S : 1GB(128Mx8 *8) Module ................................................................................16
12.2 M378T5663QZ(H)3 : 2GB(128Mx8 *16) Module ..............................................................................16
12.3 M391T2863QZ(H)3 : 1GB(128Mx8 *9) ECC Module ..........................................................................17
12.4 M391T5663QZ(H)3 : 2GB(128Mx8 *18) ECC Module ........................................................................17
12.5 M378T6464QZ(H)3 : 512MB(64Mx16 *4) Module .............................................................................18
13.0 Input/Output Capacitance ........................................................................................................19
14.0 Electrical Characteristics & AC Timing for DDR2-800/667 ....................................................19
14.1 Refresh Parameters by Device Density .........................................................................................19
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ..............................................19
14.3 Timing Parameters by Speed Grade .............................................................................................20
15.0 Physical Dimensions : ..............................................................................................................22
15.1 128Mbx8 based 128Mx64 Module (1 Rank) ....................................................................................22
15.2 128Mbx8 based 128M x72 Module (1 Rank) ...................................................................................23
15.3 128Mbx8 based 256Mx64/x72 Module (2 Ranks) .............................................................................24
15.4 64Mbx16 based 64Mx64 Module (1 Rank) ......................................................................................25
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UDIMM DDR2 SDRAM
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Revision History
Revision Month Year History
1.0 September 2007 - Initial Release
1.1 April 2008 - Correted Typo
1.2 July 2008 - Applied JEDEC update(JESD79-2E) on AC timing table
1.3 December 2008 - Added comments in physical dimension
1.31 March 2009 - Corrected Typo
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UDIMM DDR2 SDRAM
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1.0 DDR2 Unbuffered DIMM Ordering Information
2.0 Features
Note :
1. “Z” of Part number(12th digit) stands for Lead-Free and RoHS compliant products.
2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
3. “3” of Part number(13th digit) stands for Dummy Pad PCB products.
Part Number Density Organization Component Composition Number of Rank Height
x64 Non ECC
M378T2863QZ(H)S-CE7/F7/E6 1GB 128Mx64 128Mx8(K4T1G084QQ)*8 1 30mm
M378T5663QZ(H)3-CE7/F7/E6 2GB 256Mx64 128Mx8(K4T1G084QQ)*16 2 30mm
M378T6464QZ(H)3-CE7/F7/E6 512MB 64Mx64 64Mx16(K4T1G164QQ)*4 1 30mm
x72 ECC
M391T2863QZ(H)3-CE7/F7/E6 1GB 128Mx72 128Mx8(K4T1G084QQ)*9 1 30mm
M391T5663QZ(H)3-CE7/F7/E6 2GB 256Mx72 128Mx8(K4T1G084QQ)*18 2 30mm
• Performance range
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply
•V
DDQ = 1.8V ± 0.1V
• 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
- Support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 128Mx8 and 84ball FBGA - 64Mx16
• All of base components are Lead-Free, Halogen-Free, and RoHS compliant
E7 (DDR2-800) F7 (DDR2-800) E6 (DDR2-667) Unit
Speed@CL3 400 -400 Mbps
Speed@CL4 533 533 533 Mbps
Speed@CL5 800 667 667 Mbps
Speed@CL6 -800 -Mbps
CL-tRCD-tRP 5-5-5 6-6-6 5-5-5 CK
3.0 Address Configuration
Organization Row Address Column Address Bank Address Auto Precharge
128Mx8(1Gb) based Module A0-A13 A0-A9 BA0-BA2 A10
64Mx16(1Gb) based Module A0-A12 A0-A9 BA0-BA2 A10
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UDIMM DDR2 SDRAM
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NC = No Connect, RFU = Reserved for Future Use
1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5
2VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 NC
3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS
4DQ1124
VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46
5VSS 125 DM0 35 VSS 155 DM3 KEY 95 DQ42 215 DQ47
6DQS
0 126 NC 36 DQS3 156 NC 65 VSS 185 CK0 96 DQ43 216 VSS
7DQS0127VSS 37 DQS3 157 VSS 66 VSS 186 CK097 VSS 217 DQ52
8VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53
9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC 188 A0 99 DQ49 219 VSS
10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 CK2
11 VSS 131 DQ12 41 VSS 161 NC 70 A10/AP 190 BA1 101 SA2 221 CK2
12 DQ8 132 DQ13 42 NC 162 NC 71 BA0 191 VDDQ 102 NC, TEST2222 VSS
13 DQ9 133 VSS 43 NC 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6
14 VSS 134 DM1 44 VSS 164 NC 73 WE 193 S0 104 DQS6 224 NC
15 DQS1 135 NC 45 NC 165 NC 74 CAS 194 VDDQ 105 DQS6 225 VSS
16 DQS1 136 VSS 46 NC 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54
17 VSS 137 CK1 47 VSS 167 NC 76 S1196
A131107 DQ50 227 DQ55
18 NC 138 CK1 48 NC 168 NC 77 ODT1 197 VDD 108 DQ51 228 VSS
19 NC 139 VSS 49 NC 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60
20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 DQ61
21 DQ10 141 DQ15 51 VDDQ 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS
22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7
23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4 113 DQS7 233 NC
24 DQ16 144 DQ21 54 BA2 174 NC 83 DQS4203 NC 114DQS7234 VSS
25 DQ17 145 VSS 55 NC 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62
26 VSS 146 DM2 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63
27 DQS2 147 NC 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS
28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD
29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0
30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1
90 DQ41 210 VSS
4.0 x64 DIMM Pin Configurations (Front side/Back side)
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UDIMM DDR2 SDRAM
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NC = No Connect, RFU = Reserved for Future Use
1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5
2VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 NC
3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS
4DQ1124
VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46
5VSS 125 DM0 35 VSS 155 DM3 KEY 95 DQ42 215 DQ47
6DQS
0 126 NC 36 DQS3 156 NC 65 VSS 185 CK0 96 DQ43 216 VSS
7DQS0127VSS 37 DQS3 157 VSS 66 VSS 186 CK097VSS 217 DQ52
8VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53
9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC 188 A0 99 DQ49 219 VSS
10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 CK2
11 VSS 131 DQ12 41 VSS 161 CB4 70 A10/AP 190 BA1 101 SA2 221 CK2
12 DQ8 132 DQ13 42 CB0 162 CB5 71 BA0 191 VDDQ 102 NC, TEST2222 VSS
13 DQ9 133 VSS 43 CB1 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6
14 VSS 134 DM1 44 VSS 164 DM8 73 WE 193 S0 104 DQS6 224 NC
15 DQS1 135 NC 45 DQS8 165 NC 74 CAS 194 VDDQ 105 DQS6 225 VSS
16 DQS1 136 VSS 46 DQS8 166 VSS 75 VDDQ 195ODT0106 VSS 226 DQ54
17 VSS 137 CK1 47 VSS 167 CB6 76 S1 196 A13 107 DQ50 227 DQ55
18 NC 138 CK1 48 CB2 168 CB7 77 ODT1 197 VDD 108 DQ51 228 VSS
19 NC 139 VSS 49 CB3 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60
20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 DQ61
21 DQ10 141 DQ15 51 VDDQ 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS
22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7
23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4 113 DQS7 233 NC
24 DQ16 144 DQ21 54 BA2 174 NC 83 DQS4 203 NC 114 DQS7 234 VSS
25 DQ17 145 VSS 55 NC 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62
26 VSS 146 DM2 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63
27 DQS2 147 NC 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS
28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD
29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0
30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1
90 DQ41 210 VSS
5.0 x72 DIMM Pin Configurations (Front side/Back side)
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Pin Name Description Pin Name Description
A0-A13 DDR2 SDRAM address bus CK0, CK1, CK2 DDR2 SDRAM clocks (positive line of differential pair)
BA0-BA2 DDR2 SDRAM bank select CK0, CK1, CK2 DDR2 SDRAM clocks (negative line of differential pair)
RAS DDR2 SDRAM row address strobe SCL I2C serial bus clock for EEPROM
CAS DDR2 SDRAM column address strobe SDA I2C serial bus data line for EEPROM
WE DDR2 SDRAM wirte enable SA0-SA2 I2C serial address select for EEPROM
S0, S1 DIMM Rank Select Lines VDD*DDR2 SDRAM core power supply
CKE0,CKE1 DDR2 SDRAM clock enable lines VDDQ*DDR2 SDRAM I/O Driver power supply
ODT0, ODT1 On-die termination control lines VREF DDR2 SDRAM I/O reference supply
DQ0 - DQ63 DIMM memory data bus VSS Power supply return (ground)
CB0 - CB7 DIMM ECC check bits VDDSPD Serial EEPROM positive power supply
DQS0 - DQS8 DDR2 SDRAM data strobes NC Spare Pins(no connect)
DM(0-8) DDR2 SDRAM data masks RESET Not used on UDIMM
DQS0-DQS8 DDR2 SDRAM differential data strobes TEST Used by memory bus analysis tools
(unused on memory DIMMs)
6.0 Pin Description
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UDIMM DDR2 SDRAM
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Symbol Type Description
CK0-CK2
CK0-CK2Input
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of
positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK
(Both directions of crossing)
CKE0-CKE1 Input Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the
clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode
S0-S1 Input
Enables the associated SDRAM command decoder when low and disables the command decoder when
high. When the command decoder is disbled, new command are ignored but previous operations continue.
This signal provides for external rank selection on systems with multiple ranks
RAS, CAS, WE Input RAS, CAS, and WE (ALONG WITH CS) define the command being entered.
ODT0-ODT1 Input When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled
in the Extended Mode Register Set (EMRS).
VREF Supply Reference voltage for SSTL 18 inputs.
VDDQ Supply Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current
DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0-BA2 Input Selects which SDRAM BANK of four is activated.
A0-A13 Input
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the colum address, In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is
high, autoprecharge is selected and BA0-BA2 defines the bank to be precharged. If AP is low, autopre-
charge is disbled. During a precharge command cycle, AP is used in conjunction with BA0-BA2 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BA2.
If AP is low, BA0, BA1, BA2 are used to define which bank to precharge.
DQ0-DQ63
CB0-CB7 In/Out Data and Check Bit Input/Output pins.
DM0-DM8 Input
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with
that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading.
VDD,VSS Supply Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/
VDDQ planes on these modules.
DQS0-DQS8
DQS0-DQS8In/Out Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the
LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM
SA0-SA2 Input These signals and tied at the system planar to either VSS or VDD to configure the serial SPD EERPOM
address range.
SDA In/Out This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected
from the SDA bus line to VDD to act as a pullup on the system board.
7.0 Input/Output Function Description
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UDIMM DDR2 SDRAM
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S0
DQS0
DQS0
DM0
DM CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
DQS1
DQS1
DM1
DM CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS2
DQS2
DM2
DM CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DQS3
DQS3
DM3
DM NU/ CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DQS4
DQS4
DM4
DM CS DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS5
DQS5
DM5
DM CS DQS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS6
DQS6
DM6
DM CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS7
DQS7
DM7
DM CS DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
Note :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.
(Populated as 1 rank of x8 DDR2 SDRAMs)
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL
SDA
WP
*Wire per Clock Loading
Table/Wiring Diagrams
* Clock Wiring
Clock Input DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 DDR2 SDRAMs
3 DDR2 SDRAMs
3 DDR2 SDRAMs
VSS D0 - D7
VDD/VDDQ D0 - D7
D0 - D7VREF
VDDSPD Serial PD
A0 - A13 A0-A13 : DDR2 SDRAMs D0 - D7
RAS RAS : DDR2 SDRAMs D0 - D7
CAS CAS : DDR2 SDRAMs D0 - D7
WE WE : DDR2 SDRAMs D0 - D7
CKE0 CKE : DDR2 SDRAMs D0 - D7
BA0 - BA2 BA0-BA2 : DDR2 SDRAMs D0 - D7
ODT0 ODT : DDR2 SDRAMs D0 - D7
8.1 1GB, 128Mx64 Module - M378T2863QZ(H)S
8.0 Functional Block Diagram :
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
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S0
DQS0
DQS0
DM0
DM CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
DQS1
DQS1
DM1
DM CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS2
DQS2
DM2
DM CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DQS3
DQS3
DM3
DM CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DQS4
DQS4
DM4
DM CS DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS5
DQS5
DM5
DM CS DQS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS6
DQS6
DM6
DM CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS7
DQS7
DM7
DM CS DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
Note :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL
SDA
WP
*Wire per Clock Loading
Table/Wiring Diagrams
* Clock Wiring
Clock Input DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 DDR2 SDRAMs
3 DDR2 SDRAMs
3 DDR2 SDRAMs
VSS D0 - D8
VDD/VDDQ D0 - D8
D0 - D8VREF
VDDSPD Serial PD
DQS8
DQS8
DM8
DM CS DQS DQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
A0 - A13 A0-A13 : DDR2 SDRAMs D0 - D8
RAS RAS : DDR2 SDRAMs D0 - D8
CAS CAS : DDR2 SDRAMs D0 - D8
WE WE : DDR2 SDRAMs D0 - D8
CKE0 CKE : DDR2 SDRAMs D0 - D8
BA0 - BA2 BA0-BA2 : DDR2 SDRAMs D0 - D8
ODT0 ODT : DDR2 SDRAMs D0 - D8
(Populated as 1 rank of x8 DDR2 SDRAMs)
8.2 1GB, 128Mx72 ECC Module - M391T2863QZ(H)3
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
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S0
DQS0
DQS0
DM0
DM CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
DQS1
DQS1
DM1
DM CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS2
DQS2
DM2
DM CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DQS3
DQS3
DM3
DM CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DQS4
DQS4
DM4
DM CS DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS5
DQS5
DM5
DM CS DQS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS6
DQS6
DM6
DM CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS7
DQS7
DM7
DM CS DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
Note :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms ± 5%.
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL
SDA
WP
*Wire per Clock Loading
Table/Wiring Diagrams
* Clock Wiring
Clock Input DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
4 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
VSS D0 - D15
VDD/VDDQ D0 - D15
D0 - D15VREF
VDDSPD Serial PD
A0 - A13 A0-A13 : DDR2 SDRAMs D0 - D15
WE WE : DDR2 SDRAMs D0 - D15
CKE1 CKE : DDR2 SDRAMs D8 - D15
BA0 - BA2 BA0-BA2 : DDR2 SDRAMs D0 - D15
ODT0 ODT : DDR2 SDRAMs D0 - D7
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D9
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D10
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D11
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D13
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D14
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D15
S1
CKE0 CKE : DDR2 SDRAMs D0 - D7
RAS RAS : DDR2 SDRAMs D0 - D15
CAS CAS : DDR2 SDRAMs D0 - D15
ODT1 ODT : DDR2 SDRAMs D8 - D15
(Populated as 2 ranks of x8 DDR2 SDRAMs)
8.3 2GB, 256Mx64 Module - M378T5663QZ(H)3
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
11 of 25
S0
DQS0
DQS0
DM0
DM CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
DQS1
DQS1
DM1
DM CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS2
DQS2
DM2
DM CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DQS3
DQS3
DM3
DM CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DQS4
DQS4
DM4
DM CS DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS5
DQS5
DM5
DM CS DQS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS6
DQS6
DM6
DM CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS7
DQS7
DM7
DM CS DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
Note :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms ± 5%.
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL
SDA
WP
*Wire per Clock Loading
Table/Wiring Diagrams
* Clock Wiring
Clock Input DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
VSS D0 - D17
VDD/VDDQ D0 - D17
D0 - D17VREF
VDDSPD Serial PD
A0 - A13 A0-A13 : DDR2 SDRAMs D0 - D17
WE WE : DDR2 SDRAMs D0 - D17
CKE1 CKE : DDR2 SDRAMs D9 - D17
BA0 - BA2 BA0-BA2 : DDR2 SDRAMs D0 - D17
ODT0 ODT : DDR2 SDRAMs D0 - D8
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D9
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D10
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D11
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D13
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D14
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D15
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D16
S1
CKE0 CKE : DDR2 SDRAMs D0 - D8
RAS RAS : DDR2 SDRAMs D0 - D17
CAS CAS : DDR2 SDRAMs D0 - D17
ODT1 ODT : DDR2 SDRAMs D9 - D17
DQS8
DQS8
DM8
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
(Populated as 2 ranks of x8 DDR2 SDRAMs)
8.4 2GB, 256Mx72 ECC Module - M391T5663QZ(H)3
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
12 of 25
S0
DQS1
DQS1
DM1
CS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
4. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL
SDA
WP
*Wire per Clock Loading
Table/Wiring Diagrams
* Clock Wiring
Clock Input DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
NC
2 DDR2 SDRAMs
2 DDR2 SDRAMs
VSS D0 - D3
VDD/VDDQ D0 - D3
D0 - D3VREF
VDDSPD Serial PD
A0 - A12 A0-A12 : DDR2 SDRAMs D0 - D3
WE WE : DDR2 SDRAMs D0 - D3
BA0 - BA1 BA0-BA1 : DDR2 SDRAMs D0 - D3
ODT0 ODT : DDR2 SDRAMs D0 - D3
CKE0 CKE : DDR2 SDRAMs D0 - D3
RAS RAS : DDR2 SDRAMs D0 - D3
CAS CAS : DDR2 SDRAMs D0 - D3
LDQS
LDOS
LDM
DQS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
UDQS
UDOS
UDM
DQS5
DQS5
DM5
CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
LDQS
LDOS
LDM
DQS4
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
UDQS
UDOS
UDM
DQS3
DQS3
DM3
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
LDQS
LDOS
LDM
DQS2
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
UDQS
UDOS
UDM
DQS7
DQS7
DM7
CS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
LDQS
LDOS
LDM
DQS6
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
UDQS
UDOS
UDM
(Populated as 1 rank of x16 DDR2 SDRAMs)
8.5 512MB, 64Mx64 Module - M378T6464QZ(H)3
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
13 of 25
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal
to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.7 1.8 1.9 V
VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 4
VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 4
VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 1,2
VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 3
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
Symbol Parameter Rating Units Notes
VDD Voltage on VDD pin relative to VSS - 1.0 V ~ 2.3 V V 1
VDDQ Voltage on VDDQ pin relative to VSS - 0.5 V ~ 2.3 V V 1
VDDL Voltage on VDDL pin relative to VSS - 0.5 V ~ 2.3 V V 1
VIN, VOUT Voltage on any pin relative to VSS - 0.5 V ~ 2.3 V V 1
TSTG Storage Temperature -55 to +100 °C 1, 2
10.0 AC & DC Operating Conditions
10.1 Recommended DC Operating Conditions (SSTL - 1.8)
9.0 Absolute Maximum DC Ratings
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
14 of 25
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
Symbol Condition Value Units Notes
VREF Input reference voltage 0.5 * VDDQ V1
VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1
SLEW Input signal minimum slew rate 1.0 V/ns 2, 3
VDDQ
VIH(AC) min
VIH(DC) min
VREF
VIL(DC) max
VIL(AC) max
VSS
< AC Input Test Signal Waveform >
VSWING(MAX)
delta TRdelta TF
VREF - VIL(AC) max
delta TF
Falling Slew = Rising Slew = VIH(AC) min - VREF
delta TR
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Symbol Parameter Rating Units Notes
TOPER Operating Temperature 0 to 95 °C 1, 2
10.3 Input DC Logic Level
Symbol Parameter Min. Max. Units Notes
VIH(DC) DC input logic high VREF + 0.125 VDDQ + 0.3 V
VIL(DC) DC input logic low - 0.3 VREF - 0.125 V
10.4 Input AC Logic Level
Symbol Parameter DDR2-667, DDR2-800 Units Notes
Min. Max.
VIH(AC) AC input logic high VREF + 0.200 V
VIL(AC) AC input logic low VREF - 0.200 V
10.5 AC Input Test Conditions
10.2 Operating Temperature Condition
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
15 of 25
(IDD values are for full operating range of Voltage and Temperature)
Symbol Proposed Conditions Units Note
IDD0
Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDD4W
mA
IDD2P
Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
mA
IDD2Q
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
mA
IDD2N
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
mA
IDD3P
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0 mA
Slow PDN Exit MRS(12) = 1 mA
IDD3N
Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
mA
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-
max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
mA
IDD5B
Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD6
Self refresh current;
CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal mA
Low Power mA
IDD7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =
tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following
page for detailed timing conditions
mA
11.0 IDD Specification Parameters Definition
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
16 of 25
12.1 M378T2863QZ(H)S : 1GB(128Mx8 *8) Module
12.2 M378T5663QZ(H)3 : 2GB(128Mx8 *16) Module
(TA=0oC, VDD= 1.9V)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol 800@CL=5 800@CL6 667@CL=5 Units Notes
CE7 CF7 CE6
IDD0 600 600 560 mA
IDD1 680 680 640 mA
IDD2P 120 120 120 mA
IDD2Q 240 240 240 mA
IDD2N 280 280 280 mA
IDD3P-F 280 280 280 mA
IDD3P-S 144 144 144 mA
IDD3N 440 440 400 mA
IDD4W 920 920 840 mA
IDD4R 1,080 1,080 960 mA
IDD5 1,160 1,160 1,120 mA
IDD6 120 120 120 mA
IDD7 2,000 2,000 1,840 mA
(TA=0oC, VDD= 1.9V)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol 800@CL=5 800@CL=6 667@CL=5 Units Notes
CE7 CF7 CE6
IDD0 880 880 840 mA
IDD1 960 960 920 mA
IDD2P 240 240 240 mA
IDD2Q 480 480 480 mA
IDD2N 560 560 560 mA
IDD3P-F 560 560 560 mA
IDD3P-S 288 288 288 mA
IDD3N 720 720 680 mA
IDD4W 1,200 1,200 1,120 mA
IDD4R 1,360 1,360 1,240 mA
IDD5 1,440 1,440 1,400 mA
IDD6 240 240 240 mA
IDD7 2,280 2,280 2,120 mA
12.0 Operating Current Table :
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
17 of 25
12.4 M391T5663QZ(H)3 : 2GB(128Mx8 *18) ECC Module
(TA=0oC, VDD= 1.9V)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol 800@CL=5 800@CL=6 667@CL=5 Units Notes
CE7 CF7 CE6
IDD0 675 675 630 mA
IDD1 765 765 720 mA
IDD2P 135 135 135 mA
IDD2Q 270 270 270 mA
IDD2N 315 315 315 mA
IDD3P-F 315 315 315 mA
IDD3P-S 162 162 162 mA
IDD3N 495 495 450 mA
IDD4W 1,035 1,035 945 mA
IDD4R 1,215 1,215 1,080 mA
IDD5 1,305 1,305 1,260 mA
IDD6 135 135 135 mA
IDD7 2,250 2,250 2,070 mA
(TA=0oC, VDD= 1.9V)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol 800@CL=5 800@CL=6 667@CL=5 Units Notes
CE7 CF7 CE6
IDD0 990 990 945 mA
IDD1 1,080 1,080 1,035 mA
IDD2P 270 270 270 mA
IDD2Q 540 540 540 mA
IDD2N 630 630 630 mA
IDD3P-F 630 630 630 mA
IDD3P-S 324 324 324 mA
IDD3N 810 810 765 mA
IDD4W 1,350 1,350 1,260 mA
IDD4R 1,530 1,530 1,395 mA
IDD5 1,620 1,620 1,575 mA
IDD6 270 270 270 mA
IDD7 2,565 2,565 2,385 mA
12.3 M391T2863QZ(H)3 : 1GB(128Mx8 *9) ECC Module
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
18 of 25
(TA=0oC, VDD= 1.9V)
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Symbol 800@CL=5 800@CL=6 667@CL=5 Units Notes
CE7 CF7 CE6
IDD0 360 360 340 mA
IDD1 400 400 380 mA
IDD2P 60 60 60 mA
IDD2Q 120 120 120 mA
IDD2N 140 140 140 mA
IDD3P-F 140 140 140 mA
IDD3P-S 72 72 72 mA
IDD3N 220 220 200 mA
IDD4W 520 520 460 mA
IDD4R 700 700 620 mA
IDD5 580 580 560 mA
IDD6 60 60 60 mA
IDD7 1,060 1,060 980 mA
12.5 M378T6464QZ(H)3 : 512MB(64Mx16 *4) Module
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
19 of 25
(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Note : DM is internally loaded to match DQ and DQS identically.
Parameter Symbol Min Max Min Max Min Max Units
Non-ECC M378T2863QZ(H)S M378T5663QZ(H)3 M378T6464QZ(H)3
Input capacitance, CK and CK
CCK0 -24 -26 -22
pF
CCK1 -25 -28 -24
CCK2 -25 -28 -24
Input capacitance, CKE and CS CI1 - 42 -42 -34
Input capacitance, Addr, RAS, CAS, WE CI2 - 42 -42 -34
Input/output capacitance, DQ, DM, DQS, DQS CIO - 6 - 10 - 6
ECC M391T2863QZ(H)3 M391T5663QZ(H)3 Units
Input capacitance, CK and CK
CCK0 -25 -28
pF
CCK1 -25 -28
CCK2 -25 -28
Input capacitance, CKE and CS CI1-44 -44
Input capacitance, Addr, RAS, CAS, WE CI2-44 -44
Input/output capacitance, DQ, DM, DQS, DQS CIO - 6 - 10
Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units
Refresh to active/Refresh command time tRFC 75 105 127.5 195 327.5 ns
Average periodic refresh interval tREFI
0 °C ≤ TCASE ≤ 85°C7.8 7.8 7.8 7.8 7.8 µs
85 °C < TCASE ≤ 95°C3.9 3.9 3.9 3.9 3.9 µs
(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
14.1 Refresh Parameters by Device Density
Speed DDR2-800(E7) DDR2-800(F7) DDR2-667(E6)
UnitsBin(CL - tRCD - tRP) 5 - 5 - 5 6 - 6- 6 5 - 5 - 5
Parameter min max min max min max
tCK, CL=3 5 8 - - 5 8 ns
tCK, CL=4 3.75 83.75 83.75 8ns
tCK, CL=5 2.5 8 3 8 3 8 ns
tCK, CL=6 - - 2.5 8 - - ns
tRCD 12.5 -15 -15 -ns
tRP 12.5 -15 -15 -ns
tRC 57.5 -60 -60 -ns
tRAS 45 70000 45 70000 45 70000 ns
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
14.0 Electrical Characteristics & AC Timing for DDR2-800/667
13.0 Input/Output Capacitance
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
20 of 25
(Refer to notes for informations related to this table at the component datasheet)
Parameter Symbol DDR2-800 DDR2-667 Units Notes
min max min max
DQ output access time from CK/CK tAC -400 400 -450 450 ps 40
DQS output access time from CK/CK tDQSCK -350 350 -400 400 ps 40
Average clock HIGH pulse width tCH(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36
Average clock LOW pulse width tCL(avg) 0.48 0.52 0.48 0.52 tCK(avg) 35,36
CK half pulse period tHP Min(tCL(abs),
tCH(abs)) xMin(tCL(abs),
tCH(abs)) xps 37
Average clock period tCK(avg) 2500 8000 3000 8000 ps 35,36
DQ and DM input hold time tDH(base) 125 x 175 x ps 6,7,8,21,28,31
DQ and DM input setup time tDS(base) 50 x 100 x ps 6,7,8,20,28,31
Control & Address input pulse width for each input tIPW 0.6 x 0.6 x tCK(avg)
DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x tCK(avg)
Data-out high-impedance time from CK/CK tHZ x tAC(max) x tAC(max) ps 18,40
DQS/DQS low-impedance time from CK/CK tLZ(DQS) tAC(min) tAC(max) tAC(min) tAC(max) ps 18,40
DQ low-impedance time from CK/CK tLZ(DQ) 2* tAC(min) tAC(max) 2* tAC(min) tAC(max) ps 18,40
DQS-DQ skew for DQS and associated DQ signals tDQSQ x 200 x 240 ps 13
DQ hold skew factor tQHS x300 x340 ps 38
DQ/DQS output hold time from DQS tQH tHP - tQHS xtHP - tQHS xps 39
DQS latching rising transitions to associated clock edges tDQSS - 0.25 0.25 -0.25 0.25 tCK(avg) 30
DQS input HIGH pulse width tDQSH 0.35 x0.35 xtCK(avg)
DQS input LOW pulse width tDQSL 0.35 x0.35 xtCK(avg)
DQS falling edge to CK setup time tDSS 0.2 x0.2 xtCK(avg) 30
DQS falling edge hold time from CK tDSH 0.2 x0.2 xtCK(avg) 30
Mode register set command cycle time tMRD 2 x 2 x nCK
MRS command to ODT update delay tMOD 0 12 0 12 ns 32
Write postamble tWPST 0.4 0.6 0.4 0.6 tCK(avg) 10
Write preamble tWPRE 0.35 x0.35 xtCK(avg)
Address and control input hold time tIH(base) 250 x275 xps 5,7,9,23,29
Address and control input setup time tIS(base) 175 x200 xps 5,7,9,22,29
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK(avg) 19,41
Read postamble tRPST 0.4 0.6 0.4 0.6 tCK(avg) 19,42
Activate to activate command period for 1KB page size products tRRD 7.5 x 7.5 x ns 4,32
Activate to activate command period for 2KB page size products tRRD 10 x10 xns 4,32
14.3 Timing Parameters by Speed Grade
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
21 of 25
Parameter Symbol DDR2-800 DDR2-667 Units Notes
min max min max
Four Activate Window for 1KB page size products tFAW 35 x37.5 xns 32
Four Activate Window for 2KB page size products tFAW 45 x50 xns 32
CAS to CAS command delay tCCD 2 x 2 x nCK
Write recovery time tWR 15 x15 xns 32
Auto precharge write recovery + precharge time tDAL WR + tnRP xWR + tnRP xnCK 33
Internal write to read command delay tWTR 7.5 x7.5xns 24,32
Internal read to precharge command delay tRTP 7.5 x7.5xns 3,32
Exit self refresh to a non-read command tXSNR tRFC + 10 x tRFC + 10 xns 32
Exit self refresh to a read command tXSRD 200 x 200 xnCK
Exit precharge power down to any command tXP 2 x 2 x nCK
Exit active power down to read command tXARD 2 x 2 x nCK 1
Exit active power down to read command
(slow exit, lower power) tXARDS 8 - AL x7 - AL xnCK 1,2
CKE minimum pulse width (HIGH and LOW pulse width) tCKE 3 x 3 x nCK 27
ODT turn-on delay tAOND 2222
nCK 16
ODT turn-on tAON tAC(min) tAC(max)+0.7 tAC(min) tAC(max)+0.7 ns 6,16,40
ODT turn-on (Power-Down mode) tAONPD tAC(min)+2 2*tCK(avg)
+tAC(max)+1 tAC(min)+2 2*tCK(avg)
+tAC(max)+1 ns
ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 nCK 17,45
ODT turn-off tAOF tAC(min) tAC(max)+0.6 tAC(min) tAC(max)+0.6 ns 17,43,45
ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5*tCK(avg)
+tAC(max)+1 tAC(min)+2 2.5*tCK(avg)
+tAC(max)+1 ns
ODT to power down entry latency tANPD 3 x3xnCK
ODT power down exit latency tAXPD 8 x8xnCK
OCD drive mode output delay tOIT 0 12 0 12 ns 32
Minimum time clocks remains ON after CKE asynchronously
drops LOW tDelay tIS+tCK(avg)
+tIH xtIS+tCK(avg)
+tIH xns 15
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
22 of 25
Units : Millimeters
The used device is 128M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G084QQ
Tolerances on all dimensions are ± 0.15, unless otherwise specified
Physical dimension is JEDEC Compliant
1.00
0.20
2.50 ± 0.20
Detail B
5.00
Detail A
1.50 ± 0.10
0.80 ± 0.05
4.00
3.80
3.00 (4X)
4.00 (4X)
15.1 128Mbx8 based 128Mx64 Module(1 Rank)
15.0 Physical Dimensions :
- M378T2863QZ(H)S
133.35 ± 0.15
1.270 ± 0.10
MAX 2.7
SPD
128.95
2.50 (2X)
30.00 ± 0.15
2.30
AB
63.00 55.00
17.80
10.00
2.50
CENTERLINE
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
23 of 25
Units : Millimeters
- M391T2863QZ(H)3
133.35 ± 0.15
1.270 ± 0.10
MAX 2.7
SPD
(for x72)
128.95
ECC
AB
63.00 55.00
15.2 128Mbx8 based 128Mx72 Module(1 Rank)
2.50 (2X)
30.00 ± 0.15
2.30
17.80
10.00
The used device is 128M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G084QQ
Tolerances on all dimensions are ± 0.15, unless otherwise specified
Physical dimension is JEDEC Compliant
1.00
0.20
2.50 ± 0.20
Detail B
5.00
Detail A
1.50 ± 0.10
0.80 ± 0.05
4.00
3.80
3.00 (4X)
4.00 (4X)
2.50
CENTERLINE
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
24 of 25
Units : Millimeters
133.35 ± 0.15
128.95
AB
63.00 55.00
30.00 ± 0.15
SPD
1.27 ± 0.10
MAX 4.0 mm
1.0 max
N/A
(for x72)
(for x64)
ECC
N/A
(for x72)
(for x64)
ECC
- M378T5663QZ(H)3/M391T5663QZ(H)3
15.3 128Mbx8 based 256Mx64/x72 Module(2 Ranks)
2.30
2.50 (2X)
10.00
The used device is 128M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G084QQ
Tolerances on all dimensions are ± 0.15, unless otherwise specified
Physical dimension is JEDEC Compliant
1.00
0.20
2.50 ± 0.20
Detail B
5.00
Detail A
1.50 ± 0.10
0.80 ± 0.05
4.00
3.80
3.00 (4X)
4.00 (4X)
2.50
CENTERLINE
17.80
Rev. 1.31 December 2008
UDIMM DDR2 SDRAM
25 of 25
133.35 ± 0.15
128.9
30.00 ± 0.15
SPD
1.270 ± 0.10
MAX 2.7
The used device is 64M x16 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G164QQ
Tolerances on all dimensions are ± 0.15, unless otherwise specified
Physical dimension is JEDEC Compliant
AB
63.00 55.00
Units : Millimeters
- M378T6464QZ(H)3
15.4 64Mbx16 based 64Mx64 Module (1 Rank)
2.30
2.50 (2X)
1.00
0.20
2.50 ± 0.20
Detail B
5.00
Detail A
1.50 ± 0.10
0.80 ± 0.05
4.00
3.80
3.00 (4X)
4.00 (4X)
2.50
CENTERLINE
10.00
17.80
