SM2480A-MZEQ-Y - Adesto Technologies

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ADVANCE DATASHEET

Features

Dual core architecture with custom N-PLC optimized DSP and Data Link Layer 32bit controller

High speed PWM with 6 channels of outputs with programmable pairing modes and independent settings

4 comparators with independent references and programmable fault detection

16 channel Signal Monitoring ADC with simultaneous sampling of voltage/current pairs

High performing custom N-PLC DSP engine with embedded turnkey firmware featuring:

Configurable operational band within 5-500KHz range – compliant with CENELEC, FCC and ARIB bands

operation

OFDM and FSK modulations

Compliant with IEEE 1901.2, PRIME, G3-PLC, CTIA/EIA709.2, G.hnem

Proprietary operation modes: NOFDM

Selectable differential and coherent BPSK, QPSK, 8PSK and coherent 16QAM modulations

Configurable data rate up to 500kbps

Programmable frequency notching to improve coexistence

Jammer cancellation

Adaptive tone mapping (on-off sub-band bit loading)

FEC – Convolutional, Reed-Salomon and Viterbi coding

CRC16

Carrier RSSI, SNR and LQI indicators for best channel adaptation and L2/L3 metrics

Zero-crossing detector

Programmable 32bit RISC protocol engine featuring:

Data Link Layer firmware options compliant with IEEE 1901.2, G3-PLC, PRIME, IEC61334-4-32 and others

Direct access to Signal Monitoring ADC for SCADA algorithms implementation - Solar micro-inverter, Arc

detection, LED control, etc.

Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA) channel access

Automatic Repeat Request (ARQ)

Meshing and self discovery mechanisms

CCM* with AES128 / AES256 encryption core

On-chip Peripheral Interfaces:

UART

5 GPIO’s

JTAG

SPI master for external flash

Up to 2 additional SPI slaves for metering, wireless transceiver or other devices

Seamless interface to an external line driver for optimal system performance:

Integrated A/D and D/A

Integrated OpAmp’s for RX and TX

Integrated PGA

Low power operation modes

Offline mode

Listen mode

Receive mode

Transmit mode

SM2480

Integrated N-PLC SCADA Controller

for Solar Micro-inverters and Smart Ballasts

Semitech Semiconductor

Communication technology by:

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3.3V (5V tolerant) digital I/O

Receiver sensitivity of -80dBV

-40 °C to +105 °C temperature range

LQFP128 pin package

Benefits

Single-chip grid connected signal controller ideal for solar inverters, smart lighting ballasts and other SCADA

applications reducing cost and simplifying the design

Flexible high-speed PWM and high precision dual ADC allowing simultaneous sampling of I/V values as well as fast

and flexible signal adjustments ideal for power-conversion applications

Programmable comparator triggered events for fault detection and handling

High speed, flexible and reliable communication through integrated programmable multi-mode N-PLC modem

supporting all common OFDM standards including full compliance with: IEEE 1901.2, G3-PLC, PRIME, G.hnem as

well as FSK/S-FSK and proprietary communication schemes

Low latency communication schemes

Cost optimized system solution with integrated A/D's, D/A's, OpAmp's, PGA

Overview

The SM2480 is a member of the SM24xx family that expands the SM2400 Narrowband Power Line Communication (N-

PLC) modem to a fully integrated Analog Controller with Grid connectivity. It is specifically targeted for applications such

as solar panel micro-inverters, smart LED controllers and other Grid-connected devices. For easy and cost effective

system design the SM2480 combines N-PLC connectivity with analog signal monitoring and control required by such

applications. As all the members of the SM24xx family, the SM2480 features a dual core architecture, dedicating one

core to the system control application and a second core to guarantee superior communication performance, while

maintaining flexibility and programmability for OFDM based standards and proprietary communication schemes. Both

cores are supported by full development systems to facilitate implementation of proprietary application specific control

and monitoring algorithms.

Applications

Solar micro-inverters and alternative energy management

Smart lighting control

Building automation (BA)

SCADA (Supervisory Control And Data Acquisition)

Figure 0-1. SM2480 N-PLC SCADA Controller

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1. Description

The SM2480 is single chip "grid connected" that combines the most advanced N-PLC connectivity with high speed PWM

control logic and featuring extensive computational power to enable complete and flexible implementation of solar-

microinverter, Arc detection, LED control and similar algorithms. The SM2480 combines the benefits of programmable

architecture with power and cost efficiency by utilizing two 32bit cores designed specifically for N-PLC modulations,

voltage/current signal monitoring and M2M protocols.

To efficiently address applications, such as solar micro-inverters, the SM2480 features a high speed flexible PWM

controller with individually programmable 8 pairs of outputs with independent timing, and a number of analog interfaces

that include 16 12-bit ADC channels and 4 comparators for high speed monitoring of I/V and other sensors.

As a member of the SM24xx family the SM2480 features programmable OFDM based N-PLC modem including PHY,

MAC and AFE featuring ADC, DAC, gain control and two OpAmp's for optimal system cost and performance.

The SM2480 comes with a number of firmware versions implementing various N-PLC schemes, such as IEEE 1901.2,

PRIME, G3-PLC, and other special modes tailored for SCADA and smart grid applications.

The SM2480 enables secure communication with its 256-bit AES encryption core with CCM* mode support.

2. Typical Application Diagram

Figure 2-1. SM2480 Based Grid Connected Solar Micro-inverter

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3. Block Diagram

Figure 3-1. SM2480 Block Diagram

4. Signal Control

Additionally to its high computational and DSP performance, the SM2480 integrates advanced features necessary for

implementing a complete analog control system. Those include High Speed PWM, Monitoring ADC, DAC and 4 analog

comparators as well as triggering logic for fast fault detection.

4.1 High Speed PWM

The high speed PWM is designed to control analog peripherals with high short response time and high degree of

accuracy such as power inverters and LED lighting.

6 PWM channels

Each PWM channel consists of PWMLx and PWMHx pins programmable to any of the following modes:

Complementary

Mirrored

Dual Duty Cycle

Pulsed

PWMLx and PWMHx instant output pin swapping

Chopper clock with conditional gating by the PWMH/PWML pins

External reset mode to support terminating (short cycling) the current PWM cycle in two modes;

Constant period

Variable period

Accuracy of up to T=11.1ns (1/90MHz)

Individual and independent parameter setting for each output:

Duty cycle

Dead time

Phase offset

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Period

Two “Group Settings” allowing to manipulate multiple grouped outputs simultaneously (via a single configuration

instruction) to trigger simultaneous changes in PWM frequency, duty cycle, and phase shift

New setting can be applied immediately or at the end of the current period via configuration option

Individual and independent fault and current-limit inputs selectable either from a comparator or an external source

Two triggers per PWM period (falling and rising edges) from PWM to ADC to initiate sampling at T resolution with 8bit

programmable leading edge blanking.

4.2 Signal Monitoring Dual ADC

Signal monitoring is possible using the Simultaneous Sampling Dual ADC which is designed to sample a multitude

of sensors and in particular simultaneously sample current-voltage pairs.

Conversions can be independently triggered by the PWM module or by a timer.

Configurable simultaneous or independent modes are supported.

Each channel has its own data output buffer plus each ADC has a FIFO for burst acquisitions.

4.3 Timer Capture

Three timer capture modules are available for mains synchronisation and detection.

Input Single Ended

Architecture SAR

Number of Inputs 1

Sample Rate Up to 1.0 MSPS

Resolution 12 bits

Input Impedance >k

Input Setting Tiime < 1 s

Operational Power  1.86 mA

Supply Voltage 3.0 ~ 3.6 V

Standby Power <10 A

INL 0.92 LSB

DNL 0.65 LSB

SNDR >70 dB

Time Base 11.1ns

Prescaler 8 bit

Resolution 16 bit

Capture Modes Rising  Rising

Falling  Falling

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4.4 Analog Comparators & DAC’s

The SM2480 incorporates four high-speed analog comparators with individual reference DAC's and individual multi-level

hysteresis control.

5. N-PLC MODEM

Both the SM2400 and the SM2480 support all common N-PLC standards in addition to several proprietary modes of

operation. This enables maximum flexibility to the designer in implementing closed or grid connected SCADA systems

utilizing analog control functions.

Comparators

Output Single Ended

Input Voltage Range 0 ~ AVDD_AIN

Input Offset  5 mV

Output Delay  20 ns

Output Voltage Range 0 ~ AVDD_AIN

Supply Voltage 3.0 ~ 3.6 V

Operational Power < 100 A

Standby Power < 1 A

RDAC Resolution 10 bits

External RDAC

Reference Yes (AOUT_REF)

DAC’s

Output Single Ended

Number of Inputs 1

Resolution 10 bits

External Reference Yes (AOUT_REF)

Reference Voltage 1V ~ AVDD_AOUT

Output Signal Range 0V ~ AOUT_REF

INL 0.88 LSB Max

DNL 0.22 LSB Max

Gain Error < 0.1 LSB

Operational Power < 100 A

Supply Voltage 3.0 ~ 3.6 V

Standby Power < 1 A

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5.1 Selectable Modes and Modulations

The SM2480 can be configured to operate in one of several modes, such as: 1901.2, G3-PLC, PRIME, ITU1901/2,

G.hnem, S-FSK, Lon, NOFDM, etc. Different modes require different firmware images and imply different operational

frequency bands with a varying number of carriers.

The SM2480 allows for configurable modulations per carrier. While most configurations are implied by the different

standards, special modes can be created using specific combinations of carriers and modulations to achieve best

performance in given channel conditions. The following modulations are available: Differential and coherent BPSK,

QPSK and 8PSK and coherent 16QAM.

5.2 Forward Error Correction

The SM2480 supports Reed-Solomon (255,239) and (255,247), and rate half Convolutional coding with constraint length

7 (generator polynomial is [133,171]). In G3 and IEEE modes Convolutional coding is concatenated with RS to achieve

the best reliability. Special error correction modes include extra repetition coding for increased robustness and

puncturing for increased data rate on capable channels.

5.3 Communication Medium Metrics

The SM2480 provides several metrics to assist L2 and L3 channel adaptation and routing. These metrics are: RSSI, SNR

and LQI, which is a measure of the data rate. The RSSI is an estimate of received signal strength. Each packet received

can be interrogated for its estimated signal strength. This is very useful to determine the signal to noise ratio of different

nodes on the network. It may be that the noise in a particular band is low but the signal is also attenuated significantly

making data transmission unreliable. Network management systems can also interrogate each node for signal to noise

ratios to create a database of all transmission path conditions. This produces a deterministic way of finding where

repeaters are needed in a difficult environment even if they are dynamic.

5.4 Security

AES encryption engine conforms to FIPS 197 standard featuring CCM*, ECB, CBC, CTR modes and of up to 256 bit key

size.

5.5 Zero-crossing Detector

The SM2480 has a zero-crossing input pin which takes signals generated by an external zero-crossing detector based

on the transition through zero volts of a 50Hz (or 60Hz) sinusoidal on the power line. The SM2480 provides a phase

detection feature allowing the transmission beginning at an arbitrary phase offset and measuring the phase offset of the

received packet.

6. Analog Front End (AFE)

The SM2480 integrates an AFE optimized for N-PLC communication, which includes ADC, DAC, PGA and 2 OpAmp’s to

achieve the best signal power with minimum external BOM. External components include coupling circuitry and high

voltage line driver that can vary for different applications and for different operational bands.

Table 6-1. ADC

ADC

Input Single Ended

Number of Inputs 1

Sample Rate Up to 2.5MSPS

Resolution 12 bit

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Table 6-2. Main DAC

Table 6-3. OpAmps

Input Bandwidth  600 kHz

Input Impedance > 1k

Input Signal Range 0V ~ AVDD_RX

Supply Voltage 3.0V ~ 3.6V

Standby Power < 10 µA

INL 0.92 LSB

DNL 0.65 LSB

SNDR > 70 dB

DAC

Output Bandwidth 1.06 MHz (0 dB)

Signal Range 0.3 ~ (AVDD_TX - 0.30) V

Supply Voltage 3.00 ~ 3.60 V

Standby Power 7.5 A

SNDR 74 dB

INL < 1.0 LSB

DNL < 0.5 LSB

Recovery From PD < 10 s (No Filter)

Attenuation Range -21 ~ 0 dB

Attenuation Step 3 dB

OpAmps

Open loop gain > 100,000

Slew rate 23 V/µs

GBP (Gain Bandwidth Product) 101 MHz

Input Noise (5kHz ~ 1GHz) 8 µV

Phase Margin 68º

Supply Current 0.88 mA

ADC

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Table 6-4. PGA

7. Peripheral Interfaces

The SM2480 includes several peripheral interfaces for adding optional components. Those interfaces include

UART, SPI master for external flash interface and JTAG. The second SPI extends to two additional devices that

can be used for telemetry or to interface to a wireless transceiver.

Table 7-1. UART

Power Down Current < 0.5 µA

Supply voltage 3.0V ~ 3.6V

Output Rail-to-Rail

PGA

Supply Voltage 3.0 ~ 3.6 V

Standby Current < 1µA

Input Voltage Range Rail-to-Rail

Gain Range 0 ~ 30 dB

Gain Step 3 dB

Output Rail-to-Rail

OpAmps

UART

TX Fifo Yes

RX Fifo Yes

Baud Rate 300 ~ 1Mbps

Data Bits 5, 6, 7, 8

Start Bits 1

Stop Bits 1, 1.5, 2

Parity None, Odd, Even, Sticky

Auto Flow Control Configurable for Tx & Rx

Break Detection Ye s

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Table 7-2. SPI0

Table 7-3. SPI1

Table 7-4. JTAG

8. Boot Options

The SM2480 can be configured to boot in one of four ways:

SPI0

Mode Dedicated Master (boot flash)

TX Fifo Yes

RX Fifo Yes

Data Width 4 ~ 16 bit

SCK Freq Max15MHz

CPOL 0, 1

CPHA 0, 1

Num, Data Frames 0~ 65376 (Allows for automatic

reception and transmit)

SPIS

Mode Slave

TX Fifo Yes

RX Fifo Yes

Data Width 4 ~ 16 bit

SCK Freq Max 6MHz

CPOL 0, 1

CPHA 0, 1

Num, Data Frames 0~ 65376 (Allows for automatic

reception and transmit)

JTAG

JTAG interface for software development.

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Table 8-1. Boot Options

9. Pinout

The SM2480 is offered in a 128pin LQFP package.

Figure 9-1. SM2480 - 128 pin configuration

Boot Mode MODE[2:0] (1)

1. It is recommended that the MODE[2:0] pins are pulled to the desired state via pull-up and/or pull-down resistors rather than tied directly to VDDIO

or VSSIO.

Description

SPI Master "000" Read and process valid bootsector

from SPI Master SSb0

CI SPI Slave "001" Wait on Command Interface via SPI

Slave

CI UART "010" Wait on Command Interface via

UART

Parallel Memory "011" Read and process valid bootsector

from Parallel Memory

Reserved "1xx" Reserved

EXTMEM_A09 / PWM0A

EXTMEM_A08 / PWM0B

VDDIO07

VSSIO07

EXTMEM_A07 / PWM1A

EXTMEM_A06 / PWM1B

COREIO04 / FAULT05

COREIO12 / XING0

CORE I O 13 / XIN G1

CORE I O 14 / XIN G 2

COREIO10 / RXRANGE

VDDIO06

VSSIO06

TEST_EN

SCAN_EN

VSSCORE1

VDDCORE1

JTRSTb

JTCK

JTDI

JTDO

JTMS

COREIO07 / MODE2

VSSIO05

VDDIO05

EXTMEM_OEb

EXTMEM_D05

EXTMEM_D04

EXTMEM_D00

EXTMEM_CSb

EXTMEM_A04

EXTMEM_A03

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

O O LDO LDO O O IO IO IO IO IO LDO LDO I I P P I I I O I IO P P O IO IO IO O O O

EXTMEM_A05 97 O

North

O64 EXTMEM_A02

EXTMEM_WEb 98 O O63 EXTMEM_A01

EXTMEM_D03 99 IO O62 EXTMEM_A00

EXTMEM_D02 100 IO IO 61 EXTMEM_A18 / PWM5B / COREIO23

EXTMEM_D01 101 IO I O 60 EXTM E M _ A1 7 / PWM5A / COREIO22

VSSIO08 102 LDO P 59 VSSIO04

VDDIO08 103 LDO P 58 VDDIO04

AVDD3V_RX 104 P IO 57 EXTMEM_A16 / PWM4B / COREIO21

RX_COM 105 A IO 56 EXTME M _ A1 5 / PWM4A / COREIO2 0

AVSS_RX 106 P IO 55 COREIO 06 / MODE1

RXOPA_OUT 107 A IO 54 COREIO05 / MODE0

RXOPA_INN 108 A IO 53 UART_TDO / COREIO29

AVDD3V_TX 109 P IO 52 UART_RDI / COREIO28

AVSS_TX 110 P IO 51 UART_HSI / COREIO31

LDO_PD 111 A IO 50 UART_HSO / COREIO30

TXOPA_OUT 112 A P 49 VSSCORE2

TXOPA_INN 113 A P 48 VDDCORE2

DAC_COM 114 A I 47 RESETb

DAC_OUT 115 A IO 46 SPIS_OUT / FAULT09 / COREIO27

AVDD3V_PLL 116 P IO 45 SPIS_SCK / FAULT08 / COREIO26

XTAL_IN 117 A IO 44 SPIS_IN / FAULT07 / COREIO25

XTAL_OUT 118 A IO 43 SPIS_SSb / FAULT06 / COREIO24

AVSS_PLL 119 A IO 42 COREIO15 / HOSTREQ

AN_VSS 120 P IO 41 COREIO03 / FAULT04

AOUT_VDD 121 P IO 40 EXTMEM_A14 / PWM3B / COREIO19

AOUT_REF 122 A IO 39 EXTM EM_A1 3 / PWM3A / COREIO1 8

AOUT 123 A P 38 VSSIO02

AIN_VDD 124 P P 37 VDDIO02

AIN_REF 125 A IO 36 EXTMEM_A12 / PWM2B / COREIO17

AIN00 126 A IO 35 EXTME M _ A1 1 / PW M 2 A / CORE IO16

AIN01 127 A O34 EXTMEM_A10

AIN02 128 A

South

IO 33 EXTMEM_D07

LDOLDOAAAAAAAAAAAAAPPIOIOIOIOIOIOOOO I OOPPIO

1234567891011121314151617181920212223242526272829303132

VDDIO00

VSSIO00

AIN03

AIN04

AIN05

AIN06

AIN07

AIN08

AIN09

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

VSSCORE0

VDDCORE0

COREIO0 8 / TXEN

COREIO09 / PHYLED

COREIO11 / TXRANGE

COREIO00 / FAULT 0

COREIO01 / FAULT0

COREIO02 / FAULT0

SPIM_SS2b

SPIM_SS1b

SPIM_SS0

SPIM_IN

SPIM_SCK

SPIM_OU

VSSIO01

VDDIO01

EXTMEM_D0

East

West

128 pin

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Table 9-1. Pin Assignments

Pin # Pin Name Pin Type PiDescriptionn

1VDDIO00 LDO VDDIO Suplpy (3.3V)

2VSSIO00 LDO VSSIO (0V)

3AIN03 AADC Input

4AIN04 AADC Input

5AIN05 AADC Input

6AIN06 AADC Input

7AIN07 AADC Input

8AIN08 AADC Input

9AIN09 AADC Input

10 AIN10 AADC Input

11 AIN11 AADC Input

12 AIN12 AADC Input

13 AIN13 AADC Input

14 AIN14 AADC Input

15 AIN15 AADC Input

16 VSSCORE0 PVSSCORE (0V)

17 VDDCORE0 PVDDCORE Supply (1.8V)

18 COREIO08 / TXEN IO Firmware defin e d fun ctionality

19 COREIO09 / PHYLED IO Firmware defin e d fun ctionality

20 COREIO11 / TXRANGE IO Firmware defin e d fun ctionality

21 COREIO00 / FAULT01 IO User IO

22 COREIO01 / FAULT02 IO User IO

23 COREIO02 / FAULT03 IO User IO

24 SPIM_SS2b OSPI Master Interface (Boot)

25 SPIM_SS1b OSPI Master Interface (Boot)

26 SPIM_SS0b OSPI Master Interface (Boot)

27 SPIM_IN ISPI Master Interface (Boot)

28 SPIM_SCK OSPI Master Interface (Boot)

29 SPIM_OUT OSPI Master Interface (Boot)

30 VSSIO01 PVSSIO (0V)

31 VDDIO01 PVDDIO (3.3V)

32 EXTMEM_D06 IO Dedicated external memory interface

pins

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33 EXTMEM_D07 IO Dedicated external memory interface

pins

34 EXTMEM_A10 ODedicated external memory interface

pins

35 EXTMEM_A1 1 / PWM 2A

/ COREIO16 IO PWM interface

36 EXTMEM_A12 / PWM2B /

COREIO17 IO PWM interface

37 VDDIO02 PVDDIO (3.3V)

38 VSSIO02 PVSSIO (0V)

39 EXTMEM_A1 3 / PWM 3A

/ COREIO18 IO PWM interface

40 EXTMEM_A14 / PWM3B /

COREIO19 IO PWM interface

41 COREIO03 / FAULT04 IO User IO

42 COREIO15 / HOSTREQ IO Firmware defined fun c tionality

43 SPIS_SSb / FAULT06 /

COREIO24 IO Host SPI Slave Interface

44 SPIS_IN / FAULT07 /

COREIO25 IO Host SPI Slave Interface

45 SPIS_SCK / FAULT08 /

COREIO26 IO Host SPI Slave Interface

46 SPIS_OUT / FAULT09 /

COREIO27 IO Host SPI Slave Interface

47 RESETb ISystem Reset Pin

48 VDDCORE2 PVDDCORE Supply (1.8V)

49 VSSCORE2 PVSSCORE (0V)

50 UART_HSO / COREIO30 IO Host UART Interface

51 UART_HSI / COREIO31 IO Host UART Interface

52 UART_RDI / COREIO28 IO Host UART Interface

53 UART_TDO / COREIO29 IO Host UART Interface

54 COREIO05 / MODE0 IO Boot Mode Pin latched on reset

55 COREIO06 / MODE1 IO Boot Mode Pin latched on reset

56 EXTMEM_A1 5 / PWM 4A

/ COREIO20 IO PWM interface

57 EXTMEM_A16 / PWM4B /

COREIO21 IO PWM interface

58 VDDIO04 PVDDIO (3.3V)

59 VSSIO04 PVSSIO (0V)

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60 EXTMEM_A1 7 / PWM 5A

/ COREIO22 IO PWM interface

61 EXTMEM_A18 / PWM5B /

COREIO23 IO PWM interface

62 EXTMEM_A00 ODedicated external memory interface

pins

63 EXTMEM_A01 ODedicated external memory interface

pins

64 EXTMEM_A02 ODedicated external memory interface

pins

65 EXTMEM_A03 ODedicated external memory interface

pins

66 EXTMEM_A04 ODedicated external memory interface

pins

67 EXTMEM_CSb ODedicated external memory interface

pins

68 EXTMEM_D00 IO Dedicated external memory interface

pins

69 EXTMEM_D04 IO Dedicated external memory interface

pins

70 EXTMEM_D05 IO Dedicated external memory interface

pins

71 EXTMEM_Oeb ODedicated external memory interface

pins

72 VDDIO05 PVDDIO (3.3V)

73 VSSIO05 PVSSIO (0V)

74 COREIO07 / MODE2 IO Boot Mode Pin latched on reset

75 JTMS IJTAG Interface

76 JTDO OJTAG Interface

77 JTDI IJTAG Interface

78 JTCK IJTAG Interface

79 JTRSTb IJTAG Interface

80 VDDCORE1 PVDDCORE Supply (1.8V)

81 VSSCORE1 PVSSCORE (0V)

82 SCAN_EN IScan Enable

83 TEST_EN ITest Mode Enable

84 VSSIO06 LDO VSSIO (0V)

85 VDDIO06 LDO VDDIO (3.3V)

86 COREIO10 / RXRANGE IO Firmware def ined functionalit y

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87 COREIO14 / XING2 IO Firmware defin e d fun ctionality

88 COREIO13 / XING1 IO Firmware defin e d fun ctionality

89 COREIO12 / XING0 IO Firmware defin e d fun ctionality

90 COREIO04 / FAULT05 IO User IO

91 EXTMEM_A06 / PWM 1B OPWM interface

92 EXTMEM_A07 / PWM 1A OPWM interface

93 VSSIO07 LDO VSSIO (0V)

94 VDDIO07 LDO VDDIO (3.3V)

95 EXTMEM_A08 / PWM 0B OPWM interface

96 EXTMEM_A09 / PWM 0A OPWM interface

97 EXTMEM_A05 ODedicated external memory interface

pins

98 EXTMEM_Web ODedicated external memory interface

pins

99 EXTMEM_D03 IO Dedicated external memory interface

pins

100 EXTMEM_D02 IO Dedicated external memory interface

pins

101 EXTMEM_D01 IO Dedicated external memory interface

pins

102 VSSIO08 LDO VSSIO (0V)

103 VDDIO08 LDO VDDIO (3.3V)

104 AVDD3V_RX PPLC Interface

105 RX_COM APLC Analog

106 AVSS_RX PPLC Interface

107 RXOPA_OUT APLC Analog

108 RXOPA_INN APLC Analog

109 AVDD3V_TX PPLC Interface

110 AVSS_TX PPLC Interface

111 LDO_PD ALDO powerdown

112 TXOPA_OUT APLC Interface

113 TXOPA_INN APLC Interface

114 DAC_COM APLC Interface

115 DAC_OUT APLC Interface

116 AVDD3V_PLL PPLL VDD

117 XTAL_IN AOscillator Input

118 XTAL_OUT AOscillator Output

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10. Operating Conditions

Table 10-1. Recommended Operating Conditions

119 AVSS_PLL APLL VSS

120 AN_VSS PADC/DAC VSS

121 AOUT_VDD PDAC VDD

122 AOUT_REF ADAC Reference

123 AOUT ADAC Output

124 AIN_VDD PADC VDD

125 AIN_REF AADC Reference

126 AIN00 AADC Input

127 AIN01 AADC Input

128 AIN02 AADC Input

Symbol Parameter Min Typ Max Units

VDDIO VDDIO Supply Voltage 33.3 3.6 V

VDDCORE VDDCORE Supply Voltage 1.62 1.8 1.98 V

AVDD_RX 33.3 3.6 V

AVDD_TX 33.3 3.6 V

AVDD_PLL 33.3 3.6 V

AVDD_AOUT 03.3 3.6 V

AVDD_AIN 03.3 3.6 V

TOPT Ambient Operating Temperature -40 105 °C

TJJunction Temperature 025 125 ºC

VIL Input Low Voltage -0.3 0.8 V

VIN Input High Voltage 25.5 V

VTThreshold point 1.32 1.38 1.45 V

VT+Schmitt Trigger Low to High Thresh-

old point 1.48 1.55 1.71 V

VT-Schmitt Trigger High to Low Thresh-

old point 1.13 1.21 1.27 V

Adesto Technologies Confidential: For Release Only Under Non-Disclosure Agreement (NDA)

DS-SM2480-119A–PWRLN–6/2016

11. Power Usage

Table 11-1. Power Us age Specifications

VTPU Threshold Point with Pull-up Resis-

tor 1.29 1.35 1.41 V

VTPD Threshold Point with Pull-down

Resistor 1.33 1.41 1.48 V

VTPU+ Schmitt Trigger Low to High Thresh-

old Point with Pull-up 1.44 1.51 1.56 V

VTPU- Schmitt Trigger High to Low Thresh-

old Point with Pull- up 1.11 1.18 1.23 V

VTPD+ Schmitt Trigger Low to High Thresh-

old Point with Pull-down 1.51 1.58 1.64 V

VTPD-

Schmitt Trigger High to Low Thresh-

old Point with Pull-down 1.15 1.23 1.31 V

Input Leakage Current @ Vl = 3.3V

or 0V ±1 µA

IOZ

Tri-state Output Leakage Current @

Vo = 3.3V or 0V ±1 µA

RPU Pull-up resistor 36 51 75 k

RPD Pull-down resistor 33 55 102 k

VOL 0.4 V

VOH 2.4 V

IOL

Low Level Out-

put Current @

VOL(MAX)

12mA 13.7 22.5 31.6 mA

16mA 17.1 28.1 39.6 mA

IOH

High level output

current@

VOH(MAX)

12mA 19.7 38 61.7 mA

16mA 24.1 46.4 75.4 mA

Mode Device Power @1.8V (mW) Note

Reset 16 Reset pin is asserted, device is to be

bootstrapped, no comms.

Offline 22 Bootstrapped, but disabled, fast recov-

ery, no comms.

Symbol Parameter Min Typ Max Units

Adesto Technologies Confidential: For Release Only Under Non-Disclosure Agreement (NDA)

DS-SM2480-119A–PWRLN–6/2016

* Close estimate. The actual numbers may vary depending on the tracking/control algorithm(s) running

12. Ordering Information

12.1 Ordering Code Detail

Listen  55* Synchroniser preamble search/detect;

PWM is active

Receive  85* Preamble is detected, header and pay-

load being processed

Transmit  70* Packet being transmitted.

Mode Device Power @1.8V (mW) Note

SM2 4 8 M Z–0

Designator

Product Family

2480= N-PLC SCADA Controller

Package Option

MZ = 128-lead 14 x 14 x 1.4 LQFP

Device Grade

E = Green, Matte Sn or Sn alloy, extended

temperature range (-40°C to +105°C)

Shipping Carrier Option

Y = Tray

Operating Voltage

Q = 3.0-3.6V

EYQ–

Device Revision

Ordering Code (1) Package Lead

Finish Operating Voltage

(VDDCore) Operating Voltage

(VDDIO) Data

Rate Operation Range

SM2480-MZEQ-T 128QFP

SnAgCu 1.62V to 1.98V

(1.8V nominal)

3.0V to 3.6V

(3.3 nominal)

Up to

500kbps

Extended

Industrial

(-40°C to +105°C)

SM2480-MZEQ-Y 128QFP

1. The shipping carrier option code is not marked on the device.

Package Type

128QFP 128-lead, 14 x 14 x 0.1.4mm Body, 0.5 mm Pad Pitch, Very Thin Fine Pitch Quad Flat Package (QFP)

Adesto Technologies Confidential: For Release Only Under Non-Disclosure Agreement (NDA)

DS-SM2480-119A–PWRLN–6/2016

Compliance: SM2480 is designed to be compliant with FCC, Industry Canada, Japan MPT, and CENELEC specification for low

voltage signaling (EN50065). SM2480 is designed to be compliant with European Directive 2002/95EC on Restriction of

Hazardous Substances (RoHS) in electrical and electronic equipment.

13. Packaging Information

Figure 13-1. 128QFP - 128 lead QFP

14. Contact Information

For more information regarding the SM2480 including application notes, product samples, demonstration modules,

pricing and ordering please contact:

Adesto Technologies

http://www.adestotech.com

SM2480 Product Technical Support provided by:

Semitech Semiconductor Pty. Ltd.

http://www.semitechsemi.com

Adesto Technologies Confidential: For Release Only Under Non-Disclosure Agreement (NDA)

DS-SM2480-119A–PWRLN–6/2016

15. Revision History

Revision Level – Release Date History

A – June 2016 Initial release.

Corporate Office

California | USA

Adesto Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: (+1) 408.400.0578

Email: contact@adestotech.com

Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms

and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications

detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the

Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.

Adesto® and the Adesto logo are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective owners.