3 V/5 V, 2 MSPS, 8-Bit, 1-/4-/8-Channel
Sampling ADCs
AD7822/AD7825/AD7829
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
8-bit half-flash ADC with 420 ns conversion time
One, four, and eight single-ended analog input channels
Available with input offset adjust
On-chip track-and-hold
SNR performance given for input frequencies up to 10 MHz
On-chip reference (2.5 V)
Automatic power-down at the end of conversion
Wide operating supply range
3 V ± 10% and 5 V ± 10%
Input ranges
0 V to 2 V p-p, VDD = 3 V ± 10%
0 V to 2.5 V p-p, VDD = 5 V ± 10%
Flexible parallel interface with EOC pulse to allow
standalone operation
APPLICATIONS
Data acquisition systems, DSP front ends
Disk drives
Mobile communication systems, subsampling
applications
GENERAL DESCRIPTION
The AD7822/AD7825/AD7829 are high speed, 1-, 4-, and
8-channel, microprocessor-compatible, 8-bit analog-to-digital
converters with a maximum throughput of 2 MSPS. The AD7822/
AD7825/AD7829 contain an on-chip reference of 2.5 V
(2% tolerance); a track-and-hold amplifier; a 420 ns, 8-bit half-
flash ADC; and a high speed parallel interface. The converters
can operate from a single 3 V ± 10% and 5 V ± 10% supply.
The AD7822/AD7825/AD7829 combine the convert start and
power-down functions at one pin, that is, the CONVST pin.
This allows a unique automatic power-down at the end of a
conversion to be implemented. The logic level on the CONVST
pin is sampled after the end of a conversion when an EOC (end
of conversion) signal goes high. If it is logic low at that point,
the ADC is powered down. The AD7822 and AD7825 also have
a separate power-down pin (see the Operating Modes section).
The parallel interface is designed to allow easy interfacing to
microprocessors and DSPs. Using only address decoding logic,
the parts are easily mapped into the microprocessor address
space. The EOC pulse allows the ADCs to be used in a stand-
alone manner (see the Parallel Interface section.)
FUNCTIONAL BLOCK DIAGRAM
CONVST
PARALLEL
PORT
VREF IN/OUT
EOC
RD
CS
AGND
VMID
A01A11A22
VIN1
VIN24
VIN34
VIN44
VIN55
VIN65
VIN75
VIN85
COMP
PD3
2.5V
REF
V
DD
CONTROL
LOGIC
DGND
INPUT
MUX T/H
BUF
DB0
DB7
1A0, A1 AD7825/AD7829
2A2 AD7829
3PD AD7822/AD7825
4VIN2 TO VIN4 AD7825/AD7829
5VIN5 TO VIN8 AD7829
8-BIT
HALF
FLASH
ADC
01321-001
Figure 1.
The AD7822 and AD7825 are available in 20-lead and 24-lead,
0.3" wide, plastic dual in-line packages (PDIP); 20-lead and
24-lead standard small outline packages (SOIC); and 20-lead
and 24-lead thin shrink small outline packages (TSSOP). The
AD7829 is available in a 28-lead, 0.6" wide PDIP; a 28-lead
SOIC; and a 28-lead TSSOP.
PRODUCT HIGHLIGHTS
1. Fast Conversion Time. The AD7822/AD7825/AD7829
have a conversion time of 420 ns. Faster conversion times
maximize the DSP processing time in a real-time system.
2. Analog Input Span Adjustment. The VMID pin allows the
user to offset the input span. This feature can reduce the
requirements of single-supply op amps and take into
account any system offsets.
3. FPBW (Full Power Bandwidth) of Track-and-Hold.
The track-and-hold amplifier has an excellent high
frequency performance. The AD7822/AD7825/AD7829
are capable of converting full-scale input signals up to a
frequency of 10 MHz. This makes the parts ideally suited
to subsampling applications.
4. Channel Selection. Channel selection is made without the
necessity of writing to the part.
AD7822/AD7825/AD7829
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Ter mi no log y ...................................................................................... 8
Circuit Information........................................................................ 10
Circuit Description..................................................................... 10
Typical Connection Diagram ................................................... 10
ADC Transfer Function............................................................. 11
Analog Input ............................................................................... 11
Power-Up Times......................................................................... 14
Power vs. Throughput................................................................ 15
Operating Modes........................................................................ 15
Parallel Interface ......................................................................... 17
Microprocessor Interfacing........................................................... 18
AD7822/AD7825/AD7829 to 8051 ......................................... 18
AD7822/AD7825/AD7829 to PIC16C6x/PIC16C7x................ 18
AD7822/AD7825/AD7829 to ADSP-21xx ............................. 18
Interfacing Multiplexer Address Inputs .................................. 18
AD7822 Standalone Operation ................................................ 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 25
REVISION HISTORY
8/06—Rev. B to Rev. C
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Typical Connection Diagram Section ..................... 10
Updated Outline Dimensions....................................................... 20
Changes to Ordering Guide .......................................................... 25
10/01—Rev. A to Rev. B
Changes to Power Requirements.................................................... 3
Changes to Pin Function Description ........................................... 5
Changes to Circuit Description ...................................................... 7
Changes to Typical Connection Diagram Section........................7
Changes to Analog Input Section....................................................8
Changes to Analog Input Selection Section...................................9
Changes to Power-Up Times Section .......................................... 10
Changes to Power vs. Throughput Section................................. 11
Added AD7822 Stand-Alone Operation section ....................... 15
12/99—Rev. 0 to Rev. A
AD7822/AD7825/AD7829
Rev. C | Page 3 of 28
SPECIFICATIONS
VDD = 3 V ± 10%, VDD = 5 V ± 10%, GND = 0 V, VREF IN/OUT = 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Version B Unit Test Condition/Comment
DYNAMIC PERFORMANCE fIN = 30 kHz, fSAMPLE = 2 MHz
Signal to (Noise + Distortion) Ratio148 dB min
Total Harmonic Distortion1−55 dB max
Peak Harmonic or Spurious Noise1−55 dB max
Intermodulation Distortion1 fa = 27.3 kHz, fb = 28.3 kHz
Second-Order Terms −65 dB typ
Third-Order Terms −65 dB typ
Channel-to-Channel Isolation1−70 dB typ fIN = 20 kHz
DC ACCURACY
Resolution 8 Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed 8 Bits
Integral Nonlinearity (INL)1±0.75 LSB max
Differential Nonlinearity (DNL)1±0.75 LSB max
Gain Error1±2 LSB max
Gain Error Match1±0.1 LSB typ
Offset Error1 ±1 LSB max
Offset Error Match1±0.1 LSB typ
ANALOG INPUTS2 See Analog Input section
VDD = 5 V ± 10% Input voltage span = 2.5 V
VIN1 to VIN8 Input Voltage VDD V max
0 V min
VMID Input Voltage VDD − 1.25 V max Default VMID = 1.25 V
1.25 V min
VDD = 3 V ± 10% Input voltage span = 2 V
VIN1 to VIN8 Input Voltage VDD V max
0 V min
VMID Input Voltage VDD − 1 V max Default VMID = 1 V
1 V min
VIN Input Leakage Current ±1 µA max
VIN Input Capacitance 15 pF max
VMID Input Impedance 6 kΩ typ
REFERENCE INPUT
VREF IN/OUT Input Voltage Range 2.55 V max 2.5 V + 2%
2.45 V min 2.5 V − 2%
Input Current 1 A typ
100 A max
ON-CHIP REFERENCE Nominal 2.5 V
Reference Error ±50 mV max
Temperature Coefficient 50 ppm/°C typ
LOGIC INPUTS
Input High Voltage, VINH 2.4 V min VDD = 5 V ± 10%
Input Low Voltage, VINL 0.8 V max VDD = 5 V ± 10%
Input High Voltage, VINH 2 V min VDD = 3 V ± 10%
Input Low Voltage, VINL 0.4 V max VDD = 3 V ± 10%
Input Current, IIN ±1 A max 10 nA typical, VIN = 0 V to VDD
Input Capacitance, CIN 10 pF max
AD7822/AD7825/AD7829
Rev. C | Page 4 of 28
Parameter Version B Unit Test Condition/Comment
LOGIC OUTPUTS
Output High Voltage, VOH ISOURCE = 200 A
4 V min VDD = 5 V ± 10%
2.4 V min VDD = 3 V ± 10%
Output Low Voltage, VOL ISINK = 200 A
0.4 V max VDD = 5 V ± 10%
0.2 V max VDD = 3 V ± 10%
High Impedance Leakage Current ±1 A max
High Impedance Capacitance 10 pF max
CONVERSION RATE
Track-and-Hold Acquisition Time 200 ns max See Circuit Description section
Conversion Time 420 ns max
POWER SUPPLY REJECTION
VDD ± 10% ±1 LSB max
POWER REQUIREMENTS
VDD 4.5 V min 5 V ± 10%; for specified performance
5.5 V max
VDD 2.7 V min 3 V ± 10%; for specified performance
3.3 V max
IDD
Normal Operation 12 mA max 8 mA typical
Power-Down 5 A max Logic inputs = 0 V or VDD
0.2 A typ
Power Dissipation VDD = 3 V
Normal Operation 36 mW max 24 mW typical
Power-Down
200 kSPS 9.58 mW typ
500 kSPS 23.94 mW typ
1 See the Terminology section of this data sheet.
2 Refer to the Analog Input section for an explanation of the analog input(s).
AD7822/AD7825/AD7829
Rev. C | Page 5 of 28
TIMING CHARACTERISTICS
VREF IN/OUT = 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter1,
25 V ± 10% 3 V ± 10% Unit Conditions/Comments
t1 420 420 ns max Conversion time
t2 20 20 ns min Minimum CONVST pulse width
t3 30 30 ns min Minimum time between the rising edge of RD and the next falling edge of convert star
t4 110 110 ns max EOC pulse width
70 70 ns min
t5 10 10 ns max RD rising edge to EOC pulse high
t6 0 0 ns min CS to RD setup time
t7 0 0 ns min CS to RD hold time
t8 30 30 ns min Minimum RD pulse width
t93 10 20 ns max Data access time after RD low
t1045 5 ns min Bus relinquish time after RD high
20 20 ns max
t11 10 10 ns min Address setup time before falling edge of RD
t12 15 15 ns min Address hold time after falling edge of RD
t13 200 200 ns min Minimum time between new channel selection and convert start
tPOWER UP 25 25 s typ Power-up time from rising edge of CONVST using on-chip reference
tPOWER UP 1 1 s max Power-up time from rising edge of CONVST using external 2.5 V reference
1 Sample tested to ensure compliance.
2 See Figure 24, Figure 25, and Figure 26.
3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V ± 10%, and time required for an output
to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.
4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.
TIMING DIAGRAM
200µA I
OL
200µA I
OH
2.1V
TO OUTPUT
PIN C
L
50pF
01321-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
AD7822/AD7825/AD7829
Rev. C | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to AGND −0.3 V to +7 V
VDD to DGND −0.3 V to +7 V
Analog Input Voltage to AGND
VIN1 to VIN8 −0.3 V to VDD + 0.3 V
Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V
VMID Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
PDIP Package, Power Dissipation 450 mW
θJA Thermal Impedance 105°C/W
Lead Temperature, (Soldering, 10 sec) 260°C
SOIC Package, Power Dissipation 450 mW
θJA Thermal Impedance 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
TSSOP Package, Power Dissipation 450 mW
θJA Thermal Impedance 128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
ESD 1 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7822/AD7825/AD7829
Rev. C | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DB2 1
DB1 2
DB0 3
CONVST 4
DB320
DB419
DB518
DB6
17
CS 5
RD 6
DGND 7
DB7
16
AGND15
VDD
14
EOC 8VREF IN/OUT
13
PD 9VMID
12
NC 10 VIN1
11
NC = NO CONNECT
AD7822
TOP VI EW
(Not to Scale)
01321-003
DB2
1
DB1
2
DB0
3
CONVST
4
DB3
24
DB4
23
DB5
22
DB6
21
CS
5
DB7
20
RD
6
AGND
19
DGND
7
V
DD
18
EOC
8
V
REF IN/OUT
17
A1
9
V
MID
16
A0
10
V
IN1
15
PD
11
V
IN2
14
V
IN4 12
V
IN3
13
AD7825
TOP V IEW
(No t t o Scale)
0
1321-004
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB1
DB0
CONVST
DGND
RD
CS
DB2
DB4
DB5
DB6
V
DD
AGND
DB7
EOC
A2
A1
V
IN6
V
IN8
A0
V
REF IN/OUT
V
MID
V
IN1
V
IN5
V
IN7
V
IN4
V
IN3
V
IN2
DB3
AD7829
TOP VI EW
(No t t o S cale)
01321-005
Figure 3. Pin Configuration Figure 4. Pin Configuration Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Mnemonic Description
VIN1 to VIN8 Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight analog input
channels, respectively. The inputs have an input span of 2.5 V and 2 V depending on the supply voltage (VDD). This span can
be centered anywhere in the range AGND to VDD using the VMID pin. The default input range (VMID unconnected) is AGND to
2 V (VDD = 3 V ± 10%) or AGND to 2.5 V (VDD = 5 V ± 10%). See the Analog Input section of the data sheet for more information.
VDD Positive Supply Voltage, 3 V ± 10% and 5 V ± 10%.
AGND Analog Ground. Ground reference for track-and-hold, comparators, reference circuit, and multiplexer.
DGND Digital Ground. Ground reference for digital circuitry.
CONVST Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signal. The
falling edge of this signal places the track-and-hold in hold mode. The track-and-hold goes into track mode again 120 ns after
the start of a conversion. The state of the CONVST signal is checked at the end of a conversion. If it is logic low, the AD7822/
AD7825/AD7829 powers down (see the Operating Modes section of the data sheet).
EOC Logic Output. The end-of-conversion signal indicates when a conversion has finished. The signal can be used to interrupt
a microcontroller when a conversion has finished or latch data into a gate array (see the Parallel Interface section).
CS Logic Input Signal. The chip select signal is used to enable the parallel port of the AD7822/AD7825/AD7829. This is necessary
if the ADC is sharing a common data bus with another device.
PD Logic Input. The power-down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low places the AD7822 and
AD7825 in power-down mode. The ADCs power up when PD is brought logic high again.
RD Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and drive data onto
the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic low to enable the data bus.
A0 to A2 Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the RD signal
goes low.
DB0 to DB7 Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when both RD and CS
go active low.
VREF IN/OUT Analog Input and Output. An external reference can be connected to the AD7822/AD7825/AD7829 at this pin. The on-chip
reference is also available at this pin. When using the internal reference, this pin can be left unconnected or, in some cases, it
can be decoupled to AGND with a 0.1 μF capacitor.
VMID The VMID pin, if connected, is used to center the analog input span anywhere in the range of AGND to VDD (see the Analog
Input section).
AD7822/AD7825/AD7829
Rev. C | Page 8 of 28
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
The measured ratio of signal-to-(noise + distortion) at the
output of the analog-to-digital converter. The signal is the rms
amplitude of the fundamental. Noise is the rms sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent upon the number of
quantization levels in the digitization process: the more levels,
the smaller the quantization noise. The theoretical signal-to-(noise
+ distortion) ratio for an ideal N-bit converter with a sine wave
input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for an 8-bit converter, this is 50 dB.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7822/AD7825/AD7829, it is defined as
1
6532 V
VVVVV
THD 222
4
22
log20(dB) ++++
=
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this specification
is determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, … . Intermodulation terms are those for which
neither m nor n is equal to zero. For example, the second-order
terms include (fa + fb) and (fa − fb), and the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
The AD7822/AD7825/AD7829 are tested using the CCIF
standard, where two input frequencies near the top end of the
input bandwidth are used. In this case, the second- and third-
order terms are of different significance. The second-order terms
are usually distanced in frequency from the original sine waves,
and the third-order terms are usually at a frequency close to the
input frequencies. As a result, the second- and third-order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in decibels (dB).
Channel-to-Channel Isolation
A measure of the level of crosstalk between channels. It is
measured by applying a full-scale 20 kHz sine wave signal to
one input channel and determining how much that signal is
attenuated in each of the other channels. The figure given is the
worst case across all four or eight channels of the AD7825 and
AD7829, respectively.
Relative Accuracy or Endpoint Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
Differential Nonlinearity
The difference between the measured and the ideal one LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the 128th code transition (01111111) to
(10000000) from the ideal, that is, VMID.
Offset Error Match
The difference in offset error between any two channels.
Zero-Scale Error
The deviation of the first code transition (00000000) to
(00000001) from the ideal; that is, VMID − 1.25 V + 1 LSB (VDD =
5 V ± 10%), or VMID − 1.0 V + 1 LSB (VDD = 3 V ± 10%).
Full-Scale Error
The deviation of the last code transition (11111110) to (11111111)
from the ideal; that is, VMID + 1.25 V − 1 LSB (VDD = 5 V ± 10%),
or VMID + 1.0 V − 1 LSB (VDD = 3 V ± 10%).
AD7822/AD7825/AD7829
Rev. C | Page 9 of 28
Gain Error
The deviation of the last code transition (1111 . . . 110) to
(1111 . . . 111) from the ideal, that is, VREF − 1 LSB, after the
offset error has been adjusted out.
Gain Error Match
The difference in gain error between any two channels.
Track-and-Hold Acquisition Time
The time required for the output of the track-and-hold amplifier to
reach its final value, within ±1/2 LSB, after the point at which the
track-and-hold returns to track mode. This happens approximately
120 ns after the falling edge of CONVST.
It also applies to situations where a change in the selected input
channel takes place or where there is a step input change on the
input voltage applied to the selected VIN input of the AD7822/
AD7825/AD7829. It means that the user must wait for the
duration of the track-and-hold acquisition time after a channel
change/step input change to VIN before starting another
conversion, to ensure that the part operates to specification.
PSR (Power Supply Rejection)
Variations in power supply affect the full-scale transition but
not the converter linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
AD7822/AD7825/AD7829
Rev. C | Page 10 of 28
CIRCUIT INFORMATION
CIRCUIT DESCRIPTION
The AD7822/AD7825/AD7829 consist of a track-and-hold
amplifier followed by a half-flash analog-to-digital converter.
These devices use a half-flash conversion technique where one
4-bit flash ADC is used to achieve an 8-bit result. The 4-bit flash
ADC contains a sampling capacitor followed by 15 comparators
that compare the unknown input to a reference ladder to
achieve a 4-bit result. This first flash (that is, coarse conversion)
provides the four MSBs. For a full 8-bit reading to be realized,
a second flash (that is, fine conversion) must be performed to
provide the four LSBs. The 8-bit word is then placed on the data
output bus.
Figure 6 and Figure 7 show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes
into hold mode and holds the analog input for 120 ns. This is
the acquisition phase, as shown in Figure 6, when Switch 2 is in
Position A. At the point when the track-and-hold returns to its
track mode, this signal is sampled by the sampling capacitor,
as Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically, the
first flash is complete after 100 ns, that is, at 220 ns; and the end
of the second flash and, hence, the 8-bit conversion result is
available at 330 ns (minimum). The maximum conversion time
is 420 ns. As shown in Figure 8, the track-and-hold returns to
track mode after 120 ns and starts the next acquisition before
the end of the current conversion. Figure 10 shows the ADC
transfer function.
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
V
IN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DECODE
LOGIC
14
15
13
1
OUTPUT
REGISTER
OUTPUT
DRIVERS
REFERENCE
01321-006
Figure 6. ADC Acquisition Phase
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
V
IN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DECODE
LOGIC
14
15
13
1
OUTPUT
REGISTER
OUTPUT
DRIVERS
REFERENCE
01321-007
Figure 7. ADC Conversion Phase
HOLD HOLD
120ns
CONVST
EOC
CS
RD
DB0 TO DB7
t
2
TRACK
TRACK
VALID
DATA
t
1
t
3
01321-008
Figure 8. Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAM
Figure 9 shows a typical connection diagram for the AD7822/
AD7825/AD7829. The AGND and DGND are connected
together at the device for good noise suppression. The parallel
interface is implemented using an 8-bit data bus. The end of
conversion signal (EOC) idles high, the falling edge of CONVST
initiates a conversion, and at the end of conversion the falling
edge of EOC is used to initiate an interrupt service routine
(ISR) on a microprocessor (see the Parallel Interface section for
more details.) VREF and VMID are connected to a voltage source
such as the AD780, and VDD is connected to a voltage source
that can vary from 4.5 V to 5.5 V (see Table 5 in the Analog Input
section). When VDD is first connected, the AD7822/AD7825/
AD7829 power up in a low current mode, that is, power-down
mode, with the default logic level on the EOC pin on the
AD7822 and AD7825 equal to a low. Ensure the CONVST line is
not floating when VDD is applied, because this can put the
AD7822/AD7825/AD7829 into an unknown state.
AD7822/AD7825/AD7829
Rev. C | Page 11 of 28
A suggestion is to tie CONVST to VDD or DGND through a pull-up
or pull-down resistor. A rising edge on the CONVST pin causes
the AD7829 to fully power up, while a rising edge on the PD pin
causes the AD7822 and AD7825 to fully power up. For applica-
tions where power consumption is of concern, the automatic
power-down at the end of a conversion should be used to improve
power performance (see the Power vs. Throughput section).
SUPPLY
4
.5V TO 5.5
V
10µF 0.1µF
V
DD
V
REF
V
MID
V
IN1
1.25V TO
3.75V INPUT
V
IN24
V
IN4
(V
IN85
)
AGND
DB0 TO DB7
EOC
RD
CS
CONVST
A0
1
A1
1
A2
2
PD
3
PARALLEL
INTERFACE
µC/µP
AD7822/
AD7825/
AD7829
DGND
2.5V
AD780
01321-009
1
A0, A1 AD7825/AD7829
2
A2 AD7829
3
PD AD7822/AD7825
4
V
IN2
TO V
IN4
AD7825/AD7829
5
V
IN5
TO V
IN8
AD7829
Figure 9. Typical Connection Diagram
ADC TRANSFER FUNCTION
The output coding of the AD7822/AD7825/AD7829 is straight
binary. The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size =
VREF/256 (VDD = 5 V) or the LSB size = (0.8 VREF)/256 (VDD =
3 V). The ideal transfer characteristic for the AD7822/AD7825/
AD7829 is shown in Figure 10.
11111111
111...110
111...000
10000000
000...111
000...010
00000000
(VDD = 5V)
1LSB = VREF/ 256
(VDD = 3V)
1LSB = 0.8VREF/256
000...001
ADC CODE
1LSB VMID
(VDD = 5V) VMID – 1.25V
(VDD = 3V) VMID – 1V
VMID + 1.25V – 1LSB
VMID + 1V – 1LSB
ANALOG INPUT VOLTAGE
0
1321-010
Figure 10. Transfer Characteristic
ANALOG INPUT
The AD7822 has a single input channel, and the AD7825 and
AD7829 have four and eight input channels, respectively. Each
input channel has an input span of 2.5 V or 2.0 V, depending on
the supply voltage (VDD). This input span is automatically set up
by an on-chip VDD detector circuit. A 5 V operation of the ADCs
is detected when VDD exceeds 4.1 V, and a 3 V operation is
detected when VDD falls below 3.8 V. This circuit also possesses
a degree of glitch rejection; for example, a glitch from 5.5 V to
2.7 V up to 60 ns wide does not trip the VDD detector.
The VMID pin is used to center this input span anywhere in the
range of AGND to VDD. If no input voltage is applied to VMID,
the default input range is AGND to 2.0 V (VDD = 3 V ± 10%),
that is, centered about 1.0 V; or AGND to 2.5 V (VDD = 5 V ±
10%), that is, centered about 1.25 V. When using the default
input range, the VMID pin can be left unconnected, or in some
cases, it can be decoupled to AGND with a 0.1 μF capacitor.
If, however, an external VMID is applied, the analog input range
is from VMID − 1.0 V to VMID + 1.0 V (VDD = 3 V ± 10%), or
from VMID − 1.25 V to VMID + 1.25 V (VDD = 5 V ± 10%).
The range of values of VMID that can be applied depends on the
value of VDD. For VDD = 3 V ± 10%, the range of values that can
be applied to VMID is from 1.0 V to VDD − 1.0 V and from 1.25 V to
VDD − 1.25 V when VDD = 5 V ± 10%. Table 5 shows the relevant
ranges of VMID and the input span for various values of VDD.
Figure 11 illustrates the input signal range available with various
values of VMID.
Table 5.
VDD
VMID
Internal
VMID Ext
Max VIN Span
VMID Ext
Min VIN Span Unit
5.5 1.25 4.25 3.0 to 5.5 1.25 0 to 2.5 V
5.0 1.25 3.75 2.5 to 5.0 1.25 0 to 2.5 V
4.5 1.25 3.25 2.0 to 4.5 1.25 0 to 2.5 V
3.3 1.00 2.3 1.3 to 3.3 1.00 0 to 2.0 V
3.0 1.00 2.0 1.0 to 3.0 1.00 0 to 2.0 V
2.7 1.00 1.7 0.7 to 2.7 1.00 0 to 2.0 V
AD7822/AD7825/AD7829
Rev. C | Page 12 of 28
5V
4V
3V
2V
1V
V
DD
= 5V
INPUT SIGNAL RANGE
FOR VARIOUS V
MID
V
MID
= N/C (1.25V)
V
MID
= 2.5V
V
MID
= 3.75V
3V
2V
1V
V
DD
= 3V
INPUT SIGNAL RANGE
FOR VARIOUS V
MID
V
MID
= N/C (1V)
V
MID
= 1.5V
V
MID
= 2V
0
1321-011
Figure 11. Analog Input Span Variation with VMID
VMID can be used to remove offsets in a system by applying the
offset to the VMID pin as shown in Figure 12, or it can be used to
accommodate bipolar signals by applying VMID to a level-shifting
circuit before VIN, as shown in Figure 13. When VMID is being
driven by an external source, the source can be directly tied to
the level-shifting circuitry (see Figure 13). However, if the
internal VMID, that is, the default value, is being used as an
output, it must be buffered before applying it to the level-
shifting circuitry because the VMID pin has an impedance of
approximately 6 kΩ (see Figure 14).
V
IN
V
MID AD7822/
AD7825/
AD7829
V
MID
V
IN
V
MID
01321-012
Figure 12. Removing Offsets Using VMID
V
REF
V
MID
V
IN
R3
R4
R2
R1
V
V
0V
V
IN
0V
2.5V
AD7822/
AD7825/
AD7829
2.5V
01321-013
Figure 13. Accommodating Bipolar Signals Using External VMID
R2
V
REF
V
MID
V
IN
EXTERNAL
2.5V
R3
R4
R1
V
V
0
V
V
IN
0V
V
MID
AD7822/
AD7825/
AD7829
01321-014
Figure 14. Accommodating Bipolar Signals Using Internal VMID
NOTE: Although there is a VREF pin from which a voltage
reference of 2.5 V can be sourced, or to which an external
reference can be applied, this does not provide an option of
varying the value of the voltage reference. As stated in the
specifications for the AD7822/AD7825/AD7829, the input
voltage range at this pin is 2.5 V ± 2%.
Analog Input Structure
Figure 15 shows an equivalent circuit of the analog input
structure of the AD7822/AD7825/AD7829. The two diodes,
D1 and D2, provide ESD protection for the analog inputs. Care
must be taken to ensure that the analog input signal never
exceeds the supply rails by more than 200 mV. Doing so causes
these diodes to become forward biased and start conducting
current into the substrate. A maximum current of 20 mA can be
conducted by these diodes without causing irreversible damage
to the part. However, it is worth noting that a small amount of
current (1 mA) being conducted into the substrate, due to an
overvoltage on an unselected channel, can cause inaccurate
conversions on a selected channel.
AD7822/AD7825/AD7829
Rev. C | Page 13 of 28
Capacitor C2 in Figure 15 is typically about 4 pF and can be
primarily attributed to pin capacitance. The resistor, R1, is a
lumped component made up of the on resistance of several
components, including that of the multiplexer and the track-
and-hold. This resistor is typically about 310 Ω. Capacitor C1
is the track-and-hold capacitor and has a capacitance of 0.5 pF.
Switch 1 is the track-and-hold switch, and Switch 2 is that of the
sampling capacitor, as shown in Figure 6 and Figure 7.
V
IN
C2
4pF
D1
D2
R1
310Ω
SW1
C1
0.5pF A
B
SW2
V
DD
01321-015
Figure 15. Equivalent Analog Input Circuit
When in track phase, Switch 1 is closed and Switch 2 is in
Position A. When in hold mode, Switch 1 opens and Switch 2
remains in Position A. The track-and-hold remains in hold
mode for 120 ns (see the Circuit Description section), after
which it returns to track mode and the ADC enters its conversion
phase. At this point, Switch 1 opens and Switch 2 moves to
Position B. At the end of the conversion, Switch 2 moves back
to Position A.
Analog Input Selection
On power-up, the default VIN selection is VIN1. When returning
to normal operation from power-down, the VIN selected is the
same one that was selected prior to initiation of power-down.
Table 6 shows the multiplexer address corresponding to each
analog input from VIN1 to VIN4(8) for the AD7825 or AD7829.
Table 6.
A2 A1 A0 Analog Input Selected
0 0 0 VIN1
0 0 1 VIN2
0 1 0 VIN3
0 1 1 VIN4
1 0 0 VIN5
1 0 1 VIN6
1 1 0 VIN7
1 1 1 VIN8
Channel selection on the AD7825 and AD7829 is made without
the necessity of a write operation. The address of the next channel
to be converted is latched at the start of the current read operation,
that is, on the falling edge of RD while CS is low, as shown in
Figure 16. This allows for improved throughput rates in “channel
hopping” applications.
CONVST
DB0 TO DB7
A0 TO A2
EOC
CS
RD
t
2
t
1
t
3
t
13
VALID
DATA
ADDRESS CHANNEL y
TRACK CHx TRACK CHx
HOLD CHx TRACK CHy HOLD CHy
120ns
01321-016
Figure 16. Channel Hopping Timing
There is a minimum time delay between the falling edge of RD
and the next falling edge of the CONVST signal, t13. This is the
minimum acquisition time required of the track-and-hold to
maintain 8-bit performance. Figure 17 shows the typical perform-
ance of the AD7825 when channel hopping for various acquisition
times. These results are obtained using an external reference
and internal VMID while channel hopping between VIN1 and VIN4
with 0 V on Channel 4 and 0.5 V on Channel 1.
ACQUISITION TIME (ns)
8.0
5.0
10500 200
ENOB
100 50 40 30 20 15
7.5
7.0
6.5
6.0
5.5
8.5
01321-017
Figure 17. Effective Number of Bits vs. Acquisition Time for the AD7825
The on-chip track-and-hold can accommodate input frequencies
to 10 MHz, making the AD7822/AD7825/AD7829 ideal for
subsampling applications. When the AD7825 is converting a
10 MHz input signal at a sampling rate of 2 MSPS, the effective
number of bits typically remains above seven, corresponding to
a signal-to-noise ratio of 42 dBs, as shown in Figure 18.
AD7822/AD7825/AD7829
Rev. C | Page 14 of 28
INPUT FREQUENCY (MHz)
50
38
012.01
SNR (dB)
34568
48
46
44
42
40
f
SAMPLE
= 2MHz
01321-018
Figure 18. SNR vs. Input Frequency on the AD7825
POWER-UP TIMES
The AD7822/AD7825/AD7829 have a 1 μs power-up time
when using an external reference and a 25 μs power-up time
when using the on-chip reference. When VDD is first connected,
the AD7822/AD7825/AD7829 are in a low current mode of
operation. Ensure that the CONVST line is not floating when
VDD is applied. If there is a glitch on CONVST while VDD is
rising, the part attempts to power up before VDD has fully settled
and can enter an unknown state. To carry out a conversion, the
AD7822/AD7825/AD7829 must first be powered up. The
AD7829 is powered up by a rising edge on the CONVST pin,
and a conversion is initiated on the falling edge of CONVST.
Figure 19 shows how to power up the AD7829 when VDD is first
connected or after the AD7829 has been powered down using
the CONVST pin when using either the on-chip reference or an
external reference. When using an external reference, the falling
edge of CONVST may occur before the required power-up time
has elapsed; however, the conversion is not initiated on the
falling edge of CONVST but rather at the moment when the
part has completely powered up, that is, after 1 μs. If the falling
edge of CONVST occurs after the required power-up time has
elapsed, then it is upon this falling edge that a conversion is
initiated. When using the on-chip reference, it is necessary to
wait the required power-up time of approximately 25 μs before
initiating a conversion; that is, a falling edge on CONVST must
not occur before the required power-up time has elapsed, when
VDD is first connected or after the AD7829 has been powered
down using the CONVST pin, as shown in Figure 19.
VDD
t
POWER-UP
1µs
CONVST
VDD
CONVST
t
POWER-UP
25µs
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
EXTERNAL REFERENCE
ON-CHIP REFERENCE
01321-019
Figure 19. AD7829 Power-Up Time
Figure 20 shows how to power up the AD7822 or AD7825 when
VDD is first connected or after the ADCs have been powered down,
using the PD pin or the CONVST pin, with either the on-chip
reference or an external reference. When the supplies are first
connected or after the part has been powered down by the PD
pin, only a rising edge on the PD pin causes the part to power
up. When the part has been powered down using the CONVST
pin, a rising edge on either the PD pin or the CONVST pin powers
the part up again.
As with the AD7829, when using an external reference with the
AD7822 or AD7825, the falling edge of CONVST may occur
before the required power-up time has elapsed. If this is the
case, the conversion is not initiated on the falling edge of CONVST,
but rather at the moment when the part has powered up
completely, that is, after 1 μs. If the falling edge of CONVST
occurs after the required power-up time has elapsed, it is upon
this falling edge that a conversion is initiated. When using the
on-chip reference, it is necessary to wait the required power-up
time of approximately 25 μs before initiating a conversion; that
is, a falling edge on CONVST must not occur before the
required power-up time has elapsed, when supplies are first
connected to the AD7822 or AD7825, or when the ADCs have
been powered down using the PD pin or the CONVST pin, as
shown in Figure 20.
AD7822/AD7825/AD7829
Rev. C | Page 15 of 28
V
DD
PD
CONVST
t
POWER-UP
1µs
t
POWER-UP
1µs
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
EXTERNAL REFERENCE
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
V
DD
PD
CONVST
t
POWER-UP
t
POWER-UP
ON-CHIP REFERENCE
25µs 25µs
0
1321-020
Figure 20. AD7822/AD7825 Power-Up Time
POWER VS. THROUGHPUT
Superior power performance can be achieved by using the
automatic power-down (Mode 2) at the end of a conversion
(see the Operating Modes section).
Figure 21 shows how the automatic power-down is implemented
using the CONVST signal to achieve the optimum power
performance for the AD7822/AD7825/AD7829. The duration
of the CONVST pulse is set to be equal to or less than the power-up
time of the devices (see the Operating Modes section). As the
throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over time
drops accordingly.
t
POWER-UP
1µs 330ns
t
CONVERT
POWER-DOWN
tCYCLE
10µs @ 100kSPS
CONVST
0
1321-022
Figure 21. Automatic Power-Down
For example, if the AD7822 is operated in a continuous
sampling mode, with a throughput rate of 100 kSPS and using
an external reference, the power consumption is calculated as
follows. The power dissipation during normal operation is
36 mW, VDD = 3 V. If the power-up time is 1 μs and the conversion
time is 330 ns (@ +25°C), the AD7822 can be said to dissipate
36 mW (maximum) for 1.33 μs during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 μs and
the average power dissipated during each cycle is (1.33/10) ×
(36 mW) = 4.79 mW. This calculation uses the minimum
conversion time, thus giving the best-case power dissipation at
this throughput rate. However, the actual power dissipated
during each conversion cycle could increase, depending on the
actual conversion time (up to a maximum of 420 ns).
Figure 22 shows the power vs. throughput rate for automatic
full power-down.
THROUGHPUT (kSPS)
100
10
00050100
POWER (mW)
1
200 300 400
0.1
50 150 250 350 450
01321-023
Figure 22. AD7822/AD7825/AD7829 Power vs. Throughput
FREQUENCY (kHz)
0
–10
–80
(dB)
–40
–50
–60
–70
–20
–30
0
113
142
170
198
227
255
283
312
340
368
396
425
453
481
510
538
566
595
623
651
680
708
736
765
793
821
850
878
906
935
963
28
57
85
991
2048 POINT FFT
SAMPLING
2MSPS
f
IN
= 200kHz
01321-024
Figure 23. AD7822/AD7825/AD7829 SNR
OPERATING MODES
The AD7822/AD7825/AD7829 have two possible modes of
operation, depending on the state of the CONVST pulse
approximately 100 ns after the end of a conversion, that is, upon
the rising edge of the EOC pulse.
Mode 1 Operation (High Speed Sampling)
When the AD7822/AD7825/AD7829 are operated in Mode 1,
they are not powered down between conversions. This mode of
operation allows high throughput rates to be achieved.
Figure 24 shows how this optimum throughput rate is achieved
by bringing CONVST high before the end of a conversion, that
is, before the EOC pulses low. When operating in this mode, a
new conversion should not be initiated until 30 ns after the end
of a read operation. This allows the track-and-hold to acquire
the analog signal to 0.5 LSB accuracy.
AD7822/AD7825/AD7829
Rev. C | Page 16 of 28
Mode 2 Operation (Automatic Power-Down)
When the AD7822/AD7825/AD7829 are operated in Mode 2
(see Figure 25), they automatically power down at the end of
a conversion. The CONVST signal is brought low to initiate
a conversion and is left logic low until after the EOC goes high,
that is, approximately 100 ns after the end of the conversion.
The state of the CONVST signal is sampled at this point (that is,
530 ns maximum after CONVST falling edge), and the AD7822/
AD7825/AD7829 power down as long as CONVST is low.
The ADC is powered up again on the rising edge of the
CONVST signal. Superior power performance can be achieved
in this mode of operation by powering up the AD7822/AD7825/
AD7829 only to carry out a conversion. The parallel interface of
the AD7822/AD7825/AD7829 remains fully operational while
the ADCs are powered down. A read may occur while the part
is powered down, and, therefore, it does not necessarily need to
be placed within the EOC pulse, as shown in Figure 25.
t
2
t
1
t
3
VALID
DATA
CONVST
EOC
CS
RD
DB0 TO DB7
TRACK HOLD TRACK HOLD
120ns
01321-025
Figure 24. Mode 1 Operation
CONVST
EOC
CS
RD
DB0 TO DB7
t
POWER-UP
t
1
VALID
DATA
POWER
DOWN
HERE
01321-026
Figure 25. Mode 2 Operation
AD7822/AD7825/AD7829
Rev. C | Page 17 of 28
PARALLEL INTERFACE
The parallel interface of the AD7822/AD7825/AD7829 is eight
bits wide. Figure 26 shows a timing diagram illustrating the
operational sequence of the AD7822/AD7825/AD7829 parallel
interface. The multiplexer address is latched into the AD7822/
AD7825/AD7829 on the falling edge of the RD input. The on-
chip track-and-hold goes into hold mode on the falling edge of
CONVST, and a conversion is also initiated at this point. When
the conversion is complete, the end of conversion line (EOC)
pulses low to indicate that new data is available in the output
register of the AD7822/AD7825/AD7829. The EOC pulse stays
logic low for a maximum time of 110 ns.
However, the EOC pulse can be reset high by a rising edge
of RD. This EOC line can be used to drive an edge-triggered
interrupt of a microprocessor. CS and RD going low accesses
the 8-bit conversion result. It is possible to tie CS permanently
low and use only RD to access the data. In systems where the
part is interfaced to a gate array or ASIC, this EOC pulse can be
applied to the CS and RD inputs to latch data out of the AD7822/
AD7825/AD7829 and into the gate array or ASIC. This means
that the gate array or ASIC does not need any conversion status
recognition logic, and it also eliminates the logic required in the
gate array or ASIC to generate the read signal for the AD7822/
AD7825/AD7829.
CONVST
EOC
CS
RD
DB0 TO DB7
A0 TO A2
t
1
t
4
t
5
t
6
t
7
t
8
t
3
t
9
t
10
t
11
t
12
t
13
VALID
DATA
NEXT
CHANNEL
ADDRESS
t
2
01321-027
Figure 26. AD7822/AD7825/AD7829 Parallel Port Timing
AD7822/AD7825/AD7829
Rev. C | Page 18 of 28
MICROPROCESSOR INTERFACING
The parallel port on the AD7822/AD7825/AD7829 allows
the ADCs to be interfaced to a range of many different micro-
controllers. This section explains how to interface the AD7822/
AD7825/AD7829 with some of the more common microcontroller
parallel interface protocols.
AD7822/AD7825/AD7829 TO 8051
Figure 27 shows a parallel interface between the AD7822/AD7825/
AD7829 and the 8051 microcontroller. The EOCsignal on the
AD7822/AD7825/AD7829 provides an interrupt request to the
8051 when a conversion ends and data is ready. Port 0 of the 8051
can serve as an input or output port; or, as in this case when used
together with the address latch enable (ALE) of the 8051, can be
used as a bidirectional low order address and data bus. The ALE
output of the 8051 is used to latch the low byte of the address
during accesses to the device, while the high order address byte
is supplied from Port 2. Port 2 latches remain stable when the
AD7822/AD7825/ AD7829 are addressed because they do not
have to be turned around (set to 1) for data input, as is the case
for Port 0.
AD0 TO AD7
ALE
A8 TO A15
RD
INT
8051
1
LATCH DECODER
DB0 TO DB7
RD
EOC
CS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD7822/
AD7825/
AD7829
1
01321-028
Figure 27. Interfacing to the 8051
AD7822/AD7825/AD7829 TO PIC16C6x/PIC16C7x
Figure 28 shows a parallel interface between the AD7822/
AD7825/AD7829 and the PIC16C64/PIC16C65/PIC16C74.
The EOC signal on the AD7822/AD7825/AD7829 provides an
interrupt request to the microcontroller when a conversion
begins. Of the PIC16C6x/PIC16C7x range of microcontrollers,
only the PIC16C64/PIC16C65/PIC16C74 can provide the
option of a parallel slave port. Port D of the microcontroller
operates as an 8-bit wide parallel slave port when Control Bit
PSPMODE in the TRISE register is set. Setting PSPMODE
enables Port Pin RE0 to be the RD output and RE2 to be the CS
(chip select) output. For this functionality, the corresponding
data direction bits of the TRISE register must be configured as
outputs (reset to 0). See the PIC16C6x/PIC16C7x microcontroller
user manual.
PSP0 TO PSP7
RD
INT
PIC16C6x/7x
1
DB0 TO DB7
RD
EOC
CS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
CS
AD7822/
AD7825/
AD7829
1
01321-029
Figure 28. Interfacing to the PIC16C6x/ PIC16C7x
AD7822/AD7825/AD7829 TO ADSP-21xx
Figure 29 shows a parallel interface between the AD7822/
AD7825/AD7829 and the ADSP-21xx series of DSPs. As before,
the EOC signal on the AD7822/AD7825/AD7829 provides an
interrupt request to the DSP when a conversion ends.
D7 TO D0
RD
IRQ
ADSP-21xx
1
DB0 TO DB7
RD
EOC
CS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
DMS EN
ADDRESS
DECODE
LOGIC
A13 TO A0
AD7822/
AD7825/
AD7829
1
01321-030
Figure 29. Interfacing to the ADSP-21xx
INTERFACING MULTIPLEXER ADDRESS INPUTS
Figure 30 shows a simplified interfacing scheme between the
AD7825/AD7829 and any microprocessor or microcontroller,
which facilitates easy channel selection on the ADCs. The multi-
plexer address is latched on the falling edge of the RD signal,
as outlined in the Parallel Interface section, allowing the use of
the three LSBs of the address bus to select the channel address.
As shown in Figure 30, only Address Bit A3 to Address Bit A15
are address decoded, allowing A0 to A2 to be changed according to
desired channel selection without affecting chip selection.
AD7822/AD7825/AD7829
Rev. C | Page 19 of 28
AD7822 STANDALONE OPERATION
The AD7822, being the single channel device, does not have any
multiplexer addressing associated with it and can be controlled
with just one signal, that is, the CONVST signal. As shown in
Figure 31, the RD and CS pins are both tied to the EOC pin.
The resulting signal can be used as an interrupt request signal
(IRQ) on a DSP, as a WR signal to memory, or as a CLK to a
latch or ASIC. The timing for this interface, as shown in Figure 31,
demonstrates how, with the CONVST signal alone, a conversion
can be initiated, data is latched out, and the operating mode of
the AD7822 can be selected.
AD7825/
AD7829
A0
A1
A2
CS
RD
DB7 TO DB0
CS
RD
DB0 TO DB7
A15 TO A3
A2 TO A0
ADC I/O ADDRESS
MUX ADDRESS
A/D RESULT
MUX ADDRESS
(CHANNEL SELECTION A0 TO A2)
LATCHED
MICROPROCESSOR READ CYCLE
ADDRESS
DECODE
SYSTEM BUS
01321-031
A15 TO A3
Figure 30. AD7825/AD7829 Simplified Microinterfacing Scheme
CONVST
RD
CS
EOC
DB7 TO DB0
AD7822
DSP/
LATCH/ASIC
CONVST
EOC
RD
CS
DB0 TO DB7 A/D RESULT
t
1
t
4
01321-032
Figure 31. AD7822 Standalone Operation
AD7822/AD7825/AD7829
Rev. C | Page 20 of 28
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AD
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
20
110
11
0.100 (2.54)
BSC
1.060 (26.92)
1.030 (26.16)
0.980 (24.89)
PIN 1
0.210
(5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 32. 20-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-20)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
20 11
10
1
1.27
(0.0500)
BSC
060706-A
45°
Figure 33. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
AD7822/AD7825/AD7829
Rev. C | Page 21 of 28
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC
1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COPLANARIT
0.10
Figure 34. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AF
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
24
112
13
0.100 (2.54)
BSC
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
PIN 1
0.210
(5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 35. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
AD7822/AD7825/AD7829
Rev. C | Page 22 of 28
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
15.60 (0.6142)
15.20 (0.5984)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
24 13
12
1
1.27 (0.0500)
BSC
060706-A
Figure 36. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
24 13
121
6.40 BSC
4.50
4.40
4.30
PIN 1
7.90
7.80
7.70
0.15
0.05
0.30
0.19
0.65
BSC 1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 37. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
AD7822/AD7825/AD7829
Rev. C | Page 23 of 28
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-011-AB
0.100 (2.54)
BSC
1.565 (39.75)
1.380 (35.05)
PIN 1
0.580 (14.73)
0.485 (12.31)
0.022 (0.56)
0.014 (0.36)
0.200 (5.08)
0.115 (2.92)
0.070 (1.78)
0.030 (0.76)
0.250
(6.35)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.700 (17.78)
MAX
0.015 (0.38)
0.008 (0.20)
0.625 (15.88)
0.600 (15.24)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.125 (3.17)
28
114
15
Figure 38. 28-Lead Plastic Dual In-Line Package [PDIP]
Wide Body
(N-28-2)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AE
18.10 (0.7126)
17.70 (0.6969)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
28 15
14
1
1.27 (0.0500)
BSC
060706-A
Figure 39. 28-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
AD7822/AD7825/AD7829
Rev. C | Page 24 of 28
COMPLIANT TO JEDEC STANDARDS MO-153-AE
28 15
141
8°
0°
SEATING
PLANE
C
OPLANARIT
Y
0.10
1.20 MAX
6.40 BSC
0.65
BSC
PIN 1
0.30
0.19 0.20
0.09
4.50
4.40
4.30
0.75
0.60
0.45
9.80
9.70
9.60
0.15
0.05
Figure 40. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
AD7822/AD7825/AD7829
Rev. C | Page 25 of 28
ORDERING GUIDE
Model Temperature Range Package Description Package Option Linearity Error
AD7822BN −40°C to +85°C 20-Lead PDIP N-20 ±0.75 LSB
AD7822BNZ1−40°C to +85°C 20-Lead PDIP N-20 ±0.75 LSB
AD7822BR −40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB
AD7822BR-REEL −40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB
AD7822BR-REEL7 −40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB
AD7822BRZ1−40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB
AD7822BRZ-REEL1−40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB
AD7822BRZ-REEL71−40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB
AD7822BRU −40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB
AD7822BRU-REEL −40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB
AD7822BRU-REEL7 −40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB
AD7822BRUZ1−40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB
AD7822BRUZ-REEL1−40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB
AD7822BRUZ-REEL71−40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB
AD7825BN −40°C to +85°C 24-Lead PDIP N-24-1 ±0.75 LSB
AD7825BNZ1−40°C to +85°C 24-Lead PDIP N-24-1 ±0.75 LSB
AD7825BR −40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB
AD7825BR-REEL −40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB
AD7825BR-REEL7 −40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB
AD7825BRZ1−40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB
AD7825BRZ-REEL1−40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB
AD7825BRZ-REEL71−40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB
AD7825BRU −40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB
AD7825BRU-REEL −40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB
AD7825BRU-REEL7 −40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB
AD7825BRUZ1−40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB
AD7825BRUZ-REEL1−40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB
AD7825BRUZ-REEL71−40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB
AD7829BN −40°C to +85°C 28-Lead PDIP N-28-2 ±0.75 LSB
AD7829BNZ1−40°C to +85°C 28-Lead PDIP N-28-2 ±0.75 LSB
AD7829BR −40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB
AD7829BR-REEL −40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB
AD7829BR-REEL7 −40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB
AD7829BRZ1−40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB
AD7829BRZ-REEL1−40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB
AD7829BRZ-REEL71−40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB
AD7829BRU −40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB
AD7829BRU-REEL −40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB
AD7829BRU-REEL7 −40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB
AD7829BRUZ1−40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB
AD7829BRUZ-REEL1−40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB
AD7829BRUZ-REEL71−40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB
1 Z = Pb-free part.
AD7822/AD7825/AD7829
Rev. C | Page 26 of 28
NOTES
AD7822/AD7825/AD7829
Rev. C | Page 27 of 28
NOTES
AD7822/AD7825/AD7829
Rev. C | Page 28 of 28
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01321-0-8/06(C)