935286617151 - NXP SEMICONDUCTORS

1. General description

The UART are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and

embedded trace support, together with 128 kB of embedded high speed ﬂash memory. A

128-bit wide memory interface and a unique accelerator architecture enable 32-bit code

execution at maximum clock rate. For critical code size applications, the alternative 16-bit

Thumb mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, these microcontrollers are ideal for

applications where miniaturization is a key requirement, such as access control and

point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM

options up to 64 kB, they are very well suited for communication gateways and protocol

converters, soft modems, voice recognition and low end imaging, providing both large

buffer size and high processing power. Various 32-bit timers, PWM channels, and 32

GPIO lines make these microcontrollers particularly suitable for industrial control and

medical systems.

Remark: Throughout the data sheet, the term LPC2104/2105/2106 will apply to devices

with and without /00 and /01 sufﬁxes. Sufﬁxes will be used to differentiate devices

whenever they include new features.

2. Features

2.1 New features implemented in LPC2104/2105/2106/01 devices

nFast GPIO port enables port pin toggling up to 3.5 times faster than the original device

and also allows for a port pin to be read at any time regardless of its function.

nUART 0/1 include fractional baud rate generator, autobauding capabilities, and

handshake ﬂow-control fully implemented in hardware.

nBuffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.

nSPI programmable data length and master mode enhancement.

nDiversiﬁed Code Read Protection (CRP) enables different security levels to be

implemented.

nGeneral purpose timers can operate as external event counters.

2.2 Key common features

n16/32-bit ARM7TDMI-S processor.

n16/32/64 kB on-chip static RAM.

n128 kB on-chip ﬂash program memory. 128-bit-wide interface/accelerator enables high

speed 60 MHz operation.

LPC2104/2105/2106

Single-chip 32-bit microcontrollers; 128 kB ISP/IAP ﬂash with

16/32/64 kB RAM

Rev. 07 — 20 June 2008 Product data sheet

Product data sheet Rev. 07 — 20 June 2008 2 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

nIn-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or

full chip erase takes 400 ms.

nVectored Interrupt Controller with conﬁgurable priorities and vector addresses.

nEmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service

routines can continue to execute whilst the foreground task is debugged with the

on-chip RealMonitor software.

nEmbedded Trace Macrocell enables non-intrusive high speed real-time tracing of

instruction execution.

nMultiple serial interfaces including two UARTs (16C550), Fast I2C-bus (400 kbit/s), and

SPI.

nTwo 32-bit timers (7 capture/compare channels), PWM unit (6 outputs), Real Time

Clock and Watchdog.

nUp to thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 mm ×7 mm)

package.

n60 MHz maximum CPU clock available from programmable on-chip Phase-Locked

Loop with settling time of 100 µs.

nThe on-chip crystal oscillator should have an operating range of 1 MHz to 25 MHz.

nTwo low power modes, Idle and Power-down.

nProcessor wake-up from Power-down mode via external interrupt.

nIndividual enable/disable of peripheral functions for power optimization.

nDual power supply:

uCPU operating voltage range of 1.65 V to 1.95 V (1.8 V ±8.3 %).

uI/O power supply range of 3.0 V to 3.6 V (3.3 V ±10 %) with 5 V tolerant I/O pads.

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC2104BBD48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

LPC2104FBD48/00 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

LPC2104FBD48/01 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

LPC2105BBD48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

LPC2105FBD48/00 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

LPC2105FBD48/01 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

LPC2106BBD48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

LPC2106FBD48 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

Product data sheet Rev. 07 — 20 June 2008 3 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

3.1 Ordering options

LPC2106FBD48/00 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

LPC2106FBD48/01 LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2

LPC2106FHN48 HVQFN48 plastic thermal enhanced very thin quad ﬂat

package; no leads; 48 terminals; body

7×7×0.85 mm

SOT619-1

LPC2106FHN48/00 HVQFN48 plastic thermal enhanced very thin quad ﬂat

package; no leads; 48 terminals; body

7×7×0.85 mm

SOT619-1

LPC2106FHN48/01 HVQFN48 plastic thermal enhanced very thin quad ﬂat

package; no leads; 48 terminals; body

7×7×0.85 mm

SOT619-1

Table 1. Ordering information

…continued

Type number Package

Name Description Version

Table 2. Ordering options

Type number Flash memory RAM Temperature range

LPC2104BBD48 128 kB 16 kB 0 °C to +70 °C

LPC2104FBD48/00 128 kB 16 kB −40 °C to +85 °C

LPC2104FBD48/01 128 kB 16 kB −40 °C to +85 °C

LPC2105BBD48 128 kB 32 kB 0 °C to +70 °C

LPC2105FBD48/00 128 kB 32 kB −40 °C to +85 °C

LPC2105FBD48/01 128 kB 32 kB −40 °C to +85 °C

LPC2106BBD48 128 kB 64 kB 0 °C to +70 °C

LPC2106FBD48 128 kB 64 kB −40 °C to +85 °C

LPC2106FBD48/00 128 kB 64 kB −40 °C to +85 °C

LPC2106FBD48/01 128 kB 64 kB −40 °C to +85 °C

LPC2106FHN48 128 kB 64 kB −40 °C to +85 °C

LPC2106FHN48/00 128 kB 64 kB −40 °C to +85 °C

LPC2106FHN48/01 128 kB 64 kB −40 °C to +85 °C

Product data sheet Rev. 07 — 20 June 2008 4 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

4. Block diagram

(1) Shared with GPIO.

(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.

(3) Available on LPC2104/2105/2106/01 only.

Fig 1. Block diagram

SCL(1)

P0[31:0]

TRST(2)

TMS(2)

TCK(2)

TDI(2)

TDO(2) XTAL2

XTAL1

EINT[2:0](1)

AHB BRIDGE

PLL

PWM0

ARM7TDMI-S

LPC2104/2105/2106

RESET

CAP0[2:0](1)

CAP1[3:0](1)

MAT0[2:0](1)

MAT1[3:0](1)

SDA(1)

RXD[1:0](1)

TXD[1:0](1)

DSR1(1), CTS1(1),

RTS1(1), DTR1(1),

DCD1(1), RI1(1)

RTCK

ARM7 LOCAL BUS

INTERNAL

SRAM

CONTROLLER

INTERNAL

FLASH

CONTROLLER

16/32/64 kB

SRAM 128 kB

FLASH

EXTERNAL

INTERRUPTS

CAPTURE/

COMPARE

TIMER 0/TIMER 1

GENERAL

PURPOSE I/O

TEST/DEBUG

INTERFACE

EMULATION

TRACE MODULE

AMBA Advanced High-performance

Bus (AHB)

system

clock

SYSTEM

FUNCTIONS

VECTORED

INTERRUPT

CONTROLLER

AHB

DECODER

I2C-BUS SERIAL

INTERFACE

AHB T O APB

BRIDGE APB

DIVIDER

Advanced Peripheral

Bus (APB)

UART0/UART1

WATCHDOG

TIMER

SYSTEM

CONTROL

REAL-TIME CLOCK

002aaa412

VDD(3V3)

VSS

VDD(1V8)

PWM[6:1](1)

P0 HIGH-SPEED

GPIO(3)

32 PINS TOTAL

SCK(1)

MOSI(1)

MISO(1)

SSEL(1)

SPI/SSP(3)

SERIAL INTERFACE

Product data sheet Rev. 07 — 20 June 2008 5 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

5. Pinning information

5.1 Pinning

Pin conﬁguration is identical for all LQFP48 packages.

Fig 2. Pin conﬁguration (LQFP48)

LPC2104/2105/2106

P0.19/MAT1.2/TCK P0.11/CTS1/CAP1.1

P0.20/MAT1.3/TDI P0.10/RTS1/CAP1.0

P0.21/PWM5/TDO P0.24/PIPESTAT1

n.c. P0.23/PIPESTAT0

VDD(1V8) P0.22/TRACECLK

RESET VSS

VSS P0.9/RXD1/PWM6

P0.27/TRACEPKT0/TRST P0.8/TXD1/PWM4

P0.28/TRACEPKT1/TMS P0.7/SSEL/PWM2

P0.29/TRACEPKT2/TCK DBGSEL

XTAL1 RTCK

XTAL2 n.c.

P0.0/TXD0/PWM1 P0.18/CAP1.3/TMS

P0.1/RXD0/PWM3 P0.17/CAP1.2/TRST

P0.30/TRACEPKT3/TDI P0.16/EINT0/MAT0.2

P0.31/EXTIN0/TDO P0.15/RI1/EINT2

VDD(3V3) P0.14/DCD1/EINT1

P0.2/SCL/CAP0.0 VSS

VSS n.c.

n.c. P0.13/DTR1/MAT1.1

P0.3/SDA/MAT0.0 VDD(3V3)

P0.4/SCK/CAP0.1 P0.26/TRACESYNC

P0.5/MISO/MAT0.1

P0.6/MOSI/CAP0.2

P0.25/PIPESTAT2

P0.12/DSR1/MAT1.0

002aaa411

Product data sheet Rev. 07 — 20 June 2008 6 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

Pin conﬁguration is identical for LPC2106FHN48, LPC2106FHN48/00, and LPC2106FHN48/01.

Fig 3. Pin conﬁguration (HVQFN48)

002aac440

LPC2104/2105/2106

12 25

11 26

10 27

9 28

8 29

7 30

6 31

5 32

4 33

3 34

2 35

1 36

terminal 1

index area

Transparent top view

P0.19/MAT1.2/TCK P0.11/CTS1/CAP1.1

P0.20/MAT1.3/TDI P0.10/RTS1/CAP1.0

P0.21/PWM5/TDO P0.24/PIPESTAT1

n.c. P0.23/PIPESTAT0

VDD(1V8) P0.22/TRACECLK

RESET VSS

VSS P0.9/RXD1/PWM6

P0.27/TRACEPKT0/TRST P0.8/TXD1/PWM4

P0.28/TRACEPKT1/TMS P0.7/SSEL/PWM2

P0.29/TRACEPKT2/TCK DBGSEL

XTAL1 RTCK

XTAL2 n.c.

P0.0/TXD0/PWM1 P0.18/CAP1.3/TMS

P0.1/RXD0/PWM3 P0.17/CAP1.2/TRST

P0.30/TRACEPKT3/TDI P0.16/EINT0/MAT0.2

P0.31/EXTIN0/TDO P0.15/RI1/EINT2

VDD(3V3) P0.14/DCD1/EINT1

P0.2/SCL/CAP0.0 VSS

VSS n.c.

n.c. P0.13/DTR1/MAT1.1

P0.3/SDA/MAT0.0 VDD(3V3)

P0.4/SCK/CAP0.1 P0.26/TRACESYNC

P0.5/MISO/MAT0.1

P0.6/MOSI/CAP0.2

P0.25/PIPESTAT2

P0.12/DSR1/MAT1.0

Product data sheet Rev. 07 — 20 June 2008 7 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

5.2 Pin description

Table 3. Pin description

Symbol Pin Type Description

P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit bidirectional I/O port with individual direction controls for

each bit. The operation of port 0 pins depends upon the pin function selected via

the Pin Connect Block.

P0.0/TXD0/PWM1 13[1] I/O P0.0 — Port 0 bit 0.

OTXD0 — Transmitter output for UART 0.

OPWM1 — Pulse Width Modulator output 1.

P0.1/RXD0/PWM3 14[1] I/O P0.1 — Port 0 bit 1.

IRXD0 — Receiver input for UART 0.

OPWM3 — Pulse Width Modulator output 3.

P0.2/SCL/CAP0.0 18[2] I/O P0.2 — Port 0 bit 2. The output is open-drain.

I/O SCL — I2C-bus clock input/output. Open-drain output (for I2C-bus compliance).

ICAP0.0 — Capture input for Timer 0, channel 0.

P0.3/SDA/MAT0.0 21[2] I/O P0.3 — Port 0 bit 3. The output is open-drain.

I/O SDA — I2C-bus data input/output. Open-drain output (for I2C-bus compliance).

OMAT0.0 — Match output for Timer 0, channel 0. The output is open-drain.

P0.4/SCK/CAP0.1 22[1] I/O P0.4 — Port 0 bit 4.

I/O SCK — Serial clock for SPI/SSP[3]. Clock output from master or input to slave.

ICAP0.1 — Capture input for Timer 0, channel 1.

P0.5/MISO/MAT0.1 23[1] I/O P0.5 — Port 0 bit 5.

I/O MISO — Master In Slave Out for SPI/SSP[3]. Data input to SPI/SSP master or

data output from SPI/SSP slave.

OMAT0.1 — Match output for Timer 0, channel 1.

P0.6/MOSI/CAP0.2 24[1] I/O P0.6 — Port 0 bit 6.

I/O MOSI — Master Out Slave In for SPI/SSP[3]. Data output from SPI/SSP master

or data input to SPI/SSP slave.

ICAP0.2 — Capture input for Timer 0, channel 2.

P0.7/SSEL/PWM2 28[1] I/O P0.7 — Port 0 bit 7.

ISSEL — Slave Select for SPI/SSP[3]. Selects the SPI/SSP interface as a slave.

OPWM2 — Pulse Width Modulator output 2.

P0.8/TXD1/PWM4 29[1] I/O P0.8 — Port 0 bit 8.

OTXD1 — Transmitter output for UART 1.

OPWM4 — Pulse Width Modulator output 4.

P0.9/RXD1/PWM6 30[1] I/O P0.9 — Port 0 bit 9.

IRXD1 — Receiver input for UART 1.

OPWM6 — Pulse Width Modulator output 6.

P0.10/RTS1/CAP1.0 35[1] I/O P0.10 — Port 0 bit 10.

ORTS1 — Request to Send output for UART 1.

ICAP1.0 — Capture input for Timer 1, channel 0.

Product data sheet Rev. 07 — 20 June 2008 8 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

P0.11/CTS1/CAP1.1 36[1] I/O P0.11 — Port 0 bit 11.

ICTS1 — Clear to Send input for UART 1.

ICAP1.1 — Capture input for Timer 1, channel 1.

P0.12/DSR1/MAT1.0 37[1] I/O P0.12 — Port 0 bit 12.

IDSR1 — Data Set Ready input for UART 1.

OMAT1.0 — Match output for Timer 1, channel 0.

P0.13/DTR1/MAT1.1 41[1] I/O P0.13 — Port 0 bit 13.

ODTR1 — Data Terminal Ready output for UART 1.

OMAT1.1 — Match output for Timer 1, channel 1.

P0.14/DCD1/EINT1 44[1] I/O P0.14 — Port 0 bit 14.

IDCD1 — Data Carrier Detect input for UART 1.

IEINT1 — External interrupt 1 input.

P0.15/RI1/EINT2 45[1] I/O P0.15 — Port 0 bit 15.

IRI1 — Ring Indicator input for UART 1.

OEINT2 — External interrupt 2 input.

P0.16/EINT0/MAT0.2 46[1] I/O P0.16 — Port 0 bit 16.

IEINT0 — External interrupt 0 input.

OMAT0.2 — Match output for Timer 0, channel 2.

P0.17/CAP1.2/TRST 47[1] I/O P0.17 — Port 0 bit 17.

ICAP1.2 — Capture input for Timer 1, channel 2.

ITRST — Test Reset for JTAG interface, primary JTAG pin group.

P0.18/CAP1.3/TMS 48[1] I/O P0.18 — Port 0 bit 18.

ICAP1.3 — Capture input for Timer 1, channel 3.

ITMS — Test Mode Select for JTAG interface, primary JTAG pin group.

P0.19/MAT1.2/TCK 1[1] I/O P0.19 — Port 0 bit 19.

OMAT1.2 — Match output for Timer 1, channel 2.

ITCK — Test Clock for JTAG interface, primary JTAG pin group.

P0.20/MAT1.3/TDI 2[1] I/O P0.20 — Port 0 bit 20.

OMAT1.3 — Match output for Timer 1, channel 3.

ITDI — Test Data In for JTAG interface, primary JTAG pin group.

P0.21/PWM5/TDO 3[1] I/O P0.21 — Port 0 bit 21.

OPWM5 — Pulse Width Modulator output 5.

OTDO — Test Data Out for JTAG interface, primary JTAG pin group.

P0.22/TRACECLK 32[4] I/O P0.22 — Port 0 bit 22.

OTRACECLK — Trace Clock. Standard I/O port with internal pull-up.

P0.23/PIPESTAT0 33[4] I/O P0.23 — Port 0 bit 23.

OPIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.

P0.24/PIPESTAT1 34[4] I/O P0.24 — Port 0 bit 24.

OPIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.

P0.25/PIPESTAT2 38[4] I/O P0.25 — Port 0 bit 25.

OPIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 07 — 20 June 2008 9 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz speciﬁcation. It requires external pull-up to provide an output

functionality. Open-drain conﬁguration applies to all functions on this pin.

[3] SSP interface available on LPC2104/2105/2106/01 only.

[4] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ.

[5] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.

P0.26/TRACESYNC 39[4] I/O P0.26 — Port 0 bit 26.

OTRACESYNC — Trace Synchronization Standard I/O port with internal pull-up.

P0.27/TRACEPKT0/

TRST 8[4] I/O P0.27 — Port 0 bit 27.

OTRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

ITRST — Test Reset for JTAG interface, secondary JTAG pin group.

P0.28/TRACEPKT1/

TMS 9[4] I/O P0.28 — Port 0 bit 28.

OTRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

ITMS — Test Mode Select for JTAG interface, secondary JTAG pin group.

P0.29/TRACEPKT2/

TCK 10[4] I/O P0.29 — Port 0 bit 29.

OTRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

ITCK — Test Clock for JTAG interface, secondary JTAG pin group. This clock

must be slower than 1/6 of the CPU clock (CCLK) for the JTAG interface to

operate.

P0.30/TRACEPKT3/

TDI 15[4] I/O P0.30 — Port 0 bit 30.

OTRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

ITDI — Test Data In for JTAG interface, secondary JTAG pin group.

P0.31/EXTIN0/TDO 16[4] I/O P0.31 — Port 0 bit 31.

IEXTIN0 — External Trigger Input. Standard I/O port with internal pull-up.

OTDO — Test Data out for JTAG interface, secondary JTAG pin group.

RTCK 26[4] I/O Returned Test Clock output: Extra signal added to the JTAG port. Assists

debugger synchronization when processor frequency varies. Also used during

debug mode entry to select primary or secondary JTAG pins with the 48-pin

package. Bidirectional pin with internal pull-up.

DBGSEL 27 I Debug Select: When LOW, the part operates normally. When HIGH, debug

mode is entered. Input pin with internal pull-down.

RESET 6[5] I external reset input; a LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. TTL with hysteresis, 5 V tolerant.

XTAL1 11 I input to the oscillator circuit and internal clock generator circuits.

XTAL2 12 O output from the oscillator ampliﬁer.

VSS 7, 19,

31, 43 I ground: 0 V reference.

VDD(1V8) 5 I 1.8 V core power supply; this is the power supply voltage for internal circuitry.

VDD(3V3) 17, 40 I 3.3 V pad power supply; this is the power supply voltage for the I/O ports.

n.c. 4, 20,

25, 42 - not connected; these pins are not connected in the 48-pin package.

Table 3. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 07 — 20 June 2008 10 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

•The standard 32-bit ARM set.

•A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip ﬂash program memory

The LPC2104/2105/2106 incorporate a 128 kB ﬂash memory system. This memory may

be used for both code and data storage. Programming of the ﬂash memory may be

accomplished in several ways. It may be programmed In System via the serial port. The

application program may also erase and/or program the ﬂash while the application is

running, allowing a great degree of ﬂexibility for data storage ﬁeld ﬁrmware upgrades, etc.

When on-chip bootloader is used, 120 kB of ﬂash memory is available for user code.

The LPC2104/2105/2106 ﬂash memory provides a minimum of 100000 erase/write cycles

and 20 years of data retention.

6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8 bit, 16 bit, and 32 bit. The LPC2104/2105/2106 provide 16/32/64 kB of

static RAM, respectively.

Product data sheet Rev. 07 — 20 June 2008 11 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6.4 Memory map

The LPC2104/2105/2106 memory maps incorporate several distinct regions, as shown in

the following ﬁgures.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

ﬂash memory (the default) or on-chip static RAM. This is described in Section 6.18

“System control”.

(1) LPC2104/2105/2106/01 only.

Fig 4. LPC2104/2105/2106 memory map

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY)

RESERVED ADDRESS SPACE

16 kB ON-CHIP STATIC RAM (LPC2104)

32 kB ON-CHIP STATIC RAM (LPC2105)

64 kB ON-CHIP STATIC RAM (LPC2106)

RESERVED ADDRESS SPACE

FAST GPIO REGISTERS(1)

128 kB ON-CHIP FLASH MEMORY

0xFFFF FFFF

0xF000 0000

0xEFFF FFFF

0xE000 0000

0xC000 0000

0xDFFF FFFF

0x8000 0000

0x7FFF FFFF

0x7FFF E000

0x7FFF DFFF

0x4000 4000

0x4000 3FFF

0x4000 8000

0x4000 7FFF

0x4001 0000

0x4000 FFFF

0x4000 0000

0x3FFF FFFF

0x3FFF C000

0x0002 0000

0x0001 FFFF

0x0000 0000

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

0.0 GB

002aad666

Product data sheet Rev. 07 — 20 June 2008 12 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the Interrupt Request (IRQ) inputs

and categorizes, them as FIQ, vectored IRQ, and non-vectored IRQ as deﬁned by

programmable settings. The programmable assignment scheme means that priorities of

interrupts from the various peripherals can be dynamically assigned and adjusted.

Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned

to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor.

The fastest possible FIQ latency is achieved when only one request is classiﬁed as FIQ,

because then the FIQ service routine can simply start dealing with that device. But if more

than one request is assigned to the FIQ class, the FIQ service routine can read a word

from the VIC that identiﬁes which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the Vectored Interrupt Controller, but may have several

internal interrupt ﬂags. Individual interrupt ﬂags may also represent more than one

interrupt source.

Table 4. Interrupt sources

Block Flag(s) VIC channel #

WDT Watchdog Interrupt (WDINT) 0

- Reserved for software interrupts only 1

ARM Core EmbeddedICE, DbgCommRx 2

ARM Core EmbeddedICE, DbgCommTx 3

Timer 0 Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 2 (CR0, CR1, CR2) 4

Timer 1 Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3) 5

UART 0 Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Auto-Baud Time-Out (ABTO)[1]

End of Auto-Baud (ABEO)[1]

Product data sheet Rev. 07 — 20 June 2008 13 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

[1] Available on LPC2104/2105/2106/01 only.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

The Pin Control Module contains two registers as shown in Table 5.

6.7 Pin function select register 0 (PINSEL0 - 0xE002 C000)

The PINSEL0 register controls the functions of the pins as per the settings listed in

Table 6. The direction control bit in the IODIR register is effective only when the GPIO

function is selected for a pin. For other functions, direction is controlled automatically.

Settings other than those shown in Table 6 are reserved, and should not be used

UART 1 Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

Auto-Baud Time-Out (ABTO)[1]

End of Auto-Baud (ABEO)[1]

PWM0 Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8

I2C-bus SI (state change) 9

SPI and SSP[1] SPIF, MODF (SPI)

TXRIS, RXRIS, RTRIS, RORRIS (SSP)[1] 10

- reserved 11

PLL PLL Lock (PLOCK) 12

RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13

System Control External Interrupt 0 (EINT0) 14

System Control External Interrupt 1 (EINT1) 15

System Control External Interrupt 2 (EINT2) 16

Table 4. Interrupt sources

…continued

Block Flag(s) VIC channel #

Table 5. Pin control module registers

Address Name Description Access

0xE002 C000 PINSEL0 Pin function select register 0 Read/Write

0xE002 C004 PINSEL1 Pin function select register 1 Read/Write

Product data sheet Rev. 07 — 20 June 2008 14 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

Table 6. Pin function select register 0 (PINSEL0 - 0xE002 C000)

PINSEL0 Pin name Value Function Value after reset

1:0 P0.0 0 0 GPIO Port 0.0 0

0 1 TXD (UART 0)

1 0 PWM1

3:2 P0.1 0 0 GPIO Port 0.1 0

0 1 RXD (UART 0)

1 0 PWM3

5:4 P0.2 0 0 GPIO Port 0.2 0

0 1 SCL (I2C-bus)

1 0 Capture 0.0 (Timer 0)

7:6 P0.3 0 0 GPIO Port 0.3 0

01SDA (I

2C-bus)

1 0 Match 0.0 (Timer 0)

9:8 P0.4 0 0 GPIO Port 0.4 0

0 1 SCK (SPI/SSP)

1 0 Capture 0.1 (Timer 0)

11:10 P0.5 0 0 GPIO Port 0.5 0

0 1 MISO (SPI/SSP)

1 0 Match 0.1 (Timer 0)

13:12 P0.6 0 0 GPIO Port 0.6 0

0 1 MOSI (SPI/SSP)

1 0 Capture 0.2 (Timer 0)

15:14 P0.7 0 0 GPIO Port 0.7 0

0 1 SSEL (SPI/SSP)

1 0 PWM2

17:16 P0.8 0 0 GPIO Port 0.8 0

0 1 TXD (UART 1)

1 0 PWM4

19:18 P0.9 0 0 GPIO Port 0.9 0

0 1 RXD (UART 1)

1 0 PWM6

21:20 P0.10 0 0 GPIO Port 0.10 0

0 1 RTS (UART 1)

1 0 Capture 1.0 (Timer 1)

23:22 P0.11 0 0 GPIO Port 0.11 0

0 1 CTS (UART 1)

1 0 Capture 1.1 (Timer 1)

25:24 P0.12 0 0 GPIO Port 0.12 0

0 1 DSR (UART 1)

1 0 Match 1.0 (Timer 1)

Product data sheet Rev. 07 — 20 June 2008 15 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6.8 Pin function select register 1 (PINSEL1 - 0xE002 C004)

The PINSEL1 register controls the functions of the pins as per the settings listed in

Table 7. The direction control bit in the IODIR register is effective only when the GPIO

function is selected for a pin. For other functions direction is controlled automatically.

Remark: The primary JTAG port and the trace port can be selected only through the

DBGSEL pin at reset (Debug mode). Function control for the pins P0[31:17] is effective

only when the DBGSEL input is pulled LOW during reset.

27:26 P0.13 0 0 GPIO Port 0.13 0

0 1 DTR (UART 1)

1 0 Match 1.1 (Timer 1)

29:28 P0.14 0 0 GPIO Port 0.14 0

0 1 DCD (UART 1)

1 0 EINT1

31:30 P0.15 0 0 GPIO Port 0.15 0

0 1 RI (UART 1)

1 0 EINT2

Table 6. Pin function select register 0 (PINSEL0 - 0xE002 C000)

…continued

PINSEL0 Pin name Value Function Value after reset

Table 7. Pin function select register 1 (PINSEL1 - 0xE002 C004)

PINSEL1 Pin name Value Function Value after

reset

1:0 P0.16 0 0 GPIO Port 0.16 0

0 1 EINT0

1 0 Match 0.2 (Timer 0)

3:2 P0.17 0 0 GPIO Port 0.17 0

0 1 Capture 1.2 (Timer 1)

5:4 P0.18 0 0 GPIO Port 0.18 0

0 1 Capture 1.3 (Timer 1)

7:6 P0.19 0 0 GPIO Port 0.19 0

0 1 Match 1.2 (Timer 1)

9:8 P0.20 0 0 GPIO Port 0.20 0

0 1 Match 1.3 (Timer 1)

11:10 P0.21 0 0 GPIO Port 0.21 0

0 1 PWM5

13:12 P0.22 0 0 GPIO Port 0.22 0

15:14 P0.23 0 0 GPIO Port 0.23 0

17:16 P0.24 0 0 GPIO Port 0.24 0

19:18 P0.25 0 0 GPIO Port 0.25 0

21:20 P0.26 0 0 GPIO Port 0.26 0

23:22 P0.27 0 0 GPIO Port 0.27 0

0 1 TRST

Product data sheet Rev. 07 — 20 June 2008 16 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6.9 General purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.9.1 Features

•Direction control of individual bits.

•Separate control of output set and clear.

•All I/O default to inputs after reset.

6.9.2 Features added with the Fast GPIO set of registers available on

LPC2104/2105/2106/01 only

•Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O

timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.

•Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

•All Fast GPIO registers are byte addressable.

•Entire port value can be written in one instruction.

•Ports are accessible via either the legacy group of registers (GPIOs) or the group of

registers providing accelerated port access (Fast GPIOs).

6.10 UARTs

The LPC2104/2105/2106 each contain two UARTs. One UART provides a full modem

control handshake interface, the other provides only transmit and receive data lines.

6.10.1 Features

•16 byte Receive and Transmit FIFOs

•Register locations conform to 16C550 industry standard

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

•Built-in baud rate generator

25:24 P0.28 0 0 GPIO Port 0.28 0

0 1 TMS

27:26 P0.29 0 0 GPIO Port 0.29 0

0 1 TCK

29:28 P0.30 0 0 GPIO Port 0.30 0

0 1 TDI

31:30 P0.31 0 0 GPIO Port 0.31 0

0 1 TDO

Table 7. Pin function select register 1 (PINSEL1 - 0xE002 C004)

…continued

PINSEL1 Pin name Value Function Value after

reset

Product data sheet Rev. 07 — 20 June 2008 17 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

•Standard modem interface signals included on UART 1.

6.10.2 UART features available in LPC2104/2105/2106/01 only

Compared to previous LPC2000 microcontrollers, UARTs in LPC2104/2105/2106/01

introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers

to achieve standard baud rates such as 115200 Bd with any crystal frequency above

2 MHz. In addition, auto-CTS/RTS ﬂow-control functions are fully implemented in

hardware.

•Fractional baud rate generator enables standard baud rates such as 115200 Bd to be

achieved with any crystal frequency above 2 MHz.

•Autobauding.

•Auto-CTS/RTS ﬂow-control fully implemented in hardware.

6.11 I2C-bus serial I/O controller

I2C is a bidirectional bus for inter-IC control using only two wires: a serial clock line (SCL),

and a serial data line (SDA). Each device is recognized by a unique address and can

operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. I2C is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2104/2105/2106 supports bit rate up to 400 kbit/s (Fast

I2C-bus).

6.11.1 Features

•Standard I2C compliant bus interface.

•Easy to conﬁgure as Master, Slave or Master/Slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

•The I2C-bus may be used for test and diagnostic purposes.

Product data sheet Rev. 07 — 20 June 2008 18 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6.12 SPI serial I/O controller

The SPI is a full duplex serial interface, designed to be able to handle multiple masters

and slaves connected to a given bus. Only a single master and a single slave can

communicate on the interface during a given data transfer. During a data transfer the

master always sends a byte of data to the slave, and the slave always sends a byte of data

to the master.

6.12.1 Features

•Compliant with Serial Peripheral Interface (SPI) speciﬁcation.

•Synchronous, serial, full duplex communication.

•Combined SPI master and slave.

•Maximum data bit rate of one eighth of the input clock rate.

6.12.2 Features available in LPC2104/2105/2106/01 only

•Selectable transfer width of eight to 16 bit per frame.

•When the SPI interface is used in Master mode, the SSEL pin is not needed (can be

used for a different function).

6.13 SSP controller (LPC2104/2015/2106/01 only)

The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. Data transfers are in

principle full duplex, with frames of four to 16 bits of data ﬂowing from the master to the

slave and from the slave to the master.

Because the SSP and SPI peripherals share the same physical pins, it is not possible to

have both of these two peripherals active at the same time. Application can switch on the

ﬂy from SPI to SSP and back.

6.13.1 Features

•Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National

Semiconductor’s Microwire buses.

•Synchronous serial communication.

•Master or slave operation.

•8-frame FIFOs for both transmit and receive.

•Four to 16 bits per frame.

6.14 General purpose timers

The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally

generate interrupts or perform other actions at speciﬁed timer values, based on four

match registers. It also includes up to four capture inputs to trap the timer value when an

input signal transitions, optionally generating an interrupt.

Product data sheet Rev. 07 — 20 June 2008 19 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6.14.1 Features

•A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

•Up to four (Timer 1) and three (Timer 0) 32-bit capture channels, that can take a

snapshot of the timer value when an input signal transitions. A capture event may also

optionally generate an interrupt.

•Four 32-bit match registers that allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Up to four (Timer 1) and three (Timer 0) external outputs corresponding to match

registers, with the following capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

6.14.2 Features available in LPC2104/2105/2106/01 only

The LPC2104/2105/2106/01 can count external events on one of the capture inputs if the

external pulse lasts at least one half of the period of the PCLK. In this conﬁguration,

unused capture lines can be selected as regular timer capture inputs or used as external

interrupts.

•Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied

clock.

•When counting cycles of an externally supplied clock, only one of the timer’s capture

inputs can be selected as the timer’s clock. The rate of such a clock is limited to

PCLK⁄4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter

than 1⁄(2PCLK).

6.15 Watchdog timer

The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the Watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the Watchdog within a predetermined

amount of time.

6.15.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

Product data sheet Rev. 07 — 20 June 2008 20 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

•Programmable 32-bit timer with internal pre-scaler.

•Selectable time period from (Tcy(PCLK) ×256 ×4) to (Tcy(PCLK) ×232 ×4) in multiples of

Tcy(PCLK) × 4.

6.16 Real time clock

The Real Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use little

power, making it suitable for battery powered systems where the CPU is not running

continuously (Idle mode).

6.16.1 Features

•Measures the passage of time to maintain a calendar and clock.

•Ultra Low Power design to support battery powered systems.

•Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

•Programmable Reference Clock Divider allows adjustment of the RTC to match

various crystal frequencies.

6.17 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2104/2105/2106. The Timer is designed

to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or

perform other actions when speciﬁed timer values occur, based on seven match registers.

It also includes four capture inputs to save the timer value when an input signal transitions,

and optionally generate an interrupt when those events occur. The PWM function is in

addition to these features, and is based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires three

non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

Product data sheet Rev. 07 — 20 June 2008 21 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

With double edge controlled PWM outputs, speciﬁc match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

6.17.1 Features

•Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

•The match registers also allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

•Pulse period and width can be any number of timer counts. This allows complete

ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

•Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

•Match register updates are synchronized with pulse outputs to prevent generation of

erroneous pulses. Software must “release” new match values before they can become

effective.

•May be used as a standard timer if the PWM mode is not enabled.

•A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.18 System control

6.18.1 Crystal oscillator

The oscillator supports crystals in the range of 1 MHz to 25 MHz. The oscillator output

frequency is called FOSC and the ARM processor clock frequency is referred to as CCLK

for purposes of rate equations, etc. FOSC and CCLK are the same value unless the PLL

is running and connected. Refer to Section 6.18.2 “PLL” for additional information.

6.18.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

Product data sheet Rev. 07 — 20 June 2008 22 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed

following a chip Reset and may be enabled by software. The program must conﬁgure and

activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The

PLL settling time is 100 µs.

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2104/2105/2106: the RESET pin and Watchdog Reset.

The RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of

chip Reset by any source starts the wake-up timer (see wake-up timer description below),

causing the internal chip reset to remain asserted until the external Reset is de-asserted,

the oscillator is running, a ﬁxed number of clocks have passed, and the on-chip ﬂash

controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is the Reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This

is important at power on, all types of Reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.18.4 Code security (Code Read Protection - CRP)

This feature of the LPC2104/2105/2106/01 allows the user to enable different levels of

security in the system so that access to the on-chip ﬂash and use of the JTAG and ISP

can be restricted. When needed, CRP is invoked by programming a speciﬁc pattern into a

dedicated ﬂash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection:

1. CRP1 disables access to the chip via the JTAG and allows partial ﬂash update

(excluding ﬂash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and ﬂash ﬁeld updates are needed but all sectors can

not be erased.

2. CRP2 disables access to the chip via the JTAG and only allows full ﬂash erase and

update using a reduced set of the ISP commands.

Product data sheet Rev. 07 — 20 June 2008 23 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

3. Running an application with level CRP3 selected fully disables any access to chip via

the JTAG pins and the ISP. This mode effectively disables ISP override using P0[14]

pin, too. It is up to the user’s application to provide (if needed) a ﬂash update

mechanism using IAP calls or a call to reinvoke ISP command to enable ﬂash update

via UART 0.

6.18.5 External interrupt inputs

The LPC2104/2105/2106 include three external interrupt inputs as selectable pin

functions. The external interrupt inputs can optionally be used to wake up the processor

from Power-down mode.

6.18.6 Memory mapping control

The Memory mapping control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

6.18.7 Power control

The LPC2104/2105/2106 support two reduced power modes: Idle mode and Power-down

mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Idle mode and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates power used

by the processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a Reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

The power can be controlled for each peripheral individually allowing peripherals to be

turned off if they are not needed in the application and resulting in additional power

savings.

6.18.8 APB

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The ﬁrst

is to provide peripherals with the desired PCLK via APB so that they can operate at the

speed chosen for the ARM processor. In order to achieve this, the APB may be slowed

down to 1⁄2 to 1⁄4 of the processor clock rate. Because the APB must work properly at

power-up (and its timing cannot be altered if it does not work since the APB divider control

registers reside on the APB), the default condition at reset is for the APB to run at 1⁄4of the

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 07 — 20 June 2008 24 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

processor clock rate. The second purpose of the APB divider is to allow power savings

when an application does not require any peripherals to run at the full processor rate.

Because the APB divider is connected to the PLL output, the PLL remains active (if it was

running) during Idle mode.

6.19 Emulation and debugging

The LPC2104/2105/2106 support emulation and debugging via a JTAG serial port. A trace

port allows tracing program execution. Each of these functions requires a trade-off of

debugging features versus device pins. Because the LPC2104/2105/2106 are provided in

a small package, there is no room for permanently assigned JTAG or Trace pins. An

alternate JTAG port allows an option to debug functions assigned to the pins used by the

primary JTAG port (see Section 6.8).

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or even

entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program ﬂow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG

interface to operate.

6.19.2 Embedded trace

Since the LPC2104/2105/2106 have signiﬁcant amounts of on-chip memory, it is not

possible to determine how the processor core is operating simply by observing the

external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability

for deeply embedded processor cores. It outputs information about processor execution to

the trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the ﬂow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is signiﬁcantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address comparators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code cannot be traced

because of this restriction.

Product data sheet Rev. 07 — 20 June 2008 25 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6.19.3 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables

real time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC (Debug

Communications Channel), which is present in the EmbeddedICE logic. The

LPC2104/2105/2106 contain a speciﬁc conﬁguration of RealMonitor software

programmed into the on-chip ﬂash memory.

Product data sheet Rev. 07 — 20 June 2008 26 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

7. Limiting values

[1] The following applies to Table 8:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to VSS unless

otherwise noted.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5] Only valid when the VDD(3V3) supply voltage is present.

[6] Not to exceed 4.6 V.

[7] Per supply pin.

[8] The peak current is limited to 25 times the corresponding maximum current.

[9] Per ground pin.

[10] Dependent on package type.

[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

[12] Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω series resistor.

Table 8. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

VDD(1V8) supply voltage (1.8 V) [2] −0.5 +2.5 V

VDD(3V3) supply voltage (3.3 V) [3] −0.5 +3.6 V

VIinput voltage 5 V tolerant I/O pins [4][5] −0.5 +6.0 V

other I/O pins [4][6] −0.5 VDD(3V3) + 0.5 V

IDD supply current [7][8] - 100 mA

ISS ground current [8][9] - 100 mA

Tstg storage temperature [10] −65 +150 °C

Ptot(pack) total power dissipation (per

package) based on package heat

transfer,notdevicepower

consumption

- 1.5 W

Vesd electrostatic discharge voltage human body model [11]

all pins −2000 +2000 V

machine model [12]

all pins −200 +200 V

Product data sheet Rev. 07 — 20 June 2008 27 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

8. Static characteristics

Table 9. Static characteristics

amb

C to +70

C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD(1V8) supply voltage (1.8 V) [2] 1.65 1.8 1.95 V

VDD(3V3) supply voltage (3.3 V) [3] 3.0 3.3 3.6 V

Standard port pins, RESET, RTCK, and DBGSEL

IIL LOW-state input current VI= 0 V; no pull-up - - 3 µA

IIH HIGH-state input current VI=V

DD(3V3); no pull-down - - 3 µA

IOZ OFF-state output current VO=0V, V

O=V

DD(3V3);

no pull-up/down --3µA

Ilatch I/O latch-up current −(0.5VDD(3V3)) < VI <

(1.5VDD(3V3)); Tj < 125 °C100 - - mA

VIinput voltage [4][5]

[6] 0 - 5.5 V

VOoutput voltage output active 0 - VDD(3V3) V

VIH HIGH-state input voltage 2.0 - - V

VIL LOW-state input voltage - - 0.8 V

Vhys hysteresis voltage - 0.4 - V

VOH HIGH-state output voltage IOH =−4 mA [7] VDD(3V3) − 0.4 - - V

VOL LOW-state output voltage IOL = 4 mA [7] - - 0.4 V

IOH HIGH-state output current VOH =V

DD(3V3) −0.4 V [7] −4 --mA

IOL LOW-state output current VOL = 0.4 V [7] 4 --mA

IOHS HIGH-state short-circuit

output current VOH =0V [8] --−45 mA

IOLS LOW-state short-circuit

output current VOL =V

DD(3V3) [8] - - 50 mA

Ipd pull-down current VI= 5 V; applies to DBGSEL [9] 20 50 100 µA

LPC2104/2105/2106 and LPC2104/2105/2106/00

Ipu pull-up current VI=0V [10] −25 −50 −65 µA

VDD(3V3) < VI < 5 V [9][10] 000µA

LPC2104/2105/2106/01

Ipu pull-up current VI=0V [10] −15 −50 −85 µA

VDD(3V3) < VI < 5 V [9][10] 000µA

Product data sheet Rev. 07 — 20 June 2008 28 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

LPC2104/2105/2106 and LPC2104/2105/2106/00 power consumption

IDD(act) active mode supply current VDD(1V8) = 1.8 V;

CCLK = 60 MHz;

Tamb =25°C; code

while(1){}

executed from ﬂash; all

peripherals enabled via

PCONP register but not

conﬁgured to run

-35-mA

IDD(pd) Power-down mode supply

current VDD(1V8) = 1.8 V;

Tamb =25°C, -10-µA

VDD(1V8) = 1.8 V;

Tamb =85°C- 50 500 µA

LPC2104/2105/2106/01 power consumption

IDD(act) active mode supply current VDD(1V8) = 1.8 V;

CCLK = 60 MHz;

Tamb =25°C; code

while(1){}

executed from ﬂash; all

peripherals enabled via

PCONP register but not

conﬁgured to run[11]

-40-mA

IDD(idle) Idle mode supply current VDD(1V8) = 1.8 V;

CCLK = 60 MHz;

Tamb =25°C;

executed from ﬂash; all

peripherals enabled via

PCONP register but not

conﬁgured to run[11]

-7-mA

IDD(pd) Power-down mode supply

current VDD(1V8) = 1.8 V;

Tamb =25°C, -10-µA

VDD(1V8) = 1.8 V;

Tamb =85°C- - 300 µA

I2C-bus pins

VIH HIGH-state input voltage 0.7VDD(3V3) --V

VIL LOW-state input voltage - - 0.3VDD(3V3) V

Vhys hysteresis voltage - 0.5VDD(3V3) -V

VOL LOW-state output voltage IOLS = 3 mA [7] - - 0.4 V

ILI input leakage current VI=V

DD(3V3) [12] -24µA

VI=5V - 10 22 µA

Table 9. Static characteristics

…continued

amb

C to +70

C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 07 — 20 June 2008 29 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 °C), nominal supply voltages.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5] VDD(3V3) supply voltages must be present.

[6] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.

[7] Accounts for 100 mV voltage drop in all supply lines.

[8] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[9] Minimum condition for VI= 4.5 V, maximum condition for VI= 5.5 V.

[10] Applies to P0[31:22].

[11] SPI is enabled and SSP is disabled in the PCONP register (

see LPC2104/2105/2106 user manual

[12] To VSS.

8.1 Power consumption measurements for LPC2104/2105/2106/01

The power consumption measurements represent typical values for the given conditions.

The peripherals were enabled through the PCONP register, but for these measurements

the peripherals were not conﬁgured to run. Power measurements with all peripherals

enabled were performed with the SPI enabled and the SSP disabled. Peripherals were

disabled through the PCONP register. Refer to the

LPC2104/2105/2106 User Manual

for a

description of the PCONP register.

Oscillator pins

Vi(XTAL1) input voltage on pin XTAL1 0 - 1.8 V

Vo(XTAL2) output voltage on pin

XTAL2 0 - 1.8 V

Table 9. Static characteristics

…continued

amb

C to +70

C for commercial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ[1] Max Unit

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Tamb =25°C; core voltage 1.8 V.

Fig 5. Typical LPC2104/2105/2106/01 IDD(act) measured at different frequencies

frequency (MHz)

12 604428

002aad709

IDD(act)

(mA)

all peripherals enabled

all peripherals disabled

Product data sheet Rev. 07 — 20 June 2008 30 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Tamb =25°C; all peripherals enabled.

Fig 6. Typical LPC2104/2105/2106/01 IDD(act) measured at different core voltages

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Tamb =25°C; core voltage 1.8 V.

Fig 7. Typical LPC2104/2105/2106/01 IDD(idle) measured at different frequencies

core voltage (V)

1.65 1.951.851.751.70 1.901.80

002aad710

IDD(act)

(mA)

12 MHz

48 MHz

60 MHz

frequency (MHz)

12 604428

002aad711

5.0

10.0

15.0

IDD(idle)

(mA)

0.0

all peripherals enabled

all peripherals disabled

Product data sheet Rev. 07 — 20 June 2008 31 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4;

Tamb =25°C; all peripherals enabled.

Fig 8. Typical LPC2104/2105/2106/01 IDD(idle) measured at different core voltages

Test conditions: Active mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4; core

voltage 1.8 V; all peripherals disabled.

Fig 9. Typical LPC2104/2105/2106/01 IDD(act) measured at different temperatures

core voltage (V)

1.65 1.951.851.751.70 1.901.80

002aad712

5.0

10.0

15.0

IDD(idle)

(mA)

0.0

12 MHz

48 MHz

60 MHz

temperature (°C)

−40 856010 35−15

002aad713

IDD(act)

(mA)

12 MHz

48 MHz

60 MHz

Product data sheet Rev. 07 — 20 June 2008 32 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

Test conditions: Idle mode entered executing code from on-chip ﬂash; PCLK = CCLK⁄4; core voltage

1.8 V; all peripherals disabled.

Fig 10. Typical LPC2104/2105/2106/01 IDD(idle) measured at different temperatures

Test conditions: Power-down mode entered executing code from on-chip ﬂash.

Fig 11. Typical LPC2104/2105/2106/01 core power-down current IDD(pd) measured at

different temperatures

Table 10. Typical LPC2104/2105/2106/01 peripheral power consumption in Idle mode

Core voltage 1.8 V; T

amb

=25

C; all measurements in mA; PCLK =

CCLK

⁄

Peripheral CCLK = 60 MHz

Timer 0 0.258

Timer 1 0.254

UART 0 0.494

UART 1 0.561

temperature (°C)

−40 856010 35−15

002aad714

2.0

4.0

6.0

IDD(Idle)

(mA)

0.0

12 MHz

48 MHz

60 MHz

temperature (°C)

−40 853510 60−15

002aad715

100

200

300

IDD(pd)

(µA)

1.95 V

1.80 V

1.65 V

Product data sheet Rev. 07 — 20 June 2008 33 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

PWM0 0.511

I2C-bus 0.078

SPI 0.060

RTC 0.109

SSP 0.377

Table 10. Typical LPC2104/2105/2106/01 peripheral power consumption in Idle mode

…continued

Peripheral CCLK = 60 MHz

Product data sheet Rev. 07 — 20 June 2008 34 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

9. Dynamic characteristics

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Bus capacitance Cb in pF, from 10 pF to 400 pF.

Table 11. Dynamic characteristics

amb

= 0

C to +70

C for commercial applications,

−

C to +85

C for industrial applications; V

DD(1V8)

, V

DD(3V3)

over

speciﬁed ranges.

[1]

Symbol Parameter Conditions Min Typ Max Unit

External clock

fosc oscillator frequency supplied by an external

oscillator (signal generator) 1 - 25 MHz

external clock frequency

supplied by an external

crystal oscillator

1 - 25 MHz

external clock frequency if

on-chip PLL is used 10 - 25 MHz

external clock frequency if

on-chip bootloader is used

for initial code download

10 - 25 MHz

Tcy(clk) clock cycle time 20 - 1000 ns

tCHCX clock HIGH time Tcy(clk) ×0.4 - - ns

tCLCX clock LOW time Tcy(clk) ×0.4 - - ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Port pins (except P0.2 and P0.3)

trrise time - 10 - ns

tffall time - 10 - ns

I2C-bus pins (P0.2 and P0.3)

tffall time VIH to VIL [2] 20 + 0.1 ×Cb--ns

Product data sheet Rev. 07 — 20 June 2008 35 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

9.1 Timing

Fig 12. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

Product data sheet Rev. 07 — 20 June 2008 36 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

10. Package outline

Fig 13. Package outline SOT313-2 (LQFP48)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 7.1

6.9 0.5 9.15

8.85 0.95

0.55 7

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Product data sheet Rev. 07 — 20 June 2008 37 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

Fig 14. Package outline SOT619-1 (HVQFN48)

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 7.1

6.9

5.25

4.95

7.1

6.9 5.25

4.95

5.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT619-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT619-1

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 24

48 37

01-08-08

02-10-18

terminal 1

index area

terminal 1

index area

1/2 e

1/2 e AC

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 07 — 20 June 2008 38 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

11. Abbreviations

Table 12. Abbreviations

Acronym Description

AMBA Advanced Microcontroller Bus Architecture

APB ARM Peripheral Bus

CPU Central Processing Unit

DCC Debug Communications Channel

FIFO First In, First Out

GPIO General Purpose Input/Output

PLL Phase-Locked Loop

PWM Pulse Width Modulator

RAM Random Access Memory

SPI Serial Peripheral Interface

SSI Synchronous Serial Interface

SSP Synchronous Serial Port

SRAM Static Random Access Memory

TTL Transistor-Transistor Logic

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 07 — 20 June 2008 39 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

12. Revision history

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC2104_2105_2106_7 20080620 Product data sheet - LPC2104_2105_2106_6

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 3 “Ordering information”; corrected temperature range for LPC2104FBD48/00,

LPC2105FBD48/00.

•Parts LPC2104FBD48/01, LPC2105FBD48/01, LPC2106BBD48, LPC2106FBD48/01,

and LPC2106FHN48/01 added.

•Description of /01 features added.

•LPC2104/2105/2106/01 power consumption measurements added.

•Maximum frequency fosc for external oscillator and external crystal updated.

•Figure 12 “External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)”

updated.

•Condition for IOHS and IOLS updated in Table 9 “Static characteristics”.

LPC2104_2105_2106_6 20060725 Product data sheet - LPC2104_2105_2106-05

LPC2104_2105_2106-05 20041222 Product data - LPC2104_2105_2106-04

LPC2104_2105_2106-04 20040205 Product data - LPC2104_2105_2106-03

LPC2104_2105_2106-03 20031007 Product data - LPC2104_2105_2106-02

LPC2104_2105_2106-02 20030611 Product data - LPC2104_2105_2106-01

LPC2104_2105_2106-01 20030425 Product data - -

Product data sheet Rev. 07 — 20 June 2008 40 of 41

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

13. Legal information

13.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

13.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

14. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors LPC2104/2105/2106

Single-chip 32-bit microcontrollers

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 20 June 2008

Document identifier: LPC2104_2105_2106_7

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

15. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 New features implemented in

LPC2104/2105/2106/01 devices. . . . . . . . . . . . 1

2.2 Key common features. . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Functional description . . . . . . . . . . . . . . . . . . 10

6.1 Architectural overview. . . . . . . . . . . . . . . . . . . 10

6.2 On-chip ﬂash program memory . . . . . . . . . . . 10

6.3 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 10

6.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12

6.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12

6.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 13

6.7 Pin function select register 0 (PINSEL0 -

0xE002 C000). . . . . . . . . . . . . . . . . . . . . . . . . 13

6.8 Pin function select register 1 (PINSEL1 -

0xE002 C004). . . . . . . . . . . . . . . . . . . . . . . . . 15

6.9 General purpose parallel I/O. . . . . . . . . . . . . . 16

6.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.9.2 Features added with the Fast GPIO set of

registers available on LPC2104/2105/2106/01

only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.10 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.10.2 UART features available in

LPC2104/2105/2106/01 only . . . . . . . . . . . . . 17

6.11 I2C-bus serial I/O controller . . . . . . . . . . . . . . 17

6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.12 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 18

6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.12.2 Features available in LPC2104/2105/2106/01

only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.13 SSP controller (LPC2104/2015/2106/01 only) 18

6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.14 General purpose timers . . . . . . . . . . . . . . . . . 18

6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.14.2 Features available in LPC2104/2105/2106/01

only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.15 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 19

6.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.16 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . 20

6.16.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.17 Pulse width modulator . . . . . . . . . . . . . . . . . . 20

6.17.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18 System control . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 21

6.18.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 22

6.18.4 Code security (Code Read Protection - CRP) 22

6.18.5 External interrupt inputs. . . . . . . . . . . . . . . . . 23

6.18.6 Memory mapping control . . . . . . . . . . . . . . . . 23

6.18.7 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.18.8 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.19 Emulation and debugging. . . . . . . . . . . . . . . . 24

6.19.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 24

6.19.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 24

6.19.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Static characteristics . . . . . . . . . . . . . . . . . . . 27

8.1 Power consumption measurements for

LPC2104/2105/2106/01. . . . . . . . . . . . . . . . . 29

9 Dynamic characteristics. . . . . . . . . . . . . . . . . 34

9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36

11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 39

13 Legal information . . . . . . . . . . . . . . . . . . . . . . 40

13.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 40

13.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 40

13.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40

14 Contact information . . . . . . . . . . . . . . . . . . . . 40

15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41