SHARP [SPEC No. | ELOQ5177 | ISSUE: June 12 1997 SPECIFICATIONS Product Type 8M Flash Memory LH28F800SGHB-L10 Model No. (LHF 80G14) *%This specifications contains 48 pages including the cover and appendix. If you have any objections, please contact us before issuing purchasing order. CUSTOMERS ACCEPTANCE DATE: BY: eA, BY: _. noaher S. TANAKA Dept. General Manager REVIEWED BY: PREPARED BY: nd. Jt Ne Tomort. Flash Memory Engineering Dept. 2 Tenri Integrated Circuits Development Group SHARP CORPORATIONSHARP NOTICE Wi This publication is the proprietary product of Sharp and is copyrighted, with all rights reserved. Under the copy- right laws, no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical for any purpose, in whole or in part, without the express written permission of Sharp. Express written permission is also required before any use of this publication may be made by a third party. Ii The application circuit examples in this publication are provided to explain the representative applications of Sharp devices and are not intended to guarantee any circuit design or permit any industrial property right or other rights to be executed. Sharp takes no responsibility for any problems related to any industrial property right or a third party resulting from the use of Sharp's devices, except for those resulting directly from device manufacturing processes. . ll in the absence of confirmation by device specification sheets, Sharp takes no responsibility for any defects that occur in equipment using any of Sharp's devices, shown in catalogs, data books, etc. Contact Sharp in order to obtain the latest device specifications sheets before using any Sharp device. @ Sharp reserves the right to make changes in the specifications, characteristics, data, materials, structures and other contents described herein at any time without notice in order to improve design or reliability. Contact Sharp in order to obtain the latest specification sheets before using any Sharp device. Manufacturing locations are also subject to change without notice. Mi Observe the following points when using any device in this publication. Sharp takes no responsibility for damage caused by improper use of devices. @ The devices in this publication are designed for use in general electronic equipment designs, such as : * Personal computers Office automation * Telecommunication equipment (except for trunk lines) Test and measurement equipment Industrial control * Audio visual and multimedia equipment Consumer electronics @ The appropriate design measures should be taken to ensure reliability and safety when Sharp devices are used for equipment, such as : : * Main frame computers * Transportation control and safety equipment (i.e., aircraft, trains, automobiles, etc.) * Traffic signal Gas leakage sensor breakers * Alarm equipment Various safety devices etc. @ Sharp devices shall not be used for equipment that requires an extremely high level of reliability, such as: * Military and aerospace applications * Telecommunication equipment (trunk lines) * Nuclear power control equipment * Medical equipment for life support Ml Contact a Sharp representative, in advance, when intending to use Sharp devices for any "Specific" applications other than those recommended by Sharp. i Contact and consult with a Sharp representative if there are any questions about the contents of this publication.SHARP LHF80G14 1 CONTENTS PAGE PAGE FEATURES. ...........cccccsecseeseceeeseeeeseeseenascoesesseeessecesenes 2 5.0 DESIGN CONSIDERATIONS ...............0....-e 24 5.1 Three-Line Output Control ...........:cececceseee 24 1.0 INTRODUCTION ounces secesssseseceeensetentenee 3 5.2 RY/BY# and Block Erase, Word Write and 1.1 New Features .00.... cc ceecceeeseesseenseessenees 3 Lock-Bit Configuration Polling 0.0.00... 24 1.2 Product OVErview ......... ee eccessesesssssseesensceeee 3 5.3 Power Supply Decoupling ............csssceeees 24 5.4 V,, Trace on Printed Circuit Boards .......... 24 2.0 PRINCIPLES OF OPERATION ..........::ccccecscee 7 5.5 Voc Vep RP# Transitions 0... eecsseeeeenes 24 2.1 Data Protection ...........cccsscseecccsssceccceeeerseseeees 7 5.6 Power-Up/Down Protection ......... cess 24 5.7 Power Dissipation ........ ec ccecsesseseeeeeseeeeee 25 3.0 BUS OPERATION 0.0... ee scssccesseeeeeceneennecee 8 3.1 REA ieee ccceceesceseeeeceeeeereseeenseeeeseseaeecnsaenseeens 8 6.0 ELECTRICAL SPECIFICATIONS ................... 26 3.2 Output Disable oe cececreesseesecseeeeeees 8 6.1 Absolute Maximum Ratings ........... cece 26 3.3 Standby .......... Leacenuaecerseseeeceneeessneceueneneuensesese 8 6.2 Operating Conditions ...........cseceseereereeenes 26 3.4 Deep Power-DOwn 0.0... ceeseseeessereeaseenes 8 6.2.1 Capacitance .........cescsescreeesssseresereerene 26 3.5 Read Identifier Codes occ cscecceseeceeseeeeneee 9 6.2.2 AC Input/Output Test Conditions......... 27 3.6 Wit oo. ec eeececeeeeeecenceeneeesseuessstseteeeseess 1. 9 6.2.3 DC Characteristics 0.0... eee seeeneeeeeeees 28 6.2.4 AC Characteristics - Read Only 4.0 COMMAND DEFINITIONS ...............:-eesecesseetees 9 OPE rations ..........cceeeecceeesseseretesersreeees 30 4.1 Read Array COMMANA .........ccccceceeserreeeeseee 12 6.2.5 AC Characteristics for WE# - Controlled 4.2 Read Identifier Codes Command .............. 12 Write Operations ...........ceceseeeeeereeeees 33 4.3 Read Status Register Command............... 12 6.2.6 AC Characteristics for CE# - Controlled 4.4 Clear Status Register Command............... 12 Write Operations .......s.seceeseseenesseneeeeens 36 4.5 Block Erase Comma ..........c eeecseeeeeveneeees 12 6.2.7 Reset Operations... ecsesssesseeeeeees 39 4.6 Word Write Command .........-.cccscceseseeeeee 13 6.2.8 Block Erase, Word Write and Lock-Bit 4.7 Block Erase Suspend Command .............. 13 Configuration Performance ...........06 40 4.8 Word Write Suspend Command.............. 13 4.9 Set Block and Permanent Lock-Bit 7.0 PACKAGE AND PACKING COMMANAS .........eescececesseeeeeeseseseseeescesseneens 14 SPECIFICATIONS ......0....... ee ccessseceeessenseeeensens 42 4.10 Clear Block Lock-Bits Command............. 14SHARP LHF80G14 LH28F800SGHB-L10 (LHF80G14) 8M (512Kbit X 16) SmartVoltage Flash Memory FEATURES SmartVoltage Technology * 3.0V (2.7V min.) or 5V V,, > 3.0V (2.7V min.), 5V or 12V V,, High-Performance * 100 ns (5V V,,) Read Access Time * 120 ns (2.7V V,.) Read Access Time Enhanced Automated Suspend Options + Ward Write Suspend to Read * Block Erase Suspend to Word Write * Block Erase Suspend to Read Enhanced Data Protection Features - Absolute Protection with V,, = GND + Flexible Block Locking High-Density Symmetrically Blocked . Architecture Sixteen 32k-word Erasable Blocks Extended Cycling Capability 100,000 Block Erase Cycles 1.6 Million Block Erase Cycles/Device Low Power Management Deep Power-Down Mode Automatic Power Savings Mode Decreases |, in Static Mode Automated Word Write and Block Erase Command User Interface : Status Register * Block Erase/Write Lockout during Power Transitions M@ ETOX V Nonvolatile Flash Technology Mi Chip Size Packaging . + 48-Ball CSP M@ Not designed or rated as radiation hardened HM SRAM-Compatible Write Interface SHARPs LH28F800SGHB-L10 Flash memory with SmartVoltage technology is a high-density, low-cost, nonvola- tile, read/write storage solution for a wide range of applications. LH28F800SGHB-L10 can operate at V., = 2.7V and V,,, = 2.7V. Its low voltage operation capability realize longer battery life and suits for cellular phone application. Its symmetrically-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800SGHB-L10 offers three leveis of protection: absolute protection with V,, at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F800SGHB-L10 is manufactured on SHARPs 0.4 um ETOX V process technology. It comes in indus- try-standard packages: the 48-bail CSP ideal for board constrained applications. * ETOX is a trademark of Intel Corporation.SHARP LHF80G14 3 1.0 INTRODUCTION This datasheet contains LH28F800SGHB-L10 specifi- cations. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organiza- tion and functionality. Section 6 covers electrical specifications. 1.1 New Features Key enhancements of LH28F800SGHB-L10 SmartVoltage Flash memory are: + SmartVoltage Technology + Enhanced Suspend Capabilities * In-System Block Locking * Permanent Lock Capability Please note following important differences: * Vopi, Nas been lowered to 1.5V to support 3.3V and 5V block erase, word write, and lock-bit configuration operations. Designs that switch V,, off during read operations should make sure that the V,, voltage transitions to GND. * To take advantage of SmartVoltage technology, allow V.,. connection to 3.3V (2.7V min.) or $V. * Once set the permanent lock bit, the blocks which have been set block lock-bit can not be erased, written forever. 1.2 Product Overview The LH28F800SGHB-L10 is a high-performance 8- Mbit SmartVoitage Flash memory organized as 512 Kword of 16 bits. The 512 Kword of data is arranged in sixteen 32-Kword blocks which are individually eras- able, lockable, and unlockable in-system. The memory map is shown in Figure 3. SmartVoltage technology provides a choice of V,, and V,,, combinations, as shown in Table 1, to meet system performance and power expectations. 3.3V V._ consumes approximately one-fifth the power of 5V Vg: But, 5V V,, provides the highest read perfor- mance. V,, at 3.3V and SV eliminates the need for a separate 12V converter, while V,,-= 12V maximizes block erase and word write performance. In addition to flexible erase and program voltages, the dedicated V,p pin gives complete data protection when V,, < PPLK Table 1. V.. and V,, Voltage Combinations Offered by SmartVoltage Technology Vcc Voltage Vee Voitage 3.3V0 3.3V2), 5V, 12V 5V 5V, 12V NOTES: 1. Block erase, word write and lock-bit configuration operations with V., < 2.7V are not supported. 2. Block erase, word write and lock-bit configuration operations with V,, < 2.7V are not supported. Internal V.. and V,, detection circuitry automatically configures the device for optimized read and write op- erations. A command User Interface (CUI) serves as the inter- face between the system processor and internal op- eration of the device. A valid command sequence writ- ten to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timing necessary for biock erase, word write, and lock-bit configuration operations. A block erase operation erases one of the device's 32- Kword blocks typically within 1.2 second (5V V,,, 12V Vp) independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in word increments typically within 7.5 us (5V V.,, 12V V,,). Word write suspend mode enables the system to read data or ex- ecute code from any other flash memory array loca- tion. The selected biock can be locked or unlocked individualy by the combination of sixteen block lock bits and the RP# or WP#. Block erase or word write must not be carried out by setting block lock bits and setting WP# to Low and RP# to V,,. Even if WP# is High state or RP# is set to V,,,, block erase and word write to locked biocks is prohibited by setting perma- nent lock bit. The status register or RY/BY# indicates when the WSM's block erase, word write, or lock-bit configura- tion operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signai of status (versus software poiling) and status masking (interrupt masking for background block erase, for ex- ampie). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is perform-SHARP LHF80G14 ing a block erase, word write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and word write is inactive), word write is suspended, or the de- vice is in deep power-down mode. The access time is 100 ns (t,,,,) over the commercial temperature range (-40C to +85C) and V,,, supply voltage range of 4.5V-5.5V. At lower V.,. voltages, the access times are 100 ns (3.0V-3.6V), 120 ns (2.7V- 3.0V). : The Automatic Power Saving (APS) feature substan- tially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical I,,, current is 1 mA at 5V V.,. When CE# and RP# pins are at V,,, the |,, CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which mini- mizes power consumption and provides write protec- tion during reset. A reset time (t,,,,,) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (t,,,.,) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 48-ball CSP (Chip Size Package), Pinouts are shown in Figures 2.SHARP LHF80G14 10 ENTIFIER Voc REGISTER cee Wee OUTPUT MULTIPLEXER DATA REGISTER STATUS REGISTER DATA Ree COMPALATOA RYBY# Vep Y-GATING WRITE STATE MACHINE 32 KWORD Veo 416 BLOCKS < ano Figure 1. Block Diagram LH28F800SGHB-L10 48-BALL CSP STANDARD PINOUT 8mm x 8mm TOP VIEW ) @OOO @OOOOO> @QOO@O@&> O&OSO@O: OOOO @OOO &.s @OOOLHO> Figure 2. 48-Ball CSP Standard Pinout Configuration _SHARP LHF80G14 Table 2. Pin Descriptions Symbol Type Name and Function Ag- Aug INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. INPUT/OUTPUT DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; dutputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CE# INPUT CHIP ENABLE: Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RP# INPUT RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP#-high enables normai operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. RP# at V4, allows to set permanent lock-bit. Block erase, word write, or lock-bit configuration with Vj, < RP# < V4, produce spurious resuits and should not be attempted. OE# INPUT OUTPUT ENABLE: Gates the device's outputs during a read cycle. WE# INPUT WRITE ENABLE: Controis writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# puise. WP# INPUT WRITE PROTECT: Master control for block locking. When V,,, locked blocks cannot be erased and programmed, and block lock-bits can not be set and reset. RY/BY# OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSN is performing an intern! operation (block erase, word write, or lock-bit configuration). RY/BY#-high indicates that the WSM is ready for new commands, block erase is suspended, and word write is inactive, word write is suspended, or the device is in deep power-down mode. RY/BY?# is always active and does not float when the chip is deselected or data outputs are disabied. SUPPLY BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing words, or configuration lock-bits. With Vpp < Vep_q, Memory contents cannot be altered. Block erase, word write, and lock-bit configuration with an invalid Vpp (see DC Characteristics) produce spurious results and should not be attempted. SUPPLY DEVICE POWER SUPPLY: Internal detection configured the device for 3.3V or 5V operation. To switch from one voltage to another, ramp Voc down to GND and then ramp Vcc to the new voltage. Do not float any power pins.With Voc < Vig, all write attempts to the flash memory are inhibited. Device operations at invalid Vgc voltage (see DC Characteristics) produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internal connected; it may be driven or floated.SHARP LHF80G14 7 2.0 PRINCIPLES OF OPERATION 7FFFF The LH28F800SGHB-L10 SmartVoitage Flash 78000 32 Kword Block 's memory includes an on-chip WSM to manage block TIFFF 32 Kword Block 44 erase, word write, and lock-bit configuration functions. eee It allows for 100% TTL-level control inputs, fixed 68000 32 Kword Block 13 power supplies during block erasure, word write, and 67FFF lock-bit configuration, and minimal processor over- 60000 32 Kword Block 12 head with RAM-like interface timings. sone. 42 Kword Block 1 After initial device power-up or return from deep swoog 32 Kword Block 10 power-down mode (see Bus Operations), the device 4FFFF 32 Kword Block 9 defaults to read array mode. Manipulation of external 48000 memory control pins allow array read, standby, and A7FFF 32 Kword Block 8 output disabie operations. seer 38000 32 Kword Block 7 Status register and identifier codes can be accessed 37FFF 32 Kword Block 5 through the CUI independent of the V,, voltage. High 30000 voltage on V,, enables successful block erasure, arrre 32 Kword Block 5 word writing, and lock-bit configuration. All functions eee associated with altering memory contents block 20000 32 Kword Block 4 erase, word write, lock-bit configuration, status, and 1FFFF 32 Kword Block 3 identifier codes are accessed via the CUI and veri- 18000 fied through the status register. non 32 Kword Block 2 OFFFF Commands are written using standard microproces- 08000 32 Kword Block ' sor write timings. The CU! contents serve as input to O7FFF 32 Kword Block 0 the WSM, which controls the block erase, word write, o0000 and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, in- ternal verification, and margining of data. Addresses and data are internally latch during write cycles. Writ- ing the appropriate command outputs array data, ac- cesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase, word write, and lock-bit configuration can be stored in any block. This code is copied to and ex- ecuted from system RAM during flash memory up- dates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location. Figure 3. Memory Map 2.1 Data Protection Depending on the application, the system designer may choose to make the V,, power supply switchable (available only when memory block erases, word writes, or lock-bit configurations are required) or hardwired to V,o44/5- The device accommodates ei- ther design practice and encourages optimization of the processor-memory interface. When V,, S$ Vooi,. Memory contents cannot be altered. The CUI, with two-step block erase, word write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to V,,. All write functions are dis- abled when V,,, is below the write lockout voltage V,., or when RP# is at V,. The devices block locking ca- pability provides additional protection from inadvert- ent code or data alteration by gating erase and word write operations.SHARP LHF80G14 8 3.0 BUS OPERATION The local CPU reads and writes flash memory in-sys- tem. All bus cycles to or from the flash memory con- form to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the V,, volt- age. RP# can be at either V,,, or V,,,,. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automaticaily resets to read array mode. Five control pins dictate the data flow in and out of the component: CE#, OE#, WE#, RP# and WP#. CE# and OE# must be driven active to obtain data at the out- puts. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ,-DQ,,) control and when active drives the selected memory data onto the 1/O bus. WE# must be at V,, and RP# must be at V,, or V,,,,. Figure 15 illustrates read cycle. 3.2 Output Disable With OE# at a logic-high level (V,,,), the device outputs are disabled. Output pins DQ,-DQ,, are placed in a high-impedance state. 3.3 Standby CE# at a logic-high level (V,,) places the device in standby mode which substantially reduces device power consumption. DQ,-DQ,, outputs are placed ina high-impedance state independent of OE#. If dese- lected during block erase, word write, or lock-bit con- figuration, the device continues functioning, and con- suming active power until the operation completes. 3.4 Deep Power-Down RP# at V, initiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off ail internal circuits. RP# must be held low for a minimum of 100 ns. Time t,,,,, is required after re- turn from power-down until initial memory access out- puts are valid. After this wake-up interval, normal op- eration is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, word write, or lock-bit configura- tion modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tL. is required after RP# goes to logic-high (V,,) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Au- tomated flash memories provide status information. when accessed during block erase, word write, or lock-bit configuration modes. !f a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be pro- viding status information instead of array data. SHARP's flash memories allow proper CPU initializa- tion following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.SHARP LHF80G14 9 3.5 Read Identifier Codes The read identifier codes operation outputs the manu- facturer code, device code, block lock configuration codes for each block, and the permanent lock configu- ration code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and permanent lock configuration codes identify tocked and unlocked blocks and permanent lock-bit setting. : TFFFF Reserved for 78004 Future Implementation 78003 |}. 78002 Block 15 Lock Configuration Code 78001 | _ Reserved for Future implementation 78000 | s Block 15 (Blocks 2 through 14) OFFFF | Reserved for ogsoo4 | Future Implementation 08003 08002 Block 1 Lock Configuration Code 08001 Reserved for Future implementation 08000 Block 1 O7FFF Reserved for Future Implementation 00004 | 00003 Permanent Lock Configuration Code 00002 Block 0 Lock Configuration Code 00001 Device Code 00000 Manufacturer Code Block 0 Figure 4. Device Identifier Code Memory Map 3.6 Write Writing commands to the CUI enable reading of de- vice data and identifier codes. They also control in- spection and clearing of the status register. The Block Erase command requires appropriate com- mand data and an address within the block to be erased. The Word Write command requires the com- mand and address of the location to be written. Set Permanent and Block Lock-Bit commands require the command and address within the device (Permanent Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory lo- cation. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write tim- ings are used. Figures 16 and 17 illustrate WE# and CE# controlled write operations. 4.0 COMMAND DEFINITIONS When the V,., < Vao.,, Read operations from the status register, identifier codes, or blocks are enabled. Plac- ING Voputa3 ON Vep enables successful block erase, word write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these com- mands.SHARP LHF80G14 10 Table 3. Bus Operations Mode Notes RP# CE# OE# WE# |Address| Vpp DQo1s | RY/BY# Read 1,2, Vir or Vit Vit Vint x X Dout 4 3,8 Vir Output Disable 3 Vin or Vie Vin Vir x X High Z X VHH : Standby 3 Vin or Vin xX xX x xX High Z xX VHH Deep Power-Down 4 Vit x X x Xx xX High Z Vor Read Identifier Codes 8 Vin or Vit Vin Vin See x Note 5 Vor ViH Figure 4 , Write 3,6, Vin or Vit Vin Vic Xx xX Din X 7,8 VuH NOTES: 1. Refer to DC Characteristics. When V,, < V memory contents can be read, but not altered. pp = PPLK 2. X can be V, or V,, for control pins and addresses, and Vee, OF Veeuioa fOr Vap- See DC Characteristics for Veg, and V "voltages. PPH1/2/3 3. RY/BY#is V,, when the WSM is executing internal block erase, word write, or lock-bit configuration algorithms. Itis V.,, during when the WSM is not busy, in block erase suspend mode (with word write inactive), word write suspend mode, or deep power-down mode. 4. RP# at GND + 0.2V ensures the lowest deep power-down current. 5. See Section 4.2 for read identifier code data. 6. V,, < RP# < V,,, produce spurious results and should not be attempted. 7. Refer to Table 4 for valid D,, during a write operation. 8. Never hold OE# low and WE# low at the same timing.SHARP LHF80G14 1 Table 4. Command Definitions Bus Cycles First Bus Cycle Second Bus Cycle Command Reqd NS Onent) | Addr | Data | Oper) | Addr? | Data Read Array/Reset 1 Write x FFH Read Identifier Codes 22 4 Write x 90H Read IA ID Read Status Register 2 : Write Xx 70H Read X SRD Clear Status Register 1 Write X 50H Block Erase 2 5 Write BA 20H Write BA DOH Word Write 2 5,6| Write WA 40H or 10H | Write WA WD Block Erase and Word Write Suspend 1 5 Write x BOH Block Erase and Word Write Resume 1 5 Write x DOH Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H Set Permanent Lock-Bit 2 7 Write x 60H Write x FiH Clear Block Lock-Bit 2 8 Write x 60H Write x DOH NOTES: 1. Bus operations are defined in Table 3. 2. X = Any valid address within the device. IA = Identifier Code Address: see Figure 4. BA = Address within the block being erased or locked. WA = Address of memory location to be written. 3. SRD = Data read from status register. See Table 7 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). iD = Data read from identifier codes. 4. Following the Read Identifier Codes command, read operations access manufacture, device, block lock, and permanent lock codes. See Section 4.2 for read identifier code data. 5. If the block is locked, WP# must be at V,, or RP# must be at V,,,, to enable block erase or word write operations. Attempts to issue a block erase or word write to a locked biock while WP# is V,, or RP# is V,,, 6. Either 40H or 10H are recognized by the WSM as the word write setup. 7. If the permanent lock-bit is set, WP# must be at V,, or RP# must be at V,,, to set a block lock-bit. RP# must be at V,,, to set the permanent lock-bit. If the permanent lock-bit is set, a block lock-bit cannot be set. Once the permanent lock-bit is set, permanent lock-bit reset is unable. 8. If the permanent lock-bit is set, clear block lock-bits operation is unable. The clear block lock-bits operation simultaneously clears all block lock-bits. If the permanent lock-bit is not set, the Clear Block Lock-Bits command can be done while WP# is V,,, or RP# is V,,.. 9. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.SHARP LHF80G14 12 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, word write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word Write Suspend command. The Read Array command functions independently of the Vp Voltage and RP# can be V,, or V,,. 4.2 Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the com- mand write, read cycles from addresses shown in Fig- ure 4 retrieve the manufacture, device, block lock con- figuration and permanent lock configuration codes (see Table 5 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the V,, voltage and RP# can be V,, or V,,,,. Following the Read Identi- fier Codes command, the following information can be read: Table 5. Identifier Codes Code Address Data Manufacture Code 00Q000H 0OBOH Device Code 00001H 0050H Block Lock Configuration XX002H() -Unlocked DQo=0 Locked DQo=1 -Reserved for future enhancement Permanent Lock Configuration | OO003H Unlocked DQo=0 Locked DQo=1 Reserved for future enhancement DQ1-15 NOTES: 1. X selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map. 2. Block lock status and permanent lock status are output by DQ,. DQ,-DQ,, are reserved for future enhancement. 4.3. Read Status Register Command The status register may be read to determine when a biock erase, word write, or lock-bit configuration is complete and whether the operation completed suc- cessfully. It may be read at any time by writing the Read Status Register command. After writing this command, ail subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to V,,, before further reads to update the status register latch. The Read Status Register command functions independently of the V,, voltage. RP# can be V,,, or V,,.. 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3, and SR.1 are set to 1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate . various failure conditions (see Table 7). By allowing system software to reset these bits, several opera- tions (such as cumulatively erasing or locking muitiple blocks or writing several words in sequence) may be performed. The status register may be polled to deter- mine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied V,, voltage. RP# can be V,, or V,,,. This command is not functional during block erase or word write suspend modes. 4.5 Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first writ- ten, followed by an block erase confirm. This com- mand sequence requires appropriate sequencing and an address within the block to be erased (erase changes all biock data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect biock erase completion by ana- lyzing the output data of the RY/BY# pin or status reg- ister bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is de- tected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new com- mand is issued.SHARP LHF80G14 13 This two-step command sequence of set-up followed by execution ensures that block contents are not acci- dentally erased. An invalid Block Erase command se- quence will result in both status register bits SR.4 and SR.5 being set to1. Also, reliable block erasure can only occur when Vo. = Veciag ANd Veg = Vopuia: In the absence of this high voltage, block contents are pro- tected against erasure. If block erase is attempted while V.. < Veo, SR.3 and SR.5 will be set to 1. Suc- cessful biock erase requires that the corresponding block lock-bit be cleared or, if set, that WP# = V, or RP# = V,,,. If block erase is attempted when the corre- sponding block lock-bit is set and WP# = V, and RP# = V,,, SR.1 and SR.5 will be set to 1. Once perma- nent lock-bit is set, the blocks which have been set block lock-bit are unable to erase forever. Block erase operations with V,, < RP# < V,,, produce spurious re- sults and should not be attempted. 4.6 Word Write Command Word write is executed by a two-cycle command se- quence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that speci- fies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the word write and write verify algorithms internally. After the word write sequence is written, the device auto- matically outputs status register data when read (see Figure 6). The CPU can detect the completion of the word write event by analyzing the RY/BY# pin or sta- tus register bit SR.7. When word write is complete, status register bit SR.4 should be checked. If word write error is detected, the status register should be cleared. The internal WSM verify only detects errors for 1s that do not success- fully write to Os. The CUI remains in read status reg- ister mode until it receives another command. Reliable word writes can only occur when V.. = Vegi, and Vos = Veuve: In the absence of this high voltage, memory contents are protected against word writes. If word write is attempted while V,, < Vip... Status regis- ter bits SR.3 and SR.4 will be set to 1. Successful word write requires that the corresponding block lock- bit be cleared or, if set, that WP# = V,,or RP# = V,,,. If word write is attempted when the corresponding block lock-bit is set and WP# = V, and RP# = V,,, SR.1 and SR.4 will be set to 1. Once permanent lock-bit is set, the blocks which have been set block lock-bit are un- able ta write forever. Word write operations with V,, < RP# < V,,, produce spurious results and should not be attempted. 4.7 Block Erase Suspend Command The Block Erase Suspend command allows block- erase interruption to read or word-write data in an- other block of memory. Once the biock-erase process starts, writing the Block Erase Suspend command re- quests that the WSM suspend the biock erase se- quence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Poiling Status register bits SR.7 and SR.6 can determine when the biock erase operation has been suspended (both will be set to 1"). RY/BY# will also transition to Von Specification t,.,. defines the block erase sus- pend latency. At this point, a Read Array command can be written to read data from blocks other than that which is sus- pended. A Word Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Word Write Suspend com- mand (see Section 4.8), a word write operation can also be suspended. During a word write operation with block erase suspended, status register bit SR.7 will return to 0 and the RY/BY# output will transition to Vo,. However, SR.6 will remain 1 to indicate biock erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to Vo: After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 7). V,, must remain at Vega (the same V,, level used for block erase) while block erase is suspended. RP# must also remain at V,,, or Vy (the same RP# level used for block erase). WP# must also remain at V,, or V,,, (the same WP# level used for block erase). Block erase cannot resume un- til word write operations initiated during block erase suspend have completed. 4.8 Word Write Suspend Command The Word Write Suspend command allows word write interruption to read data in other flash memory loca- tions. Once the word write process starts, writing the Word Write Suspend command requests that the WSM suspend the word write sequence at a predeter- mined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Poiling status reg- ister bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be setSHARP LHF80G14 14 to 1"). RY/BY# will also transition to V,,,. Specification twunn, defines the word write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is sus- pended. The only other valid commands while word write is suspended are Read Status Register and Word Write Resume. After Word Write Resume com- mand is written to the flash memory, the WSM will continue the word write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V.,. After the Word Write Resume com- mand is written, the device automatically outputs sta- tus register data when read (see Figure 8). V,, must remain at Vo, (the same V,, level used for word write) while in word write suspend mode. RP# must also remain at V,, or V,,, (the same RP# level used for word write). WP# must also remain at V, or V,, (the same WP# level used for word write). 4.9 Set Block and Permanent Lock-Bit Commands The combination of the software command sequence and hardware WP#, RP# pin provides most flexible block lock (write protection) capability. The word write/ block erase operation is restricted by the status of block lock-bit, WP# pin, RP# pin and permanent lock- bit. The status of WP# pin, RP# pin and permanent lock-bit restricts the set block bit. When the permanent lock-bit has not been set, and when WP# = V,,, or RP# = V,, the block lock bit can be set with the status of the RP#pin. When RP# = V,,,,, the permanent lock-bit can be set with the permanent lock-bit set command. After the the permanent lock-bit has been set, the write/erase operation to the block lock bit can never be accepted. Please refer to the Table 6 for the hard- ware and the software write protection. Set block lock-bit and permanent lock-bit are ex- ecuted by a two-cycle command sequence. The set block or permanent lock-bit setup along with appropri- ate block or device address is written followed by ei- ther the set block fock-bit confirm (and an address within the block to be locked) or the set permanent lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the se- quence is written, the device automatically outputs status register data when read (see Figure 9). The CPU can detect the completion of the set lock-bit event by analyzing the RY/BY# pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is de- tected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execu- tion ensures that lock-bits are not accidentally set. An invalid Set Block or Permanent Lock-Bit command will result in status register bits SR.4 and SR.5 being set to 1. Also, reliable operations occur only when V_,,. = Vecuer 2d Vee = Vepitg: In the absence of this high voltage, lock-bit contents are protected against alter- ation. A successful set block lock-bit operation requires that the permanent lock-bit be cleared and WP# = V,,, or RP# = V,,,,. If it is attempted with the permanent lock- bit set, SR.1 and SR.4 will be set to 1 and the opera- tion will fail. Set block lock-bit operations while V,,, < RP# < V,,, produce spurious results and should not be attempted. A successful set permanent lock-bit opera- tion requires that RP# = V,,.. If it is attempted with RP# = V,,, SR.1 and SR.4 will be set to 1 and the opera- tion will fail. Set permanent lock-bit operations with V,,, < RP# < V,,, produce spurious results and should not be attempted. 4.10 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the permanent lock-bit not set and WP# = V,, or RP# = V,,,, block lock-bits can be cleared using the Clear Block Lock- Bits command. If the permanent lock-bit is set, clear block lock-bits operation is unable. See Table 6 fora summary of hardware and software write protection options. Clear block lock-bits option is executed by a two-cycle command sequence. A clear block lock-bits setup is first written. After the command is written, the device automatically outputs status register data when read (see Figure 10). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/ BY# pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until an- other command is issued. , This two-step sequence of set-up followed by execu- tion ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to 1. Also, a reliable clear block lock- bits operation can only occur when V.. = Veer and Vee = Veer: In a clear Block lock-bits operation is atternpted while V,, < V SR.3 and SA.5 will be set pp = pei?SHARP LHF80G14 15 to 1. In the absence of this high voitage, the block lock-bits content are protected against alteration. A successful clear block lock-bits operation requires that the permanent lock-bit is not set and WP# = V,, or RP# = V,,, If it is attempted with the permanent lock-bit set or WP# = V, and RP# = V,,, SR.1 and SA.5 will be set to 1 and the operation will fail. A clear block lock-bits operation with V,,, < RP# < V,,, produce spurious re- sults and should not be attempted. if a clear block lock-bits operation is aborted due to Vpp OF Ve, transitioning out of valid range or WP# or RP# active transition, block !ock-bit values are left in an undetermined state. A repeat of clear block lock- bits is required to initialize block lock-bit contents to known values. Once the permanent lock-bit is set, it cannot be cleared.SHARP LHF80G14 16 Table 6. Write Protection Alternatives Permanent Block Operation Lock-Bit Lock-Bit WP# RP# Effect X 0 Xx Vin Or VHH| Block Erase and Word Write Enabled Vin Vin or Vix Block Lock-Bit Override. . Block Erase and Word Write Enabled Word Write - - or 0 Vai Block Lock-Bit Override. Block Erase 1 Mi Block Erase and Word Write Enabled Vv Block is Locked. Iq Block Erase and Word Write Disabled 1 x X Permanent Lock-Bit is set. Block Erase and Word Write Disabled Vin Vin or VoH| Set Block Lock-Bit Enabled Set Block 0 x Vic VHH Set Block Lock-Bit Enabled Lock-Bit Vit Vin | Set Block Lock-Bit Disabled 1 x X Permanent Lock-Bit is set. Set Block Lock-Bit Disabled VHH Set Permanent Lock-Bit Enabled Set Permanent X x xX Lock-Bit Vin | Set Permanent Lock-Bit Disabled Vin Vin Or VHH| Clear Block Lock-Bits Enabled 0 Vit Vii Clear Block Lock-Bits Enabled Clear Biock x Lock-Bits Vit Vin | Clear Block Lock-Bits Disabled 1 X X Permanent Lock-Bit is set. Clear Bloek Lock-Bits DisabledSHARP LHF80G14 17 . Table 7. Status Register Definition [ wsms | ess _{| ECLBS | BWSLBS vpps [| Bwss | oPS | R 7 6 5 4 3 2 1 0 NOTES: SR.7= WRITE STATE MACHINE STATUS Check RY/BY# or SR.7 to determine block erase, word 1 = Ready write, or lock-bit configuration completion. SR.6-0 are 0 = Busy invalid while SR.7 = 0. SR.6= ERASE SUSPEND STATUS If both SR.5 and SR.4 are 1s after a block erase or lock-bit 1 = Block Erase Suspended configuration attempt, an improper command sequence 0 = Block Erase in Progress/Compieted was entered. SR.5= ERASE AND CLEAR LOCK-BITS SR.3 does not provide a continuous indication of V,, level. STATUS The WSM interrogates and indicates the V,, level only after 1 = Error in Block Erasure or Clear Lock-Bits Block Erase, Word Write, Set Block/Permanent Lock-Bit, or 0 = Successful Block Erase or Clear Lock-Bits Clear Block Lock-Bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when V,, = SR.4= WORD WRITE AND SET LOCK-BIT Vopetaa" STATUS 1 = Error in Word Write or Set SR.1 does not provide a continuous indication of permanent Permanent/Block Lock-Bit and block lock-bit values. The WSM interrogates the 0 = Successful Word Write or Set permanent lock-bit, block lock-bit, WP# and RP# only after Permanent/Block Lock-Bit Block Erase, Word Write, or Lock-Bit configuration . command sequences. It informs the system, depending on SR.3= V,, STATUS the attempted operation, if the block lock-bit is set, 1=V,, Low Detect, Operation Abort permanent lock-bit is set, and/or WP# is not V,,, RP# is not 0=V,, OK Viy Reading the block lock and permanent lock: configuration codes after writing the Read Identifier Codes SR.2= WORD WRITE SUSPEND STATUS command indicates permanent and block lock-bit status. 1 = Word Write Suspended 0 = Word Write in Progress/Completed SR.0 is reserved for futare use and should be masked out when polling the status register. SR.1= DEVICE PROTECT STATUS 1 = Permanent Lock-Bit, Block Lock-Bit and/or WP#/RP# Lock Detected, Operation Abort 0 = Unlock SR.0= RESERVED FOR FUTURE ENHANCEMENTSSHARP LHF80G14 18 Operation ommand Comments : Data=20H Write 20H, Write | Erase Setup | 4 14r=Within Block to be Erased Block Address Write Erase Data=DOH y Confirm Addr= Within Block to be Erased Write DOH, Block , Read Status Register Data Read Check SR.7 Status Register Standby 1=WSM Ready Suspend Block O=WSM Busy Erase Loop Repeat for subsequent block erasures. - Full status check can be done after each block erase or after a Block Erasg sequence of block erasures. Write FFH after the last operation to place device in read array mode. Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Bus Data (See Above) Operation Command Comments Check SR.3 Standby 1=Vpp Error Detect Vpp Range Error Check SR.1 1=Device Protect Detect Standby RP#=Vj,,, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Device Protect Error Standb Check SR.4,5 y Both 1=Command Sequence Error Standby Check SR.5 Command Sequence Error Block Erase Error Block Erase Successfui 1=Block Erase Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the Status Register before attempting retry or other error recovery. Figure 5. Automated Block Erase FlowchartSHARP LHF80G14 19 Start Bus Command Comments Operation en - Write Setup Data=40H Write 40H, Word Write | Addr=Location to Be Written Address . A Data= Data to Be Written v Write Word Write Addr=Location to Be Written Write Word Data Read Status Register Data Read Check SR.7 Status Register Standby 1=WSM Ready Suspend Word O=WSM Busy Write Loop Repeat for subsequent Word writes. SR full status check can be done after each word write, or after a sequence of word writes. Write FFH after the last word write operation to place device in read array mode. Full Status Check if Desired FULL STATUS CHECK PROCEDURE Read Status Registe Data (See Above) Vpp Range Error Word Write Error Word Write Successful Bus Operation Command Comments Cheek SR.3 Standby 1=Vpp Error Detect Check SR.1 1= Device Protect Detect Standby RP#=Vjy, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4 Standby 1= Data Write Error SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery. Figure 6. Automated Word Write FlowchartSHARP LHF80G14 Read Read Array Data Block Erase Completed Vv Write DOH Write FFH Block Erase Read Resumed Array Data 20 B Operation Command Comments . Erase Data=BOH Write = Write BOH Suspend Addr=X Status Register Data Y Read Addr=X Read Check SR.7 Status Register Standby 1=WSM Ready O=WSM Busy Check SR.6 Standby 1=Block Erase Suspended 0=Block Erase Completed Writ Erase Data=DOH rie Resume | Addr=X Figure 7. Block Erase Suspend/Resume FlowchartSHARP LHF80G14 21 Bus Operation Command Comments : Word Write | Data=BOH Write _ Write BOH Suspend | Addr=X Status Register Data v Read Addr=X Read Check SR.7 Status Register Standby 1=WSM Ready 0=WSM Busy Check SR.2 Standby 1=Word Write Suspended 0=Word Write Completed Write Read Array al mn Word Write Read Read Array locations other Completed than that being written 1 Word Write | Data= DOH Write Resume Addr=X Write FFH. v Read Array Data Done Reading YES Vv Write DOH Write FFH Word Write Resumed Read Array Data Figure 8. Word Write Suspend/Resume FlowchartSHARP LHF80G14 Bus Operation Command Comments Set Block/ ; Data=60H Write 60H, Write Permanent | aqdr=Block Address (Block), Block/Device Address; Lock-Bit Device Address (Permanent) : Setup Write Set Block/ Data =01H (Block), Write 01H/F1H, Permanent F1H (Permanent) Block/Device Address . Lock-Bit Addr= Block Address (Block), : Confirm Device Address (Permanent) Read Read Status Register Data Status Register Check SR.7 Standby 1=WSM Ready O=WSM Busy Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Full Status read ayray after the last lock-bit set operation to place device in Check if Desired , Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Bus Operation Command Comments Check SR.3 Standby 1=Vpp Error Detect Vpp Range Error Check SR.1 1= Device Protect Detect Standby RP#= Vin (Set Permanent Lock-Bit Operation) WP#=V)_ and RP#=Vj4 Device Protect Error or Permanent Lock-Bit is Set (Set Block Lock-Bit Operation) Check SR.4,5 Standby Both 1=Command Sequence Error Command Check SR.4 Sequence Error Standby 1=Set Lock-Bit Error . SR.5, SR.4, SR.3 and SA.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. Set Lock-Bit if error is detected, clear the Status Register before attempting Error retry or other error recovery. Set Lock-Bit Successful Figure 9. Set Block and Permanent Lock-Bit FlowchartSHARP Full Status Check if Desired Clear Block Lock-Bits Complete Read Status Registe Data (See Above) Clear Block Lock-Bits Successful Clear Block Lock-Bits FULL STATUS CHECK PROCEDURE Bus Operation Command Comments Check SR.3 Standby 1=Vpp Error Detect Check SR.1 Vpp Range Error Standb 1=Device Protect Detect nay WP#=Vj, and RP#=V),; or Permanent Lock-Bitis Set. Check SR.4,5 . Standby Both 1=Command Sequence Error Device Protect Error Check SR.5 ndb 5 Standby 1=Clear Block Lock-Bits Error SR.5, SR.4, SR.3 and SA.1 are only cleared by the Clear Status Command Register command. Sequence Error If error is detected, clear the Status Register before attempting : retry or other error recovery. Error LHF80G14 23 a | Operation ommand Comments Clear Block : Data=60H Write 60H Write Lock-Bits | agdr=x Setup Clear Block | pata=DOH Write Lock-Bits Addr=X Write DOH Contirm v Read Status Register Data Read . <_ Check SR.7 Status Register Standby 1=WSM Ready O=WSM Busy 0 Write FFH after the Clear Block Lock-Bits operation to place device in read array mode. 1 Figure 10. Clear Block Lock-Bits FlowchartSHARP LHF80G14 24 5.0 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control pro- vides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address de- coder should enable CE# while OE# should be con- nected to all memory devices and the systems READ# contro! line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to pre- vent unintended writes during system power transi- tions. POWERGOOD should also toggle during sys- tem reset. . 5.2 RY/BY# and Block Erase, Word Write, and Lock-Bit Configuration Polling RY/BY# is a full CMOS output that provides a hard- ware method of detecting block erase, word write and lock-bit configuration completion. It transitions low af- ter block erase, word write, or lock-bit configuration commands and returns to V,,, when the WSM has fin- ished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/ BY# is also V,,, when the device is in block erase sus- pend (with word write inactive), word write suspend or deep power-down modes. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are in- terested in three supply current issues; standby cur- rent levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device shouid have a 0.1 uF ceramic capacitor connected between its V,, and GND and between its V,, and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Addi- tionally, for every eight devices, a 4.7 pF electrolytic capacitor should be placed at the arrays power sup- ply connection between V., and GND. The bulk ca- pacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 V,, Trace on Printed Circuit Boards Updating flash memories that reside in the target sys- tem requires that the printed circuit board designer pay attention to the V,,, power supply trace. The V,, pin supplies the memory cell current for word writing and block erasing. Use similar trace widths and layout considerations given to the V,,, power bus. Adequate Vp Supply traces and decoupling will decrease V,, voltage spikes and overshoots. 5.5 Vics Vep AP# Transitions Block erase, word write and lock-bit configuration are not guaranteed if V,, falls outside of a valid Vu. range, V,, falls outside of a valid Voc... range, or RP# * V,,, or Vi. If Vpp error is detected, status register bit SR.3 is set to 1 along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to V,, during block erase, word write, or lock-bit configura- tion, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the de- vice will enter deep power-down. The aborted opera- tion may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transi- tions to V,, clear the status register. The CUI latches commands issued by system soft- ware and is not altered by V,, or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after Voc transitions below V,,,. After block erase, word write, or lock-bit configuration, even after V,, transitions down to V,,,,,, the CUI must be placed in read array mode via the Read Array com- mand if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against ac- cidental block erasure, word writing, or lock-bit con- figuration during power transitions. Upon power-up, the device is indifferent as to which power supply (V,, or V,,) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for V,, voltages above V,,,. when V,, is active. Since both WE# and CE# must be low for a command write, driving either to V,,, will inhibit writes. The CUIs two-SHARP LHF80G14 25 step command sequence architecture provides added level of protection against data alteration. in-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP# = V,, regardless of its control inputs state. 5.7 Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility in- creases usable battery life because data is retained when system power is removed. in addition, deep power-down mode ensures ex- tremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering RP# to V,, standby or sleep modes. If access is again needed, the devices can be read following the t,o, and touw. wake-up cycles required after RP# is first raised to V,,,. See AC Characteristics - Read Only and Write Op- erations and Figures 15, 16 and 17 for more informa- tion.SHARP LHF80G14 26 6.0 ELECTRICAL SPECIFICATIONS NOTICE: Revised information will be published . a when the product is available. Verify with your lo- 6.1 Absolute Maximum Ratings cal SHARP Sales office that you have the latest datasheet before finalizing a design. <Operating Temperature> Extended Temperature Products During Read, Block Erase, Word Write, *WARANING: Stressing the device beyond the Abso- and Lock-Bit Configuration ........ -40C to + 85C lute Maximum Ratings" may cause permanent dam- Temperature under Bias............... -40C to + 85C age. These are stress ratings only. Operation beyond <Storage Temperature> ................- - 65C to + 125C the Operating Conditions" is not recommended and <Voltage On Any Pin> extended exposure beyond the "Operating Condi- except V.,, Vop, and RP# .......... -2.0V to + 7.0V tions" may affect device reliability. Vog Supply Voltage ..............-+ -2.0V to + 7.0V V,p Update Voltage during NOTES: Block Erase, Word Write, and 1. Operating temperature is for commercial product Lock-Bit Configuration ........... -2.0V to + 14.0V 29) defined by this specification. RP# Voltage with Respect to 2. All specified voltages are with respect to GND. GND during Lock-Bit Minimum DC voltage is - 0.5V on input/output pins Configuration Operations...... -2.0V to + 14.0V 24) and - 0.2V on V,. and V,, pins. During transitions, <Output Short Circuit Current> .......... 100 mA ) this level may undershcot to - 2.0V for periods < 20 ns. Maximum DC voitage on input/output pins and Voc IS Veg + 0.5V which, during transitions, may overshoot to V.,, + 2.0V for periods < 20 ns. 3. Maximum DC voltage on V,, and RP# may overshoot to +14.0V for periods < 20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. . 6.2 Operating Conditions Temperature and V.,. Operating Conditions Symbol Parameter Notes Min. Max. Unit Test Condition Ta Operating Temperature -40 +85 c Ambient Temperature Extended Temperature Products: Vec1 Vcc Supply Voltage (2.7V-3.6V) 2.7 3.6 Vv Vec2 Vcc Supply Voltage (3.3V+0.3V) 3.0 3.6 V Vees Vcc Supply Voltage (5.0V+0.5V) 4.50 5.50 Vv 6.2.1 Capacitance T, = + 25C, f= 1 MHz Symbol Parameter Typ. Max. Unit Condition Cin Input Capacitance 7 10 pF Vin=0.0V Cour Output Capacitance 9 12 pF Vour=0.0V NOTES: 1. Sampled, not 100% tested.SHARP LHF80G14 27 6.2.2 AC Input/Output Test Conditions 27 5 INPUT Ms TEST POINTS - 1.35 OUTPUT Cj 0.0 Se AC test inputs are driven at 2.7V fora Logic 1 and 0.0V for a Logic 0. Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) < 10 ns. Figure 11. Transient Input/Output Reference Waveform for 2.7V < V,.. < 3.0V 2.0 f 2 INPUT TEST POINTS > J 1.5 OUTPUT 0.0 f AC test inputs are driven at 3.0V for a Logic 1 and 0.0V for a Logic 0. Input timing begins, and output timing ends, at 1.5V. Input rise and fail times (10% to 90%) < 10 ns. Figure 12. Transient Input/Output Reference Waveform for 3.0V < V_,. < 3.6V 62 24 20 2 20 INPUT > TEST POINTS <C OUTPUT 0.8 6. 0.8 2h , 0.45 AC test inputs are driven at V,,, (2.4 V_,,) for a Logic 1 and V,, (0.45 V,,,) for a Logic O. Input timing begins at V,, (2.0 V,.,) and V, (0.8 V_,,). Output timing ends at V,, and V,,. Input rise and fall times (10% to 90%) < 10 ns. Figure 13. Transient Input/Output Reference Waveform for 4.5V< Veg $ 5.5V Test Configuration Capacitance Loading Value Test Configuration Cu(pF) Vec=2.7V-3.6V 50 Vec=5V+0.5V 100 DEVICE UNDER OUT TEST Cu Inctudes Jig Capacitance Figure 14. Transient Equivalent Testing Load CircuitSHARP LHF80G14 28 6.2.3 DC Characteristics DC Characteristics Symbol Parameter Notes To. 2.7V-9.8V Toe Nox Unit Test Conditions lu | input Load Current 1 +0.5 +1 BA | Vcc=VecMax, Vin=Veoc or GND luo | Output Leakage 1 +0.5 10 HA | Vec=VecMax, Current Vout=Vec or GND Iccs | Vcc Standby Current 1,3,6 100 100 yA | CMOS inputs Vec=Vec Max CE#=RP#=Vcct0.2V 2 2 mA | TTL inputs Vec=VccMax CE#=RP#=Vin Icco | Vec Deep Power-Down 1 12 16 pA | RP#=GND+0.2V Current lour(RY/BY#)=0mA Icca | Vcc Read Current 1,5,6 25 50 mA | CMOS inputs Vec=VccMax, CE#=GND f=5MH2(3.3V, 2.7V), 8MHz(5V) lour=OmA 30 65 mA | TTL inputs Vec=VccMax, CE#=GND f=5MH2(3.3V, 2.7V), 8MHz(5V) lour=OmA lecw | Veco Word Write or 1,7 17 ~ = mA | Vpp=3.3V+0.3V Set Lock-Bit Current 17 35 mA | Vep=5.0V+0.5V 12 30 mA | Vep=12.0V+0.6V Icce | Voc Block Erase or 1,7 17 - = mA _| Vep=3.3V+0.3V Clear Block Lock-Bits 17 30 mA _| Vpe=5.0V+0.5V Current 12 25 mA | Vee=12.0V+0.6V lccws | Vec Word Write or Block | 1,2 6 10 mA | CE#=Vin tcces | Erase Suspend Current : ipps | Vpp Standby or Read 1 +15 +15 uA | Ver<Vcc lppa_| Current 200 200 pA | Vpp>Vcc Ippo | Vpp Deep Power-Down 1 5 5 pA | RP#=GND+0.2V Current lppw | Vep Word Write or 1,7 80 - - mA | Vep=3.3V+0.3V Set Lock-Bit Current 80 80 mA _| Vep=5.0V+0.5V 30 30 mA _| Vee=12.0V+0.6V Ippe | Veep Block Erase or 1,7 40 - - mA_| Vep=3.3Vt0.3V Set Lock-Bit Current 40 40 mA _| Vpp=5.0V+0.5V 30 30 mA | Vepp=12.0V+0.6V Ippws | Veep Word Write or Block | .1 200 200 WA | Vep=Vepu1/2/3 lppes | Erase Suspend CurrentSHARP LHF80G14 29 Dc Characteristics (Continued) Symbol Parameter Notes 7 7 es ee Unit Test Conditions Vit Input Low Voltage 7 -0.5 0.8 -0.5 0.8 V Vin Input High Voitage 7 2.0 Vec 2.0 Vec Vv . +0.5 +0.5 Vo. | Output Low Voltage 3,7 0.4 0.45 Vo | Vec=VecMin loc=5.8MA(Vcc=5V), loL=2.0MA(Vcc=3.3V) Vou: | Output High Voitage 3,7 2.4 : 2.4 Vt Vec=VecMin (TTL) lon=-2.5MA(Voc=5V), lo#=-2.0MA(Vcc=3.3V) Von2 | Output High Voltage 3,7 0.85 0.85 Vo] Vec=VeccMin (CMOS) Vec Vec loH=-2.5uA Vec Vec Vo | Vec=VecMin -0.4 -0.4 lon=-100LA Veptk | Vep Lockout during 4,7 1.5 1.5 Vv Normal Operations Vppxi | Vee during Word Write, 2.7 3.6 - - Vv BLock Erase, or Lock-Bit Operations VeeH2 | Ver during Word Write, 4.5 5.5 4.5 5.5 Vv BLock Erase, or Lock-Bit Operations Vepx3 | Vep during Word Write, 11.4 12.6 11.4 12.6 Vv BLock Erase, or 1 Lock-Bit Operations Viko_| Voc Lockout Voltage 2.0 2.0 Vv Vo | RP# Unlock Voitage 8 11.4 12.6 11.4, 12.6 V_ | Set Permanent Lock-Bit Override Block Lock-Bit NOTES: 1 2. 3. _ All currents are in RMS unless otherwise noted. These currents are valid for all product versions (package and speeds). Contact your local sales office for information about typical specifications. lows ANG loces are Specified with the device de-selected. If read or word written while in erase suspend mode, the device's current draw is the sum Of lows OF Ioces AND Ioog OF logy, respectively. Includes RY/BY#. 4. Block erases, word writes, and lock-bit configurations are inhibited when V,, < Vpp,,. and not guaranteed in the aAaNan range between V,,,,, (max) and V,.,,, (min), between V,,,,, (max) and V,,,,. (min), between Veo, (Max) aNd Veen, (min), and above V,,,,, (max). . Automatic Power Saving (APS) reduces typical |,,, to 1 mA at 5V V,, and 3 mA at 3.3V V,, in static operation. . CMOS inputs are either V., + 0.2V or GND + 0.2V. TTL inputs are either V,, or Vue . Sampled, not 100% tested. . Permanent lock-bit set operations are inhibited when RP# = V,,. Block lock-bit configuration operations are inhibited when the permanent lock-bit is set or RP# = V,, and WP# = V,. Block erases and word writes are inhibited when the corresponding block-lock bit is set and RP# = V,,, and WP# = V,, or the permanent lock-bit is set. Block erase, word write, and lock-bit configuration operations are not guaranteed with V,, < 2.7V or V,, < RP# < V,,, and should not be attempted.SHARP LHF80G14 30 6.2.4 AC Characteristics - Read Only Operations Veg = 2.7V - 3.6V, T, = ~40C to + 85C Versions LH28F800SGHB-L10 Unit Symbol Parameter Notes Min. Max. tavav Read Cycle Time 120 ns tavav Address to Output Delay 120 ns teLav CE# to Output Delay 2 120 ns teHav RP# High to Output Delay 600 ns tetav OE# to Output Delay 2 50 ns teLax CE# to Output in Low Z 3 0 ns teHoz CE# High to Output in High Z 3 55 ns terax OE# to Output in Low Z 3 0 ns tgHoz OE# High to Output in High Z 3 25 ns tou Output Hold from Address, CE# ot OE# 3 0 ns Change, Whichever Occurs First Veg = 3-3V + 0.3V, T, = -40C to + 85C Versions LH28F800SGHB-L10 Unit Symbol Parameter Notes Min. Max. tavav Read Cycle Time 100 ns tavav_ Address to Output Delay , 100 ns teLav CE# to Output Delay 2 100 ns teHav RP# High to Output Delay 600 ns teLav OE# to Output Delay 2: 45 ns teLax CE# to Output in Low Z 3 0 ns teHaz CE# High to Output in High Z 3 45 ns taLax OE# to Output in Low Z 3 0 ns teaHaz OE# High to Output in High Z 3 20 ns tou Output Hold from Address, CE# ot OE# 3 O- ns Change, Whichever Occurs FirstSHARP LHF80G14 31 6.2.4 AC Characteristics - Read Only Operations (Cont.) Vig = 5.0V + O.5V, T, =-40C to + 85C Vv LH28F800SGHB-L1 Notes Min. Max. 100 100 100 RP# 400 # : 50 CE# in Z CE# to i Zz 55 OE# in Low OE# in Zz 15 Output Hold from Address, CE# ot # Whichever Occurs NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to t,, ay - tegy after the falling edge of CE# without impact on tay. 3. Sampled, not 100% tested. 4. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit for testing characteristics.SHARP LHF80G14 DEVICE STANOBY ADDRESS SELECTION DATA VALID Mi woressesay " XK XK XX ssness st x Vie -___.- tavav eh CER (E} " J... | oN _f JF Vie tave i leHaz VIH OE# (G) / \ /. . \ Wo meanness aw em 'gHaz tav Vik wer tao + \ Yin teLox L- terax ton > Vou HIGH Z fi DATA (D/Q) i L i VAUD OUTPUT \ _HIGHZ (000 - Da15) \ \\ x VoL }-_ tavav Voc / Vin RP# (P) / VIL J) Figure 15. AC Wavetorm for Read OperationsSHARP LHF80G14 33 6.2.5 AC Characteristics for WE#- Controled Write Operations ) Vig = 2.7V - 3.6V, T, = -40C to + 85C Vv : LH28F800SGHB-L10 Parameter Notes Min. Max. Write Time 120 # 2 1 # to WE# Low 10 WE# 50 Vv to 100 Vi; WE# 100 Address to 50 to WE# 50 Data WE# 5 Address Hold from WE# 5 CE# Hold from WE# 10 WE# Width 30 WE# to RY/BY# Low Write Read Vpp Hold from Valid SRD, RY/BY# H RP# Van Hold from Valid SRD, RY/BY# Veg = 3.3V + 0.3V, T, = -40C to + 85C Versions LH28F800SGHB-L10 Parameter Notes Min. Max. Write Time 100 RP# to WE# Low 2 1 # to WE# Low 10 WE# Width RP# V; to WE# H Vv: to WE# H Address WE# H Data to WE# H Data Hold from WE# H from WE# H # Hold from WE# WE# Puiles Width WE# to RY/BY# Low Write before Read Vpp Hold from Valid SRD, RY/BY# H RP# Vin Hold from Valid SRD, RY/BY#SHARP LHF80G14 | 34 6.2.5 AC Characteristics for WE# - Controled Write Operations (Cont.) Veg = SV O.5V, T, = ~40C to + 85C Vv Vv Parameter Notes Min. Write Time . 100 RP# # 2 1 to # 10 WE# Pluse Width 40 RP# V WE# : 100 Vv WE# 100 to WE# 40 to # 40 Hold from WE# 5 Address Hold from WE# 5 CE# Hoid from WE# 10 WE# Pules WE# to RY/BY# Low Vv from Valid RY/BY# RP# Hold from Valid SRD, RY/BY# NOTES: 1. Read timing characteristics during block erase, word write and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. . 3. Refer to Table 4 for valid A,, and D,, for block erase, word write, or lock-bit configuration. 4. V,, should be held at Veo.104 (and if necessary RP# should be held at V,,,) until determination of block erase, word write, or lock-bit configuration success (SR.1/3/4/5 = 0). - 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit for testing characteristics.SHARP LHF80G14 35 ADORESS (A) OEs# (G) WEs (W) DATA (04Q) RY/BY~# (A) WP# (S) FP@ (P) Vep (Vv) Va Veg POWER-UP WRITE BLOCK ERASE WRITE BLOCK ERASE AUTOMATED ERASE READ STATUS WRITE READ AARAY AND STANOBY OR CONFIRM OR OR PROGRAM DELAY REGISTER DATA COMMAND WORD WRITE SETUP VALID ADDRESS & DATA as No Vow An An Vv, * beavav >}e- Vor Va Vie Va Vie Va Via Va Ven Vine Vn. Vie Vn Verua. VppuK Va Figure 16. AC Waveform for WE#-Controlled Write OperationsSHARP LHF80G14 36 6.2.6 AC Characteristics for CE#-Controlled Writes Operations Veg = 2.7V - 3.6V, T, = -40C to + 85C V Notes Write Time . RP# to CE# 2 WE# CE# Low CE# Width RP# V to CE# V # to CE# Data CE# from CE# CE# WE# CE# CE# Pulse Width CE# to RY/BY# Write before Vpp Hold from Valid SRD, RY/BY# H RP# Van Hold from V SRD, RY/BY# Veg = 3-3V + 0.3V, T, = -40C to + 85C Versions Parameter Notes Write RP#H to CE# 2 WE# to CE# Low CE# Pulse Width RP# V; to Vep to CE# Address to # Data to CE# Data from # Address Hold from CE# WE# Hold from CE# CE# Width H CE#H RY/BY# Low Write before Read Vee Hold from Valid SRD, RY/BY#H RP# Vix Hold from Valid SRD, RY/BY#H LH28F800SGHB-L10 Min. Max. 120 1 0 70 100 100 50 50 5 5 0 25 0 0 0 LH28F800SGHB-L10 Min. Max. 100 1 0 70 100 1 50 50 5 5 0 25 0 0 0SHARP LHF80G14 37 6.2.6 AC Characteristics for CE#-Controlled Writes Operations (Cont.) Voce = SV 0.5V, T, = -40C to + 85C Vv Vv LH28F800SGHB-L1 Notes Min. Max. Write Time . 100 RP# to 2 1 WE to CE# 0 CE# Width 50 RAP#V # : 100 Vv # 100 # 40 to CE# 40 from CE# Address Hold from CE# WE# from CE# Cc Width CE# to RY/BY# Write before Read Vv Valid SRD, RY/BY# RP# Vu Hold from Valid SRD, RY/BY# NOTES: 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. . 3. Refer to Table 4 for valid A,, and D,,, for block erase, word write, or lock-bit configuration. 4. V,. should be held at Vou, (and if necessary RP# shouid be held at V,,,) until determination of block erase, word write, or lock-bit configuration success (SR. 1/3/4/5 = 0). 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit for testing characteristics.SHARP LHF80G14 38 Veo POWER-UP WRITE BLOCK ERASE WRITE BLOCK ERASE AUTOMATED ERASE READ STATUS WRITE READ ARRAY AND STANOBY OA CONFIRM OA OR PROGRAMOELAY AEGISTER DATA COMMAND WORD WRITE SETUP VALIO ADDRESS & DATA Ae cH 7 A Cc A ADDRESS (A) Aw WEs (W) Oe (G) CEs (e) DATA (va) RY/BY# (A) WP (S) . RP# (P) Vpp (V) Figure 17. AC Waveform for CE#-Controlled Write OperationsSHARP LHF80G14 39 6.2.7 Reset Operations Vine RYPBYe (A) Ve Vine APe (P) Va tpupH (A) Reset Ouring Read Array Mode Ve RY/BY# (A) f Va. tpupH { Vine APs (P) \ Vie Sm (B) Reset During Block Erase, Word Write, or Lock-Bit Configuration 2.7VE3.3V5V ' Vee w ' lessven Viva _RP# (P) . Va (C) Vec Rising Timing Figure 18. AC Waveform for Reset Operation Reset AC Specifications Vec=2.7V-3.6V Voc=5V+0.5V Symbol Parameter Notes Min. Max. Min. Max. Unit RP# Putse Low Time {PLPH (If RP# is tied to Vcc, this 100 100 ns specification is not applicable) RP# Low to Reset during Block 20 teLAH Erase, Word Write, or Lock-Bit 2,3 12 us Configuration 28(2.7V Vcc) Vcc 2.7V to RP# High teasveH | Vcc 3.0V to RP# High 4 100 100 ns Vcc 4.5V to RP# High NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, word write, or lock-bit configuration operation is not executing, the reset will complete within 100 ns. 3. A reset time, taoy, is required from the latter of RY/BY# or RP# going high until outputs are valid. 4. When the device power-up, holding RP# low minimum 100 ns is required after V,,, has been in predefined range and also has been in stable there.SHARP LHF80G14 40 6.2.8 Block Erase, Word Write and Lock-Bit Configuration Performance Veg = 3.3V + 0.3V, T, = -40C to + 85C Vep=3.0-3.6V Vep=4.5-5.5V Vpp=11.4-12.6V . Symbol Parameter Notes [iin. [Typ.( Max. | Min. [Typ.] Max. | Min. [Typ.] Max. | UN" twHavt | Word Write Time 35 | 45 14 | 20 11 us tEHov1 Block Write Time 1.2 1.5 0.5 | 0.7 0.4 sec twHav2 . tenove Block Erase Time 2.1 1.4 1.3 sec twravs | Set Lock-Bit Time 2 31 20 17.4 us teHavs twHova Clear Block Lock-Bits teHove Time 2 2.7 1.8 1.6 sec tWHRH1 Word Write Suspend tEHRH) Latency Time to 9 7.5 7.5 Hs tWHRH2 Read teHRH2 Erase Suspend 24.3 14.4 14.4 Hs Veg = SV 0.5V, T, = -40C to + 85C , Vpp=4.5-5.5V Vpp=11.4-12.6V . Symbol Parameter Notes ain Typ.) | Max. |_Min. | Typ.) | Max. Unit twHavt | Word Write Time 10 | 14 7.5 us - teHov1 Block Write Time 0.4 0.5 0.25 sec twHave Block Erase Time 2 1,3 1.2 sec teHave tweavs | Set Lock-Bit Time 2 18 15 us teHovs twHav4 | Clear Block Lock-Bits Time 2 1.6 1.5 sec teHava tWHRH1 Word Write Suspend Latency teHRHi Time to Read 75 6 us twHAHe | Erase Suspend Latency Time tenRH2 to Read 14.4 14.4 HS NOTES: 1. Typical values measured at T, = + 25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled but not 100% tested.SHARP LHF80G14 at Veg = 2-7V -3.0V, T, = -40C to + 85C Vpe=2.7-3.0V Vep=4.5-5.5V Vpp=11.4-12.6V . Symbol Parameter Notes Min. |Typ.! Max. | Min. [Typ.] Max. | Min. [Typ.] Max. Unit wneu Word Write Time 2 | 49 | 63 20 | 28 15.4 ys Block Write Time 2 1.7 2.1 0.7 1.0 0.56 sec Mwave | Block Erase Time 2 3.0 2.0 1.9 sec teHave tWHaVs | Set Lock-Bit Time 2 44 28 24.4 us |_teHav3 twHovs Clear Block Lock-Bits tenova Time 2 3.8 2.6 2.3 sec tWHRH1 Word Write Suspend teHRH1 Latency Time to 12.6 10.5 10.5 Hs tWHRH2 Read tennis Erase Suspend 34.1 20.2 20.2 ys NOTES: 1. Typical values measured at T, = + 25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled but not 100% tested.SHARP . LHF80G14 49 7.0 Package and packing specification | 1. Package Outline Specification Refer to drawing NO. AA2034 2. Markings 2-1. Marking contents (1) Product name -: FSO0OSGHB- Li0 | (2) Company name -: SHARP (3) Date code (Example) YY Ww xxx! Indicates the product was manufactured in the WWth week of 19YY. Denotes the production ref.code (1~3) > Denotes the production week. (01,02,03,-- +: 52,53) Denotes the production year. (Lower two digits of the year.) (4) The marking of JAPAN indicates the country of origin. 22. Marking layout Refer to drawing NO.AA2Z034 (This layout does not define the dimensions of marking character and marking position.) 3. Packing Specification (Dry packing for surface mount packages) Dry packing is used for the purpose of maintaining IC quality after mounting packages on the PCB (Printed Circuit Board). If the surface mount type package absorbs a large amount of moisture, this moisture may suddenly vaporize into steam when the entire package is heated during the reflow soldering process. This causes expansion and results in separation between the resin and insert material, and sometimes cracking of the package. This dry packing is designed to prevent the above problem from occurring in surface mount packages. 31,. Packing Materials Material Name Material Specificaiton Purpose Tray Conductive plastic (80devices/tray)| Fixing of device Upper cover tray Conductive plastic (ltray/case) Fixing of device Laminated aluminum bag Aluminum polyethylene (lbag/case) | Drying of device Des iccant Silica gel Drying of device P P band Polypropylene (3pces/case) | Fixing of tray Inner case Card board (800devices/case) | Packaging of device Label Paper Indicates part number, quantity . and date of manufacture Outer case Card board Outer packing of tray (Devices shall be placed into a tray in the same direction.)SHARP ; LHF80G14 43 32. Outline dimension of tray Refer to attached drawing 4. Storage and Opening of Dry Packing 41. Store under conditions shown below before opening the dry packing (1) (2) 42. Notes (1) (2) Temperature range : 5~40C Humidity : 80% RH or less on opening the dry packing Before opening the dry packing, prepare a working table which is grounded against ESD and use a grounding strap. The tray has been treated to be conductive or anti-static. If the device is transferred to another tray, use a equivalent tray. 48, Storage after opening the dry packing Perform the following to prevent absorption of moisture after opening. (1) After opening the dry packing, store the ICs in an environment with a temperature of 5~25C and a relative humidity of 60% or less. If doing reflow soldering once, mount ICs within 4 days after the opening. If doing reflow soldering twice, do the first mounting within 4 days after the opening and do the second mounting within 4 days after the first mounting. (2) To re-store the ICs for an extended period of time within 4 days after opening the dry packing, use a dry box or re-seal the ICs in the dry packing with desiccant (whoes indicater is blue}, and store in an environment with a temperature of 5~40C and a relative humidity of 80% or less, and mount ICs within 2 weeks. (3) Total period of storage after first opening and re-opening is within 4 days, and stere the ICs in the same environment as section 4-3.(1). First opening X, -*re-sealinge Y re-opening X. mount ing O O O ICs in dry 5~25C 5~40C 5~25C packing 60% RH or less 80% RH or less 60% RH or less X,+X, within 4 days Y twithin 2 weeks 44, Baking (drying) before mounting (1) Baking is necessary (A) If the humidity indicator in the desiccant becomes pink (B) If the procedure in section 43 could not be performed (2) Recommended baking conditions If the above conditions (A) and (B) are applicable, bake it before mounting. The recommended conditions are 1~3 hours at 120 * jC. Heat resistance tray is used for shipping tray. (3) Storage after baking After baking ICs, store the ICs in the same environment as section 4-3.(1).SHARP . LHF80G14 44 5. Surface Mount Conditions Please perform the following conditions when mounting ICs not to deteriorate IC quality. 51 .Soldering conditions Mount ing Method Temperature and Duration Measurement Point Reflow soldering | Peak temperature of 240C or less, IC package surface duration of less than 15 seconds above 230C, temperature increase rate of 1~4C/second. 52. Conditions for removal of residual flux (1) Ultrasonic washing power : 25 Watts/liter or less (2) Washing time : Total 1 minute maximum (3) Solvent temperature > 15~40CSHARP LHF80G14 45 INDEX | 40.30 @ |S/AB $140.15 @ |SicD 0. 45 +0. 03 nN Boe TOP VIEW._._- _ 2-2 5 D = N | \ : : \ SIDE VIEW , ) C ) } y elo t 15) , i 4 0 a! al of ~ a oO | >| > _ BE) fb} f +I 0.8 TYP | wo] o to 0.4 TYH oO] 3] a S -60000000 wOOQ0IO00O --fsQO999N999O fot fi. cO0000000 BOTTOM VIEW 20 00010000 <O900|G0900 123 415) 6 7 | 1.2 TYP. BR | we NAME ! FBGA048P-0808 NOTE . Bir DRAWING NO. : AA2034 UNIT | mm46 LHF80GI14 SHARP 315.9 78: 13.240. 1 *15=288.04+6.5 iS NOTE } i rend Un U -] rr il tie Tt | Bo o +] S| Pao | iat 43 oe Qo A FD a Ll G)a w ra Fo Fs ep nh Bers ttt _ of \ es { D 0 \ Daa rertp PD J oo 6-R4 \ea3e18 No holes (Vacuum pickup cell) m oO my __ tg + ! ; \_ i i ered Tl _) 20 i 200 | 20 | CSP80-O0808TCMRH NAME8 Mbit, Queen Cobra, I-temp, CSP, ETOX, Non- Volatile, LH28F800SGHB-L10