PRELIMINARY GALVANTECH, INC. ASYNCHRONOUS ULTRA LOW POWER FULL CMOS SRAM GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM 128K x 8 SRAM LOW POWER SUPPLY VOLTAGE LOW STANDBY CURRENT FEATURE GENERAL DESCRIPTION * * * The GVT73024UL8 is organized as a 131,072 x 8 SRAM using a six-transistor full CMOS memory cell along with lowpower CMOS process, using double-layer polysilicon, double-layer metal technology. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers two chip enables (CE1# and CE2) along with output enable (OE#) for this organization. The chip is enabled when CE1# is LOW and CE2 is HIGH. With chip being enabled, writing to this device is accomplished when write enable (WE#) is LOW and reading is accomplished when (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements. * * * * * * * Low standby current: 5ua (max.) Low operating current: 1.5mA/MHz (typ.) Wide power supply voltage range: 3.0V to 3.6V for GVT73024UL8XX family 2.7V to 3.3V for GVT73024UL8XXB family 2.3V to 2.7V for GVT73024UL8XXC family 1.8V to 2.2V for GVT73024UL8XXD family Low data retention voltage: 1.5V (Min) Full CMOS 6-transistor memory cell Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Easy memory expansion with CE1#, CE2 and OE# options Automactic power-down when deselected OPTIONS * * * * Power supply voltage 3.3V + 0.3V 3.0V + 0.3V 2.5V + 0.2V 2.0V + 0.2V Timing 55ns access 70ns access 85ns access 100ns access 300ns access Packages 32-pin SOJ (300 mil) 32-pin TSOP (type I) 32-pin sTSOP (type I) Temperature Commercial Industrial MARKING -None -B -C -D PIN ASSIGNMENT 32-Pin SOJ 32-Pin DIP -55 -70 -85 -100 -300 32 2 31 3 30 A12 A7 A6 A5 A4 A3 A2 A1 A0 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC A15 CE2 WE# A13 A8 A9 A11 OE# A10 CE1# DQ8 DQ7 DQ6 DQ5 DQ4 PIN ASSIGNMENT 32-Pin TSOP (Type I) I ) 32-PIN TSOP/sTSOP (TYPE (0C to 70C) (-40C to 85C) A11 A9 A8 A13 WE# CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com Rev. 8/99 1 DQ1 DQ2 DQ3 VSS SJ TS ST None I NC A16 A14 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 OE# A10 CE1# DQ8 DQ7 DQ6 DQ5 DQ4 VSS DQ3 DQ2 DQ1 A0 A1 A2 A3 Galvantech, Inc. reserves the right to chang e products or specifications without notice. PRELIMINARY GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM GALVANTECH, INC. FUNCTIONAL BLOCK DIAGRAM VCC VSS A0 MEMORY ARRAY 512 ROWS X 256 X 8 COLUMNS I/O CONTROL ADDRESS BUFFER ROW DECODER DQ1 DQ8 CE2 CE1# WE# OE# POWER DOWN A16 COLUMN DECODER TRUTH TABLE MODE CE1# CE2 WE# OE# DQ POWER L L L H X H H H X L H L H X X L X H X X Q D HIGH-Z HIGH-Z HIGH-Z ACTIVE ACTIVE ACTIVE STANDBY STANDBY READ WRITE OUTPUT DISABLE STANDBY STANDBY PIN DESCRIPTIONS SOJ Pin Numbers TSOP & sTSOP Pin Numbers 12, 11, 10, 9, 8, 7, 20, 19, 18, 17, 16, 6, 5, 27, 28, 23, 15, 14, 13, 3, 2, 31, 25, 4, 28, 3, 31, 2 1, 12, 4, 11, 7, 10 SYMBOL TYPE DESCRIPTION A0-A16 Input Address Inputs: These inputs determine which cell is addressed. 29 5 WE# Input Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle . 22, 30 30, 6 CE1#, CE2 Input Chip Enables: These inputs are used to enable the device. When CE1# is LOW and CE2 is HIGH, the chip is selected. When either CE1# is HIGH or CE2 is LOW, the chip is disabled and automatically goes into standby power mode. Output Enable: This active LOW input enables the output drivers. 24 32 OE# Input 13, 14, 15, 17, 18, 19, 20, 21 21, 22, 23, 25, 26, 27, 28, 29 DQ1-DQ8 Input/ Outpu t SRAM Data I/O: Data inputs and data outputs . 32 8 VCC Supply Power Supply: 1.8V to 3.6V, depending upon the product family. 16 24 VSS Supply Ground August 16, 1999 Rev. 8/99 2 Galvantech, Inc. reserves the right to change products or specifications without notice. PRELIMINARY GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM GALVANTECH, INC. *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Supply Relative to VSS........-0.3V to +4.0V VIN ..........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ......................-65o C to +150 oC Power Dissipation ...........................................................0.7W Soldering Temperature (10s) ........................................260o C RECOMMENDED DC OPERATING CONDITIONS DESCRIPTION SYMBOL PRODUCT Supply Voltage VCC Input High (Logic 1) voltage V IH MIN TYP MAX UNITS NOTES GVT73024UL8XX 3.0 3.3 3.6 V 1 GVT73024UL8XX B 2.7 3.0 3.3 GVT73024UL8XX C 2.3 2.5 2.7 GVT73024UL8XX D 1.8 2.0 2.2 GVT73024UL8XX 2.2 - VCC+0.2 V 1, 2 GVT73024UL8XX B 2.2 GVT73024UL8XX C 2.0 0.4 V 1, 2 GVT73024UL8XX D Input Low (Logic 0) Voltage 1.6 V Il -0.2 DC AND OPERATING ELECTRICAL CHARACTERISTICS (All Temperature Ranges; VCC = 1.8 V to 3.6V. unless otherwise noted, VLC =0.2V, VHC =VCC-0.2V) DESCRIPTION SYM CONDITIONS MIN. TYP. MAX. UNIT S NOTES Input Leakage Current IL I 0V < V IN < VCC -1 1 uA Output Leakage Current IL O Output(s) disabled, 0V < V OU T < VCC -1 1 uA Operating Power Supply Current Icc1 Cycle Time=1us; CE1# = V IL & CE2 = V IH;Other Inputs = V IH/V IL ; IOUT = 0mA - 1.5 3 mA 3, 14 Icc2 Cycle Time=Min; CE1# = V IL & CE2 = V IH;Other Inputs = V IH/V IL; IOUT = 0mA VCC=3.6V@55ns - - 55 mA 3 VCC=3.3V@70ns - - 50 VCC=2.7V@85ns - - 30 VCC=2.2V@300ns - - 15 TTL Standby Current ISB CE1# > V IH or CE2 < V IL; Other Inputs=V IH or V IL ; f= 0 - - 0.3 mA CMOS Standby Current ISB1 CE1# > V HC or CE2< V LC; Other Inputs =V HC or V LC; f= 0 - - 5 uA Output Low Voltage V OL IOL = 2.1mA @ VCC=2.7V IOL = 0.5mA @ VCC=2.3V IOL = 0.33mA @ VCC=1.8V - - 0.4 V 1 Output High Voltage V OH IOH = -1.0mA @ VCC=3.0V 2.4 - - V 1 IOH = -0.5mA @ VCC=2.5V 2.0 - - IOH = -0.44mA @ VCC=2.0V 1.6 - - CAPACITANCE DESCRIPTION CONDITIONS Input Capacitance TA = 25 o C; f = 1 MHz VCC = 3V Input/Output Capacitance (DQ) August 16, 1999 Rev. 8/99 SYMBOL MAX UNITS NOTES CI 6 pF 4 CI/O 8 pF 4 3 Galvantech, Inc. reserves the right to change products or specifications without notice. PRELIMINARY GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM GALVANTECH, INC. PRODUCT LIST Part Name Voltage Range & Speed Grade GVT73024UL8XX 3.3V + 0.3V; 55ns, 70ns, 85ns and 100ns GVT73024UL8XXB 3.0V + 0.3V; 55ns, 70ns, 85ns and 100ns GVT73024UL8XXC 2.5V + 0.2V; 70ns, 85ns and 100ns GVT73024UL8XXD 2.0V + 0.2V; 300ns AC ELECTRICAL CHARACTERISTICS (Note 5) (All Temperature Ranges; VCC = 3.0V to 3.6V for GVT73024ULXX family; VCC = 2.7V to 3.3V for GVT73024ULXXB family; VCC = 2.3V to 2.7V for GVT73024ULXXC family; VCC = 1.8V to 2.2V for GVT73024ULXX family)) - 55 DESCRIPTION SY M MIN - 70 MAX MIN - 85 MAX MIN - 100 MAX MIN MAX - 300 MIN MAX UNITS NOTE S READ Cycle READ cycle tim e t Address access time t AA 55 70 85 100 300 ns 13 ACE 55 70 85 100 300 ns 13 t Chip Enable access time t Output hold from address chang e RC 55 OH 10 LZC E 10 Chip Enable to output in Low- Z t Chip disable to output in High-Z t HZC E AO E Output Enable to output in Low- Z t Output Enable to output in High-Z t LZOE t Chip disable to power-down tim e t PU 10 20 PD 25 0 55 50 5 25 0 70 ns 4, 7 60 ns 4, 6, 7 150 ns 13 ns 4, 7 ns 4, 6, 7 ns 4 ns 4 30 25 0 85 ns 50 25 40 5 ns 30 10 25 30 5 300 15 10 25 20 0 100 15 10 5 HZOE Chip Enable to power-up time 85 20 t Output Enable access time 70 60 0 100 300 WRITE Cycle WRITE cycle tim e t WC 55 70 85 100 300 ns Chip Enable to end of write t CW 40 45 50 60 300 ns Address valid to end of write, with OE# HIGH t 40 45 50 60 300 ns Address setup time t AS 0 0 0 0 0 ns Address hold from end of write t AH 0 0 0 0 0 ns AW WRITE pulse width t WP2 40 45 50 60 200 ns WRITE pulse width, with OE# HIGH t WP1 40 45 50 60 200 ns Data setup tim e t DS 25 30 35 40 120 ns Data hold tim e t DH 0 0 0 0 0 ns LZWE 5 5 5 5 20 Write disable to output in Low-Z t Write Enable to output in High-Z t August 16, 1999 Rev. 8/99 HZW E 20 25 4 25 25 60 ns 4, 7 ns 4, 6, 7 Galvantech, Inc. reserves the right to change products or specifications without notice. PRELIMINARY GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM GALVANTECH, INC. AC TEST CONDITIONS Input pulse levels Input rise and fall times Input and output reference levels Output load 0.4V to 2.4V for VCC=3.3V &3.0V; 0.4V to 2.2V for VCC=2.5V; 0.4V to 1.8V for VCC=2.0V 5ns 1.5V for VCC=3.3V and 3.0V; 1.1V for VCC=2.5V; 0.9V for VCC=2.0V CL = 100pF and 1 TTL Gate NOTES 1. All voltages referenced to VSS (GND). 2. Undershoot:VIL -1.0V for t 20ns Overshoot:VIH > VCC+1.0V for t 20ns 3. Ic c is given with no output current. Ic c increases with greater output loading and faster cycle times. 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in the table of AC Test Conditions unless otherwise noted. 6. High-Z is defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 7. At any given temperature and voltage condition, t HZCE is less than tLZCE and t HZWE is less than t LZWE. 8. WE# is HIGH for READ cycle. 9. Device is continuously selected. Chip enable and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in AC Test Condition table. 14. Typical values are measured at 3.3V and 25o C. DATA RETENTION ELECTRICAL CHARACTERISTICS DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX VDR ICCDR 1.5 - - - Chip Deselect to Data Retention Tim e tCDR 0 Operation Recovery Time tR tRC Vcc for Retention Data Data Retention Current August 16, 1999 Rev. 8/99 CE1# > VCC -0.2 or CE2< VSS +0.2; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0;Vcc = 3.0V 5 UNITS NOTES 3.6 V 1 5 uA - - ns 4 - - ns 4, 11 Galvantech, Inc. reserves the right to change products or specifications without notice. PRELIMINARY GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM GALVANTECH, INC. LOW VCC DATA RETENTION WAVEFOR M DATA RETENTION MODE VCC CE# VDR tCDR tRC VIH VIL READ CYCLE NO. 1(8, 9 ) tRC ADDR VALID tAA tOH Q PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 2(7, 8, 10, 12 ) tRC CE1# CE2 tAOE tLZOE OE# t HZCE tACE tHZOE tLZCE Q HIGH Z DATA VALID DON'T CARE UNDEFINED August 16, 1999 Rev. 8/99 6 Galvantech, Inc. reserves the right to change products or specifications without notice. PRELIMINARY GALVANTECH, INC. GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM WRITE CYCLE NO. 1(7, 12) (Write Enable Controlled with Output Enable OE# active LOW)) tWC ADDR tAW tAH t CW CE2 CE1# tAS tWP2 WE# tDS D tDH DATA VALID tHZWE tLZWE Q HIGH Z WRITE CYCLE NO. 2(12) (Write Enable Controlled with Output Enable OE# inactive HIGH) tWC ADDR tAW tAH tCW CE2 CE1# t tWP1 AS WE# tDS D Q tDH DATA VALID HIGH Z DON'T CARE UNDEFINED August 16, 1999 Rev. 8/99 7 Galvantech, Inc. reserves the right to change products or specifications without notice. PRELIMINARY GALVANTECH, INC. GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM WRITE CYCLE NO. 3(12) (Chip Enable Controlled) tWC ADDR tAW tAH tCW tAS CE2 CE1# tWP1 WE# t DS D Q t DH DATA VALID HIGH Z DON'T CARE August 16, 1999 Rev. 8/99 8 Galvantech, Inc. reserves the right to change products or specifications without notice. PRELIMINARY GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM GALVANTECH, INC. Package Dimensions 32-pin 300 Mil Plastic SOJ (SJ) .825 (20.96) .810 (20.57) .305 (7.75) .292 (7.42) PIN #1 INDEX .340 (8.64) .330 (8.38) .140 (3.55) .120 (3.04) .050 (1.27) TYP .095 (2.41) .080 (2.03) SEATING PLANE .020 (0.51) .015 (0.38) .274 (6.95) .254 (6.44) .025 (0.63) MIN Note: All dimensions in inches (millimeters) MAX MIN or typical, min where noted. 32-pin Plastic TSOP (TS) .795 (20.20) .780 (19.80) .012 (0.30) .006 (0.15) .319 (8.10) .311 (7.90) .020 (0.50) TYP .047 (1.20) MAX Note: All dimensions in inches (millimeters) August 16, 1999 Rev. 8/99 .728 (18.50) .720 (18.30) MAX MIN .041 (1.05) .037 (0.95) or typical, max where noted. 9 Galvantech, Inc. reserves the right to change products or specifications without notice. PRELIMINARY GALVANTECH, INC. GVT73024UL8 ULTRA LOW POWER 128K X 8 SRAM Package Dimensions (continued) 32-pin Plastic STSOP (ST) .536 (13.60) .520 (13.20) .012 (0.30) .006 (0.15) .319 (8.10) .311 (7.90) .020 (0.50) TYP .047 (1.20) MAX .469 (11.90) .461 (11.70) Note: All dimensions in inches (millimeters) MAX MIN .041 (1.05) .037 (0.95) or typical, max where noted. Ordering Information GVT 73024UL8 XX X - XXX X Galvantech Prefix Temperature (Blank = Commercial I = Industrial), Part Number Speed (55 = 55ns, 70= 70ns, 85 = 85ns, 100 = 100ns, 300 = 300ns) Voltage (Blank = 3.0V to 3.6V, B = 2.7V to 3.3V, C = 2.3V to 2.7V, D = 1.8V to 2.2V) Package (SJ = 300 mil SOJ, TS= TSOP TYPE I, ST= sTSOP TYPE I) August 16, 1999 Rev. 8/99 10 Galvantech, Inc. reserves the right to change products or specifications without notice.