9 kHz to 30 GHz,
Silicon SPDT Switch
Data Sheet
ADRF5021
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
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Devices. Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 ©2016–2020 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Ultrawideband frequency range: 9 kHz to 30 GHz
Nonreflective 50 Ω design
Low insertion loss: 2.0 dB to 30 GHz
High isolation: 60 dB to 30 GHz
High input linearity
1 dB power compression (P1dB): 28 dBm typical
Third-order intercept (IP3): 52 dBm typical
High power handling
24 dBm through path
24 dBm terminated path
ESD sensitivity: Class 1, 1 kV human body model (HBM)
20-terminal, 3 mm × 3 mm land grid array package
No low frequency spurious
Radio frequency (RF) settling time (to 0.1 dB of final RF
output): 6.2 µs
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, electronic counter measures (ECMs)
Broadband telecommunications systems
FUNCTIONAL BLOCK DIAGRAM
14580-001
RF2
RF1
RFC
EN
VSS
CTRL
VDD
50Ω
50Ω
DRIVER
ADRF5021
Figure 1.
GENERAL DESCRIPTION
The ADRF5021 is a general-purpose single-pole, double-throw
(SPDT) switch manufactured using a silicon process. It comes
in a 3 mm × 3 mm, 20-terminal land grid array (LGA) package
and provides high isolation and low insertion loss from 9 kHz
to 30 GHz.
This broadband switch requires dual supply voltages, +3.3 V
and −2.5 V, and provides CMOS/LVTTL logic-compatible
control.
ADRF5021 Data Sheet
Rev. B | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Absolute Maximum Ratings ........................................................... 5
Power Derating Curves ............................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions ............................ 6
Interface Schematics .....................................................................6
Typical Performance Characterics ..................................................7
Insertion Loss, Return Loss, and Isolation ................................7
Input Power Compression and Third-Order Intercept (IP3) 8
Theory of Operation .........................................................................9
Applications Information ............................................................. 10
Evaluation Board ........................................................................ 10
Probe Matrix Board ................................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
3/2020—Rev. A to Rev. B
Changes to Digital Control Inputs Parameter, Table 2 .............. 5
Added Endnote 1, Table 2; Renumbered Sequentially ............... 5
Changes to Theory of Operation Section .................................... 10
2/2017—Rev. 0 to Rev. A
Changed VEN = 3.3 V to 5 V to VEN = 0 V or 3.3 V to 5 V ........... 3
7/2016—Revision 0: Initial Version
Data Sheet ADRF5021
Rev. B | Page 3 of 12
SPECIFICATIONS
VDD = 3.3 V to 5 V, VSS = −2.5 V, VCTRL = 0 V or 3.3 V to 5 V, VEN = 0 V or 3.3 V to 5 V, TCASE = 25°C, 50 Ω system, unless otherwise
noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 0.009 30,000 MHz
INSERTION LOSS
Between RFC and RF1/RF2 9 kHz to 10 GHz 1.1 dB
10 GHz to 20 GHz 1.4 dB
20 GHz to 30 GHz 2.0 dB
ISOLATION
Between RFC and RF1/RF2 9 kHz to 10 GHz 65 dB
10 GHz to 20 GHz 60 dB
20 GHz to 30 GHz 60 dB
Between RF1 and RF2 9 kHz to 10 GHz 70 dB
10 GHz to 20 GHz 65 dB
20 GHz to 30 GHz 60 dB
RETURN LOSS
RFC and RF1/RF2 (On) 9 kHz to 10 GHz 23 dB
10 GHz to 20 GHz 17 dB
20 GHz to- 30 GHz 13 dB
RF1/RF2 (Off) 9 kHz to 10 GHz 30 dB
10 GHz to 20 GHz 18 dB
20 GHz to 30 GHz 8 dB
SWITCHING
Rise and Fall Time tRISE, tFALL 10% to 90% of RF output 1.0 µs
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 1.1 µs
RF Settling Time
0.1 dB 50% VCTL to 0.1 dB of final RF output 6.2 µs
0.05 dB 50% VCTL to 0.05 dB of final RF output 10 µs
INPUT LINEARITY1 1 MHz to 30 GHz
Power Compression
0.1 dB P0.1dB 27 dBm
1 dB P1dB 28 dBm
Third-Order Intercept IP3 Two-tone input power = 14 dBm each tone,
Δf = 1 MHz
52 dBm
SUPPLY CURRENT VDD, VSS pins
Positive IDD VDD = 3.3 V 80 300 µA
VDD = 5 V 100 600 µA
Negative ISS VSS = −2.5 V <1 10 µA
DIGITAL CONTROL INPUTS
CTRL, EN pins
Voltage
Low VINL VDD = 3.3 V 0 0.8 V
VDD = 5 V 0.9 V
High VINH VDD = 3.3 V 1.2 3.3 V
VDD = 5 V 1.7 5.0 V
Current
Low and High IINL, IINH <1 µA
ADRF5021 Data Sheet
Rev. B | Page 4 of 12
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive VDD 3.0 5.4 V
Negative VSS −2.75 −2.25 V
Digital Control Voltage VCTL 0 VDD V
RF Input Power2 PIN f = 1 MHz to 30 GHz, TCASE = 85°C
Through Path RF signal is applied to RFC or through
connected RF1/RF2
24 dBm
Terminated Path RF signal is applied to terminated RF1/RF2 24 dBm
Hot Switching RF signal is present at RFC while switching
between RF1 and RF2
18 dBm
Case Temperature TCASE −40 +85 °C
1 For input linearity performance at frequencies less than 1 MHz, see Figure 15 to Figure 17.
2 For power derating at frequencies less than 1 MHz, see Figure 2 to Figure 4.
Data Sheet ADRF5021
Rev. B | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Supply Voltage
Positive −0.3 V to +5.5 V
Negative −2.75 V to +0.3 V
Digital Control Inputs1 −0.3 V to VDD + 0.3 V
or 3.3 mA, whichever
occurs first
RF Input Power2 (f = 1 MHz to 30 GHz,
TCASE) = 85°C)
Through Path 27 dBm
Terminated Path 25 dBm
Hot Switching 21 dBm
Temperature
Junction (TJ) 135°C
Storage −65°C to +150°C
Reflow (MSL3 Rating) 260°C
Junction to Case Thermal Resistance
(θJC)
Through Path 420°C/W
Terminated Path 160°C/W
ESD Sensitivity
HBM 1 kV (Class 1)
1 Overvoltages at digital control inputs are clamped by internal diodes.
Current must be limited to the maximum rating given.
2 For power derating at frequencies less than 1 MHz, see Figure 2 to Figure 4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Only one absolute maximum rating can be applied at any one
time.
POWER DERATING CURVES
4
–14
–12
–10
–8
–6
–4
–2
0
2
POWER DE RATI NG (dB)
FREQUENCY ( Hz )
10k 1M 100M 10G 30G100k 10M 1G
T
CASE
= 85° C
14580-002
Figure 2. Power Derating for Through Path vs. Frequency, TCASE = 85°C
4
–14
–12
–10
–8
–6
–4
–2
0
2
POWER DE RATI NG (dB)
T
CASE
= 85° C
14580-003
FREQUENCY ( Hz )
10k 1M 100M 10G 30G100k 10M 1G
Figure 3. Power Derating for Terminated Path vs. Frequency, TCASE = 85°C
4
–14
–12
–10
–8
–6
–4
–2
0
2
POWER DE RATI NG (dB)
TCASE = 85°C
14580-004
FREQUENCY ( Hz )
10k 1M 100M 10G 30G
100k 10M 1G
Figure 4. Power Derating for Hot Switching vs. Frequency, TCASE = 85°C
ESD CAUTION
ADRF5021 Data Sheet
Rev. B | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
RF2
GND
GND
GND
GND
GND
RF1
GND
GND
GND
GND
RFC
GND
GND
GND
EN
VSS
CTRL
VDD
1
2
3
4
5
6 7 8 9 10
11
12
13
14
15
1617181920
ADRF5021
TOP VIEW
(No t t o Scal e)
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO THE RF/DC GROUND OF THE PRINTED
CIRCUI T BO ARD ( P CB) .
14580-005
Figure 5. Pin Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 4 to 7, 9, 10,
13, 16, 17, 19, 20
GND Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB).
3 RFC RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
8 RF1 RF1 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
11 VDD Positive Supply Voltage.
12 CTRL Control Input. See Figure 7 for the interface schematic.
14 EN Enable Input. See Figure 7 for the interface schematic.
15 VSS Negative Supply Voltage.
18 RF2 RF2 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2
14580-006
Figure 6. RFC, RF1, and RF2 Pins Interface Schematic
CTRL, EN
VDD
VDD
14580-007
Figure 7. Digital Pins (CTRL and EN) Interface Schematic
Data Sheet ADRF5021
Rev. B | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
Insertion loss and return loss measured on the probe matrix board using the ground, signal, ground (GSG) probes close to the RF pins;
isolation measured on an evaluation board because signal coupling between the probes limits the isolation performance of the
ADRF5021 on the probe matrix board (see the Applications Information section for details of evaluation and probe matrix boards).
0
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
0403530
2520
15105
T
CASE
= –40° C
T
CASE
= +25°C
T
CASE
= +85°C
14580-008
Figure 8. Insertion Loss Between RFC and RF1/RF2 vs. Frequency over
Temperature
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
ISOLATION (dB)
FRE Q UE NCY ( GHz)
04035302520
15105
T
CASE
= –40° C
T
CASE
= +25°C
T
CASE
= +85°C
14580-009
Figure 9. Isolation Between RFC and RF1/RF2 vs. Frequency over
Temperature
0
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
RET URN LOS S ( dB)
FRE Q UE NCY ( GHz)
04035
30252015
105
RF2 OFF
RF1 ON
RFC
14580-010
Figure 10. Return Loss vs. Frequency (RFC, RF1 On, and RF2 Off)
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
ISOLATION (dB)
FRE Q UE NCY ( GHz)
0403530
252015105
T
CASE
= –40° C
T
CASE
= +25°C
T
CASE
= +85°C
14580-011
Figure 11. Isolation Between RF1 and RF2 vs. Frequency over
Temperature
ADRF5021 Data Sheet
Rev. B | Page 8 of 12
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT (IP3)
All large signal performance parameters were measured on the evaluation board.
32
10
12
14
16
18
20
22
24
26
30
28
INPUT P0.1d B ( dBm)
FRE Q UE NCY ( GHz)
03025201510
5
T
CASE
= –40° C
T
CASE
= +25°C
T
CASE
= +85°C
14580-012
Figure 12. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Temperature
32
10
12
14
16
18
20
22
24
26
30
28
INPUT P1dB (dBm)
FRE Q UE NCY ( GHz)
030252015
105
T
CASE
= –40° C
T
CASE
= +25°C
T
CASE
= +85°C
14580-013
Figure 13. Input 1 dB Power Compression (P1dB) vs. Frequency over
Temperature
60
20
25
30
35
40
45
50
55
INPUT I P 3 ( dBm)
FRE Q UE NCY ( GHz)
030252015
105
T
CASE
= –40° C
T
CASE
= +25°C
T
CASE
= +85°C
14580-014
Figure 14. Input IP3 vs. Frequency over Temperature
32
10
12
14
16
18
20
22
24
26
28
30
INPUT P0.1d B ( dBm)
FRE Q UE NCY ( Hz )
10k 1M 100M100k 10M 1G
T
CASE
= –40° C
T
CASE
= +25°C
T
CASE
= +85°C
14580-015
Figure 15. Input 0.1 dB Power Compression (P0.1dB) vs. Frequency over
Temperature (Low Frequency Detail)
32
10
12
14
16
18
20
22
24
26
28
30
INPUT P1dB (dBm)
T
CASE
= –40° C
T
CASE
= +25°C
T
CASE
= +85°C
14580-016
FRE Q UE NCY ( Hz )
10k 1M 100M100k 10M 1G
Figure 16. Input 1 dB Power Compression (P1dB) vs. Frequency over
Temperature (Low Frequency Detail)
60
20
25
30
35
40
45
50
55
INPUT I P 3 ( dBm)
TCASE = –40°C
TCASE = + 25°C
TCASE = + 85°C
14580-017
FREQUENCY ( Hz )
10k 1M 100M100k 10M 1G
Figure 17. Input IP3 vs. Frequency over Temperature (Low Frequency Detail)
Data Sheet ADRF5021
Rev. B | Page 9 of 12
THEORY OF OPERATION
The ADRF5021 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
minimize RF coupling.
The ADRF5021 is internally matched to 50 Ω at the RF common
port (RFC) and the RF throw ports (RF1 and RF2); therefore,
no external matching components are required. All of the RF
ports are dc-coupled to 0 V, and no dc blocking is required at the
RF ports when the RF line potential is equal to 0 V. The design
is bidirectional; the RF input signal can be applied to the RFC
port while the RF throw port (RF1 or RF2) is output or vice versa.
The ADRF5021 incorporates a driver to perform logic functions
internally and to provide the user with the advantage of a
simplified control interface. The driver features two digital
control input pins, CTRL and EN.
When the EN pin is logic low, the RF1 to RFC path is in an
insertion loss state, and the RF2 to RFC path is in an isolation
state, or vice versa, depending on the logic level applied to the
CTRL pin. The insertion loss path (for example, RF1 to RFC)
conducts the RF signal equally well in both directions between
its throw port (for example, RF1) and common port (RFC). The
isolation path (for example, RF2 to RFC) provides high loss
between the insertion loss path and its throw port (for example,
RF2) terminated to an internal 50 Ω resistor.
When the EN pin is logic high, both the RF1 to RFC path and
the RF2 to RFC path are in an isolation state regardless of the
logic state of CTRL. RF1 and RF2 ports are terminated to
internal 50 Ω resistors, and RFC becomes open reflective.
The ideal power-up sequence is as follows:
1. Connect GND.
2. Power up VDD and VSS. Powering up VSS after VDD
avoids current transients on VDD during ramp-up.
3. Apply the digital control inputs, CTRL and EN. Applying
the digital control inputs before the VDD supply may
inadvertently forward bias and damage the internal ESD
protection structures. In such a case, use a series 1.5 kΩ
resistor to limit the current flowing in to the control pin. If
the control pins are not driven to a valid logic state (for
example, if the controller output is in a high impedance
state) after VDD is powered up, it is recommended to use
pull-up and pull-down resistors.
4. Apply an RF input signal.
The ideal power-down sequence is the reverse order of the
power-up sequence.
Table 4. Control Voltage Truth Table
Digital Control Input RF Paths
EN CTRL RF1 to RFC RF2 to RFC
Low Low Isolation (off) Insertion loss (on)
Low High Insertion loss (on) Isolation (off)
High Low Isolation (off) Isolation (off)
High High Isolation (off) Isolation (off)
ADRF5021 Data Sheet
Rev. B | Page 10 of 12
APPLICATIONS INFORMATION
EVALUATION BOARD
Figure 18 and Figure 19 show the top and cross sectional views
of the evaluation board, which uses 4-layer construction with a
copper thickness of 0.5 oz (0.7 mil) and dielectric materials
between each copper layer.
1500mil
940mil
828mil
40mil
40mil
EDGE P LAT ING 5 × 520mil
570mil
R 32mil
14580-018
Figure 18. Evaluation Board Layout (Top View)
0.5oz Cu (0. 7m i l ) 0.5oz Cu (0. 7m i l )
0.5oz Cu (0. 7m i l )
0.5oz Cu (0. 7m i l )
0.5oz Cu (0. 7m i l )
RO4003
FR4
FR4
0.5oz Cu (0. 7m i l )
TO TAL THICKNESS
~62mil
W = 14m i l
G = 5mil
T = 0.7m i l
H = 8 m il
14580-019
Figure 19. Evaluation Board (Cross Sectional View)
All RF and dc traces are routed on the top copper layer whereas
the inner and bottom layers are grounded planes that provide
a solid ground for the RF transmission lines. Top dielectric
material is 8 mil Rogers RO4003, offering good high frequency
performance. The middle and bottom dielectric materials are
FR-4 type materials to achieve an overall board thickness of
62 mil.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model with a width of 14 mil and ground
spacing of 5 mil to have a characteristic impedance of 50 Ω. For
good RF and thermal grounding, as many plated through vias
as possible are arranged around transmission lines and under
the exposed pad of the package.
Figure 20 shows the actual ADRF5021 evaluation board with
component placement. Two power supply ports are connected
to the VDD and VSS test points, TP5 and TP2, and the ground
reference is connected to the GND test point, TP1. On each
supply trace, a 100 pF bypass capacitor is used, and unpopulated
components positions are available for applying extra bypass
capacitors.
14580-020
Figure 20. Populated Evaluation Board
Two control ports are connected to the EN and CTRL test
points, TP3 and TP4. On each control trace, a resistor position
is available to improve the isolation between the RF and control
signals. The RF ports are connected to the RFC, RF1, and RF2
connectors (J1, J2, and J3) that are end launch 2.4 mm RF
connectors. A through transmission line that connects
unpopulated RF connectors (J7 and J8) is also available to
measure the loss of the PCB. Figure 21 and Table 5 are the
evaluation board schematic and bill of materials, respectively.
The evaluation board shown in Figure 20 is available from
Analog Devices, Inc., upon request.
Data Sheet ADRF5021
Rev. B | Page 11 of 12
GND
RF2
GND
GND
GND
GND
GND
RF1
GND
GND
GND
GND
RFC
GND
GND
GND
EN
VSS
VSS
CTRL
VDD
EN
CTRL
VDD
1
2
3
4
5
6 7 8 9 10
11
12
13
14
15
1617181920
U1
J1
J3
J2
J7
DEPOP J8
DEPOP
THR_CAL
RF2
RFC
RF1
R2
0Ω
R1
0Ω
TP5
TP4
TP3
TP2
TP1
C5
100pF C2
100pF
DEPOP
C1
10µF
DEPOP
C4
100pF C3
100nF
DEPOP
C6
10µF
DEPOP
14580-021
Figure 21. Evaluation Board Schematic
Table 5. Bill of Materials, Evaluation Board Components
Component Description
J1, J2, J3 End launch connectors, 2.4 mm
J7, J8 Unpopulated end launch connectors, 2.4 mm
TP1 to TP5 Through hole mount test points
C4, C5 100 pF capacitors, 0402 package
C2, C3 Unpopulated capacitors, 0402 package
C1, C6 Unpopulated capacitors, 0603 package
R1, R2 0 Ω resistors, 0402 package
U1 ADRF5021 SPDT switch
PCB 600-01583-00-1 evaluation PCB
PROBE MATRIX BOARD
Figure 22 and Figure 23 show the top and cross sectional views
of the probe matrix board that measures the s-parameters of the
ADRF5021 at close proximity to RF pins using the GSG probes.
The actual board duplicates the same layout in matrix form to
assemble multiple devices and uses RF traces for through,
reflect, and line (TRL) calibration.
220mil
340mil
14580-022
Figure 22. Probe Board Layout (Top View)
0.5oz Cu 0.5oz Cu
0.5oz Cu
RO4003
0.5oz Cu
W = 14m i l
G = 5mil
T = 0.7m i l
H = 8 m il
14580-023
Figure 23. Probe Matrix Board (Cross Sectional View)
ADRF5021 Data Sheet
Rev. B | Page 12 of 12
OUTLINE DIMENSIONS
05-25-2016-B
PKG-004908
3.10
3.00
2.90
0.776
0.726
0.676
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1
5
6
10
11
15
16 20
1.70
1.60 SQ
1.50
0.40
BSC
0.13
REF
0.70
REF
1.60 REF
SQ
0.25
0.20
0.15
0.30
0.25
0.20
0.236
0.196
0.156
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PADS, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
0.530 REF
CHAMFERED
PIN 1 (0. 3 × 45°)
PIN 1
CORNER ARE A
Figure 24. 20-Terminal Land Grid Array [LGA]
3 mm × 3 mm Body and 0.72 mm Package Height
(CC-20-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description Package Option Branding3
ADRF5021BCCZN −40°C to +85°C MSL3 20-Terminal Land Grid Array [LGA] CC-20-3
XXXX
021
ADRF5021BCCZN-R7 −40°C to +85°C MSL3 20-Terminal Land Grid Array [LGA] CC-20-3
XXXX
021
ADRF5021-EVALZ Evaluation Board
1 Z = RoHS-Compliant Part.
2 See the Absolute Maximum Ratings section.
3 XXXX is the 4-digit lot number.
©2016–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14580-3/20(B)
