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Single-chip built-in FET type Switching Regulator Series
Output 1.5A or Less High Efficiency
Step-down Switching Regulators
with Built-in Power MOSFET
BD9102FVM, BD9104FVM, BD9106FVM
●Description
ROHM’s high efficiency step-down switching regulator (BD9102FVM, BD9104FVM, BD9106FVM) is a power supply
designed to produce a low voltage including 1.24 volts from 5 volts power supply line. Offers high efficiency with our
original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster
transient response to sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET)
and SLLMTM (Simple Light Load Mode)
3) Incorporates soft-start function.
4) Incorporates thermal protection and ULVO functions.
5) Incorporates short-current protection circuit with time delay function.
6) Incorporates shutdown function
7) Employs small surface mount package MSOP8
●Use
Power supply for HDD, power supply for portable electronic devices like PDA, and power supply for LSI including CPU and
ASIC
●Lineup
Parameter BD9102FVM BD9104FVM BD9106FVM
Vcc voltage 4.0～5.5V 4.5～5.5V 4.0～5.5V
Output voltage 1.24V±2% 3.30V±2% Adjustable(1.0～2.5V)
Output current 0.8A Max. 0.9A Max. 0.8A Max.
UVLO Threshold voltage 2.7V Typ. 4.1V Typ. 3.4V Typ.
Short-current protection with time delay function built-in built-in built-in
Soft start function built-in built-in built-in
Standby current 0μA Typ. 0μA Typ. 0μA Typ.
Operating temperature range -25～+85℃ -25～+85℃ -25～+85℃
Package MSOP8 MSOP8 MSOP8
●Absolute Maximum Rating (Ta=25℃)
Parameter Symbol Limits Unit
VCC voltage VCC -0.3～+7 *1 V
PVCC voltage PVCC -0.3～+7 *1 V
EN voltage EN -0.3～+7 V
SW,ITH voltage SW,ITH -0.3～+7 V
Power dissipation 1 Pd1 387.5*2 mW
Power dissipation 2 Pd2 587.4*3 mW
Operating temperature range Topr -25～+85 ℃
Storage temperature range Tstg -55～+150 ℃
Maximum junction temperature Tjmax +150 ℃
*1 Pd should not be exceeded.
*2 Derating in done 3.1mW/℃ for temperatures above Ta=25℃.
*3 Derating in done 4.7mW/℃ for temperatures above Ta=25℃,Mounted on 70mm×70mm×1.6mm Glass Epoxy PCB
No.09027EAT34
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
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●Recommended Operating Conditions (Ta=25℃)
Parameter Symbol
BD9102FVM BD9104FVM BD9106FVM
Unit
Min. Max. Min. Max. Min. Max.
VCC voltage VCC 4.0 5.5 4.5 5.5 4.0 5.5 V
PVCC voltage PVCC*4 4.0 5.5 4.5 5.5 4.0 5.5 V
EN voltage EN 0 VCC 0 VCC 0 VCC V
SW average output current Isw*4 - 0.8 - 0.8 - 0.8 A
*4 Pd should not be exceeded.
●Electrical Characteristics
◎BD9102FVM(Ta=25℃,VCC=5V,EN=VCC unless otherwise specified.)
Parameter Symbol Min. Typ. Max. Unit Conditions
Standby current ISTB - 0 10 μA EN=GND
Bias current ICC - 250 400 μA
EN Low voltage VENL - GND 0.8 V Standby mode
EN High voltage VENH 2.0 VCC - V Active mode
EN input current IEN - 1 10 μA VEN=5V
Oscillation frequency FOSC 0.8 1 1.2 MHz
Pch FET ON resistance *5 RONP - 0.35 0.60 Ω PVCC=5V
Nch FET ON resistance *5 RONN - 0.25 0.50 Ω PVCC=5V
Output voltage VOUT 1.215 1.24 1.265 V
ITH SInk current ITHSI 10 20 - μA VOUT=H
ITH Source Current ITHSO 10 20 - μA VOUT=L
UVLO threshold voltage VUVLOTh 2.6 2.7 2.8 V VCC=H→L
UVLO hysteresis voltage VUVLOHys 50 100 200 mV
Soft start time TSS 0.5 1 2 ms
Timer latch time TLATCH 0.5 1 2 ms
*5 Design Guarantee（Outgoing inspection is not done on all products）
◎BD9104FVM(Ta=25℃,VCC=5V,EN=VCC unless otherwise specified.)
Parameter Symbol Min. Typ. Max. Unit Conditions
Standby current ISTB - 0 10 μA EN=GND
Bias current ICC - 250 400 μA
EN Low voltage VENL - GND 0.8 V Standby mode
EN High voltage VENH 2.0 VCC - V Active mode
EN input current IEN - 1 10 μA VEN=5V
Oscillation frequency FOSC 0.8 1 1.2 MHz
Pch FET ON resistance *5 RONP - 0.35 0.60 Ω PVCC=5V
Nch FET ON resistance *5 RONN - 0.25 0.50 Ω PVCC=5V
Output voltage VOUT 3.234 3.300 3.366 V
ITH SInk current ITHSI 10 20 - μA VOUT=H
ITH Source Current ITHSO 10 20 - μA VOUT=L
UVLO threshold voltage VUVLOTh 3.9 4.1 4.3 V VCC=H→L
UVLO hysteresis voltage VUVLOHys 50 100 200 mV
Soft start time TSS 0.5 1 2 ms
Timer latch time TLATCH 0.5 1 2 ms
*5 Design Guarantee（Outgoing inspection is not done on all products）
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
3/17
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© 2009 ROHM Co., Ltd. All rights reserved.
◎BD9106FVM(Ta=25℃,VCC=5V,EN=VCC,R1=20kΩ,R2=10kΩunless otherwise specified.)
Parameter Symbol Min. Typ. Max. Unit Conditions
Standby current ISTB - 0 10 μA EN=GND
Bias current ICC - 250 400 μA
EN Low voltage VENL - GND 0.8 V Standby mode
EN High voltage VENH 2.0 VCC - V Active mode
EN input current IEN - 1 10 μA VEN=5V
Oscillation frequency FOSC 0.8 1 1.2 MHz
Pch FET ON resistance *5 RONP - 0.35 0.60 Ω PVCC=5V
Nch FET ON resistance *5 RONN - 0.25 0.50 Ω PVCC=5V
ADJ reference voltage VADJ 0.780 0.800 0.820 V
Output voltage VOUT - 1.200 - V
ITH SInk current ITHSI 10 20 - μA ADJ=H
ITH Source Current ITHSO 10 20 - μA ADJ=L
UVLO threshold voltage VUVLOTh 3.2 3.4 3.6 V VCC=H→L
UVLO hysteresis voltage VUVLOHys 50 100 200 mV
Soft start time TSS 1.5 3 6 ms
Timer latch time TLATCH 0.5 1 2 ms
*5 Design Guarantee（Outgoing inspection is not done on all products）
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
4/17
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●Characteristics data
■VCC-VOUT
■VEN-VOUT
■IOUT-VOUT
■Soft start
0
1
2
3
4
012345
INPUT VOLTAGE:VCC[V]
OUTPUT VOLTAGE:VOUT[V]
0
0.5
1
1.5
2
0123
OUTPUT CURRENT:IOUT[A]
OUTPUT VOLTAGE:VOUT[V]
0
0.5
1
1.5
2
0123
OUTPUT CURRENT:IOUT[A]
OUTPUT VOLTAGE:VOUT[V]
0
0.5
1
1.5
2
012345
EN VOLTAGE:VEN[V]
OUTPUT VOLTAGE:VOUT[V]
0
1
2
3
4
012345
EN VOLTAGE:VEN[V]
OUTPUT VOLTAGE:VOUT[V]
0
0.5
1
1.5
2
012345
EN VOLTAGE:VEN[V]
OUTPUT VOLTAGE:VOUT[V]
0
0.5
1
1.5
2
012345
INPUT VOLTAGE:VCC[V]
OUTPUT VOLTAGE:VOUT[V]
0
0.5
1
1.5
2
012345
INPUT VOLTAGE:VCC[V]
OUTPUT VOLTAGE:VOUT[V]
Fig.2 Vcc-Vout Fig.3 Vcc-Vout
Fi
g
.4 Ven-Vout Fig.5 Ven-Vout Fig.6 Ven-Vout
Fig.7 Iout-Vout Fig.9 Iout-Vout
Fig.10 Soft start waveform Fig.11 Soft start waveform Fig.12 Soft start waveform
VOUT
VCC=PVCC=EN
[BD9102FVM]
VOUT
VCC=PVCC=EN
[BD9104FVM]
VOUT
VCC=PVCC=EN
[BD9106FVM]
Ta=25℃ Ta=2 5 ℃ Ta=25℃
Fig.1 Vcc-Vout
[BD9102FVM]
Ta=25℃ [BD9104FVM]
Ta=25℃[BD9106FVM]
Ta=25℃
[BD9102FVM] VCC=5V
Ta=25℃
[BD9104FVM] [BD9106FVM]
[BD9102FVM]
0
1
2
3
4
0123
OUTPUT CURRENT:IOUT[A]
OUTPUT VOLTAGE:VOUT[V]
Fig.8 Iout-Vout
[BD9104FVM] [BD9106FVM]
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
5/17
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■SW waveform IO=10mA
■SW waveform IO=200mA
■Transient response IO=100mA → 600mA
■Transient response IO=600mA → 100mA
Fig.13 SW waveform
Io=10mA
(
SLLMTM control
)
Fig.16 SW waveform
Io=200mA(PWM control)
Fig.19 Transient response
Io=100→600mA(10μs)
VOUT
IOUT
[BD9102FVM]
VOUT
IOUT
[BD9102FVM]
SW
VOUT
[BD9102FVM]
SW
VOUT
[BD9102FVM]
SW
VOUT
[BD9104FVM]
SW
VOUT
[BD9104FVM]
SW
VOUT
[BD9106FVM]
SW
VOUT
[BD9106FVM]
VOUT
IOUT
[BD9104FVM]
VOUT
IOUT
[BD9104FVM]
VOUT
IOUT
[BD9106FVM]
VOUT
IOUT
[BD9106FVM]
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
Fig.14 SW waveform
Io=10mA
(
SLLMTM control
)
Fig.15 SW waveform
Io=10mA
(
SLLMTM control
Fig.17 SW waveform
Io=200mA(PWM control)
Fig.18 SW waveform
Io=200mA(PWM control VOUT=1.8V)
Fig.20 Transient response
Io=100→600mA(10μs)
Fig.21 Transient response
Io=100→600mA(10μs)
(VOUT=1.8V)
Fig.22 Transient response
Io=600→100mA(10μs)
Fig.23 Transient response
Io=600→100mA(10μs)
Fig.24 Transient response
Io=600→100mA(10μs)
(VOUT=1.8V)
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
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■Ta-VOUT
■Efficiency
■Reference characteristics
1.75
1.76
1.77
1.78
1.79
1.8
1.81
1.82
1.83
1.84
1.85
-25 -15 -5 5 15 25 35 45 55 65 75 85
TEMPERATURE:Ta[℃]
OUTPUT VOLTAGE:VOUT[V]
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
OUTPUT CURRENT:IOUT[mA]
EFFICIENCY:η[%]
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
-25-15-5 5 1525354555657585
TEMPERATURE:Ta[℃]
PMOS ON RESISTANCE:RONP[Ω]
3
3.05
3.1
3.15
3.2
3.25
3.3
3.35
3.4
3.45
3.5
-25-15-5 5 1525354555657585
TEMPERATURE:Ta[℃]
OUTPUT VOLTAGE:VOUT[V]
Fig.34 Ta-VEN Fig.35 Ta-ICC Fig.36 Vcc-Fosc
Fig.25 Ta-VOUT Fig.26 Ta-VOUT Fig.27 Ta-VOUT
Fig.28 Efficiency
(V
CC
=EN=5V V
OUT
=1 24V)
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
OUTPUT CURRENT:IOUT[mA]
EFFICIENCY:η[%]
Fig.29 Efficiency
(VCC=EN=5V,VOUT=3.3V)
[BD9104FVM][BD9102FVM]
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
OUTPUT CURRENT:IOUT[mA]
EFFICIENCY:η[%]
Fig.30 Efficiency
(VCC=EN=5V,VOUT=1.8V)
Ta=25℃
[BD9106FVM]
1.2
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
-25-15-5 5 1525354555657585
TEMPERATURE:Ta[℃]
OUTPUT VOLTAGE:VOUT[V]
[BD9102FVM]VCC=5V [BD9104FVM] [BD9106FVM]
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
-25-15-5 5 1525354555657585
TEMPERATURE:Ta[℃]
FREQUENCY:FOSC[MHz]
BD9102FVM
BD9104FVM
BD9106FVM
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
-25-15-5 5 1525354555657585
TEMPERATURE:Ta[℃]
NMOS ON RESISTANCE:RONN[Ω]
BD9102FVM
BD9104FVM
BD9106FVM
BD9102FVM
BD9104FVM
BD9106FVM
Fig.32 Ta-RONN Fig.33Ta-RONP
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-25-15-5 5 1525354555657585
TEMPERATURE:Ta[℃]
EN VOLTAGE:VEN[V]
BD9102FVM
BD9104FVM
BD9106FVM
0
50
100
150
200
250
300
350
-25-15-5 5 1525354555657585
TEMPERATURE:Ta[℃]
CIRCUIT CURRENT:ICC[μA]
VCC=5V
BD9102FVM
BD9104FVM
BD9106FVM
0.8
0.9
1
1.1
1.2
44.555.5
INPUT VOLTAGE:VCC[V]
FREQUENCY:FOSC[MHz]
BD9102FVM
BD9104FVM
BD9106FVM
Ta=25℃
Fig.31 Ta-FOSC
VCC=5V VCC=5V
Ta=25℃ Ta=25℃
VCC=5V VCC=5V VCC=5V
VCC=5V
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
7/17
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●Block diagram, Application circuit
【BD9102FVM,BD9104FVM】
Fig.37 BD9102FVM BD9104FVM TOP View Fig.38 BD9102FVM BD9104FVM Block diagram
Fig.39 BD9106FVM TOP View Fig.40 BD9106FVM Block diagram
●Pin No. & function table
Pin No. Pin name PIN function
1 VOUT/ADJ Output voltage detect pin/ ADJ for BD9106FVM
2 ITH GmAmp output pin/Connected phase compensation capacitor
3 EN Enable pin(Active High)
4 GND Ground
5 PGND Nch FET source pin
6 SW Pch/Nch FET drain output pin
7 PVCC Pch FET source pin
8 VCC VCC power supply input pin
8
7
6
5
VCC
PVCC
SW
PGND
1
2
3
4
VOUT
ITH
EN
GND
TOP View
8
7
6
5
VCC
PVCC
SW
PGND
1
2
3
4
DJ
ITH
EN
GND
TOP View
BD9106FVM
VREF
OSC
UVLO
TSD
Current
Sense/
Protect
Driver
Logic
+
Soft
Start
8
7
6
5
4
21
3
RQ
S
EN
VCC
PVCC
10μF
5V
Input
4.7μH
SW
10μF
Output
PGND
GND
ITH VOUT
VCC
SLOPE
Current
Comp.
Gm Amp.
VCC
CLK
VREF
OSC
UVLO
TSD
Current
Sense/
Protect
Driver
Logic
+
Soft
Start
8
7
6
5
4
21
3
RQ
S
EN
VCC
PVCC
10μF
5V
Input
4.7μH
SW
10μF
Output
PGND
GND
ITH
DJ
VCC
SLOPE
Current
Comp.
Gm Amp.
VCC
CLK
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
8/17
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●Information on advantages
Advantage 1：Offers fast transient response with current mode control system.
Voltage drop due to sudden change in load was reduced by 50%.
Fig.41 Comparison of transient response
Advantage 2： Offers high efficiency for all load range.
・For lighter load:
Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching
dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance
dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance
MOS FETs incorporated as power transistor.
ON resistance of P-channel MOS FET: 0.35 Ω (Typ.)
ON resistance of N-channel MOS FET: 0.25 Ω (Typ.)
Achieves efficiency improvement for heavier load.
Offers high efficiency for all load range with the improvements mentioned above.
Advantage 3：・Supplied in smaller package like MOSP8 due to small-sized power MOS FET incorporated.
・Allows reduction in size of application products
Reduces a mounting area required.
Fig.43 Example application
・Output capacitor Co required for current mode control: 10 μF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 4.7 μH inductor
DC/DC
Convertor
Controller
RITH
L
Co
VOUT
CITH
VCC
Cin
10mm
15mm
RITH
CITH
CIN
CO
L
VOUT
IOUT
228mV
VOUT
IOUT
110mV
Conventional product (VOUT of which is 3.3 volts) BD9104FVM(Load response IO=100mA→600mA)
0.001 0.01 0.1 1
0
50
100
①
②
PWM
SLLM
TM
①inprovement by SLLM system
②improvement by synchronous rectifier
Efficiency η[%]
Output current Io[A]
Fig.42 Efficiency
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
9/17
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●Operation
BD9102FVM, BD9104FVM, BD9106FVM are the synchronous rectifying step-down switching regulator that achieves faster
transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width
Modulation) mode for heavier load, while it utilizes SLLMTM (Simple Light Load Mode) operation for lighter load to improve
efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,
and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a
N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp)
receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback
control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the
P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control
repeat this operation.
・SLLMTM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse
is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without
voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa.
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current
Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is
tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the
switching dissipation and improves the efficiency.
Fig.44 Diagram of current mode PWM control
OSC
Level
Shift Driver
Logic
RQ
S
IL
SW
ITH
Current
Comp
Gm Amp.
SET
RESET
FB
Load
SENSE
VOUT
VOUT
Fig.45 PWM switching timing chart Fig.46 SLLMTM switching timing chart
Curren
t
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
IL(AVE)
VOUT(AVE)
SENSE
FB
Curren
t
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
0A
VOUT(AVE)
SENSE
FB
IL
Not switching
IL
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
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●Description of operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0 μF (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of
100 mV (Typ.) is provided to prevent output chattering.
・BD9102FVM BD9104FVM
TSS=1msec(typ.)
・BD9106FVM
TSS=3msec(typ.)
Fig.47 Soft start, Shutdown, UVLO timing chart
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
at least 1 ms. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO.
Fig.48 Short-current protection circuit with time delay timing chart
Hysteresis 100mV
Ts s Tss Ts s
Soft start
Standby mode Operating mode
Standby
mode Operating mode
Standby
mode Operating mode Standby mode
UVLO
EN UVLO
UVLO
VCC
EN
VOU
T
1msec
Output OFF
latch
EN
VOUT
Limi
t
IL
Standby
mode Operating mode
Standby
mode Operating mode
EN Timer latch EN
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
11/17
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© 2009 ROHM Co., Ltd. All rights reserved.
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
1) ON resistance dissipation of inductor and FET：PD(I2R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
1)PD(I2R)=IOUT2×(RCOIL×RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET
IOUT[A]：Output current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET,f[H]：Switching frequency,V[V]：Gate driving voltage of FET)
4)PD(ESR)=IRMS2×ESR (IRMS[A]：Ripple current of capacitor,ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
●Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
P=IOUT2×(RCOIL+RON)
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RCOIL：DC resistance of coil
RONP：ON resistance of P-channel MOS FET
RONN：ON resistance of N-channel MOS FET
IOUT：Output current
If VCC=5V, VOUT=3.3V, RCOIL=0.15Ω, RONP=0.35Ω, RONN=0.25Ω
IOUT=0.8A, for example,
D=VOUT/VCC=3.3/5=0.66
RON=0.66×0.35+(1-0.66)×0.25
=0.231+0.085
=0.316[Ω]
P=0.82×(0.15+0.316)
≒298[mV]
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration
on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
η= VOUT×IOUT
Vin×Iin
×100[%]= POUT
Pin
×100[%]= POUT
POUT+PDα
×100[%]
Ambient temperature:Ta [℃]
Fig.49 Thermal derating curves
Vin2×CRSS×IOUT×f
IDRIVE
3)PD(SW)= (CRSS[F]：Reverse transfer capacitance of FET,IDRIVE[A]：Peak current of gate.)
0
200
400
600
800
1000
②387.5mW
①587.4mW
①using an IC alone
θj-a=322.6℃/W
②mounted on glass epoxy PCB
θj-a=212.8℃/W
Power dissipation:Pd [mW]
0 25 50 75 100 125 150 85
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
12/17
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© 2009 ROHM Co., Ltd. All rights reserved.
●Selection of components externally connected
1. Selection of inductor (L)
* Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
If VCC=5V, VOUT=3.3V, f=1MHz, ΔIL=0.3×0.8A=0.24A, for example,
*Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency.
2. Selection of output capacitor (CO)
As the output rise time must be designed to fall within the soft-start time, the capacitance of output capacitor should be
determined with consideration on the requirements of equation (5):
In case of BD9104FVM, for instance, and if VOUT=3.3V, IOUT=0.8A, and TSS=1ms,
Inappropriate capacitance may cause problem in startup. A 10 μF to 100 μF ceramic capacitor is recommended.
3. Selection of input capacitor (Cin)
A low ESR 10μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
The inductance significantly depends on output ripple current.
A
s seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
Δ
IL=(VCC-VOUT)×VOUT
L×VCC×f
[
A
]
・・・
(
1
)
A
ppropriate ripple current at output should be 30% more or less of the
maximum output current.
ΔIL=0.3×IOUTmax. [A]・・・(2)
L= (VCC-VOUT)×VOUT
ΔIL×VCC×f [H]・・・
(
3
)
(ΔIL: Output ripple current, and f: Switching frequency)
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
Output ripple voltage is determined by the equation (4)：
ΔVOUT=ΔIL×ESR [V]・・・(4)
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
*Rating of the capacitor should be determined allowing sufficient margin against
output voltage. Less ESR allows reduction in output ripple voltage.
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage. The
ripple current IRMS is given by the equation (6):
IRMS=IOUT× VCC
(
VCC-VOUT
)
VCC [A]・・・
(
6
)
√
When VCC is twice the Vout, IRMS=IOUT
2
Fig.51 Output capacitor
(
5-3.3
)
×3.3
0.24×5×1M
L= =4.675μ → 4.7[μH]
< Worst case > IRMS(max.)
If VCC=5V, VOUT=3.3V, and IOUTmax.=0.8A,
IRMS=0.8×
5
(
5-3.3
)
5=0.46
[
ARMS
]
√
Co≦ TSS×(Ilimit-IOUT)
VOUT ・・・
(
5
)
Tss: Soft-start time
Ilimit: Over current detection level, 2A(Typ)
Fig.52 Input capacitor
ΔIL
Fig.50 Output ripple current
IL
VCC
IL
L
Co
VOUT
VCC
L
Co
VOUT
ESR
Co≦ 1m×(2-0.8)
3.3 ≒364 [μF]
VCC
L Co
VOUT
Cin
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
13/17
www.rohm.com 2009.05 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance
with CR zero correction by the error amplifier.
5. Determination of output voltage (for BD9106FVM only)
The output voltage VOUT is determined by the equation (7):
VOUT=(R2/R1+1)×VADJ・・・(7)
VADJ: Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined
as required.(Adjustable output voltage range： 1.0V～2.5V)
Use 1 kΩ～100 kΩ resistor for R1. If a resistor of the resistance
higher than100 kΩ is used, check the assembled set carefully for
ripple voltage etc.
Fig.56 Determination of output voltage
Gain
[dB]
Phase
[deg]
Fig.53 Open loop gain characteristics
A
0
0
-90
A
0
0
-90
fz(Amp.)
Fig.54 Error amp phase compensation characteristics
fp=
2π×RO×CO
1
fz(ESR)=2π×ESR×CO
1
Pole at power amplifie
r
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
fp(Min.)=2π×ROMax.×CO
1[Hz]←with lighter load
fp(Max.)=2π×ROMin.×CO
1[Hz]←with heavier load
Zero at power amplifie
r
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This
is because when the capacitance is doubled, the capacitor
ESR reduces to half.)
fz(Amp.)=2π×RITH.×CITH
1
GND,PGND
SW
VCC,PVCC
EN
VOUT
ITH
VCC
VOUT
Cin
RITH
CITH
L
ESR
CO
RO
VOUT
Fig.55 Typical application
fz(Amp.)= fp(Min.)
2π×RITH×CITH
1 = 2π×ROMax.×CO
1
SW
6
1
DJ
4.7μH
10μF R2
R1
Output
fp(Min.)
fp(Max.)
fz(ESR)
IOUTMin. IOUTMax.
Gain
[dB]
Phase
[deg]
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
14/17
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© 2009 ROHM Co., Ltd. All rights reserved.
●BD9102FVM, BD9104FVM, BD9106FVM Cautions on PC Board layout
Fig.57 Layout diagram
① For the sections drawn with heavy line, use thick conductor pattern as short as possible.
② Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin
PGND.
③ Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
Table1.Recommended parts list of application [BD9102FVM]
symbol part value manufacturer series
L Inductor 4.7μH Sumida CMD6D11B
CIN Ceramic capacitor 10μF Kyocera CM316X5R106M10A
CO Ceramic capacitor 10μF Kyocera CM316X5R106M10A
CITH Ceramic capacitor 330pF murata GRM18series
RITH Resistor 30kΩ ROHM MCR10 3002
Table2. Recommended parts list of application [BD9104FVM]
symbol part value manufacturer series
L Inductor 4.7μH Sumida CMD6D11B
CIN Ceramic capacitor 10μF Kyocera CM316X5R106M10A
CO Ceramic capacitor 10μF Kyocera CM316X5R106M10A
CITH Ceramic capacitor 330pF murata GRM18series
RITH Resistor 51kΩ ROHM MCR10 5102
Table3.Recommended parts list of application [BD9106FVM]
symbol part value manufacturer series
L Inductor 4.7μH Sumida CMD6D11B
CIN Ceramic capacitor 10μF Kyocera CM316X5R106M10A
CO Ceramic capacitor 10μF Kyocera CM316X5R106M10A
CITH Ceramic capacitor 750pF murata GRM18series
Table4.BD9106FVM RITH recommended value
Vout[V] RITH
1.0 18kΩ
1.2 22kΩ
1.5 22kΩ
1.8 27kΩ
2.5 36kΩ
*BD9106FVM: As the resistance recommended for RITH depends on the output voltage, check the
output voltage for determination of resistance.
8
7
6
5
1
2
3
4
VOUT/ADJ
ITH
EN
GND
VCC
PVCC
SW
PGND
CO
GND
VOUT
VCC
L①
③
EN
RITH
CITH
CIN
②
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
15/17
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© 2009 ROHM Co., Ltd. All rights reserved.
●I/O equivalence circuit
Fig.58 I/O equivalence circuit
VCC
VOUT
10kΩ
1pin(VOUT)
VCC
DJ
10kΩ
※BD9106FVM 1pin(ADJ)
VCC
ITH
2pin(ITH)
VCC VCC
EN
10kΩ
3pin(EN)
2.8MΩ
2.2kΩ
PVCC
SW
6pin(SW)
PVCC PVCC
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
16/17
www.rohm.com 2009.05 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
●Notes for use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4.Operation in Strong electromagnetic field
Be noted that using the IC in the strong electromagnetic radiation can cause operation failures.
5. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
6. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
7. Input to IC terminals
This is a monolithic IC with P+ isolation between P-substrate and each element as illustrated below. This P-layer and the
N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 59:
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or
GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Fig.59 Simplified structure of monorisic IC
8. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
(Pin A)
P+ P+
N N
N
P
P substrate Parasitic diode
GND GND
Parasitic diode or transistor
N
P
N
C
(Pin B) B
E
GND
P+ P+
N
N
Resistance Transistor (NPN)
(Pin B)
C
E
B
GND
(Pin A)
GND
P substrate
Parasitic diode
Parasitic diode or transistor
BD9102FVM, BD9104FVM, BD9106FVM
Technical Note
17/17
www.rohm.com 2009.05 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
●Ordering part number
B D 9 1 0 2 F V M - T R
Part No. Part No.
9102,9104,9106
Package
FVM: MSOP8
Packaging and forming specification
TR: Embossed tape and reel
(MSOP8)
(Unit : mm)
MSOP8
0.08 S
S
4.0±0.2
8
3
2.8±0.1
1
6
2.9±0.1
0.475
4
57
(MAX 3.25 include BURR)
2
1PIN MARK
0.9MAX
0.75±0.05
0.65
0.08±0.05
0.22 +0.05
–0.04
0.6±0.2
0.29±0.15
0.145 +0.05
–0.03
4°
+6°
−4°
Direction of feed
Reel
∗
Order quantity needs to be multiple of the minimum quantity.
<Tape and Reel information>
Embossed carrier tapeTape
Quantity
Direction
of feed
The direction is the 1pin of product is at the upper right when you hold
reel on the left hand and you pull out the tape on the right hand
3000pcs
TR
()
1pin
R0039
A
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
Notice
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consent of ROHM Co.,Ltd.
The content specied herein is subject to change for improvement without notice.
The content specied herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
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Please be sure to implement in your equipment using the Products safety measures to guard
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