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Rev. I

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liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-

pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon

Solution, Inc. receives written assurance to its satisfaction, that:

• Clock frequency: 200, 166, 143, 133 MHz

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access/precharge

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length

– (1, 2, 4, 8, full page)

• Programmable burst sequence:

• Burst read/write and burst read/single write

operations capability

• Burst termination by burst stop and precharge

• Package:

54-pin TSOP II

54-ball FBGA (8mm x 8mm)

• Operating Temperature Range

bits x 16-bit x 4-bank for improved performance. The

synchronous DRAMs achieve high-speed data transfer

using pipeline architecture. All inputs and outputs signals

refer to the rising edge of the clock input.

KEY TIMING PARAMETERS

Parameter -5 -6 -7 Unit

Clk Cycle Time

other three banks will hide the

cycles and provide

seamless, high-speed, random-access operation.

used to select the bank and row to be accessed (BA0,

BA1 select the bank; A0-A11 select the row). The READ

or WRITE commands in conjunction with address bits

registered are used to select the starting column location

for the burst access.

Programmable READ or WRITE burst lengths consist of

1, 2, 4 and 8 locations, or full page, with a burst terminate

option.

A0-A11 Row Address Input

A0-A7 Column Address Input

BA0, BA1 Bank Select Address

DQ0 to DQ15 Data I/O

CLK System Clock Input

CKE Clock Enable

PIN FUNCTIONS

22, 35

BA0, BA1

20, 21 Input Pin

17 Input Pin

37 Input Pin

38 Input Pin

15, 39 Input Pin

18 Input Pin

When the ACTIVE COMMAND is activated, BA0, BA1

inputs selects a bank to be accessed, and the address

inputs on A0-A11 selects the row. Until a PRECHARGE

command is issued to the bank, the row remains open

for accesses.

CURRENT STATE

Any COMMAND INHIBIT

(NOP/Continue previous operation)

H X X X

NO OPERATION

(NOP/Continue previous operation)

L H H H

Idle ACTIVE (Select and activate row) L L H H

CURRENT STATE COMMANDn ACTIONn CKEn-1 CKEn

All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry H L

All Banks Idle AUTO REFRESH Self Refresh Entry H L

Reading or Writing VALID Clock Suspend Entry H L

H H

FUNCTIONAL DESCRIPTION

The 64Mb SDRAMs (1 Meg x 16 x 4 banks) are quad-bank

DRAMs which operate at 3.3V and include a synchronous

interface (all signals are registered on the positive edge of

the clock signal, CLK). Each of the 16,777,216-bit banks is

organized as 4,096 rows by 256 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented;

a programmed number of locations in a programmed

command. The address bits registered coincident with the

be accessed

(BA0 and BA1 select the bank, A0-A11 select the

ized. The following sections provide detailed information

covering device initialization, register definition, command

descriptions and device operation.

predefined manner.

The 64Mb SDRAM is initialized after the power is applied

to Vdd and Vddq (simultaneously), and the clock is stable

with DQM High and CKE High.

A 100µs delay is required prior to issuing any command

other than a

or a

continue should at least through the end of the period.

With at least one COMMAND INHIBIT or NOP command

having been applied, a PRECHARGE command should

be applied once the 100µs delay has been satisfied. All

must be performed. After the

unknown state. After the Load Mode Register command,

any command.

M11 are reserved for future use.

The mode register must be loaded when all banks are

initiating the subsequent operation. Violating either of these

requirements will result in unspecified operation.

4 0 1 1-2-3-0 1-0-3-2

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, mean-

Operating Mode

The normal operating mode is selected by setting M7 and M8

to zero; the other combinations of values for M7 and M8 are

reserved for future use and/or test modes. The programmed

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued

to a bank within the SDRAM, a row in that bank must be

which selects both the bank and the row to be activated

(see

After opening a row

(issuing an ACTIVE command)

or WRITE command may be issued to that row, subject to

the trcd specification. Minimum trcd should be divided by

the clock period and rounded up to the next whole number

to determine the earliest clock edge after the ACTIVE

A subsequent ACTIVE command to a different row in the

row has been “closed” (precharged). The minimum time

interval between successive ACTIVE commands to the

same bank is defined by trc.

A subsequent ACTIVE command to another bank can be

issued while the first bank is being accessed, which results

in a reduction of total row-access overhead. The minimum

time interval between successive ACTIVE commands to

different banks is defined by trrd.

Example: Meeting tRCD (MIN) when 2 < [tRCD (min)/tCK] ≤ 3