W83195BR-25 200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET W83195BR-25 Data Sheet Revision History Pages Dates Version Version Main Contents On Web 1 n.a. 2 n.a. 02/Apr 1.0 n.a. All of the versions before 0.50 are for internal use. 1.0 Change version and version on web site to 1.0 3 4 5 6 7 8 9 10 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -1- Publication Release Date: May 2000 Revision 1.0 W83195BR-25 1.0 GENERAL DESCRIPTION The W83195BR-25 is a Clock Synthesizer for Intel 815 Solano chipset. W83195BR-25 provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83195BR-25 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI. The W83195BR-25 provides stepless frequency programming by controlling the VCO freq. and the clock output divisor ratio. Also skew of CPU,SDRAM and 3V66 clock outputs are programmable. A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal. The W83195BR-25 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES * * * * * * * 2 CPU clocks (2.5V) 3 3V-66 clocks (3.3V) 12 SDRAM clocks for 3 DIMMs(3.3V) 8 PCI synchronous clocks. Optional single or mixed supply: (VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V) Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200MHz I2C 2-Wire serial interface and I2C read back 0.25% center and 0.5% center type spread spectrum Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) 48 MHz for USB 24 MHz for super I/O * Packaged in 56-pin SSOP * * * * * -2- Publication Release Date: May 2000 Revision 1.0 W83195BR-25 3.0 PIN CONFIGURATION VDDR Xin Xout VSS VSS 3V66-0 3V66-1 3V66-2 VDD3 VDDP PCICLK0/ FS0& PCICLK1/ *FS1 PCICLK2/SEL24_48* VSS PCICLK3^/Mode1* PCICLK4^ PCICLK5^ VDDP PCICLK6^ PCICLK7 VSS PD#/RESET$ *SDCLK *SDATA VDDS SDRAM 11 SDRAM 10 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 23 24 25 26 27 28 REF0/ FS4&^ VddA IOAPIC VDDC CPUCLK0 CPUCLK1 VSS VSS SDRAM 0 SDRAM 1 SDRAM 2 VDDS SDRAM 3 SDRAM 4 SDRAM 5 VSS SDRAM 6 SDRAM 7 SDRAM_F VDDS VSS 24_48MHz/ FS2& 48MHz/ *FS3 ^ VDD48 VDDS SDRAM 8 SDRAM 9 VSS Note: * Internal pull-up &: Internal pull-down ^ 1.5~2 strength $: Open drain 4.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250k pull-up -3- Publication Release Date: May 2000 Revision 1.0 W83195BR-25 4.1 Crystal I/O SYMBOL Xin Xout PIN 2 I/O IN 3 OUT FUNCTION Crystal input with internal loading capacitors(36pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors(36pF). 4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs SYMBOL CPUCLK [0:1] PIN 52,51 I/O OUT PD#/RESET$ 22 IN IOAPIC 54 OUT OUT PCICLK0/ FS0& 38, 48,47,46, 44,43,42,40, 39,31, 30,27, 26 11 PCICLK1/ *FS1 12 I/O PCICLK2/ *SEL24_48 13 I/O PCICLK3/ Mode1* 15 I/O 16,17,19,20 6,7,8 OUT OUT SDRAM_F, SDRAM[0:11] PCICLK [ 4:7 ] 3V66 [0:2] I/O FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU and Chipset. Mode1*=1, Power Down mode when driven low. Mode1*=0, RESET# open drain (4ms low active pulse when Watch Dog time out) Clock outputs synchronous with PCI clock and powered by VddA. SDRAM clock outputs. 3.3V 33MHz PCI clock during normal operation. Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=1). Low skew (< 250ps) PCI clock outputs. Latched input for SEL24_48 at initial power up for the output frequency of 24MHz(HIGH) and 48MHz(LOW) clocks. Low skew (< 250ps) PCI clock outputs. Latched input for Mode* pin at initial power up for the output PD# /RESET# output selection. Low skew (< 250ps) PCI clock outputs. 3.3V output clocks for the chipset. -4- Publication Release Date: May 2000 Revision 1.0 W83195BR-25 4.3 I2C Control Interface SYMBOL PIN I/O FUNCTION 2 *SDATA 24 I/O Serial data of I C 2-wire control interface with internal pull-up resistor. *SDCLK 23 IN Serial clock of I2C 2-wire control interface with internal pull-up resistor. 4.4 Fixed Frequency Outputs SYMBOL REF0 / FS4& PIN I/O 56 I/O FUNCTION 14.318MHz reference clock. This REF output is the stronger buffer for ISA bus loads. Latched input for FS4 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=0). 24_48MHz/FS2& 35 I/O 24MHz or 48MHz output clock. Default is 24MHz. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks(Default=0). 48MHz/ FS3* 34 I/O 48MHz / Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks (Default=1). 4.5 Power Pins SYMBOL VddC,VddA PIN 53,55 FUNCTION Power supply for CPU & IOAPIC, 2.5V or 3.3V. Vdd48 33 Power supply for 48MHz output,3.3V. Vdd3 9 Power supply for 3V_66 output, 3.3V. VddP 10,18 VddR 1 VddS 45,37,32,25 Vss Power supply for PCICLK, 3.3V. Power supply for REF0, 3.3V. Power supply for SDRAM_F,SDRAM[0:11], nominal 3.3V. 4,5,14,21,28,29,36, Circuit Ground. 41, 49.50 -5- Publication Release Date: May 2000 Revision 1.0 W83195BR-25 5.0 Frequency Selection BY hardware FS4 FS3 FS2 FS1 FS0 CPU(MHz) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 83.30 90.00 100.30 103.00 112.50 115.00 120.00 125.00 128.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 125.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 SDRAM(MHz) 3V66(MHz) 82.50 90.00 100.20 102.50 105.00 108.00 112.50 115.50 83.30 90.00 100.30 103.00 112.50 115.00 120.00 125.00 128.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 93.75 97.50 100.28 102.75 105.00 108.75 112.50 115.00 -6- 55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 55.53 60.00 66.87 68.67 75.00 76.67 80.00 83.33 64.00 65.00 66.85 68.50 70.00 72.50 75.00 76.67 62.50 65.00 66.85 68.50 70.00 72.50 75.00 76.67 PCI(MHz) IOAPIC (MHz) 27.50 30.00 33.40 34.17 35.00 36.00 37.50 38.50 27.77 30.00 33.43 34.33 37.50 38.33 40.00 41.67 32.00 32.50 33.43 34.25 35.00 36.25 37.50 38.33 31.25 32.50 33.43 34.25 35.00 36.25 37.50 38.33 13.75 15.00 16.70 17.08 17.50 18.00 18.75 19.25 13.88 15.00 16.72 17.17 18.75 19.17 20.00 20.83 16.00 16.25 16.71 17.13 17.50 18.13 18.75 19.17 15.63 16.25 16.71 17.13 17.50 18.13 18.75 19.17 Publication Release Date: May 2000 Revision 1.0 W83195BR-25 6. SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. Frequency Table Setting by I2C (SEL5 ~ SEL0) SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 83.30 90.00 100.30 103.00 112.50 115.00 120.00 125.00 128.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 125.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 SDRAM (MHz) 82.50 90.00 100.20 102.50 105.00 108.00 112.50 115.50 83.30 90.00 100.30 103.00 112.50 115.00 120.00 125.00 128.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 93.75 97.50 100.28 102.75 105.00 108.75 112.50 115.00 -7- 3V66 (MHz) 55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 55.53 60.00 66.87 68.67 75.00 76.67 80.00 83.33 64.00 65.00 66.85 68.50 70.00 72.50 75.00 76.67 62.50 65.00 66.85 68.50 70.00 72.50 75.00 76.67 PCI(MHz) 27.50 30.00 33.40 34.17 35.00 36.00 37.50 38.50 27.77 30.00 33.43 34.33 37.50 38.33 40.00 41.67 32.00 32.50 33.43 34.25 35.00 36.25 37.50 38.33 31.25 32.50 33.43 34.25 35.00 36.25 37.50 38.33 IOAPIC (MHz) 13.75 15.00 16.70 17.08 17.50 18.00 18.75 19.25 13.88 15.00 16.72 17.17 18.75 19.17 20.00 20.83 16.00 16.25 16.71 17.13 17.50 18.13 18.75 19.17 15.63 16.25 16.71 17.13 17.50 18.13 18.75 19.17 Publication Release Date: May 2000 Revision 1.0 W83195BR-25 SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU (MHz) SDRAM (MHz) 3V66 (MHz) PCI(MHz) IOAPIC (MHz) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 66.8 135.00 142.00 143.00 144.00 146.00 147.00 148.00 133.00 135.00 142.00 143.00 144.00 146.00 147.00 148.00 66.80 67.50 71.00 71.50 72.00 73.00 73.50 74.00 33.40 33.75 35.50 35.75 36.00 36.50 36.75 37.00 16.70 16.88 17.75 17.88 18.00 18.25 18.38 18.50 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 100.20 156.00 158.00 160.00 135.00 139.00 141.00 142.00 143.00 144.00 146.00 147.00 148.00 149.00 153.00 157.00 159.00 162.00 164.00 170.00 175.00 180.00 190.00 200.40 133.00 156.00 158.00 160.00 101.25 104.25 105.75 106.50 107.25 108.00 109.50 110.25 111.00 111.75 114.75 117.75 119.25 121.50 123.00 127.50 116.67 120.00 190.00 133.60 66.80 78.00 79.00 80.00 67.50 69.50 70.50 71.00 71.50 72.00 73.00 73.50 74.00 74.50 76.50 78.50 79.50 81.00 82.00 85.00 58.30 60.00 63.33 66.80 33.40 39.00 39.50 40.00 33.75 34.75 35.25 35.50 35.75 36.00 36.50 36.75 37.00 37.25 38.25 39.25 39.75 40.50 41.00 42.50 29.15 30.00 31.67 33.40 16.70 19.50 19.75 20.00 16.88 17.38 17.63 17.75 17.88 18.00 18.25 18.38 18.50 18.63 19.13 19.63 19.88 20.25 20.50 21.25 14.58 15.00 15.83 16.70 -8- Publication Release Date: May 2000 Revision 1.0 W83195BR-25 6.1 Register 0: CPU Frequency Select Register Bit 7 6 5 4 3 @PowerUp 0 0 0 0 0 Pin - 2 1 0 0 0 0 - Description SSEL3 (Frequency table selection by software via I2C ) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit (2, 7:4) SSEL4 (Frequency table selection by software via I2C ) SSEL5 (Frequency table selection by software via I2C ) 0 = Running 1 = Tristate all outputs 6.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin escription 7 X - FS0# 6 X - FS1# 5 X - FS2# 4 X - FS3# 3 X - FS4# 2 0 - 1 0 - 0 1 - 1 = 0.25% Center type Spread Spectrum Modulation 0 = 0.5% Center type Spread Spectrum Modulation 0 = Normal 1 = Spread Spectrum enabled 1 = Center type Spread Spectrum Modulation 0 = Down type Spread Spectrum Modulation 6.3 Register 2: SDRAM Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 39 40 42 43 44 46 47 48 Description SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive) -9- Publication Release Date: May 2000 Revision 1.0 W83195BR-25 6.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 20 PCICLK7 (Active / Inactive) 6 1 19 PCICLK6 (Active / Inactive) 5 1 17 PCICLK5 (Active / Inactive) 4 1 16 PCICLK4 (Active / Inactive) 3 1 15 PCICLK3 (Active / Inactive) 2 1 13 PCICLK2 (Active / Inactive) 1 1 12 PCICLK1 (Active / Inactive) 0 1 11 PCICLK0 (Active / Inactive) 6.5 Register 4: Additional Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 8 3V66_2(Active / Inactive) 6 1 7 3V66_1(Active / Inactive) 5 1 6 3V66_0(Active / Inactive) 4 1 26 SDRAM11 (Active / Inactive) 3 1 27 SDRAM10 (Active / Inactive) 2 1 30 SDRAM9 (Active / Inactive) 1 1 31 SDRAM8(Active / Inactive) 0 1 38 SDRAM_F (Active / Inactive) 6.6 Register 5: SDRAM Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 1 1 Pin 51 52 Description CSkew2 (CPU to SDRAM skew program bit) CSkew1 (CPU to SDRAM skew program bit) CSkew0 (CPU to SDRAM skew program bit) CASkew2 (CPU to 3V66 skew program bit) CASkew1 (CPU to 3V66 skew program bit) CASkew0 (CPU to 3V66 skew program bit) CPUCLK1(Active / Inactive) CPUCLK0(Active / Inactive) 6.7 Register 6~10: Step-less M/N mode control Register - 10 - Publication Release Date: May 2000 Revision 1.0 W83195BR-25 6.12 Register 11: Winbond Chip ID Register (Read Only) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 0 1 0 0 0 0 Pin - Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID 6.14 Register 12: Winbond Chip ID Register (Read Only) Bit 7 6 5 4 3 2 1 0 Bit6 DS3 0 0 0 0 0 0 0 0 1 1 @PowerUp 0 0 0 1 0 0 1 0 Pin - Register10 Bit3-6 Bit 5 Bit 4 DS2 DS1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 x 1 x Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Winbond Version ID Winbond Version ID Winbond Version ID Ratio Bit 3 DS0 0 1 0 1 0 1 0 1 x x CPU 4 3 2 2 6 3 6 4 2 2 SDRAM 4 3 3 2 4 4 3 3 2 4 - 11 - 3V66 6 6 6 6 6 6 6 6 4 6 Publication Release Date: May 2000 Revision 1.0 W83195BR-25 7.0 SPECIFICATIONS 7.1 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Symbol Parameter Rating Vdd , VIN Voltage on any pin with respect to GND - 0.5 V to + 7.0 V TSTG Storage Temperature - 65C to + 150C TB Ambient Temperature - 55C to + 125C TA Operating Temperature 0C to + 70C 7.2 Electronical Characteristics---Input/Output Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V, VddL1 =VddL2= 2.5V , TA = 0C to +70C Parameter Symbol Min Input Low Voltage VIL Input High Voltage Typ Max Units Test Conditions Vss-0.3 0.8 Vdc VIH 2.0 Vdd+0.3 Vdc Input Low Current IIL -5 A No pull-up resistors Input Low Current IIL -200 A Pull-up resistros Input High Current IIH -5 Input Capacitance 5 A CIN 5 pF Logic inputs COUT 6 pF Output capacitance 45 pF Xin and Xout CPU = 66.6 MHz PCI = 33.3 Mhz with load CINX 27 Operating Supply Current Idd3 100 MA Power Down Supply Current Idd2 600 A Settling Time Ts 3 mS From first crossing to 1% target freq. Delay tPZH,tPZH 1 10 nS Output enable delay tPLZ,tPZH 1 10 nS Output enable delay - 12 - Publication Release Date: May 2000 Revision 1.0 W83195BR-25 - 13 - Publication Release Date: May 2000 Revision 1.0 W83195BR-25 7.3 Electronical Characteristics of CPU Clock Vdd=2.5V +/- 5%; CL=10-20pF Parameter Symbol Min Typ Max Units Ouput Impedance RDSP Ouput Impedance RDSN Output Low Voltage VOL Output High Voltage VOH 2.0 Output Low Current IOL 27 30 MA Output High Current IOH -27 -27 MA Pull-Up Current Min IOH(min) -27 Pull-Up Current Max IOH(max) Rise/Fall Time Min Between 0.4 V and 2.0 V TRF(min) Rise/Fall Time Max Between 0.4 V and 2.0 V TRF(max) 13.5 40 Ohm 13.5 40 Ohm 0.4 V IOL=1mA V IOH=-1mA MA Vout = 1.0 V MA Vout = 2.0V ns 10pF Load 1.6 ns 20pF Load 55 % VT=1.25V -27 0.4 45 Test Conditions Duty Cycle Dt Skew TSK 175 ps VT=1.25V Jitter Tsc-c 250 ps VT=1.25V Max Units 7.4 Electronical Characteristics of 3V66 Clock Vdd=3.3V +/- 5%; CL=10-30pF Parameter Symbol Min Typ Ouput Impedance RDSP 15 55 Ohm Ouput Impedance RDSN 15 55 Ohm Output Low Voltage VOL 0.55 V IOL=1mA Output High Voltage VOH 2.4 V IOH=-1mA Output Low Current IOL 30 38 MA Output High Current IOH -33 -33 MA Rise/Fall Time Min Between 0.4 V and 2.0 V TRF(min) 0.4 Rise/Fall Time Max Between 0.4 V and 2.0 V TRF(max) 45 Test Conditions ns 10pF Load 1.6 ns 20pF Load 55 % VT=1.5V Duty Cycle Dt Skew TSK 175 ps VT=1.5V Jitter Tsc-c 500 ps VT=1.5V - 14 - Publication Release Date: May 2000 Revision 1.0 W83195BR-25 7.5 Electronical Characteristics of SDRAM Clock Vdd=3.3V +/- 5%; CL=20-30pF Parameter Symbol Min Typ Max Units Ouput Impedance RDSP Ouput Impedance RDSN Output Low Voltage VOL Output High Voltage VOH 2.4 Output Low Current IOL 54 54 MA Output High Current IOH -54 -45 MA Rise/Fall Time Min Between 0.4 V and 2.0 V TRF(min) 0.4 Rise/Fall Time Max Between 0.4 V and 2.0 V TRF(max) 13.5 40 Ohm 13.5 40 Ohm 0.45 V IOL=1mA V IOH=-1mA 45 Test Conditions ns 10pF Load 1.6 ns 20pF Load 55 % VT=1.5V Duty Cycle Dt Skew TSK 250 ps VT=1.5V Jitter Tsc-c 250 ps VT=1.5V Max Units 7.6 Electronical Characteristics of PCI Clock Vdd=3.3V +/- 5%; CL=10-30pF Parameter Symbol Min Typ Ouput Impedance RDSP 15 55 Ohm Ouput Impedance RDSN 15 55 Ohm Output Low Voltage VOL 0.55 V IOL=1mA Output High Voltage VOH 2.4 V IOH=-1mA Output Low Current IOL 30 38 MA Output High Current IOH -33 -33 MA Rise/Fall Time Min Between 0.4 V and 2.0 V TRF(min) 0.5 Rise/Fall Time Max Between 0.4 V and 2.0 V TRF(max) 45 Test Conditions ns 10pF Load 2.0 ns 20pF Load 55 % VT=1.5V Duty Cycle Dt Skew TSK 500 ps VT=1.5V Jitter Tsc-c 500 ps VT=1.5V - 15 - Publication Release Date: May 2000 Revision 1.0 W83195BR-25 7.7 Electronical Characteristics of 48MHz, REF Clock Vdd=3.3V +/- 5%; CL=10-20pF Parameter Symbol Min Typ Max Units Ouput Impedance RDSP 20 55 Ohm Ouput Impedance RDSN 20 55 Ohm Output Low Voltage VOL 0.4 V IOL=1mA Output High Voltage VOH 2.4 V IOH=-1mA Output Low Current IOL 29 27 MA Output High Current IOH -29 -23 MA RiseTime TR 1.8 4 ns 10pF Load Fall Time TF 1.7 4 ns 20pF Load Duty Cycle Dt 55 % VT=1.5V Skew TSK 500 ps VT=1.5V Jitter Tsc-c 1000 ps VT=1.5V 45 - 16 - Test Conditions Publication Release Date: May 2000 Revision 1.0 W83195BR-25 8.0 ORDERING INFORMATION Part Number Package Type Production Flow W83195BR-25 56 PIN SSOP Commercial, 0C to +70C 9.0 HOW TO READ THE TOP MARKING W83195BR-25 28051234 814GAB 1st line: Winbond logo and the type number: W83195BR-25 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G A B 814: packages made in '98, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 17 - Publication Release Date: May 2000 Revision 1.0 W83195BR-25 10.0 PACKAGE DRAWING AND DIMENSIONS .035 .045 END VIEW HE SEE DETAIL "A" D MAX. 0.110 0.016 0.092 0.0135 c 0.13 0.005 0.010 D HE 18.2 18.42 18.54 910.16 10.31 10.41 E 7.42 0.51 7.52 0.64 0.61 0.81 1.40 0.720 0.400 0.292 0.020 0.024 0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 A2 e L L1 A A1 DIMENSION IN INCH MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 A A1 A2 b 0.40/0.50 DIA TOP VIEW DIMENSION IN MM SYMBOL .045 .055 Y PARTING LINE SIDE VIEW 0 0.25 7.59 0.76 1.02 0.08 8 0.003 0 8 DETAIL"A" Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics No. 4, Creation Rd. III Science-Based Industrial Park Rm. 803, World Trade Square, Tower II (North America) Corp. Hsinchu, Taiwan TEL: 886-35-770066 123 Hoi Bun Rd., Kwun Tong 2727 North First Street Kowloon, Hong Kong San Jose, California 95134 TEL: 852-27516023-7 TEL: 1-408-9436666 FAX: 852-27552064 FAX: 1-408-9436668 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Taipei Office 9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use. - 18 - Publication Release Date: May 2000 Revision 1.0