Data Sheet 1
LHF00L02
Data Sheet 8M LPC Flash Memory
FEATURES
• Conforms to Intel LPC Interface Specification 1.0
• Optimized Array Block Architecture
– Fifteen 64KB Uniform Blocks
– Eight 8KB Boot Sectors
– Boot Sector Data protection for each 8KB Sector
– Full Chip Erase (A/A Mode Only)
•V
CC = 3.0 V - 3.6 V Operation
• Extended Cycling Capability
– Minimum 100,000 Block Erase Cycles
• Low Power Consumption (LPC Interface)
– Standby Current: 15 µA (MAX.)
– Read Current: 15 mA (MAX.)
– Erase or Program Current: 25 mA (MAX.)
• Erase or Program Operation
– Byte Program Time: 25 µs (TYP.)
– Sector Erase Time: 0.6 sec. (TYP.)
– Block Erase Time: 1.2 sec. (TYP.)
– Full Chip Erase Time: 40 sec. (TYP.)
– Sector Rewrite Time: 0.8 sec. (TYP.)
– Block Rewrite Time: 2.8 sec. (TYP.)
• Operating Temperature 0°C to +85°C
• CMOS Process (P-type silicon substrate)
• Two Operational Modes
– Low Pin Count (LPC) Interface mode for In-system
Operation
– Address/Address Multiplexed Interface (A/A)
Mode for Production Erasing and Programming
• LPC Interface Mode
– Five-Signal Communication Interface Supporting
Byte Read and Write
– 33 MHz Clock Frequency Operation
–WP
and TBL Pins Provide Hardware Data
protection for Entire Chip and/or Boot Sector
– Status Polling and Toggle Bit for End-of-Write
Detection
– Five GPI Pins for System Design Flexibility
– ID Pins for Mutli-chip Selection
• Multi Byte Read Mode (LPC)
– Maximum 128-Byte Sequential Read Operation
for Data Transfer
• A/A Interface Mode
– 11 Pin Multiplexed Address and 8-pin Data I/O
Interface
– Supports Fast In-system or PROM Programming
for Manufacturing
• CMOS and PCI I/O Compatibility
• ETOX™ Nonvolatile Flash Technology
• Not Designed or Rated as Radiation Hardened
DESCRIPTION
The LHF00L02 is offered in a 32-pin TSOP (normal
bend) package. Refer to Figure 1 for pinouts and Table
1 for pin descriptions.
Figure 1. LHF00L02 Pinout
LHF00L02-1
TOP VIEW32-PIN TSOP
2
3
4
5
8
9
MODE
29
28
27
26
25
24
21
18
6
7
A10
NC
NC
NC
NC
23
22
DQ4
10
11
12
31
30 VCC
13 20 A0
A1
A2
19
DQ5
DQ6
DQ7
WE
OE
14
15
16
NOTE: Functions inside ( ) are for LPC mode.
17
A9
RST
A8
A7
A6
A5
A4
DQ3
DQ1
DQ2
DQ0
GND
A3
32
1
RY/BY
VCC
R/C
(MODE)
(GPI4)
(CE)
(NC)
(NC)
(NC)
(GPI3)
(RST)
(GPI2)
(GPI1)
(GPI0)
(WP)
(TBL)
(RY/BY)
(VCC)
(LCLK)
(RES)
(RES)
(RES)
(INIT)
(VCC)
(LFRAME)
(LAD1)
(LAD2)
(LAD0)
(ID0)
(ID1)
(ID2)
(ID3)
(GND)
(LAD3)
(RES)
* ETOX is a trademark of Intel Corporation.
LHF00L02 8M LPC Flash Memory
2 Data Sheet
Table 1. Pin Descriptions
SYMBOL TYPE INTERFACE DESCRIPTION
A/A LPC
RST Input • •
Reset When LOW (VIL), RST resets internal automation and inhibits erase and program
operations, which provides data protection. RST HIGH (VIH) enables normal operation.
After power-up or reset mode, the device is automatically set to read array mode.
MODE Input • •
Mode This pin determines which interface is operational. This pin must be held HIGH
(VIH) for A/A mode and LOW (VIL) for LPC mode. This pin is internally pulled-down with
a resistor between 20 kΩ - 100 kΩ.
INIT Input • Initialize This is a second reset pin for in-system use. This pin is internally combined
with the RST pin; if this pin or RST is driven LOW, identical operations occur.
CE Input • Chip Enable This signal must be asserted to select the device. When CE is LOW, the
device is enabled. When CE is HIGH, the device is placed in low power (standby) mode.
LFRAME Input • Frame Indiciates the start of a data transfer operation. This pin is also used to abort
an LPC cycle in process.
LAD3 - LAD0
Input/
Output •Address and Data Provides address and data for LPC mode.
LCLK Input • Clock To provide a clock input to the control unit.
ID3 - ID0Input •
Identification Inputs These four pins are part of the mechanism that allows multiple
parts to be attached to the same bus. The strapping of these pins is used to identify the
component. These pins are internally pulled-down with a resistor between 20 kΩ - 100 kΩ.
GPI4 - GPI0Input • General Purpose Inputs These individual inputs can be used for additional flexibility.
The state of these pins can be read through GPI registers.
TBL Input •
Top Boot Lock When LOW, prevents erasing and programming to the boot sectors
at top (highest address) of memory. When TBL is HIGH, it disables hardware data pro-
tection for the the boot sectors. Do not float this pin.
WP Input •
Write Protect When LOW, prevents erasing and programming to all blocks other than
top boot sector. When WP is HIGH, it disables hardware data protection for these
blocks. Do not float this pin.
RES • Reserved Allows pins to float.
OE Input • Output Enable Gates the device’s outputs during a read cycle.
WE Input • Write Enable Controls writes to the memory array. Data is latched on the rising edge
of WE.
R/C Input • Row/Column Select For A/A interface mode, this pin determines whether the ad-
dress pins are porting to the row address, or to the column address.
A10 - A0Input •
Address Inputs Inputs for low-order addresses during read and write operations. Ad-
dresses are internally latched by R/C during an erase or program cycle. These address-
es share the same pins as the high-order address inputs.
DQ7 - DQ0
Input/
Output •
Data Inputs/Outputs Inputs data and commands during write cycles, outputs data
during memory array, status register and identifier code reads. Data pins float to high-
impedance (High-Z) when the chip or outputs are deselected. Data is internally latched
during an erase or program cycle.
RY/BY
Open
Drain
Output
••
Ready/Busy This output pin is a reflection LPF bit 7 in the status register. This pin is
used to determine the erase or program completion. This pin must be pulled-up with an
external resistor on board.
VCC Supply • •
Device Power Supply (3.0 V - 3.6 V): With VCC ≤ VLKO, all write attempts to the flash
memory are inhibited. Device operations at invalid VCC voltage (refer to DC Character-
istics) produce spurious results and should not be atempted.
GND Supply • • Ground Do not float any ground pins.
NC • • No Connect Lead is not internally connected; it may be driven or foated.
8M LPC Flash Memory LHF00L02
Data Sheet 3
DEVICE OPERATION
Mode Selection
The LHF00L02 can operate in two interface modes:
• LPC interface mode for in-system erasing and pro-
gramming
• Address/Address Multiplexed (A/A) interface mode
for factory erasing and programming.
The state of the MODE pin determines which inter-
face is in use. If the MODE pin is set HIGH, the device is
in A/A mode; if the MODE pin is set LOW, the device is
in the LPC mode. The MODE selection pin must be con-
figured prior to device operation.
LPC Mode
The LPC mode uses a 5-signal communication inter-
face, 4-bit address/data bus, LAD3 - LAD0, and a control
line, LFRAME, to control operation. Cycle type opera-
tions such as Memory Read and Memory Write are
defined in Intel Low Pin Count Interface Specification,
Rev. 1.0. Erase and Program command sequences are
incorporated into the standard LPC memory cycle.
LPC signals are transmitted via the 4-bit Address/
Data bus (LAD3 - LAD0), and follow a particular
sequence, depending on whether they are Read or
Write operations. The standard LPC memory cycle is
defined in Table 2 and Table 3.
CE, LFRAME
The CE (Chip Enable) pin, controls read and write
access. To enable the output, the CE pin must be
driven LOW one cycle prior to LFRAME being drive
LOW. For write (erase or program) cycles, the CE pin
must remain LOW during the internal operation. When
CE is HIGH, the chip is placed in standby mode.
The LFRAME signifies the start of a frame or the ter-
mination of a broken frame. Asserting LFRAME for one
or more clock cycle and driving a valid ‘START’ value
on LAD3 - LAD0 will initiate operation. The device
enters standby mode when LFRAME and CE are HIGH
and no internal operation is in progress.
ABORT MECHANISM
If LFRAME is driven LOW for 4 clock cycles during a
LPC cycle, the cycle will be terminated and the device
will wait for the ABORT command. To return the device
to the ready mode, the host must drive LAD3 - LAD0
with ‘1111b’ (‘ABORT’ command) while LFRAME is
driven LOW, and LAD3 - LAD0 must remain unchanged
until LFRAME goes to VIH (refer to Figure 18). When an
abort procedure is performed between two command
write cycles, such as sector/block erase or byte pro-
gram, the device turns the bus around to the host but
the command termination for the internal operation is
not guaranteed. If the system needs to abort after the
first command cycle, the host must write ‘FFH’ and
check the status register after performing the abort pro-
cedure. The status register indicates termination of
internal operation and error conditions. If an abort
occurs during the internal write cycle, the data may be
incorrectly programmed or erased. The write operation
must complete prior to initiation of an abort command.
Check the write status with status polling (DQ7) or tog-
gle bit (DQ6). One other option is to wait for the fixed
write time to expire.
Status Polling DQ7 (LPC Mode, A/A Mode)
When the device is performing an internal operation
(program, erase, etc.), WSM (Write State Machine)
status bit DQ7 (SR.7) will read ‘0’. Once the internal
operation is completed, DQ7 will read ‘1’. The SR.7 bit
can be polled to find the end of the operation. The other
status bits (SR.5-0) should not be checked until the
WSM completes the operation and the status bit SR.7
is ‘1’. Refer to Table 13 for status register definitions.
Toggle Bit DQ6 (LPC Mode, A/A Mode)
During any automatic internal operation (program,
erase, etc.) consecutive attempts to read DQ6 (SR.6)
will produce alternating ‘0’s and ‘1’s; i.e., toggling
between ‘0’ and ‘1’. When the internal operation is com-
pleted, the value will be static.
LHF00L02 8M LPC Flash Memory
4 Data Sheet
LPC MEMORY CYCLE FIELD DEFINITIONS
Table 2. LPC Read Cycle Field Definitions
FIELD CLOCKS LAD3 - LAD0
DIRECTION DESCRIPTION
START 1 Input Start of Cycle: ‘0000b’ appears on LPC bus to indicate the start.
CYCTYPE 1 Input Cycle Type: LAD3 - LAD2 must be ‘01b’ for memory cycle. LAD1 indicates the direction
of the transfer: ‘0b’ for read. LAD0 is reserved for future implementation.
ADDR 8 Input
Address Phase for Memory Cycle: LPC supports 32-bit addressing. It is transferred most
significant nibble first. All the values of A31 - A24 must be set to ‘1’. For A23 - A20 values,
refer to Table 6.
TAR 2 Input
then High-Z
Turn-Around: Indicates a turn-around cycle to drive LAD3 - LAD0 to ‘1111b’ during the
first clock and to drive LAD3 - LAD0 to High-Z during the second clock by the host.
Sync 1 - 3 Output
Sync: Synchronizes to host or peripheral by adding wait states. ‘0000b’ means Ready,
‘0101b’ means Short Wait. The product supports three types of wait states: ‘no wait’,
‘1-wait’, or ‘2-wait’.
Data 2 Output Data Phase: The data byte is transferred least significant nibble first. DQ3 - DQ0 on
LAD3 - LAD0 first, DQ7 - DQ4 on LAD3 - LAD0 last.)
TAR 2 Output then
High-Z
Turn-Around: Indicates a turn-around cycle to drive LAD3 - LAD0 to ‘1111b’ during the first
clock and to drive LAD3 - LAD0 to High-Z during the second clock by the Flash Memory.
Table 3. LPC Write Cycle Field Definitions
FIELD CLOCKS LAD3 - LAD0
DIRECTION DESCRIPTION
START 1 Input Start of Cycle: ‘0000b’ appears on LPC bus to indicate the start.
CYCTYPE 1 Input
Cycle Type: Indicates the type of cycle. LAD3 - LAD2 must be ‘01b’ for memory cycle.
LAD1 indicates the direction of the transfer: ‘1b’ for write. LAD0 is reserved for future
implementation.
ADDR 8Input
Address Phase for Memory Cycle: LPC supports 32-bit addressing. It is transferred
most significant nibble first. All the values of A31 - A24 must be set to ‘1’. For A23 - A20
values, refer to Table 6.
Data 2Input Data Phase: The data byte is transferred least significant nibble first. DQ3 - DQ0 on
LAD3 - LAD0 first, DQ7 - DQ4 on LAD3 - LAD0 last.)
TAR 2 Input
then High-Z
Turn-Around: Indicates a turn-around cycle to drive LAD3 - LAD0 to ‘1111b’ during the
first clock and to drive LAD3 - LAD0 to High-Z during the second clock by the last com-
ponents driving LAD3 - LAD0.
Sync 1Output Sync: This device only supports ‘0000b’ to indicate ready.
TAR 2Output then
High-Z
Turn-Around: Indicates a turn-around cycle to drive LAD3 - LAD0 to ‘1111b’ during the first
clock and to drive LAD3 - LAD0 to High-Z during the second clock by the Flash Memory.
8M LPC Flash Memory LHF00L02
Data Sheet 5
Multi-byte Read (LPC Mode)
This device provides Multi-byte Read operation in
LPC mode. Multi-Byte Read mode enables two or more
byte of sequential data, read at one operation cycle.
This increases data transfer rate compared with normal
memory read operation. The transfer multi-byte size
can be selected from four types.
Table 4. LPC Multi-byte Read Cycle Field Definitions
FIELD CLOCKS LAD3 - LAD0
DIRECTION DESCRIPTION
START 1 Input Start of Cycle: ‘0000b’ appears on LPC bus to indicate the start of cycle
CYCTYPE 1 Input Cycle Type: ‘1100b’ = Multi-byte Read
MSIZE 1 Input
Transfer Multi-byte Size for LAD0 - LAD1:
00 = 2 byte
01 = 8 byte
01 = 32 byte
11 = 128 byte
ADDR 8 Input Address: Start address of Multi-byte Read: A31 - A0.
TAR 2 Input then
High-Z Turn-Around: ‘111b’ and High-Z
Sync 1 N+1 Output
Sync:
‘0101b’ = Short Wait
‘0000b’ = Ready
(N = the number of Short Wait)
Data 1 2 Output Data Phase: First byte; DQ3 - DQ0 on LAD3 - LAD0 (1st cycle)
DQ7 - DQ4 on LAD3 - LAD0 (2nd cycle)
Sync M (N+1) × M Output
Sync:
‘0101b’ = Short Wait
‘0000b’ = Ready
(N = the number of Short Wait) (M = number of Multi Byte)
Data M 2 × M Output Data Phase: Multi-byte; DQ3 - DQ0 on LAD3 - LAD0 (1st cycle)
DQ7 - DQ4 on LAD3 - LAD0 (2nd cycle)
TAR 2 Output then
High-Z Turn-Around: ‘1111b’ and High-Z
Table 5. LPC Multi-byte Read Bandwidth (ƒ(CLK) = 33 MHz)
128-BYTE
MULTI-BYTE READ CLOCKS UNIT 128-BYTE
NORMAL READ CLOCKS UNIT
START 1 START 1 × 128
CYCTYPE 1 CYCTYPE 1 × 128
MSIZE+ADDR 9 MSIZE+ADDR 8 × 128
TAR 2 TAR 2 × 128
Sync (no-wait) 1 × 128 Sync (no-wait) 1 × 128
Data 2 × 128 Data 2 × 128
TAR 2 TAR 2 × 128
Total Clocks 399 Total Clocks 17 × 128
Transfer Time 12 µs Transfer Time 65 µs
Bandwidth 10.69 Mbit/s Bandwidth 1.96 Mbit/s
LHF00L02 8M LPC Flash Memory
6 Data Sheet
Multiple Device Selection (LPC Mode)
Multiple LPC Flash devices may be strapped to
increase memory densities in a system. LPC protocol
of the product supports up to 8 LPC Flash devices.
The four ID pins, ID3 - ID0, allow up to 8 devices to
be attached to the same bus by using different ID strap-
ping in a system. If the memory is used as a boot
device, ID3 - ID0 must be strapped to ‘000x’, all subse-
quent devices should use a sequential up-count strap-
ping (i.e. ‘000x’, ‘001x’, ‘010x’, ‘011x’, etc.) ID0 is not
used and may be either ‘0’ or ‘1’.
General Purpose Input (GPI) Register
(LPC Mode)
The GPI_REG (General Purpose Input Register)
reads the status of the GPI4 - GPI0 pins on the chip.
Since this is a pass-through register, there is no default
value, only the state of the pins at power-up. The pins
must have stable data from before the start of the cycle
that reads the GPI_REG until after the cycle is com-
plete. These pins must not be left to float and they
should be driven VIL or VIH.
Refer to Table 7 for the GPI_REG bits and function,
and Table 8 for memory address locations for respec-
tive device strapping. If this address is input, GPI_REG
can be read in Read Identifier Codes mode, Read Sta-
tus Register mode or Read Array mode.
Product Identifier Codes
(LPC Mode, A/A Mode)
The product identifier codes identify the device and
manufacturer as SHARP.
• In LPC mode:
– The Read Identifier Codes command is unneces-
sary and only an address shown in Table 9 is re-
quired. However, A22 must be ‘0’ in this operation.
Command operation is also possible after writing
the Read Identifier Code command. In this mode,
the state of A22 does not matter.
• In A/A mode:
– The Read Identifier Codes command is necessar.
– Refer to Table 12 for command definitions.
Figure 2. Multiple LPC Device Mapping
Table 6. ID Strapping Values (LPC Mode)
DEVICE
NUMBER ID3 - ID0A23 A22 A21 - A20
0
(Boot device) 000x
1Read:
1 = Memory Read
11
1001x 10
2010x 01
3011x 00
4100x
0
Write:
0 or 1 = Memory
Write
11
5101x 10
6110x 01
7111x 00
LHF00L02-2
8M
8M
Boot Device 0
Device 1
8M
8M
Device 6
Device 7
.
.
.
Table 7. General Purpose Input Register
BIT FUNCTION
7:5 Reserved for future implementation
4 GPI4: Reads status of general purpose input (Pin 6)
3 GPI3: Reads status of general purpose input (Pin 11)
2 GPI2: Reads status of general purpose input (Pin 12)
1 GPI1: Reads status of general purpose input (Pin 13)
0 GPI0: Reads status of general purpose input (Pin 14)
Table 8. Memory Map for General Purpose
Input Register Addresses
DEVICE NUMBER GPI_REG
0 (Boot device) FFBC0100H
1 FFAC0100H
2 FF9C0100H
3 FF8C0100H
4 FF3C0100H
5 FF2C0100H
6 FF1C0100H
7 FF0C0100H
8M LPC Flash Memory LHF00L02
Data Sheet 7
Lock Registers (LPC Mode, A/A Mode)
This memory offers double write protection. The
boot lock provides hardware write protection for each
8KB boot sector. Furthermore, the whole block lock
provides software write protection for all sectors and
blocks. The write protection status is controlled by each
lock bit. Refer to Write Protection’ for details. The pro-
tection status can be checked via the lock registers.
NOTES:
1. A31 - A20 are not used in A/A mode.
2. A22 must be ‘0’ when the registers are read in LPC mode.
3. A23, A21 - A20 correspond to the address for ID strapping (refer to Table 6). DQ7 - DQ2 are reserved for future implementation.
4. The registers shown here must not be read while the WSM is busy.
Table 9. LPC Flash Registers Configuration Map
DEVICE ADDRESS
REGISTER NAME
PROTECTED
ADDRESS RANGE
(A19 - A0)
DEFAULT
VALUE TYPE
A23 A22 A21 - A20 A19 - A0
1 or 0
0
(Register
Access)
11 or 10 or
01 or 00
XX002H Whole Block Lock Register FFFFFH - 00000H DQ1 = 1 RO
FE002H Block Lock Register (Sector 7) FFFFFH - FE000H DQ0 = 0 RO
FC002H Block Lock Register (Sector 6) FDFFFH - FC000H DQ0 = 0 RO
FA002H Block Lock Register (Sector 5) FBFFFH - FA000H DQ0 = 0 RO
F8002H Block Lock Register (Sector 4) F9FFFH - F8000H DQ0 = 0 RO
F6002H Block Lock Register (Sector 3) F7FFFH - F6000H DQ0 = 0 RO
F4002H Block Lock Register (Sector 2) F5FFFH - F4000H DQ0 = 0 RO
F2002H Block Lock Register (Sector 1) F3FFFH - F2000H DQ0 = 0 RO
F0002H Block Lock Register (Sector 0) F1FFFH - F0000H DQ0 = 0 RO
C0100H LPC General Purpose Input Register N/A N/A RO
00001H Device Code Register N/A C9H RO
00000H Manufacturer Code Register N/A B0H RO
LHF00L02 8M LPC Flash Memory
8 Data Sheet
Write Protection
TBL AND WP HARDWARE WRITE PROTECTION
(LPC MODE)
The top boot lock (TBL) and write protect (WP) pins
are provided for hardware write protection of the mem-
ory area in the product. TBL pin is used to write protec-
tion of 8 boot sectors (8KB) at the highest memory
address range for the product. WP pin is used for the
remaining blocks in the flash memory.
An active LOW signal at the TBL pin prevents erase
and program operations in the boot sectors. TBL pro-
tection is effective only in the sector in which the boot
lock bit is set. When TBL pin is held HGH, the write pro-
tection of the boot sectors is disabled. The WP pin
serves the same function for the remaining blocks of
the memory array. The TBL and WP write protection
functions operate independently of one another.
Both TBL and WP pins must be set to their required
protection states prior to starting an erase or program
operation. A logic level change occurring at the TBL or
WP pin during an erase or program operation could
cause unpredictable results.
WHOLE BLOCK LOCK SOFTWARE WRITE
PROTECTION (LPC MODE, A/A MODE)
The whole block lock is provided for software write
protection. Whole block lock protects all sectors and
blocks by lock bit. The lock bit is set to locked after
power-up or reset operation. The lock bit must be
cleared (to unlocked) before starting erase or program
operation. The lock bit is cleared by clear Whole Block
Lock Bit operation. After the erase or program opera-
tion is finished, the memory array can be protected by
set whole block lock bit operation.
NOTES:
1. Lock Bit: ‘1’ = Locked State, ‘0’ = Unlocked State.
2. x = Don’t Care
Figure 3. Memory Map
TBL FOR BOOT SECTOR 0 - 7
64KB
BLOCK 15
FFFFFH
FE000H
FC000H
FA000H
F8000H
F6000H
F4000H
F2000H
F0000H
EFFFFH
E0000H
D0000H
C0000H
B0000H
A0000H
90000H
80000H
70000H
60000H
50000H
40000H
30000H
20000H
10000H
00000H
8KB Boot Sector
TOP BOOT
7
8KB Boot Sector 6
8KB Boot Sector 5
8KB Boot Sector 4
8KB Boot Sector 3
8KB Boot Sector 2
8KB Boot Sector 1
8KB Boot Sector 0
64KB Block 14
64KB Block 13
64KB Block 12
64KB Block 11
64KB Block 10
64KB Block 9
64KB Block 8
64KB Block 7
64KB Block 6
64KB Block 5
64KB Block 4
64KB Block 3
64KB Block 2
64KB Block 1
64KB Block 0
WP FOR BLOCK 0 - 14
LHF00L02-4
Table 10. Write Protection Alternatives
OPERATION
WHOLE
BLOCK
LOCK BIT
TBL BOOT
LOCK BIT WP EFFECT
Sector Erase or Block Erase or
Full Chip Erase or Byte Program
1 x x x All sectors and blocks are Locked
0
VIL 1 x Boot sector is Locked
VIL 0 x Boot sector is Unlocked
VIH x x All boot sectors are Unlocked
VIH xV
IL
The remaining blocks other than boot
sectors are Locked
VIH xV
IH All sectors and blocks are Unlocked
8M LPC Flash Memory LHF00L02
Data Sheet 9
A/A Mode
Commands are used to initiate memory operation
functions. The data portion of the software command
sequence is latched on the rising edge of WE. During
the software command sequence, the row address is
latched on the falling edge of R/C and the column
address is latched on the rising edge of R/C.
NOTES:
1. Never hold OE LOW and WE LOW at the same time.
2. RST at GND ±0.2 V ensures the lowest power consumption.
3. Command writes involving sector/block erase, full chip erase,
byte program, set whole block lock bit, clear whole block lock bit,
set boot lock bit and clear boot lock bits execute reliably when
VCC = 3.0 V - 3.6 V.
4. Refer to Table 12 for valid DIN during a write operation.
5. x = Don’t Care.
6. DQ refers to DQ7 - DQ0.
Figure 4. Block Diagram
Table 11. Operation Modes Selection
MODE RST OE WE ADDRESS DQ NOTES
Read Array VIH VIL VIH AIN DOUT 1
Output Disable VIH VIH VIH x High-Z
Standby VIH VIH VIH x High-Z
Reset VIL x x x High-Z 2
Read Identifier Codes VIH VIL VIH
Refer to
Table 9
Refer to
Table 9 1
Read Status Register VIH VIL VIH AIN AOUT 1
Write VIH VIH VIL AIN AIN 1, 3, 4
LAD3 - LAD0
ID3 - ID0
A10 - A0
GPI4 - GPI0
DQ7 - DQ0
LCLK LPC
INTERFACE ADDRESS
BUFFERS
and
LATCHES
COMMAND
USER
INTERFACE
LFRAME
R/C
OE
WE
8M FLASH
CELL ARRAY
Y-DECODER
I/O BUFFERS
and
DATA LATCHES
X-DECODER
CONTROL
LOGIC
MODE RST CE
TBL WP INIT
LHF00L02-3
LHF00L02 8M LPC Flash Memory
10 Data Sheet
Command Definitions
NOTES:
1. Bus operations are defined in Table 11.
2. Any command is acceptable not only when A22 = ‘1’ but also when A22 = ‘0’ in LPC mode.
X = Any valid address within the device.
IA = Identifier codes address (Refer to Table 9).
BA = Address within the sector/block for sector/block erase.
WA = Address of memory location (for write).
SA = Address within the boot sector (for set boot lock bit).
ID = Data to be read from identifier codes. (Refer to Table 9).
SRD = Data to be read from status register. (Refer to Table 13 for a description of the status register bits.
WD = Data to be written at location WA.
3. The device returns to the read array mode even after a Clear Status Register operation by RST/INIT.
4. Following the Read Identifier Codes command, read operations access manufacturer code, device code
and block lock configuration code (Refer to Table 9). The identifier codes must not be read while the WSM is busy.
5. Sector/block erase, full chip erase and byte program operations cannot be executed in the boot sector
when TBL goes to VIL. Sector/block erase, full chip erase and byte program operations cannot be executed
to blocks other than boot sector when WP goes to VIL.
6. Whole block lock bit must be cleared when executing sector/block erase, full chip erase and byte program operations.
Sector/block erase, full chip erase and byte program operations cannot be executed the block lock bit is set.
7. Supported in A/A Mode only. Any boot sector which is locked by the boot lock bit is protected from alteration.
Boot lock bit should be cleared before performing an erase operation.
8. Either 40H or 10H are recognized as the program first bus cycle command.
9. Lock bit can be set to each sector within the boot block (block 15). Since this lock bit is non-volatility,
it holds the lock state even after power-off or reset.
10.All boot lock bits of each sector are cleared at a time.
SA = Address within the boot sector (F0000H-FFFFH).
11.Commands other than those shown above are reserved for future implementations.
Table 12. Commmand Definitions
COMMAND
INTERFACE BUS
CYCLES
REQ’D
FIRST BUS CYCLE SECOND BUS CYCLE
NOTES
A/A LPC OPER1ADDR2DATA OPER1ADDR2DATA
Read Array • • 1 Write X FFH 3
Read Identifier Codes • • ≥2 Write X 90H Read IA ID 4
Read Status
Register • • 2 Write X 70H Read X SRD
Clear Status
Register •• 1 WriteX 50H 3
Sector/Block Erase • • 2 Write BA 20H Write BA D0H 5, 6
Full Chip Erase • • 2 Write X 30H Write X D0H 5, 6, 7, 8
Byte Program • • 2 Write X 40H or 10H Write WA WD 5, 6, 7, 9
Set Whole Block Lock Bit • • 2 Write X 60H Write X X
Clear Whole Block Lock Bit • • 2 Write X 60H Write X X 6
Set Boot Lock Bit • • 2 Write X 60H Write SA SA 9
Clear Boot Lock Bits • • 2 Write X 60H Write SA SA 10
8M LPC Flash Memory LHF00L02
Data Sheet 11
Status Register
NOTES:
1. Check SR.7 or SR.6 or RY/BY to determine sector/block erase, full chip erase, byte program,
set whole block lock bit, clear whole block lock bit, set boot lock bit or clear boot lock bits completion.
SR.5, SR.4, SR.3, and SR.1 are invalid while SR.7 = ‘0’.
2. If both SR.5 and SR.4 =1 after a sector/block erase, full chip erase, set whole block lock bit,
clear whole block lock bit, set boot lock bit and clear boot lock bits attempt, an improper command sequence was entered.
3. SR.3 indicates the program or erase voltage conditions. The program or erase voltage is the internal voltage
which is used for the program or erase operation in the flash memory. SR.3 does not provide a continuous indication
of the program or erase voltage level. The WSM interrogates and indicates the program or erase voltage level only
after Sector/Block Erase, Full Chip Erase, Byte Program, Set Boot Lock Bit, and Clear Boot Lock Bits command sequences.
4. SR.1 does not provide a continuous indication of the block lock bit. The WSM interrogates TBL, WP or
the block lock bit only after Sector/Block Erase, Full Chip Erase or Byte Program command sequences.
It informs the system, depending on the attempted operation, if the block is locked.
5. SR.2 and SR.0 is reserved for future use and should be masked out when polling the status register.
76543210
WSMS TB ECLS PSLS PVEVS /// DPS ///
Table 13. Status Register Definitions
REGISTER
NUMBER
REGISTER
SYMBOL DEFINITION NOTES
SR.7 WSMS
Write State Machine Status
1 = Ready
0 = Busy
1
SR.6 TB Toggle Bit toggles between ‘0’ and ‘1’ during an erase or program operation.
SR.5 ECLS
Sector/Block Erase, Full Chip Erase and Clear Boot Lock Bits Status
1 = Error in Sector/Block Erase, Full Chip Erase or Clear Boot Lock Bits
0 = Successful Sector/Block Erase, Full Chip Erase or Clear Boot Lock Bits
2
SR.4 PSLS
Byte Program and Set Boot Lock Bit Status
1 = Error in Byte Program or Set Boot Lock Bit
0 = Successful Byte Program or Set Boot Lock Bit
2
SR.3 PVEVS
Program Voltage or Erase Voltage Status
1 = Invalid Program or Erase Voltage Detect, Operation Abort
0 = Program or Erase Voltage OK
3
SR.2 /// Reserved for Future Enhancements
SR.1 DPS
Device Protect Status
1 = Block Lock Bit, Block lock bit and/or RP lock detected, operation abort
0 = Unlock
4
SR.0 /// Reserved for Future Enhancements 5
LHF00L02 8M LPC Flash Memory
12 Data Sheet
Figure 5. Automated Block Erase Flowchart
START BUS
OPERATION COMMAND COMMENTS
WRITE D0H,
BLOCK ADDRESS
SR.7 = 0
NO
YES
1
1
1
1
0
0
0
0
FULL STATUS
CHECK IF DESIRED
BLOCK ERASE
COMPLETE
WRITE 20H,
BLOCK ADDRESS
BLOCK ERASE
SUCCESSFUL
VPP
RANGE ERROR
READ STATUS REGISTER
DATA (see above)
SUSPEND
BLOCK
ERASE
SUSPEND
BLOCK
ERASE
LOOP
SR.3 =
SR.1 =
Write
Write
Read
Standby
Erase
Setup
Erase
Confirm
Data = 20H
Addr = Within Block to be Erased
Data = D0H
Addr = Within Block to be Erased
Status Register Data
Repeat for subsequent block erasures.
Full status check can be done after each block erase
or after a sequence of block erasures.
Write FFH after the last operation to place the device
into read array mode.
Check SR.7
1 = WSM Ready
0 = WSM Busy
BUS
OPERATION COMMAND
FULL STATUS CHECK PROCEDURE
COMMENTS
Standby
Standby
Standby
Check SR.3
1 = V
PP
Error Detect
Check SR.4, 5
Both 1 = Command Sequence Error
Standby Check SR.5
1 = Block Erase Error
CSR.5, SR.4, SR.3, and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is checked.
If an error is detected, clear the Status Register before attempting a
retry or other error recovery operations.
28F016SCT-L95-5
READ STATUS
REGISTER
Check SR.1
1 = Device Protect Detect
RP = V
IH
, Block Lock-Bit
is Set. Only required for
systems implementing
lock-bit configuration.
DEVICE
PROTECT ERROR
1
COMMAND SEQUENCE
ERROR
SR.4, 5 =
SR.5 = BLOCK ERASE
ERROR
8M LPC Flash Memory LHF00L02
Data Sheet 13
Figure 6. Automated Byte Write Flowchart
START BUS
OPERATION COMMAND COMMENTS
WRITE BYTE
DATA and ADDRESS
SR.7 = 0
NO
YES
1
1
1
1
0
0
0
FULL STATUS
CHECK IF DESIRED
BYTE WRITE
COMPLETE
WRITE 40H,
ADDRESS
BYTE WRITE
SUCCESSFUL
VPP
RANGE ERROR
READ STATUS REGISTER
DATA (see above)
SUSPEND
BYTE
WRITE
SUSPEND
BYTE
WRITE
LOOP
SR.3 =
SR.1 =
Write
Write
Read
Standby
Setup
Byte Write
Byte
Write
Data = 40H
Addr = Location to be Written
Data = Data to be Written
Addr = Location to be Written
Status Register Data
Repeat for subsequent byte writes.
SR full status check can be done after each byte write, or after
a sequence of byte writes.
Write FFH after the last byte write operation to place the device
into read array mode.
Check SR.7
1 = WSM Ready
0 = WSM Busy
BUS
OPERATION COMMAND
FULL STATUS CHECK PROCEDURE
COMMENTS
Standby
Standby
Standby
Check SR.3
1 = VPP Error Detect
Check SR.4
1 = Data Write Error
SR.4, SR.3, and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are written
before full status is checked.
If an error is detected, clear the Status Register before attempting a
retry or other error recovery operations.
28F016SCT-L95-6
READ STATUS
REGISTER
Check SR.1
1 = Device Protect Detect
RP = VIH, Block Lock-Bit
is Set. Only required for
systems implementing
lock-bit configuration
DEVICE
PROTECT ERROR
BYTE WRITE
ERROR
SR.4 =
LHF00L02 8M LPC Flash Memory
14 Data Sheet
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
NOTES:
1. Commercoal operating temperature range.
2. All specified voltages are with respect to GND. During transitions,
this level may undershoot to -2.0 V for periods < 20 ns. Maximum
DC voltage during transitions may overshoot to VCC + 2.0 V for
periods < 20 ns.
3. Output shorted for no more than one second. No more than one
output shorted at a time.
Operating Conditions
NOTE: *Refer to DC Characteristics tables for voltage-range-specific specification.
CAPACITANCE
TA = +25°c, F = 1 MHz
NOTE: Sampled, not 100% tested.
AC Input/Output Test Conditions
PARAMETER CONDITION MIN. MAX. NOTE
Operating Temperature During Read, Block Erase, Byte Write, and Lock Bit Configuration 0°C 85°C 1
Storage Temperature Under Bias 10°C 85°C
Non Bias -65°C 125°C
Voltage on any pin Except VCC -0.5 V 0.5 V 2
VCC Supply Voltage -2.0 V 3.9 V 2
Output Short Circuit Current 100 mA 3
Stressing the device beyond the ‘Absolute Maximum Ratings’ may
cause permanent damage. These are stress ratings only. Operation be-
yond the ‘Operating Conditions’ is not recommended and extended ex-
posure beyond the ‘Operating Conditions’ may affect device reliability.
CAUTION
SYMBOL PARAMETER MIN. TYP. MAX. UNIT TEST CONDITION
TAOperating Temperature 0 +25 +85 °C Ambient Temperature
VCC VCC Supply Voltage* 3.0 3.3 3.6 V
Sector/Block Erase Cycling 100,000 Cycles
SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITION
CIN Input Capacitance 7 10 pF VIN = 0.0 V
CI/O Input/Output Capacitance 9 12 pF VI/O = 0.0 V
Figure 7. Transient Input/Output Reference
Waveform for VCC = 3.0 V - 3.6 V
INPUT
TEST POINTS
OUTPUT
3.0
0.0
1.5 1.5
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1'
and 0.0 V for a Logic '0'. Input timing begins
and output timing ends at 1.5 V. Input rise
and fall times (10% to 90%) < 5 ns.
LHF00L02-5
Table 14. Configuration Capacitance Loading Value
CONFIGURATION CL (pF)
VCC = 3.0 V - 3.6 V 30
Figure 8. Transient Equivalent Testing Load Circuit
DEVICE
UNDER
TEST
CL INCLUDES
JIG CAPACITANCE CL
RL = 3.3 kΩ
OUT
1N914
1.3 V
LHF00L02-6
8M LPC Flash Memory LHF00L02
Data Sheet 15
DC Characteristics
VCC = 3.0 V to 3.6 V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values
at VCC = 3.3 V and TA = +25°C unless VCC is specified.
2. CMOS inputs are either VCC ±0.2 V or GND ±0.2 V.
3. Sector/block erase, full chip erase, byte program, set whole block lock bit, clear whole block lock bit,
set boot lock bit and clear boot lock bits operations are inhibited when VCC ≤ VLKO.
These operations are not guaranteed outside the specified voltage (VCC = 3.0 V - 3.6 V)
4. Sampled, not 100% tested.
5. Includes RY/BY.
SYMBOL PARAMETER MIN. TYP. MAX. UNIT TEST CONDITIONS NOTES
ILI Input Load Current -1 +1 µA
VCC = VCCMax,
VIN /V
OUT = VCC or GND
1
ILID
Input Load Current for
MODE, ID3 - ID0 pins -200 +200 µA 1
ILO Output Leakage Current -1 +1 µA 1
ICCS1
VCC Standby Current (LPC
Interface) 515µA
CMOS Inputs, VCC = VCCMax,
CE = VIH, RST = VCC ±0.2 V 1, 2, 5
ICCS2
VCC Standby Current
(LPC Interface) 515µA
CMOS Inputs, VCC = VCCMax,
CE = VIL, ƒ(CLK) = 33 MHz
LFRAME = VIH, RST = VCC ±0.2 V
1, 2, 5
ICCRY
VCC Ready Mode Current
(LPC Interface) 58mA
CMOS Inputs, VCC = VCCMax,
CE = VIL, ƒ(CLK) = 33 MHz
LFRAME = VIL, RST = VCC ±0.2 V
1, 2, 5
ICCS3
VCC Standby Current
(A/A Interface) 58mA
CMOS Inputs, VCC = VCCMax,
RST = VCC ±0.2 V,
R/C = OE = WE, VIH
1, 2, 5
ICCD VCC Reset Current 5 15 µA CMOS Inputs, VCC = VCCMax,
CE = VIH, RST = VCC ±0.2 V 1
ICCR1
VCC Read Current
(LPC Interface) 15 mA
CMOS Inputs, VCC = VCCMax,
CE = LFRAME = VIL,
ƒ(CLK) = 33 MHz, IOUT = 0 mA
1, 2
ICCR2
VCC Read Curent
(A/A Interface) 15 mA CMOS Inputs, VCC = VCCMax,
ƒ = 4 MHz IOUT = 0 mA 1, 2
ICCW
VCC Byte Program, Set Boot
Lock Bit Current 25 mA CMOS Inputs, VCC = VCCMax 1, 2, 4
ICCE
VCC Sector/Block Erase,
Full Chip Erase, Clear Boot
Lock Bits Current
25 mA CMOS Inputs, VCC = VCCMax 1, 2, 4
VIH Input High Voltage 0.5 × VCC VCC + 0.5 V VCC = VCCMax 4
VIL Input Low Voltage -0.5 0.3 × VCC VV
CC = VCCMin 4
VOH Output HIGHVoltage 0.9 × VCC VV
CC = VCCMi., IOH = 0.5 mA 4
VOL Output LOW Voltage 0.1 × VCC VV
CC = VCCMin, IOL = 1.5 mA 4, 5
VLKO VCC Lockout Voltage 2.0 V 3
LHF00L02 8M LPC Flash Memory
16 Data Sheet
AC Characteristics (LPC Mode)
VCC = 3.0 V - 3.6 V, TA = 0°C to +85°C
NOTES:
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Typical values measured at VCC = 3.3 V and tA = +25°C. Assumes TBL, WP and corresponding lock bits are not set.
3. Sampled, not 100% tested.
4. Excludes external system-level overhead.
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES
tCYC Clock Cycle Time 30 ns 1, 2
tHIGH LCLK HIGH Time 11 ns 1, 2
tLOW LCLK LOW Time 11 ns 1, 2
LCLK Slew Rate (peak-to-peak) 1 4 V/ns 1, 2
tSU Data Set-up Time to Clock Rising 9 ns 1, 2
tDH Data Hold Time from Clock Rising 0 ns 1, 2
tFSU LFRAME Set-up Time to Clock Rising 18 ns 1, 2
tFDH LFRAME Hold Time from Clock Rising 2 ns 1, 2
tVAL Clock Rising to Data Valid 2 15 ns 1, 2
tON Clock Rising to Output in Low-Z 2 ns 1, 2, 3
tOFF Clock Rising to Output in High-Z 28 ns 1, 2, 3
tWQV1 Byte Program Time 25 200 µs 1, 2, 3, 4
tWQV2 Sector Erase Time 0.6 5 s 1, 2, 3, 4
tWQV3 Block Erase Time 1.2 6 s 1, 2, 3, 4
tWQV4 Full Chip Erase Time 40 200 s 1, 2, 3, 4
tSWBL Set Whole Block Lock Bit Time 5 8 µs 1, 2, 3, 4
tCWBL Clear Whole Block Lock Bit Time 5 8 µs 1, 2, 3, 4
tSTBL Set Boot Lock Bit Time 35 200 µs 1, 2, 3, 4
tCTBL Clear Boot Lock Bits Time 0.4 1 s 1, 2, 3, 4
Figure 9. Output Timing Parameters
VIL
LCLK
VIH
VOL
LAD3 - LAD0
(VALID OUTPUT DATA)
tVAL
tON
tOFF
LAD3 - LAD0
(FLOAT OUTPUT DATA)
VOH
VOL
VOH
LHF00L02-8
Figure 10. Input Timing Parameters
tDH
tSU
LHF00L02-9
VIL
LCLK
VALID
INPUT
VIH
VIL
VIH
LAD3 - LAD0
(VALID INPUT DATA)
8M LPC Flash Memory LHF00L02
Data Sheet 17
Figure 11. LCLK Waveform
Figure 12. Read Cycle Timing (LPC Mode)
tCYC
tHIGH
0.6 VCC
0.2 VCC
0.5 VCC
0.4 VCC
LCLK
0.3 VCC
tLOW
0.4 VCC
PEAK-TO-PEAK (MIN.)
LHF00L02-7
LFRAME
VIH, VOH
VIL, VOL
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
tCYC
tDH
tSU tVAL
VIL
CE
LAD3 - LAD0
010Xb
MEMORY
READ
CYCLE
A[31:28]0000b
START
See
Note ADDRESS TAR SYNC DATA NEXT START
1 CLOCK
NOTE: All the values of A[31:24] must be '1'.
1 CLOCK 2 CLOCKS
1 CLOCK
1 CLOCKDATA OUT
2 CLOCKS
LOAD ADDRESS
IN 8 CLOCKS
A[23:20]
A[27:24]
A[15:12]
A[11:8]A[19:16] A[3:0]
A[7:4]
TRI-STATE
TA R
0000b1111b 0000b
D[7:4]
D[3:0]
tFDH
tFSU
LHF00L02-10
LHF00L02 8M LPC Flash Memory
18 Data Sheet
Figure 13. Write Cycle Timing (LPC Mode)
LFRAME
VIH
VIL
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
tCYC
tDH
tSU
VIL
CE
LAD3 - LAD0
011Xb
MEMORY
WRITE
CYCLE
A[31:28]0000b
START ADDRESS TAR SYNCDATA NEXT START
NOTE: All the values of A[31:24] must be '1'.
A[23:20]
A[27:24]
A[15:12]
A[11:8]A[19:16] A[3:0]
A[7:4]
D[7:4]
TA R
1111bD[3:0] 0000b
0000b
TRI-STATE
LHF00L02-11
1 CLOCK
1 CLOCK
2 CLOCKS
1 CLOCK
1 CLOCKLOAD DATA IN
2 CLOCKS
LOAD ADDRESS
IN 8 CLOCKS
See
Note
tFDH
tFSU
8M LPC Flash Memory LHF00L02
Data Sheet 19
Figure 14. Multi-byte Read Cycle Timing (LPC Mode)
Figure 15. Multi-byte Read Exceeding the Last Address (LPC Mode)
NOTES:
1. All the values of A[31:24] must be '1'.
2. 128 byte multi-byte read, no wait states. LHF00L02-12
LFRAME
VIH, VOH
VIL, VOL
VIH, VOH
VIL, VOL
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
VIL
CE
LAD3 - LAD0
1100b
Multi-byte
READ
CYCLE
XX110000b
START MSIZE
See
Note 1 SYNCSYNC
1st BYTE
DATA
2nd BYTE
DATA
TA R
A[27:24]
A[31:28]
A[19:16]
A[15:12]A[23:20] A[7:4]
A[11:8]
1111b
D[3:0]
0000b
TRI-STATE
D[7:4]
D[3:0] 0000bD[7:4]
D[3:0]
1 CLOCK
1 CLOCK
2 CLOCKS 2 CLOCKS
1 CLOCK
LOAD ADDRESS
IN 8 CLOCKS
DATA
OUT
LFRAME
VIH
VIL
LCLK
VIH
VIL
VIH
VIL
CE
LAD3 - LAD0
0000b
SYNC
127th
BYTE
DATA
128th BYTE
DATA
(the last byte)
SYNCSYNC
D[7:4]
D[3:0]
D[3:0]
D[7:4]0000bD[3:0]
TA R
D[7:4]0000bD[3:0]
0000bD[7:4]
1 CLOCK 2 CLOCKS
See Note 2
See Note 2
DATA
OUT
VIH, VOH
VIL, VOL
VIH
VIL
LCLK
LAD3 - LAD0
D[3:0]
D[7:4]
0000b
125th BYTE
DATA
126th BYTE
DATA
127th BYTE
DATA
128th BYTE
DATA
(the last byte)
SYNC SYNC SYNCSYNC
1111b
0000b
0000b
1111b1111b 0000b
TA R
1111b
1111b
1111b
(DATA FOR
THE LAST
ADDRESS)
NOTE: '1111b' is presented on data field until the last byte. LHF00L02-13
1111b*
LHF00L02 8M LPC Flash Memory
20 Data Sheet
Figure 16. Byte Program Cycle Timing (LPC Mode)
NOTE: All the values of A[31:24] must be '1'. LHF00L02-14
LFRAME
VIH
VIL
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
VIL
CE
LAD3 - LAD0
011Xb
MEMORY
WRITE
CYCLE
A[31:28]0000b
1st
START
See
Note
ADDRESS
(WA)
See
Note
ADDRESS
(WA)
TAR SYNCDATA
START
NEXT
COMMAND
A[23:20]
A[27:24]
A[15:12]
A[11:8]A[19:16] A[3:0]
A[7:4]
D[7:4]
TA R
1111bD[3:0] 0000b
0000b
TRI-STATE
1 CLOCK
1 CLOCK
2 CLOCKS
1 CLOCK
1 CLOCKLOAD DATA '40'
IN 2 CLOCKS
LOAD ADDRESS
IN 8 CLOCKS
LFRAME
VIH
VIL
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
VIL
CE
LAD3 - LAD0
011Xb
MEMORY
WRITE
CYCLE
A[31:28]0000b
2nd
START TAR SYNC
DATA
INTERNAL
OPERATION
START
A[23:20]
A[27:24]
A[15:12]
A[11:8]A[19:16] A[3:0]
A[7:4]
D[7:4]
TA R
1111bD[3:0] 0000b
TRI-STATE
1 CLOCK
1 CLOCK
2 CLOCKS
1 CLOCK
LOAD DATA IN
2 CLOCKS
LOAD ADDRESS
IN 8 CLOCKS
8M LPC Flash Memory LHF00L02
Data Sheet 21
Figure 17. Sector/Block Erase Cycle Timing (LPC Mode)
NOTES:
1. All the values of A[31:24] must be '1'.
2. BA = Sector/block address: A11 - A0 Don’t Care. LHF00L02-15
LFRAME
VIH
VIL
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
VIL
CE
LAD3 - LAD0
011Xb
MEMORY
WRITE
CYCLE
A[31:28]0000b
1st
START
See
Note 2
See
Note 1
ADDRESS
(BA)
See
Note 2
See
Note 1
ADDRESS
(BA)
TAR SYNCDATA
START
NEXT
COMMAND
A[23:20]
A[27:24]
A[15:12]
XXXXA[19:16] XXXX
XXXX
D[7:4]
TA R
1111bD[3:0] 0000b
0000b
TRI-STATE
1 CLOCK
1 CLOCK
2 CLOCKS
1 CLOCK
1 CLOCKLOAD DATA '20'
IN 2 CLOCKS
LOAD ADDRESS
IN 8 CLOCKS
LFRAME
VIH
VIL
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
VIL
CE
LAD3 - LAD0
011Xb
MEMORY
WRITE
CYCLE
A[31:28]0000b
2nd
START TAR SYNC
DATA
INTERNAL
OPERATION START
A[23:20]
A[27:24]
A[15:12]
XXXXA[19:16] XXXX D[7:4]
XXXX
TA R
1111bD[3:0] 0000b
TRI-STATE
1 CLOCK
1 CLOCK
2 CLOCKS 1 CLOCK
LOAD ADDRESS
IN 8 CLOCKS
LOAD DATA 'D0'
IN 2 CLOCKS
LHF00L02 8M LPC Flash Memory
22 Data Sheet
Figure 18. Status Polling, Toggle Bit Timing (LPC Mode)
NOTE: All the values of A[31:24] must be '1'. LHF00L02-16
LFRAME
VIH
VIL
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
VIL
CE
LAD
3
- LAD
0
011Xb
MEMORY
WRITE
CYCLE
WRITE THE LAST COMMAND (PROGRAM, ERASE, ETC.) TO THE DEVICE IN LPC MODE
INTERNAL OPERATION (PROGRAM, ERASE, ETC.) NOT YET COMPLETE
INTERNAL OPERATION (PROGRAM, ERASE, ETC.) COMPLETE
A[31:28]0000b
START See
Note ADDRESS TAR SYNCDATA
INTERNAL
OPERATION
START
A[23:20]
A[27:24]
A[15:12]
XXXXA[19:16] XXXX
XXXX
D[7:4]
TA R
1111bD[3:0] 0000b
TRI-STATE
RY/BY
VOH
VOL
1 CLOCK
1 CLOCK
2 CLOCKS
1 CLOCK
LOAD DATA 'D'
IN 2 CLOCKS
LOAD ADDRESS
IN 8 CLOCKS
LFRAME
VIH, VOH
VIL, VOL
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
VIL
CE
LAD
3
- LAD
0
010Xb
MEMORY
READ
CYCLE
A[31:28]0000b
START See
Note ADDRESS TAR SYNC DATA
A[23:20]
A[27:24]
A[15:12]
A[11:8]
A[19:16] A[3:0]
A[7:4]
TA R
0000b
XXXXb
1111b
TRI-STATE
0000b
RY/BY
VOH
VOL
1 CLOCK
1 CLOCK
1 CLOCK
1 CLOCK2 CLOCKS DATA OUT
2 CLOCKS
LOAD ADDRESS
IN 8 CLOCKS
LFRAME
VIH
VIL
LCLK
VIH
VIL
RST
VIH
VIL
VIH
VIL
CE
LAD
3
- LAD
0
010Xb
MEMORY
READ
CYCLE
A[31:28]0000b
START See
Note ADDRESS TAR SYNC DATA
NEXT
START
NEXT
START
A[23:20]
A[27:24]
A[15:12]
A[11:8]A[19:16] A[3:0]
A[7:4]
TA R
1111b 0000b D7, D6, XX
XXXXb
TRI-STATE
RY/BY
VOH
VOL
1 CLOCK
1 CLOCK
2 CLOCKS
HIGH Z
HIGH Z
1 CLOCK
1 CLOCK
DATA OUT
2 CLOCKS
LOAD ADDRESS
IN 8 CLOCKS
VIH, VOH
VIL, VOL
0000b
D7, D6, XX
8M LPC Flash Memory LHF00L02
Data Sheet 23
RESET AND ABORT OPERATIONS (LPC MODE) VCC = 3.0 V - 3.6 V, TA = 0°C - +85°C
NOTES:
1. Reset is not guaranteed if tRSTP < 100 ns.
2. Sampled, not 100% tested.
3. There will be a latency of tRSTE if a reset/abort procedure is performed during an internal operation.
4. If RST/INT asserted while a sector/block erase, full chip erase, byte program, set whole block lock bit,
clear whole block lock bit, set boot lock bit and clear boot lock bits operations are not executing,
the reset will complete within 100 ns.
SYMBOL PARAMETER MIN. MAX. UNIT NOTES
tPRSTH VCC 3.0 V stable to RST/INIT HIGH 100 ns 2
tPRSTL VCC 3.0 V stable to RST/INIT LOW 1 ms 2
tKRST Clock stable to RST/INIT LOW 100 µs 2
tRSTP RST/INIT Pulse Width LOW 100 ns 1, 2
RST/INIT Slew Rate 50 mV/ns 2
tRSTF RST/INIT LOW to Output in HIGH Z 48 ns 2
tRSTL RST/INIT HIGH to LFAME LOW 1 µs 2, 3
tABTL Abort Command to LFRAME LOW 60 ns 2
tRSTE0 RST/INIT LOW to Reset during internal operation 30 µs 2, 4
LHF00L02 8M LPC Flash Memory
24 Data Sheet
Figure 19. Reset Operation by RST/INIT Timing (LPC Mode)
Figure 20. Abort Operation Timing (LPC Mode)
tPRSTL
tKRST
VIH
VIL
VCC (MIN.)
GND
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tPRSTH tRSTP
tRSTF
High-Z
VCC
LAD3 - LAD0
LCLK
RST/INIT
High-Z
DURING ERASE
or PROGRAM
ERASE
or PROGRAM
OPERATION
ABORTED
tRSTL
tRSTE
LFRAME
RY/BY
LHF00L02-17
VIH
VIL
VIH
VIL
VIH
VIL
LAD3 - LAD0
LFRAME
PERIPHERAL MUST STOP DRIVING
4 CLOCKS
1111b: ABORT COMMAND
START
0000b
LCLK
tABTL
LHF00L02-18
8M LPC Flash Memory LHF00L02
Data Sheet 25
AC Characteristics (A/A Mode)
READ CHARACTERISTICS
VCC = 3.0 V - 3.6 V, TA = 0°C - +85°C
NOTES:
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. OE may be delayed up to TAA - TOE after the rising edge of R/C without impact to TAA.
3. Sampled, not 100% tested.
SYMBOL PARAMETER MIN. MAX. UNIT NOTES
tRC Read Cycle Time 250 ns
tRSTA RST High Recovery to Row Address 1 us
tAS Address Setup to R/C 50 ns
tAH Address Hold from R/C 50 ns
tAA Address to Output Delay 100 ns 2
tOE OE to Output Delay 60 ns 2
tOLZ OE to Output in Low-Z 0 ns 3
tOHZ OE to Output in High-Z 35 ns 3
tOH Output Hold from Address 0 ns 3
Figure 21. Read Cycle Timing (A/A Mode)
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
DATA VALID
tRSTA
tAS tAH tAS tAH
tAA
tRC
tOE
tOLZ
tOH
High-ZHigh-Z
tOHZ
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
R/C
DQ7 - DQ0
RST
ADDRESSES
WE
OE
VIH
VIL
LHF00L02-19
LHF00L02 8M LPC Flash Memory
26 Data Sheet
WRITE CHARACTERISTICS
VCC = 3.0 V - 3.6 V, TA = 0°C - +85°C
NOTES:
1. Typical values measured at VCC = 3.3 V and TA = +25°C. Assumes TBL, WP and corresponding lock bits are not set.
2. The timing characteristics for reading the status register during sector/block erase, byte program,
set whole block lock bit, clear whole block lock bit, set boot lock bit and clear boot lock bits operations
are the same as during read-only operations. Refer to Read Characteristics (A/A Mode) for read-only operations.
3. Sampled, not 100% tested.
4. Refer to Table 12 for valid address and data for sector/block erase, full chip erase, byte program,
set whole block lock bit, clear whole block lock bit, set boot lock bit and clear boot lock bits.
5. Excludes external system-level overhead.
SYMBOL PARAMETER MIN. TYP. (1) MAX. UNIT NOTE
tWC Write Cycle Time 200 ns
tRSTA RST HIGH Recovery to Row Address 30 µs
tAS Address Setup to R/C 50 ns 4
tAH Address Hold from R/C 50 ns
tCWH R/C to WE HIGH Time 50 ns
tOES OE High Setup Time 20 ns
tOEH OE High Hold Time 20 ns
tOEP OE to Status Polling Delay 40 ns 2
tOET OE to Toggle Bit Delay 40 ns 2
tWP WE Pulse Width LOW 100 ns
tWPH WE Pulse Width HIGH 100 ns
tDS Data Setup to WE HIGH 50 ns 4
tDH Data Hold from WE HIGH 5 ns
tIDA ID Access Time 150 ns
tRB WE HIGH to RY/BY going LOW 100 ns 3
tWQV1 Byte Program Time 25 200 µs 3, 5
tWQV2 Sector Erase Time 0.6 5 s 3, 5
tWQV3 Block Erase Time 1.2 6 s 3, 5
tWQV4 Full Chip Erase Time 40 200 s 3, 5
tSWBL Set Whole Block Lock Bit Times 5 8 µs 3, 5
tCWBL Clear Whole Block Lock Bit Time 5 8 µs 3, 5
tSTBL Set Boot Lock Bit Time 35 200 µs 3, 5
tCTBL Clear Boot Lock Bits Time 0.4 1 s 3, 5
8M LPC Flash Memory LHF00L02
Data Sheet 27
Figure 22. Write Cycle Timing (A/A Mode)
SYMBOL PARAMETER MIN. MAX. UNIT NOTES
tPRSTH VCC 3.0 V stable to RST HIGH 100 ns 2
tPRSTL VCC 3.0 V stable to RST LOW 1 ms 2
tRSTP RST Pulse Width LOW 100 ns 1, 2
RST Slew Rate 50 mV/ns 2
tRSTF RST LOW to Output in High-Z 48 ns 2
tRSTA RST HIGH to Row Address Valid 1 µs 2, 3
tRSTE RST LOW to Reset during erase or program operation 30 µs 2, 4
tRSTA
ROW
ADDRESS
DATA VALID
COLUMN
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
DATA VALID
SRD VALID
ID VALID
High-Z
tAS tAH tAS tAH
tCWH
tOES tOEH
tDS tDH
tWC
tWQV1, 2, 3, 4
tIDA
tRB
tWP tWPH
High-Z
High-Z
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
R/C
DQ7 - DQ0
VOH
VOL
RY/BY
RST
ADDRESSES
WE
OE
VIH
VIL
LHF00L02-20
VIH, VOH
VIL, VOL
LHF00L02 8M LPC Flash Memory
28 Data Sheet
RESET AND ABORT OPERATIONS
VCC = 3.0 V - 3.6 V, TA = 0°C - +85°C
NOTES:
1. Sampled, not 100% tested.
2. Reset is not guaranteed tRSTP < 100 ns.
3. There will be a latency of tRSTE if a reset procedure is performed during an internal operation.
4. Reset will complete within 100 ns, if RST asserted while a sector/block erase, full chip erase,
byte program, set whole block lock bit, clear whole block lock bit, set boot lock bit and
clear boot lock bits operations are not executing.
SYMBOL PARAMETER MIN. MAX. UNIT NOTES
tPRSTH VCC 3.0 V stable to RST HIGH 100 ns 1
tPRSTL VCC 3.0 V stable to RST LOW 1 ms 1
tRSTP RST Pulse Width LOW 100 ns 1, 2
RST Slew Rate 50 mV/ns 1
tRSTF RST LOW to Output in High-Z 48 ns 1
tRSTA RST HIGH to Row Address Valid 1 µs 1, 3
tRSTE RST LOW to Reset during erase or program operation 30 µs 1, 4
Figure 23. Reset Operation Timing (A/A Mode)
tPRSTL
tRSTP
tRSTF
tRSTE
tPRSTH
tRSTA
ROW ADDRESS
DATA VALID
High-Z
ERASE
or PROGRAM
OPERATION
ABORTED
VCC (MIN.)
GND
VIH
VIL
VIH
VIL
VIH
VIL
R/C
VCC
ADDRESSES
RST
DQ7 - DQ0
VOH
VOL
RY/BY
VOH
VOL
LHF00L02-21
8M LPC Flash Memory LHF00L02
Data Sheet 29
PACKAGING
Figure 24. TSOP032-P-0813 Dimensions
32TSOP (TSOP032-P-0813)
32TSOP-0813
DETAIL
0.08 M
0.10
0.50
0.20 ±0.08
0.15 ±0.05
0.15
0.425
0.10 ±0.10
1.0 ±0.10
1.20 MAX.
SEATING PLANE
See Detail
8.0 ±0.05
1.0 ±0.10
0.10 ±0.10
11.80 ±0.05
12.40 ±0.10
0.55 ±0.15
0 - 8°
0.25 0.425
13.40 ±0.10
1
16 17
32
0.80 ±0.15
NOTE: Dimensions in mm.
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
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(Shanghai) Co., Ltd.
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Head Office:
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Email: smc@china.global.sharp.co.jp
SHARP-ROXY (Hong Kong) Ltd.
3rd Business Division,
17/F, Admiralty Centre, Tower 1
18 Harcourt Road, Hong Kong
Phone: (852) 28229311
Fax: (852) 28660779
www.sharp.com.hk
Shenzhen Representative Office:
Room 13B1, Tower C,
Electronics Science & Technology Building
Shen Nan Zhong Road
Shenzhen, P.R. China
Phone: (86) 755-3273731
Fax: (86) 755-3273735
LHF00L02 8M LPC Flash Memory
©2004 by SHARP Corporation Reference Code SMA04035
