© Semiconductor Components Industries, LLC, 2017
July, 2017 − Rev. 1 1Publication Order Number:
NCV8133/D
NCV8133
500 mA, Very Low Dropout
Bias Rail CMOS Voltage
Regulator
The NCV8133 is a 500 mA VLDO equipped with NMOS pass
transistor and a separate bias supply voltage (VBIAS). The device
provides very stable, accurate output voltage with low noise suitable
for space constrained, noise sensitive applications. In order to
optimize performance for battery operated portable applications, the
NCV8133 features low IQ consumption. The XDFN6 1.2 mm x
1.2 mm package is optimized for use in space constrained
applications.
Features
•Input Voltage Range: 0.8 V to 5.5 V
•Bias Voltage Range: 2.4 V to 5.5 V
•Fixed Output Voltage Device
•Output Voltage Range: 0.8 V to 2.1 V
•±1.5% Accuracy over Temperature, 0.5% VOUT @ 25°C
•Ultra−Low Dropout: Typ. 140 mV at 500 mA
•Very Low Bias Input Current of Typ. 80 mA
•Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA
•Logic Level Enable Input for ON/OFF Control
•Output Active Discharge Option Available
•Stable with a 2.2 mF Ceramic Capacitor
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable; Device Temperature Grade 1: −40°C to
+125°C Ambient Operating Temperature Range
•These are Pb−Free Devices
Typical Applications
•Automotive, Consumer and Industrial Equipment Point of Load
Regulation
•Battery−powered Equipment
•FPGA, DSP and Logic Power Supplies
•Switching Power Supply Post Regulation
•Cameras, DVRs, STB and Camcorders
BIAS
IN
EN
OUT
GND
2.2 mF
VOUT
1 V up to 500 mA
VBIAS
>2.7 V
VIN
1.5 V
VEN
1 mF
100 nF NCV8133
Figure 1. Typical Application Schematics
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See detailed ordering and shipping information on page 10 o
f
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
XDFN6
CASE 711AT
PIN CONNECTIONS
GND
T
1
2
3
6
5
4
OUT
NC
EN
IN
GND
BIAS
(Top VIew)
XX = Specific Device Code
M = Date Code
XX M
NCV8133
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3
PIN FUNCTION DESCRIPTION
Pin No.
XDFN6 Pin Name Description
1 OUT Regulated Output Voltage pin
2 N/C Not internally connected (Note 1)
3 EN Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode.
4 BIAS Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage
Lockout Circuit.
5 GND Ground
6 IN Input Voltage Supply pin
Pad Should be soldered to the ground plane for increased thermal performance.
1. True no connect. Printed circuit board traces are allowable
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage (Note 2) VIN −0.3 to 6 V
Output Voltage VOUT −0.3 to (VIN+0.3) ≤ 6 V
Chip Enable, Bias and Adj Input VEN, VBIAS −0.3 to 6 V
Output Short Circuit Duration tSC unlimited s
Maximum Junction Temperature TJ150 °C
Storage Temperature TSTG −55 to 150 °C
ESD Capability, Human Body Model (Note 3) ESDHBM 2000 V
ESD Capability, Machine Model (Note 3) ESDMM 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
2. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
3. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002
ESD Machine Model tested per AEC−Q100−003
Latchup Current Maximum Rating ≤150 mA per AEC−Q100−004.
RECOMMENDED OPERATING CONDITIONS
Rating Symbol Min Max Unit
Input Voltage VIN (VOUT + VDO_IN) 5.5 V
Bias Voltage VBIAS (VOUT + 1.4) ≥ 2.4 5.5 V
Junction Temperature TJ−40 +125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Characteristics, XDFN6 1.2 mm x 1.2 mm
Thermal Resistance, Junction−to−Air RqJA 170 °C/W
NCV8133
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ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VBIAS = 2.7 V or (VOUT + 1.6 V), whichever is greater, VIN = VOUT(NOM) +
0.3 V, IOUT = 1 mA, VEN = 1 V, unless otherwise noted. CIN = 1 mF, COUT = 2.2 mF. Typical values are at TJ = +25°C. Min/Max values are
for −40°C ≤ TJ ≤ 125°C unless otherwise noted. (Note 4)
Parameter Test Conditions Symbol Min Typ Max Unit
Operating Input Voltage
Range VIN VOUT +
VDO 5.5 V
Operating Bias Voltage
Range VBIAS (VOUT +
1.40) ≥ 2.4 5.5 V
Undervoltage Lock−out VBIAS Rising
Hysteresis UVLO 1.6
0.2 V
Output Voltage Accuracy VOUT ±0.5 %
Output Voltage Accuracy −40°C ≤ TJ ≤ 125°C, VOUT(NOM) + 0.3 V ≤ VIN ≤
VOUT(NOM) + 1.0 V, 2.7 V or (VOUT(NOM) +
1.6 V), whichever is greater < VBIAS < 5.5 V,
1 mA < IOUT < 500 mA
VOUT −1.5 +1.5 %
VIN Line Regulation VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V LineReg 0.01 %/V
VBIAS Line Regulation 2.7 V or (VOUT(NOM) + 1.6 V), whichever is
greater < VBIAS < 5.5 V LineReg 0.01 %/V
Load Regulation IOUT = 1 mA to 500 mA LoadReg 1.5 mV
VIN Dropout Voltage IOUT = 150 mA (Note 5) VDO 37 90 mV
IOUT = 500 mA (Note 5) VDO 140 300
VBIAS Dropout Voltage IOUT = 500 mA, VIN = VBIAS (Notes 5, 6) VDO 1.1 1.5 V
Output Current Limit VOUT = 90% VOUT(NOM) ICL 550 800 1100 mA
Bias Pin Operating Current VBIAS = 2.7 V IBIAS 80 110 mA
Bias Pin Disable Current VEN ≤ 0.4 V IBIAS(DIS) 0.5 1.5 mA
Vinput Pin Disable Current VEN ≤ 0.4 V IVIN(DIS) 0.5 1.5 mA
EN Pin Threshold Voltage EN Input Voltage “H” VEN(H) 0.9 V
EN Input Voltage “L” VEN(L) 0.4
EN Pull Down Current VEN = 5.5 V IEN 0.3 1.5 mA
T urn−On Time From assertion of VEN to VOUT =
98% VOUT(NOM). VOUT(NOM) = 1.0 V tON 150 ms
Power Supply Rejection
Ratio VIN to VOUT, f = 1 kHz, IOUT = 150 mA,
VIN ≥ VOUT +0.5 V PSRR(VIN) 70 dB
VBIAS to VOUT, f = 1 kHz, IOUT = 150 mA,
VIN ≥ VOUT +0.5 V PSRR(VBIAS) 80 dB
Output Noise Voltage VIN = VOUT +0.5 V, VOUT(NOM) = 1.0 V,
f = 10 Hz to 100 kHz VN40 mVRMS
Thermal Shutdown
Threshold Temperature increasing 160 °C
Temperature decreasing 140
Output Discharge
Pull−Down VEN ≤ 0.4 V, VOUT = 0.5 V, NCV8133A options
only RDISCH 150 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Performance g u a r anteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C.
Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible.
5. Dropout voltage is characterized when VOUT falls 3% below VOUT(NOM).
6. For output voltages below 0.9 V, VBIAS dropout voltage does not apply due to a minimum Bias operating voltage of 2.4 V.
NCV8133
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted.
Figure 3. VIN Dropout Voltage vs. IOUT and
Temperature TJ
IOUT, OUTPUT CURRENT (mA)
3002001000
0
20
40
60
80
100
120
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
+125°C
+25°C
−40°C
Figure 4. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
VBIAS − VOUT (V)
4.03.53.02.52.01.51.00.5
0
20
60
80
120
140
180
200
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
4.5
IOUT = 100 mA
40
100
160
140
160
180
200
+85°C
400 500
+125°C+25°C−40°C
+85°C
Figure 5. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
VBIAS − VOUT (V)
4.03.53.02.52.01.51.00.5
0
50
100
200
250
4.5
150
300
+125°C
+25°C−40°C
IOUT = 300 mA
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
+85°C
Figure 6. VIN Dropout Voltage vs. (VBIAS −
VOUT) and Temperature TJ
VBIAS − VOUT (V)
4.03.53.02.52.01.51.00.5
0
50
150
200
300
350
450
500
VDO (VIN − VOUT) DROPOUT VOLTAGE (mV)
4.5
IOUT = 500 mA
100
250
400
+125°C
+25°C−40°C
+85°C
Figure 7. VBIAS Dropout Voltage vs. IOUT and
Temperature TJ
IOUT, OUTPUT CURRENT (mA)
3002001000
900
1000
1100
1200
1300
1400
VDO (VBIAS − VOUT) DROPOUT VOLTAGE (mV)
+125°C
+25°C
−40°C
25015050
+85°C
Figure 8. BIAS Pin Current vs. IOUT and
Temperature TJ
IOUT, OUTPUT CURRENT (mA)
5002001000
0
20
60
80
120
140
IBIAS (mA)
40
100
25015050
+125°C
+85°C
−40°C+25°C
1500
300 350 400 450
NCV8133
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted.
Figure 9. BIAS Pin Current vs. VBIAS and
Temperature TJ
VBIAS (V)
5.04.54.0 5.53.53.02.52.0
0
20
60
80
100
140
180
200
IBIAS (mA)
+125°C
+85°C
−40°C
40
120
160
+25°C
Figure 10. Current Limit vs. (VBIAS − VOUT)
VBIAS − VOUT (V)
4.54.03.02.51.51.00.50
0
100
300
400
500
700
1000
ICL, CURRENT LIMIT (mA)
+125°C
+25°C
−40°C
2.0 3.5 5.0
200
600
+85°C
800
900
NCV8133
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted.
50 mV/div200 mA/div
Figure 11. Load Transient Response,
IOUT = 50 mA to 500 mA, COUT = 10 mF
50 ms/div
tR = tF = 1 ms
IOUT
VOUT
Figure 12. Load Transient Response,
IOUT = 50 mA to 500 mA, COUT = 2.2 mF
50 ms/div
VOUT
Figure 13. Load Transient Response,
IOUT = 1 mA to 500 mA, COUT = 10 mFFigure 14. Load Transient Response,
IOUT = 1 mA to 500 mA, COUT = 2.2 mF
IOUT
tR = tF = 1 ms
50 mV/div200 mA/div
50 mV/div200 mA/div
500 ms/div
tR = tF = 1 ms
IOUT
VOUT
500 ms/div
VOUT
IOUT
tR = tF = 1 ms
50 mV/div200 mA/div
Figure 15. Enable Turn−on Response,
Output Resistive Load 500 mA, COUT = 10 mF
200 mV/div 1 V/div
IOUT
100 ms/div
VENABLE
VOUT
Figure 16. Enable Turn−on Response,
IOUT = 0 mA, COUT = 2.2 mF
100 ms/div
200 mA/div
200 mV/div 1 V/div
VENABLE
VOUT
NCV8133
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA,
CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted.
10 mV/div1 V/div
Figure 17. VIN Line Transient Response,
VIN = 1.3 V to 2.3 V, IOUT = 100 mA, COUT = 10 mF
20 ms/div
tR = tF = 5 ms
VIN
VOUT
Figure 18. VIN Line Transient Response,
VIN = 1.3 V to 2.3 V, IOUT = 100 mA, COUT = 2.2 mF
20 ms/div
VOUT
VIN
tR = tF = 5 ms
10 mV/div1 V/div
NCV8133
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APPLICATIONS INFORMATION
IN
EN FB
LX
GND
Processor
I/O
BIAS
IN
OUT
GND
NCV8133
LOAD
VBAT
1.5 V
1.0 V
To other circuits
I/O
EN
Figure 19. Typical Application: Low−Voltage DC/DC Post−Regulator with ON/OFF Functionality
Switch−mode DC/DC
VOUT = 1.5 V
The NCV8133 dual−rail very low dropout voltage
regulator is using NMOS pass transistor for output voltage
regulation from VIN voltage. All the low current internal
control circuitry is powered from the VBIAS voltage.
The use of an NMOS pass transistor offers several
advantages i n applications. Unlike PMOS topology devices,
the output capacitor has reduced impact on loop stability.
Vin to Vout operating voltage difference can be very low
compared with standard PMOS regulators in very low Vin
applications.
The NCV8133 offers smooth monotonic start-up. The
controlled voltage rising limits the inrush current.
The Enable (EN) input is equipped with internal
hysteresis.
NCV8133 is a Fixed Voltage linear regulator.
Dropout Voltage
Because of two power supply inputs VIN and VBIAS and
one VOUT regulator output, there are two Dropout voltages
specified.
The first, the VIN Dropout voltage is the voltage
difference (VIN – VOUT) when VOUT starts to decrease by
percent specified in the Electrical Characteristics table.
VBIAS is high enough; specific value is published in the
Electrical Characteristics table.
The second, VBIAS dropout voltage is the voltage
difference (VBIAS – VOUT) when VIN and VBIAS pins are
joined together and VOUT starts to decrease.
Input and Output Capacitors
The device is designed to be stable for ceramic output
capacitors with Effective capacitance in the range from
2.2 mF to 10 mF. The device is also stable with multiple
capacitors in parallel, having the total effective capacitance
in the specified range.
In applications where no low input supplies impedance
available (PCB inductance in VIN and/or VBIAS inputs as
example), the recommended CIN = 1 mF and CBIAS = 0.1 mF
or greater. Ceramic capacitors are recommended. For the
best performance all the capacitors should be connected to
the NCV8133 respective pins directly in the device PCB
copper layer, not through vias having not negligible
impedance.
When using small ceramic capacitor, their capacitance is
not constant but varies with applied DC biasing voltage,
temperature and tolerance. The effective capacitance can be
much lower than their nominal capacitance value, most
importantly in negative temperatures and higher LDO
output voltages. That is why the recommended Output
capacitor capacitance value is specified as Effective value in
the specific application conditions.
Enable Operation
The enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table i n this data sheet. If the enable function is not to be used
then the pin should be connected to VIN or VBIAS.
Current Limitation
The internal Current Limitation circuitry allows the
device to supply the full nominal current and surges but
protects the device against Current Overload or Short.
Thermal Protection
Internal thermal shutdown (TSD) circuitry is provided to
protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When TSD activated , the
regulator output turns of f. When cooling down under the low
temperature threshold, device output is activated again. This
TSD feature is provided to prevent failures from accidental
overheating.
NCV8133
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Power Dissipation
The maximum power dissipation supported by the device
is dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. For reliable operation, junction temperature
should be limited to +125°C.
ORDERING INFORMATION
Device
Nominal
Output
Voltage Marking Option Package Shipping†
NCV8133BMX080TCG 0.80 V JL
Non−Active Discharge XDFN6
(Pb−Free) 3000 / Tape & Reel
NCV8133BMX100TCG 1.00 V JM
NCV8133BMX110TCG 1.10 V JD
NCV8133BMX120TCG 1.20 V JE
NCV8133BMX130TCG 1.30 V JN
NCV8133BMX150TCG 1.50 V JF
NCV8133BMX180TCG 1.80 V JG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-
cifications Brochure, BRD8011/D.
To order other package and voltage variants, please contact your ON Semiconductor sales representative
NCV8133
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11
PACKAGE DIMENSIONS
XDFN6 1.20x1.20, 0.40P
CASE 711AT
ISSUE C
MOUNTING FOOTPRINT*
DIMENSIONS: MILLIMETERS
0.35
6X
0.24
6X
1.40
0.40
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
RECOMMENDED
PACKAGE
OUTLINE
1.08
0.40 1
ÍÍÍ
ÍÍÍ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO THE PLATED
TERMINALS.
4. COPLANARITY APPLIES TO THE PAD AS
WELL AS THE TERMINALS.
A
SEATING
PLANE
A
A1
DIM
A
MIN TYP
MILLIMETERS
0.30 0.37
A1 0.00 0.03
b0.13 0.18
D
E
e
L
PIN ONE
REFERENCE
0.05 C
0.05 C
NOTE 3
L
eb
3
66X
1
4
0.15 0.20
BOTTOM VIEW
E2
E2 0.20 0.30
TOP VIEW
B
SIDE VIEW
NOTE 4 C
6X
A
M
0.10 BC
D2 0.84 0.94
L1
1.20
1.20
0.40 BSC
0.05
D2
D
E
DET AIL A
L1
6X
MAX
0.45
0.05
0.23
0.25
0.40
1.04
1.15 1.25
1.15 1.25
0.00 0.10
DETAIL A
OPTIONAL
CONSTRUCTION
L
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