ees 8= AT 81 V0) 1) Features @ Single 3.3V + 10% Supply @ Fast Read Access Time - 200 ns @ Automatic Page Write Operation internal Address and Data Latches for 128-Bytes Internal Control Timer @ Fast Write Cycle Time Page Write Cycle Time - 10 ms Maximum 1 to 128-Byte Page Write Operation @ Low Power Dissipation 15 mA Active Current 1 Megabit 20 pA CMOS Standby Current Hardware and Software Data Protection | (1 28K xX 8) DATA Polling for End of Write Detection High Reliability CMOS Technology Endurance: 100,000K Cycles Low Voltage Data Retention: 10 Years @ JEDEC Approved Byte-Wide Pinout Paged CMOS @ Commercial and Industrial Temperature Ranges EPROM Description The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Program- mable Read Only Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 pA. Pin Configurations (continued) Pin Name Function AQ - A16 Addresses cE Chip Enable OE Output Enable WE Write Enable Data YOO - VO7 Inputs/Outputs NC No Connect oc Don't Connect PLCC Top View - A12 AI6VCG_NC Ais DC WE TSOP 3 2 14154617 1g !929 Vols 12 3456 GND O395A AlEL 2188AIMEL Description (Continued) The AT28LV010 is accessed like a Static RAM for the read or write cycle without the need for external compo- nents. The device contains a 128-byte page register to al- low writing of up to 128-bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of 1/07. Once the end of a write cycle has been detected a new access for a read or write can begin. Block Diagram Voc - Atmel's 28LV010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. Software data protection is implemented to guard against inadvertent writes. The de- vice also includes an extra 128-bytes of E7PROM for de- vice identification or tracking. DATA INPUTS/OUTPUTS ied GND > _ YOO - VO7 a a4 4 aa aa oe --> | OE "| OF, CE AND WE DATA LATCH LOGIC .|_ INPUT/OUTPUT CE - 4 BUFFERS ppress | -L__Y DECODER | S| GATING A _ INPUTS | rt] CELL MATRIX X DECODER IDENTIFICATION Absolute Maximum Ratings* Temperature Under Bias................ -55C to +125C Storage Temperature... -65C to +150C All input Voltages {including NC Pins) with Respect to Ground .............06 -0.6V to +6.25V All Output Voltages with Respect to Ground ............. -0.6V to Voc + 0.6V Voltage on OE and AQ with Respect to Ground ...... -0.6V to +13.5V 2-156 NOTICE: Stresses beyond those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT28LV010 mmmes 8=6f\ | 23 \/() | () Device Operation READ: The AT28LV010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The_outputs are put in the high impedance state when either CE or OE is high. This dual- line control gives designers flexibility in preventing bus contention in their system. WRITE: The write operation of the AT28LV010 allows 1 to 128-bytes of data to be written into the device during a single internal programming period. Each write operation must be preceded by the software data protection (SDP) command sequence. This sequence is a series of three unique write command operations that enable the internal write circuitry. The command sequence and the data to be written must conform to the software protected write cycle timing. Addresses are latched on the falling edge of WE or CE, whichever occurs last and data is latched on the rising edge of WE or CE, whichever occurs first. Each succes- sive byte must be written within 150 us (taLc) of the pre- vious byte. if the tatc limit is exceeded the AT28LV010 will cease accepting data and commence the interal program- ming operation. If more than one data byte is to be written during a single programming operation, they must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same. The AO to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28LV010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be pre- sented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Palling may begin at anytime during the write cycle. AIMEL TOGGLE BIT: in addition to DATA Polling the AT28LV010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in 1/O6 toggling be- tween one and zero. Once the write has completed, /O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. Atmel has incorporated both hardware and software features that wilt protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28LV010 in the follow- ing ways: (a) Vcc power-on delay - once Vcc has reached 2.0V (typical) the device will automatically time out 5 ms (typical) before allowing a write:(b) write inhibit - holding any one of OE low, CE high or WE high inhibits write cy- cles; (c) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: The AT28LV010 in- corporates the industry standard software data protection (SDP) function. Unlike standard 5-volt only E7PROM's, the AT28LV010 has SDP enabled at all times. Therefore, all write operations must be preceded by the SDP com- mand sequence. The data in the 3-byte command sequence is not written to the device; the addresses in the command sequence can be utilized just like any other location in the device. Any attempt to write to the device without the 3-byte se- quence will start the internal timers. No data will be written to the device. However, for the duration of twc, read op- erations will effectively be polling operations. 2-157AlmEt DC and AC Operating Range AT28LV010-20 AT28LV010-25 Operating Com. arc - 70C 0e - 70C Temperature (Case) ind, -40C - 85C -40C - 85C Vcc Power Supply 3.3V + 5% 3.3V + 10% Operating Modes Mode cE OE WE vo Read ViL VIL VIH Dout Write (2) Vit Vin Vie Din Standby/Write Inhibit Vin x Xx High Z Write Inhibit x x ViH Write Inhibit X Vit x Output Disable X ViH X High Z Notes: 1. X can be Vit or Vin. 2. Refer to AC Programming Waveforms. DC Characteristics Symbol Parameter Condition Min Max Units tu Input Load Current VIN = OV to Voc 1 pA ILo Output Leakage Current Vio = OV to Veco 1 pA Isp Vcc Standby Current CMOS CE = Voc - 0.3V to Voc + 1V Com. 20 HA Ind, 50 WA lec Vcc Active Current { = 5 MHz; lout = 0 mA; Vcc = 3.6V 15 mA VIL input Low Voltage 0.8 Vv VIH Input High Voltage 2.0 Vv VoL Output Low Voltage lot = 1.6 MA; Voc = 3.0V 45 Vv VOH Output High Voltage oH = -100 WA; Voc = 3.0V 2.4 v 2-158 AT28LV0O10 mummersees 8= fA | 28 \/() 1 0) AC Read Characteristics AT28LV010-20 AT28LV010-25 Symbol Parameter Min Max Min Max Units tacc Address to Output Delay 200 250 ns tce (1) CE to Output Delay 200 250 ns toe 2) OE to Output Delay 80 0 100 ns tor 34) CE or OE to Output Float 0 55 0 60 ns Output Hold from OE, CE or toH ngeress. whichever occurred 0 0 ns AC Read Waveforms ** _ _ __. ADDRESS x ADDRESS VALID CE taco > OUTPUT HIGH Z Notes: 1. CE may be delayed up to tacc - tce after the address transition without impact on tacc. 2. OE may be delayed up to tce - toe after the falling edge of CE without impact on tce or by tacc - toe after an address change without impact on tacc. Input Test Waveforms and Measurement Level q OUTPUT VALID 3. tor is specified trom OE or CE whichever occurs first (C_ = 5pF). 4. This parameter is characterized and is not 100% tested. Output Test Load 5.0V 3.0V AC AC ms OUTPUT DRIVING MEASUREMENT _ PIN LEVELS LEVEL 0.0V 1.3K 100 pF tr, tp < 5 ns J : . 1 Pin Capacitance (f = 1 MHz, T = 25C) Typ Max Units Conditions CIN 4 6 pF Vin = OV Cout 8 12 pF Vout = OV Note: 1. This parameter is characterized and is not 100% tested. AIMEL 2-159ATMEL AC Write Characteristics Symbol Parameter Min Max Units tas, toes Address, OE Set-up Time 0 ns tAH Address Hold Time 100 ns tes Chip Select Set-up Time 0 ns {CH Chip Select Hold Time 0 ns twp Write Pulse Width (WE or CE) 200 ns tos Data Set-up Time 100 ns 10H, toEH Data, OE Hold Time 10 ns Note: 1. All write operations must be preceded by the SDP command sequence. AC Write Waveforms WE Controlled | mo . OE 4s | tOES 1OEH ~ _ ADDRESS >< be x CE | on) \ WE 2 oor NN I~ tWPH tWP ; 10S --|'- (DH - DATA IN 4 CE Controiled OE _ oh AOEH ADDRESS _ - - _ NS - tAH tr We tCH 4 \. WE A NN CE OOS. -- tWPH - . WP. = (DV +} tS | |--tDH DATA IN ae oe 2-160 AT28LV010AT28LV010 Software Protected Write Characteristics Symbol Parameter Min Max Units two Write Cycle Time - _ 10 ms tas Address Set-up Time 0 ns taH | Address Hold Time 100 ns tps Data Set-up Time 100 ns toH Data Hold Time 10 ns twp Write Pulse Wicth 200 ns tBic Byte Load Cycle Time 150 hs twPH Write Pulse Width High 100 ns Programming Algorithm LOAD DATA AA TO Notes: ADDRESS 5555 1. Data Format: /O7 - 1/00 (Hex); Address Format: A14 - AQ (Hex). 2. Data protect state will be re-activated at the end of program cycle. 3. 1 to 128-bytes of data are loaded. LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA AO TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS) LOAD LAST BYTE WRITES ENABLED ) TO (3) LAST ADDRESS ENTER DATA PROTECT STATE Software Protected Program Cycle Waveforms se ) A fof fo oP a h AL mA NS poo anne ae + twP : 7 Af 2 ffm We at 7 VISOR NS a ce pea _ AO- AG Kk x _Yfevre aooness ar ee mn AT-AN6 py al - ee . ks PAGE i 1DS {0H . A para Xm KR Kw KX =e BYTE 0 BYTE 126 BYTE 127 ee wo 4 Notes: 1. AO - A14 must conform to the addressing sequence for the first 3-bytes as shown above. 2. After the command sequence has been issued and _a page write operation follows, the page address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE). 3. OE must be high only when WE and CE are both low. AIMEL 2-161Data Polling Characteristics Symbol Parameter Min Typ Max Units tox Data Hold Time 10 ns toeH OE Hold Time 10 ns toe OE to Output Delay (2) ns twR Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Data Polling Waveforms We PO IE tf \ * \ f ON f = {WR VO7 poms Ap | ee yp - ry AOA ARAN XANAX AK Toggle Bit Characteristics Symbol Parameter Min Typ Max Units toH Data Hold Time 10 ns toEH OE Hold Time 10 ns toe OE to Output Delay ) ns toEHP OE High Pulse 150 ns twa Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Toggle Bit Waveforms oo Go WE vo poo cr cE LS NS NS S\N. _ Prot) tOER ; yy OE SVS NS VS Nk Toe tOE ao HL HIGHZ pe vO6 NY Ne Notes: 1. Toggling either OE or CE or both OE and CE will 3. Any address location may be used but the operate toggle bit. address should not vary. 2. Beginning and ending state of I/O6 will vary. 2-162 AT28LV010ees 8=f\ | 28 L. \/() | () Ordering Information tacc Iec (mA) . - Ordering Code Package Operation Range (ns) Active | Standby 200 15 0.2 AT28LV010-20UC 32J Commercial AT28LV010-20PC 32P6 (0 to 70C) | AT 2BLVOIO-2OTC I 15 0.2 AT28LV010-20JI 32J Industrial AT28LV010-20P1 32P6 (-40 to 85C) | | | AT2BLVOTO-20T! | AT 250 15 0.2 AT28LV010-25JC 32J Commercial AT28LV010-25PC 32P6 (0 to 70C) P| Areaivotozste | eT _ 15 0.2 AT28LV010-25J1 32J Industrial AT28LV010-25PI 32P6 (-40 to 85C) AT28LV010-25T| 32T Note: 1. See Valid Part Number table below. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28LV010 | 20 JC, JI, PC, Pi, TC, TI AT28LV010 | 25 JC, Jl, PC, Pl, TC, TI Package Type 320 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 32P6 32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32T 32 Lead, Plastic Thin Small Outline Package (TSOP) AIMEL 2-163