LM555JAN Timer General Description The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output circuit can source or sink up to 200mA or drive TTL circuits. Features n Direct replacement for SE555/NE555 n Timing from microseconds through hours n Operates in both astable and monostable modes n n n n n Adjustable duty cycle Output can source or sink 200 mA Output and supply TTL compatible Temperature stability better than 0.005% per C Normally on and normally off output Applications n n n n n n n Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulation Pulse position modulation Linear ramp generator Ordering Information NS Part Number JAN Part Number JL555SPA JM38510/10901SPA NS Package Number J08A Package Description 8LD Ceramic Dip JL555SGA JM38510/10901SGA H08A 8LD Metal Can Connection Diagrams Dual-In-Line Package Metal Can Package 20153733 Top View 20153703 Top View (c) 2005 National Semiconductor Corporation DS201537 www.national.com LM555JAN Timer August 2005 LM555JAN Schematic Diagram 20153701 www.national.com 2 LM555JAN Absolute Maximum Ratings (Note 1) Supply Voltage +18V Discharge Current +200mA Output Sink Current +200mA Output Source Current -200mA Power Dissipation (Note 2) Metal Can 300mW @ +125C CERDIP 370mW @ +125C -55C TA +125C Operating Temperature Range Maximum Junction Temperature (TJmax) +175C -65C TA +150C Storage Temperature Range Soldering Information (Soldering 10 Seconds) 300C Thermal Resistance JA CERDIP Still Air 123C/W CERDIP 500LF / Min Air Flow 69C/W Metal Can Still Air 171C/W Metal Can 500LF / Min Air Flow 92C/W JC CERDIP 18C/W Metal Can 41C/W ESD Tolerance (Note 3) 1KV Recommended Operating Conditions Supply Voltage Range +4.5V to +16VDC Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp C 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling time at 25 13 Settling time at 125 14 Settling time at -55 3 www.national.com LM555JAN Electrical Characteristics DC Parameters Symbol ICC VTrig Parameter Power Supply Current Trigger Voltage Conditions Notes Min Max 5.0 mA 1, 2, 3 VCC = 16.5V 20 mA 1, 2, 3 1.3 1.8 V 1 1.3 2.1 V 2 VCC = 4.5V 1.15 1.8 V 3 5.2 5.8 V 1 5.2 6.1 V 2 5.0 5.8 ITrig Trigger Current VCC = 16.5V -5.0 VTh Threshold Voltage VCC = 4.5V 2.7 2.6 VCC = 16.5V 10.7 10.6 ITh Threshold Current VCC = 16.5V VOL Logical "0" Output Voltage VCC = 4.5V, ISink = 5mA VCC = 4.5V, ISink = 50mA VCC = 16.5V, ISink = 10mA VCC = 16.5V, ISink = 50mA VCC = 16.5V, ISink = 100mA V 3 A 1, 2, 3 V 1 3.4 V 2, 3 11.3 V 1 11.4 V 2, 3 250 nA 1, 2 2,500 nA 3 0.25 V 1 0.35 V 2, 3 1, 2 3.3 2.2 V 2.6 V 3 0.15 V 1, 3 0.25 V 2 1, 3 0.5 V 0.7 V 2 2.2 V 1 2.8 Logical "1" Output Voltage VSat Discharge Transistor Leakage Current V 2, 3 V 1, 2 VCC = 4.5V, ISource = -100mA 2.6 2.2 V 3 VCC = 16.5V, ISource = -100mA 14.6 V 1, 2 14 ICEX Subgroups VCC = 4.5V VCC = 16.5V VOH Unit V 3 100 nA 1, 3 3,000 nA 2 0.8 V 1, 3 1.0 V 2 1.3 V 1, 2, 3 mA 1, 2, 3 Max Unit Subgroups VCC = 4.5V 800 nS 9, 11 900 nS 10 VCC = 16.5V 800 nS 9, 11 900 nS 10 VCC = 4.5V 12 S 9, 10, 11 VCC = 16.5V 12 S 9, 10, 11 VCC = 16.5V Discharge Transistor Saturation VCC = 16.5V Voltage VR Reset Voltage VCC = 16.5V IR Reset Current VCC = 16.5V (Note 4), (Note 5) 0.1 -1.6 AC Parameters Symbol tPLH tPHL Parameter Propagation Delay Time Propagation Delay Time www.national.com Conditions 4 Notes Min AC Parameters Symbol (Continued) (Continued) Parameter Conditions Notes Min Max Unit Subgroups tTLH Transition Time VCC = 4.5V 300 nS 9, 10, 11 VCC = 16.5V 300 nS 9, 10, 11 tTHL Transition Time VCC = 4.5V 300 nS 9, 10, 11 VCC = 16.5V 300 nS 9, 10, 11 9, 10, 11 tDOH Time Delay Output High RT = 1K Time Delay Output High RT = 100K VCC = 4.5V 106.7 113.3 S VCC = 16.5V 106.7 113.3 S 9, 10, 11 VCC = 4.5V 10.67 11.33 mS 9, 10, 11 VCC = 16.5V 10.67 11.33 mS 9, 10, 11 tD / VCC Drift In Time Delay VCC = 12, VCC = 4.5V to 16.5V tD / T Temperature Coefficient of Time Delay VCC = 16.5V tCh Capacitor Charge Time RT = 1K VCC = 4.5V tDis (Note 6) -220 220 nS/V 9 -11 11 nS/C 10, 11 120 156 S 9, 10, 11 VCC = 16.5V 120 156 S 9, 10, 11 Capacitor Charge Time RT = 100K VCC = 4.5V 11.3 15 mS 9, 10, 11 VCC = 16.5V 11.3 15 mS 9, 10, 11 Capacitor Discharge Time RT = 1K VCC = 4.5V 57.5 80 S 9, 10, 11 VCC = 16.5V 57.5 80 S 9, 10, 11 VCC = 4.5V 5.4 7.7 mS 9, 10, 11 VCC = 16.5V 5.4 7.7 mS 9, 10, 11 -820 820 nS/V 9 -68 68 nS/C 10, 11 1.5 S 9, 11 2.0 S 10 Min Max Unit Subgroups Capacitor Discharge Time RT = 100K tCh / VCC Drift In Capacitor Charge Time VCC = 12, VCC = 4.5V to 16.5V tCh / T Temperature Coefficient Capacitor Charge Time VCC = 16.5V tRes Reset Time VCC = 16.5V (Note 6) DC Drift Parameters Delta calculations performed on JAN S devices at Group B, Subgroup 5, only. Symbol Parameter Conditions Notes VTrig Trigger Voltage VCC = 16.5V -0.05 0.05 V 1 VTh Threshold Voltage VCC = 16.5V -0.05 0.05 V 1 VOL Logical "0" Output Voltage VCC = 16.5V, ISink = 10mA -0.05 0.05 V 1 ICEX Discharge Transistor Leakage Current VCC = 16.5V -50 50 nA 1 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), JA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: Human body model, 1.5K in series with 100pF. Note 4: Parameter tested go-no-go, only. Note 5: Datalog reading of 0.7V will reflect the Reset Voltage levels passing and a reading of 0.5V or 1.5V reflects the Reset voltage levels failing the low level or high level respectfully. Note 6: Calculated parameter. 5 www.national.com LM555JAN Electrical Characteristics LM555JAN Typical Performance Characteristics Minimum Pulse Width Required for Triggering Supply Current vs. Supply Voltage 20153719 20153704 High Output Voltage vs. Output Source Current Low Output Voltage vs. Output Sink Current 20153721 20153720 Low Output Voltage vs. Output Sink Current Low Output Voltage vs. Output Sink Current 20153723 20153722 www.national.com 6 LM555JAN Typical Performance Characteristics (Continued) Output Propagation Delay vs. Voltage Level of Trigger Pulse Output Propagation Delay vs. Voltage Level of Trigger Pulse 20153725 20153724 Discharge Transistor (Pin 7) Voltage vs. Sink Current Discharge Transistor (Pin 7) Voltage vs. Sink Current 20153727 20153726 7 www.national.com LM555JAN during this time by the application of a negative pulse to the reset terminal (pin 4). The output will then remain in the low state until a trigger pulse is again applied. Applications Information MONOSTABLE OPERATION When the reset function is not in use, it is recommended that it be connected to VCC to avoid any possibility of false triggering. In this mode of operation, the timer functions as a one-shot (Figure 1). The external capacitor is initially held discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high. Figure 3 is a nomograph for easy determination of R, C values for various time delays. NOTE: In monostable operation, the trigger should be driven high before the end of timing cycle. 20153705 20153707 FIGURE 1. Monostable FIGURE 3. Time Delay The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 2 shows the waveforms generated in this mode of operation. Since the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing internal is independent of supply. ASTABLE OPERATION If the circuit is connected as shown in Figure 4 (pins 2 and 6 connected) it will trigger itself and free run as a multivibrator. The external capacitor charges through RA + RB and discharges through RB. Thus the duty cycle may be precisely set by the ratio of these two resistors. 20153706 VCC = 5V Top Trace: Input 5V/Div. TIME = 0.1 ms/DIV. RA = 9.1k Middle Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 2V/Div. C = 0.01F 20153708 FIGURE 2. Monostable Waveforms FIGURE 4. Astable During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10s before the end of the timing interval. However the circuit can be reset In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage. www.national.com 8 FREQUENCY DIVIDER (Continued) The monostable circuit of Figure 1 can be used as a frequency divider by adjusting the length of the timing cycle. Figure 7 shows the waveforms generated in a divide by three circuit. Figure 5 shows the waveforms generated in this mode of operation. 20153709 VCC = 5V Top Trace: Output 5V/Div. TIME = 20s/DIV. Bottom Trace: Capacitor Voltage 1V/Div. 20153711 VCC = 5V Top Trace: Input 4V/Div. RA = 3.9k TIME = 20s/DIV. Middle Trace: Output 2V/Div. RB = 3k RA = 9.1k Bottom Trace: Capacitor 2V/Div. C = 0.01F C = 0.01F FIGURE 5. Astable Waveforms FIGURE 7. Frequency Divider The charge time (output high) is given by: t1 = 0.693 (RA + RB) C And the discharge time (output low) by: t2 = 0.693 (RB) C Thus the total period is: T = t1 + t2 = 0.693 (RA +2RB) C The frequency of oscillation is: PULSE WIDTH MODULATOR When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output pulse width can be modulated by a signal applied to pin 5. Figure 8 shows the circuit, and in Figure 9 are some waveform examples. Figure 6 may be used for quick determination of these RC values. The duty cycle is: 20153712 FIGURE 8. Pulse Width Modulator 20153710 FIGURE 6. Free Running Frequency 9 www.national.com LM555JAN Applications Information LM555JAN Applications Information (Continued) 20153713 VCC = 5V 20153715 Top Trace: Modulation 1V/Div. TIME = 0.2 ms/DIV. VCC = 5V Bottom Trace: Output Voltage 2V/Div. Top Trace: Modulation Input 1V/Div. TIME = 0.1 ms/DIV. RA = 9.1k Bottom Trace: Output 2V/Div. RA = 3.9k C = 0.01F RB = 3k C = 0.01F FIGURE 9. Pulse Width Modulator FIGURE 11. Pulse Position Modulator PULSE POSITION MODULATOR This application uses the timer connected for astable operation, as in Figure 10, with a modulating signal again applied to the control voltage terminal. The pulse position varies with the modulating signal, since the threshold voltage and hence the time delay is varied. Figure 11 shows the waveforms generated for a triangle wave modulation signal. LINEAR RAMP When the pull-up resistor, RA, in the monostable circuit is replaced by a constant current source, a linear ramp is generated. Figure 12 shows a circuit configuration that will perform this function. 20153716 20153714 FIGURE 12. FIGURE 10. Pulse Position Modulator Figure 13 shows waveforms generated by the linear ramp. The time interval is given by: VBE . 0.6V www.national.com 10 LM555JAN Applications Information (Continued) 20153717 VCC = 5V Top Trace: Input 3V/Div. TIME = 20s/DIV. Middle Trace: Output 5V/Div. R1 = 47k Bottom Trace: Capacitor Voltage 1V/Div. 20153718 R2 = 100k RE = 2.7 k FIGURE 14. 50% Duty Cycle Oscillator C = 0.01 F Note that this circuit will not oscillate if RB is greater than 1/2 RA because the junction of RA and RB cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator. FIGURE 13. Linear Ramp 50% DUTY CYCLE OSCILLATOR For a 50% duty cycle, the resistors RA and RB may be connected as in Figure 14. The time period for the output high is the same as previous, t1 = 0.693 RA C. For the output low it is t2 = ADDITIONAL INFORMATION Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1F in parallel with 1F electrolytic. Lower comparator storage time can be as long as 10s when pin 2 is driven fully to ground for triggering. This limits the monostable pulse width to 10s minimum. Delay time reset to output is 0.47s typical. Minimum reset pulse width must be 0.3s, typical. Thus the frequency of oscillation is Pin 7 current switches within 30ns of the output (pin 3) voltage. 11 www.national.com LM555JAN Revision History Date Released 08/04/05 www.national.com Revision A Section Originator New Release to corporate format 12 L. Lytle Changes 1 MDS datasheet converted into corporate format. MJLM555-X Rev 1A0 to be archived LM555JAN Physical Dimensions inches (millimeters) unless otherwise noted 8LD Ceramic Dip Package (J) NS Package Number J08A 13 www.national.com LM555JAN Timer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8LD Metal Can Package (H) NS Package Number H08A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ``Banned Substances'' as defined in CSP-9-111S2. Leadfree products are RoHS compliant. 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