Rev.2.00, Mar 30, 2006 page 1 of 8
HD74HC4518, HD74HC4520
Dual BCD Up Counters
Dual Binary Up Counters REJ03D0653–0200
(Previous ADE-205-542)
Rev.2.00
Mar 30, 2006
Description
The HD74HC4518 dual BCD counter and the HD74HC4520 dual binary counter consist of two identical, independent,
internally synchronous 4-stage counters. The counter stages are type D flip-flops, with interchangeable Clock and
Enable lines for incrementing on either the positiv e-going or negative-going transition as required when cascading
multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the HD74HC4518
will count out of all undefined states within two clock periods. These complementary MOS up counters find primary
use in multi-stage synchronous or ripple counting app lications requiring low power dissipation and/or high noise
immunity.
Features
• High Speed Operation
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74HC4518P
HD74HC4520P DILP-16 pin PRDP0016AE-B
(DP-16FV) P —
HD74HC4518FPEL
HD74HC4520FPEL SOP-16 pin (JEITA) PRSP0016DH-B
(FP-16DAV) FP EL (2,000 pcs/reel)
HD74HC4520RPEL SOP-16 pin (JEDEC) PRSP0016DG-A
(FP-16DNV) RP EL (2,000 pcs/reel)
Note: Please consult the sales office for the above packa ge availability.
Function Table
Clock Enable Reset Operation
H L Increment counter
L L Increment counter
X L No change
X L No change
L L No change
H L No change
X X H Q0 to Q3 = L
Notes: 1. X: Don’t care
HD74HC4518, HD74HC4520
Rev.2.00, Mar 30, 2006 page 2 of 8
Pin Arrangement
1
2
3
4
5
6
7
8
Clock A
Enable A
Q0 A
Q1 A
Q2 A
Q3 A
Reset A
GND
VCC
Reset B
Q3 B
Q2 B
Q1 B
Q0 B
Enable B
Clock B
CR
RC
Q3
Q2
Q1
Q0
Q0
Q1
Q2
Q3
16
15
14
13
12
11
10
9
(Top view)
Block Diagram
HD74HC4518
D
C
R
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
Reset
Clock
Enable
Q
0
Q
1
Q
2
Q
3
RR R
HD74HC4518, HD74HC4520
Rev.2.00, Mar 30, 2006 page 3 of 8
HD74HC4520
Reset
D
C
R
Q
Q
D
C
Q
Q
D
C
Q
Q
D
C
Q
Q
Clock
Enable
Q0Q1Q2Q3
RR R
Timing Diagram
123456789
10 11 12 13 14 15 16 17 18
123456789
10 11 12 13 14 15
012 34
12345678901234567890
Clock
Enable
Reset
Q
0
Q
3
Q
2
Q
1
Q
0
Q
3
Q
2
Q
1
HD74HC4518
HD74HC4520
HD74HC4518, HD74HC4520
Rev.2.00, Mar 30, 2006 page 4 of 8
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage range VCC –0.5 to 7.0 V
Input / Output voltage VIN, VOUT –0.5 to VCC +0.5 V
Input / Output diode current IIK, IOK ±20 mA
Output current IOUT ±25 mA
VCC, GND current ICC or IGND ±50 mA
Power dissipation PT 500 mW
Storage temperature Tstg –65 to +150 °C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item Symbol Ratings Unit Conditions
Supply voltage VCC 2 to 6 V
Input / Output voltage VIN, VOUT 0 to VCC V
Operating temperature Ta –40 to 85 °C
0 to 1000 VCC = 2.0 V
0 to 500 VCC = 4.5 V
Input rise / fall time*1 t
r, tf
0 to 400
ns
VCC = 6.0 V
Notes: 1. This item guarantees maximum limit when one input s witches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25°C Ta = –40 to+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
2.0 1.5 — — 1.5 —
4.5 3.15 — — 3.15 —
VIH
6.0 4.2 — — 4.2 —
V
2.0 — — 0.5 — 0.5
4.5 — — 1.35 — 1.35
Input voltage
VIL
6.0 — — 1.8 — 1.8
V
2.0 1.9 2.0 — 1.9 —
4.5 4.4 4.5 — 4.4 —
6.0 5.9 6.0 — 5.9 —
IOH = –20 µA
4.5 4.18 — — 4.13 — IOH = –4 mA
VOH
6.0 5.68 — — 5.63 —
V Vin = VIH or VIL
IOH = –5.2 mA
2.0 — 0.0 0.1 — 0.1
4.5 — 0.0 0.1 — 0.1
6.0 — 0.0 0.1 — 0.1
IOL = 20 µA
4.5 — — 0.26 — 0.33 IOH = 4 mA
Output voltage
VOL
6.0 — — 0.26 — 0.33
V Vin = VIH or VIL
IOH = 5.2 mA
Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND
Quiescent supply
current ICC 6.0 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA
HD74HC4518, HD74HC4520
Rev.2.00, Mar 30, 2006 page 5 of 8
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C Ta = –40 to +85°C
Item
Symbol
VCC (V) Min Typ Max Min Max
Unit Test Conditions
2.0 — — 5 — 4
4.5 — — 27 — 21
Maximum clock
frequency fmax
6.0 — — 32 — 25
MHz
2.0 — — 190 — 240
4.5 — 22 38 — 48
tPLH
tPHL 6.0 — — 32 — 41
ns Clock to Q
2.0 — — 200 — 250
4.5 — 22 40 — 50
tPLH
tPHL 6.0 — — 34 — 43
ns Reset to Q
2.0 — — 190 — 240
4.5 — 17 38 — 48
Propagation delay time
tPLH
tPHL 6.0 — — 32 — 41
ns Enable to Q
2.0 80 — — 100 —
4.5 16 7 — 20 —
Pulse width tw
6.0 14 — — 17 —
ns
2.0 0 — — 0 —
4.5 0 –3 — 0 —
Removal time trem
6.0 0 — — 0 —
ns Reset clock
2.0 — — 75 — 95
4.5 — — 15 — 19
Output rise/fall time tTLH
tTHL 6.0 — — 13 — 16
ns
Input capacitance Cin — — 5 10 — 10 pF
Test Circuit
V
CC
C
L
= 50 pF
Clock
V
CC
Z
out
= 50 Ω
Q3
Reset
C
L
= 50 pF
Q0
Z
out
= 50 Ω
Enable
Pulse Generator
Output
Note : 1. C
L
includes probe and jig capacitance.
See Function Table
Input
Output
Input
Pulse Generator
HD74HC4518, HD74HC4520
Rev.2.00, Mar 30, 2006 page 6 of 8
Waveforms
Clock
Reset
V
OL
V
OH
0 V
V
CC
90%
10% 10%
t
THL
t
TLH
90%
•
Waveform – 1
50% 50%
50%
t
rem
t
r
10%
90%
t
f
10%
90%
Qn
V
OL
V
OH
90%
10% 10%
t
THL
t
TLH
90%
50%
t
PHL
t
w
1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 nsNote:
Enable
Qn
V
CC
50%
50%
V
OL
V
OH
0 V
t
w
90%
10% 10%
t
TLH
90%
•
Waveform – 3
50%
50%
t
THL
t
PHL
90%
10%
90%
10%
Qn
Clock
V
OL
V
OH
0 V
V
CC
50%
50%
t
PHL
50%
50%
t
w
90%
10% 10%
t
f
t
THL
t
r
t
TLH
90%
•
Waveform – 2
50%
t
PLH
50%
t
f
t
r
t
PLH
1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t
r
≤ 6 ns, t
f
≤ 6 nsNote:
1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t
r
≤ 6 ns, t
f
≤ 6 nsNote:
HD74HC4518, HD74HC4520
Rev.2.00, Mar 30, 2006 page 7 of 8
Package Dimensions
7.62
MaxNomMin
Dimension in Millimeters
Symbol
Reference
19.2
6.3
5.06
A1
Z
b3
D
E
A
bp
c
θ
e
L
e1
0.51
0.56
1.30
0.19 0.25 0.31
2.29 2.54 2.79
0° 15°
20.32
7.4
0.40 0.48
1.12
2.54
1
p
1
3
1 8
16 9
e
b
A
LA
Z
e c
E
D
b
0.89
θ
( Ni/Pd/Au plating )
P-DIP16-6.3x19.2-2.54 1.05g
MASS[Typ.]
DP-16FVPRDP0016AE-B
RENESAS CodeJEITA Package Code Previous Code
0.635
0.15
1.27
5.80 6.20
0.400.34
A1
10.30
MaxNomMin
Dimension in Millimeters
Symbol
Reference
1.75
1.270.600.40
3.95
0.250.140.10
0.46
0.250.200.15
6.10
8°0°
0.25
1.08
9.90
L1
Z
HE
y
x
θ
c
bp
A2
E
D
b1
c1
e
e
L
A
Index mark
E
1
y
xM
p
*3
*2
*1 F
8
916
E
H
D
A
Zb
Terminal cross section
( Ni/Pd/Au plating )
p
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
P-SOP16-3.95x9.9-1.27 0.15g
MASS[Typ.]
FP-16DNVPRSP0016DG-A
RENESAS CodeJEITA Package Code Previous Code
HD74HC4518, HD74HC4520
Rev.2.00, Mar 30, 2006 page 8 of 8
0.80
0.15
1.27
7.50 8.00
0.400.34
A1
10.5
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
5.50
0.200.100.00
0.46
0.250.200.15
7.80
8°0°
0.12
1.15
10.06
L1
Z
HE
y
x
θ
c
bp
A2
E
D
b1
c1
e
L
A
*1
*2
E
81
16 9
xM
p
*3
y
F
Index mark
b
D
E
H
Z
A
Terminal cross section
( Ni/Pd/Au plating )
p
c
b
1
1
Detail F
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
P-SOP16-5.5x10.06-1.27 0.24g
MASS[Typ.]
FP-16DAVPRSP0016DH-B
RENESAS CodeJEITA Package Code Previous Code
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