PESD24VS2UAT,215 - NEXPERIA

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DATA SH EET

Product data sheet 2004 Feb 18

DISCRETE SEMICONDUCTORS

PESDxS2UAT series

Double ESD protection diodes

in SOT23 package

2004 Feb 18 2

NXP Semiconductors Product data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

FEATURES

•Unidirectional ESD protection of up to two lines

•Common-cathode configu ration

•Max. peak pulse power: Ppp = 330 W at tp = 8/20 µs

•Low clamping voltage: V(CL)R = 20 V at Ipp = 18 A

•Ultra-lo w reverse leakage current: IRM < 700 nA

•ESD protection > 30 kV

•IEC 61000-4-2; level 4 (ESD)

•IEC 61000-4-5 (s urge); Ipp = 18 A at tp = 8/20 µs.

APPLICATIONS

•Computers and pe ripherals

•Communication syste ms

•Audio and video eq uipment

•Data lines

•CAN bus protection .

DESCRIPTION

Unidirectional double ESD protection diodes in common

cathode configuration in the SOT23 plastic package.

Designed to protec t up to two transmission or data lin es

against damage from Electr oStatic Discharge (ESD) and

other transients.

MARKING

Note

1. * = p : made in Hong Kong .

* = t : made in Malaysia.

* = W : made in China.

QUICK REFERENCE DATA

PINNING

TYPE NUMBER MARKING CODE(1)

PESD3V3S2UAT *7A

PESD5V0S2UAT *7B

PESD12VS2UAT *7C

PESD15VS2UAT *7D

PESD24VS2UAT *7E

SYMBOL PARAMETER VALUE UNIT

VRWM reverse stand-off

voltage 3.3, 5, 12, 15

and 24 V

Cddiode capacitance

VR = 0 V;

f = 1 MHz

207, 152, 38, 32

and 23 pF

number of

protected lines 2

PIN DESCRIPTION

1anode 1

2anode 2

3common cathode

sym002

001aaa40

Fig.1 Simplified outline (SOT23 ) and symbo l .

2004 Feb 18 3

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

ORDERING INFORMATION

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. Non-repetitive current pulse 8/20µ µs exponential deca y waveform; see Fig.2.

2. Measured across either pins 1 and 3 or pins 2 and 3.

TYPE NUMBER PACKAGE

NAME DESCRIPTION VERSION

PESD3V3S2UAT −plastic surface mounted package; 3 leads SOT23

PESD5V0S2UAT

PESD12VS2UAT

PESD15VS2UAT

PESD24VS2UAT

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Ppp peak pulse power 8/20 µs pulse; notes 1 and 2

PESD3V3S2UAT −330 W

PESD5V0S2UAT −260 W

PESD12VS2UAT −180 W

PESD15VS2UAT −160 W

PESD24VS2UAT −160 W

Ipp peak pulse current 8/20 µs pulse; notes 1 and 2

PESD3V3S2UAT −18 A

PESD5V0S2UAT −15 A

PESD12VS2UAT −5 A

PESD15VS2UAT −5 A

PESD24VS2UAT −3 A

Tjjunction temperature −150 °C

Tamb operating ambient temperature −65 +150 °C

Tstg storage temperature −65 +150 °C

2004 Feb 18 4

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

ESD maximum ratings

Notes

1. Device stressed with ten non-repetitive ESD pulses; see Fig.3.

2. Measured from pin 1, 2, 3, 4, 5 or 8 to pin 6 or 7.

SYMBOL PARAMETER CONDITIONS VALUE UNIT

ESD electrostatic discharge IEC 61000-4-2 (c ontact disc harge);

notes 1 and 2

PESD3V3S2UAT 30 kV

PESD5V0S2UAT 30 kV

PESD12VS2UAT 30 kV

PESD15VS2UAT 30 kV

PESD24VS2UAT 23 kV

HBM MIL-Std 883

PESDxS2UAT-series 10 kV

ESD standards compliance

ESD STANDARD CONDITIONS

IEC 61000-4-2 ; level 4 (ESD); see Fig.3 > 15 kV (air); > 8 kV (cont a ct)

HBM MIL-Std 883; class 3 > 4 kV

handbook, halfpage

010

e−t

20 t (µs)

Ipp

(%)

120

MLE218

100 % Ipp; 8 µs

50 % Ipp; 20 µs

Fig.2 8/20 µs pulse waveform according to

IEC 61000-4-5.

001aaa19

Ipp

00 %

90 %

30 ns 60 ns

10 %

tr = 0.7 to 1 ns

Fig.3 ElectroStatic Discharge (ESD) pulse

waveform according to IEC 61000-4-2.

2004 Feb 18 5

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

ELECTRICAL CHARACTERISTIC S

Tj = 25 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VRWM revers e stand-off voltage

PESD3V3S2UAT − − 3.3 V

PESD5V0S2UAT − − 5 V

PESD12VS2UAT − − 12 V

PESD15VS2UAT − − 15 V

PESD24VS2UAT − − 24 V

IRM reverse leakage curre nt

PESD3V3S2UAT VRWM = 3.3 V −0.7 2µA

PESD5V0S2UAT VRWM = 5 V −0.1 1µA

PESD12VS2UAT VRWM = 12 V −<1 50 nA

PESD15VS2UAT VRWM = 15 V −<1 50 nA

PESD24VS2UAT VRWM = 24 V −<1 50 nA

VBR breakdown voltage IZ = 5 mA

PESD3V3S2UAT 5.2 5.6 6.0 V

PESD5V0S2UAT 6.4 6.8 7.2 V

PESD12VS2UAT 14.7 15.0 15.3 V

PESD15VS2UAT 17.6 18.0 18.4 V

PESD24VS2UAT 26.5 27.0 27.5 V

Cddiode capacitance f = 1 MHz; VR = 0 V

PESD3V3S2UAT −207 300 pF

PESD5V0S2UAT −152 200 pF

PESD12VS2UAT −38 75 pF

PESD15VS2UAT −32 70 pF

PESD24VS2UAT −23 50 pF

V(CL)R clamping voltage notes 1 and 2

PESD3V3S2UAT Ipp = 1 A − − 7 V

Ipp = 18 A − − 20 V

PESD5V0S2UAT Ipp = 1 A − − 9 V

Ipp = 15 A − − 20 V

PESD12VS2UAT Ipp = 1 A − − 19 V

Ipp = 5 A − − 35 V

PESD15VS2UAT Ipp = 1 A − − 23 V

Ipp = 5 A − − 40 V

PESD24VS2UAT Ipp = 1 A − − 36 V

Ipp = 3 A − − 70 V

2004 Feb 18 6

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

Notes

1. Non-repetitive current pulse 8/20 µs exponential decay waveform; see Fig.2.

2. Measured either across pins 1 and 3 or pins 2 and 3.

Rdiff differential resistance

PESD3V3S2UAT IR = 1 mA − − 400 Ω

PESD5V0S2UAT IR = 1 mA − − 80 Ω

PESD12VS2UAT IR = 1 mA − − 200 Ω

PESD15VS2UAT IR = 1 mA − − 225 Ω

PESD24VS2UAT IR = 0.5 mA − − 300 Ω

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

GRAPHICAL DATA

001aaa147

103

102

104

Ppp

(W)

tp (µs)

110

103

10 102

(1)

(2)

Fig.4 Peak pulse power dissipation as a function

of pulse time; typical values.

Tamb = 25 °C.

tp = 8/20 µs exponential decay waveform; see Fig.2.

(1) PESD3V3S2UAT and PESD5V0S2UAT.

(2) PESD12VS2UAT, PESD15VS2UAT, PESD24VS2UAT

Tj (°C)

0 20015050 100

001aaa193

0.4

0.8

1.2

PPP

PPP(25°C)

Fig.5 Relative var iation of peak puls e power as a

function of junction temperature; typical

values.

2004 Feb 18 7

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

VR (V)

054231

001aaa148

120

160

200

240

(pF)

(1)

(2)

Fig.6 Diode capacitance as a function of reverse

voltage; typical values.

Tamb = 25 °C; f = 1 MHz.

(1) PESD3V3S2UAT; VRWM = 3.3 V.

(2) PESD5V0S2UAT; VRWM = 5 V.

VR (V)

0252010 155

001aaa149

(pF)

(1)

(3)

(2)

Fig.7 Diode capacitance as a function of reverse

voltage; typical values.

Tamb = 25 °C; f = 1 MHz.

(1) PESD12VS2UAT; VRWM = 12 V.

(2) PESD15VS2UAT; VRWM = 15 V.

(3) PESD24VS2UAT; VRWM = 24 V.

2004 Feb 18 8

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

001aaa270

10−1

Tj (°C)

−100 150100050−50

IR(25˚C)

(1)

Fig.8 Relative variation of reverse leakag e

current as a func tion of junction

temperature; typical values.

IR is less than 10 nA at 150 °C for:

PESD12V52UAT; VRWM = 12 V.

PESD15VS2UAT; VRWM = 15 V.

PESD24VS2UAT; VRWM = 24 V.

(1) PESD3V3S2UAT; VRWM = 3.3 V.

PESD5V0S2UAT; VRWM = 5 V.

2004 Feb 18 9

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

001aaa15

450 Ω

50 Ω

Note 1: IEC61000-4-2 network

CZ = 150 pF; RZ = 330 Ω

D.U.T.: PESDxS2UAT

RG 223/U

50 Ω coax

ESD TESTER 4 GHz DIGITAL

OSCILLOSCOPE

10×

ATTENUATOR

vertical scale = 200 V/div

horizontal scale = 50 ns/div vertical scale = 20 V/div

horizontal scale = 50 ns/div

vertical scale = 200 V/div

horizontal scale = 50 ns/div vertical scale = 10 V/div

horizontal scale = 50 ns/div

GND

unclamped +1 kV ESD voltage waveform

(IEC61000-4-2 network) clamped +1 kV ESD voltage waveform

(IEC61000-4-2 network)

unclamped −1 kV ESD voltage waveform

(IEC61000-4-2 network) clamped −1 kV ESD voltage waveform

(IEC61000-4-2 network)

note 1

PESD24VS2UAT

PESD15VS2UAT

PESD12VS2UAT

PESD5V0S2L

PESD3V3S2UAT

Fig.9 ESD clamping test set-up an d waveforms.

2004 Feb 18 10

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

APPLICATION INFORMATION

The PESDxS2UAT series can protect up to two lines against damage caused by unidirectional ElectroStatic Discharge

(ESD) and surge pulses. The PESDxS2UAT series can protect lines whose signal polarities are below ground.

PESDxS2UAT series provide a surge capability of up to 330 Watts peak pulse power per line for a 8/20 µs waveform.

Circuit board layout and protection device placement

Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The

following guidelines are recommended:

1. Place the PESDxS2UAT as close as possible to the input terminal or connector.

2. Minimize the path length between the PESDxS2UAT and the protected line.

3. Keep parallel signal paths to a minimum.

4. Avoid running prote cted conductors in pa rallel with unprotec ted conductors.

5. Minimize all printed-ci rcuit board conductive loops including powe r and ground loops.

6. Minimize the length of transien t retur n paths to ground.

7. Avoid using shared trans i ent return paths to a common gro und point.

8. Ground planes should be used whenever possible.

9. Use vias for multi-layer printed-circuit boards.

001aaa17

PESDxS2UAT

line 1 to be protected

unidirectional protection

of two lines bidirectional protection

of one line

line 2 to be protected

ground

PESDxS2UAT

line 1 to be protecte

ground

Fig.10 Typical application: ESD protection of data lines.

2004 Feb 18 11

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

PACKAGE OUTLINE

UNIT A

max. b

cDE e

Qwv

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

04-11-04

06-03-16

IEC JEDEC JEITA

mm 0.1 0.48

0.38 0.15

0.09 3.0

2.8 1.4

1.2 0.95

1.9 2.5

2.1 0.55

0.45 0.1

0.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15

SOT23 TO-236AB

detail X

0 1 2 mm

scale

1.1

0.9

Plastic surface-mounted package; 3 leads SOT2

2004 Feb 18 12

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes

in SOT23 package PESDxS2UAT series

DATA SHEET STATUS

Notes

1. Please consult the most recently issued document before initiating or completing a design.

2. The product s ta tus of device(s ) described in this document may have changed since this document was published

and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

DOCUMENT

STATUS(1) PRODUCT

STATUS(2) DEFINITION

Objective data sheet Development This document contains data from the objective specification for pro duct

development.

Preliminary data sheet Qualification This document contains data from the preliminary specification.

Product data sheet Production T his document contains the product specification.

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Printed in The Netherlands R76/01/pp13 Date of release: 2004 Feb 18 Document order number: 9397 750 12247