ICS874002 - Integrated Circuit Systems, Inc.

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

GENERAL DESCRIPTION

The ICS874002 is a high performance Differential-

to-LVDS Jitter Attenuator designed for use in PCI

Express™ systems. In some PCI Express™

systems, such as those found in desktop PCs,

the PCI Express™ clocks are generated from a

low bandwidth, high phase noise PLL frequency synthesizer.

In these systems, a jitter attenuator may be required to

attenuate high frequency random and deterministic jitter

components from the PLL synthesizer and from the system

board. The ICS874002 has 3 PLL bandwidth modes:

200KHz, 400KHz, and 800KHz. The 200KHz mode will pro-

vide maximum jitter attenuation, but with higher PLL tracking

skew and spread spectrum modulation from the motherboard

synthesizer may be attenuated. 400KHz provides an

intermediate bandwidth that can easily track triangular

spread profiles, while providing good jitter attenuation.

800KHz bandwidth provides the best tracking skew and will

pass most spread profiles, but the jitter attenuation will not be

as good as the lower bandwidth modes. Because some 2.5

Gb serdes have x20 multipliers while others have than x25

multipliers, the 874002 can be set for 1:1 mode or 5/4

multiplication mode (i.e. 100MHz input/125MHz output) using

the F_SEL pin.

The ICS874002 uses ICS 3rd Generation FemtoClockTM

PLL technology to achieve the lowest possible phase noise.

The device is packaged in a 20 Lead TSSOP package, making

it ideal for use in space constrained applications such as PCI

Express™ add-in cards.

FEATURES

•(2) Differential LVDS output pairs

•(1) Differential clock input

•CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

•Output frequency range: 98MHz - 160MHz

•Input frequency range: 98MHz - 128MHz

•VCO range: 490MHz - 640MHz

•Cycle-to-cycle jitter: 50ps (maximum) design target

•3.3V operating supply

•3 bandwidth modes allow the system designer to make jitter

attenuation/tracking skew design trade-offs

•0°C to 70°C ambient operating temperature

HiPerClockS™

ICS

QA0

nQA0

BLOCK DIAGRAM

BW_SEL

0 = PLL Bandwidth: ~200KHz

Float = PLL Bandwidth: ~400KHz (Default)

1 = PLL Bandwidth: ~800KHz

PLL BANDWIDTH

0 ÷5

1 ÷4

÷5 (fixed)

VCO

490 - 640 MHz

Phase

Detector

(default)

F_SEL

BW_SEL

0 = ~200KHz

Float = ~400KHz

1 = ~800KHz

CLK

nCLK

FB_IN

nFB_IN

QA1

nQA1

FB_OUT

nFB_OUT

Float

PIN ASSIGNMENT

ICS874002

20-Lead TSSOP

6.5mm x 4.4mm x 0.92mm

package body

G Package

Top View

nQA0

VDDO

FB_OUT

nFB_OUT

BW_SEL

VDDA

F_SEL

VDD

QA0

VDDO

QA1

nQA1

nFB_IN

FB_IN

GND

nCLK

CLK

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

rebmuNemaNepyTnoitpircseD

02,10AQ,0AQntuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD

91,2V

ODD

rewoP.snipylppustuptuO

3TUO_BFtuptuO.tuptuokcabdeeflaitnereffidgnitrevni-noN

4TUO_BFntuptuO.tuptuokcabdeeflait

nereffidgnitrevnI

5RMtupnInwodlluP

erasredividlanretnieht,HGIHcigolnehW.teseRretsaMHGIHevitcA

stuptuodetrevniehtdnawologot)xQn(stuptuoeurtehtgnisuacteser

stuptuoehtdnasredividlanretnieht,WOLcigolnehW.hgihogot)

xQ(

.slevelecafretniLTTVL/SOMCVL.delbaneera

6LES_WBtupnI /pulluP

nwodlluP .slevelecafretniLTTVL/SOMCVL.tupni

htdiWdnaBLLPstceleS

7cndesunU.tcennocoN

ADD

rewoP.nipylppusgolanA

9LES_FtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.niptcelesycneuqerF

01V

rewoP.nipylppuseroC

11EOtupnIpulluP eht,WOLnehW.evitcaerastuptuoeht,HGIHnehW.nipelbanetuptuO

.slevelecafretn

iLTTVL/SOMCVL.etatsecnadepmihgihanierastuptuo

21KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN

31KLCntu

pnIpulluP.tupnikcolclaitnereffidgnitrevnI

41DNGrewoP.dnuorgylppusrewoP

51NI_BFtupnInwodlluP.tupnikcabdeeflaitner

effidgnitrevni-noN

61NI_BFntupnIpulluP.tupnikcabdeeflaitnereffidgnitrevnI

81,711AQ,1AQntuptuO.slevelecafretniS

DVL.riaptuptuolaitnereffiD

:ETON

pulluP

dna

nwodlluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15KΩ

NWODLLUP

rotsiseRnwodlluPtupnI 15KΩ

TABLE 3A. OUTPUT ENABLE FUNCTION TABLE TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL

stupnIstuptuO

EOxAQn/xAQTUO_BFn/TUO_BF

0ZiHdelbanE

1delbanEdelbanE

stupnI LLP

htdiwdnaB

LES_WB

0zHK002~

1zHK008~

taolFzHK004~

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5 V

Outputs, VO-0.5V to VDD + 0.5V

Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ADD

egatloVylppuSgolanA 531.33.3564.3V

ODD

egatloVylppuStuptuO 531.33.3564.3V

tnerruCylppuSrewoP 06Am

ADD

tnerruCylppuSgolanA 8Am

ODD

tnerruCylppuStuptuO 28Am

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI RM,EO,LES_F2V

3.0+V

LES_WBV

3.0-V

3.0+V

egatloVwoLtupnI RM,EO,LES_F3.0-8.0V

LES_WB3.0-3.0+V

tnerruChgiHtupnI

EOV

V564.3=5Aµ

,LES_WB

RM,LES_F V

V564.3=051Aµ

tupnItnerruCwoL LES_WB,EOV

V,V564.3=

V0=051-Aµ

RM,LES_FV

V,V564.3=

V0=5-Aµ

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

tnerruChgiHtupnI NI_BF,KLCV

V564.3=051Aµ

NI_BFn,KLCnV

V564.3=5 Aµ

tnerruCwoLtupnI NI_BF,KLCV

V564.3=051Aµ

NI_BFn,KLCnV

V564.3=051-Aµ

egatloVtupnIkaeP-ot-kaeP 51.03.1V

RMC

2,1ETON;egatloVtupnIedoMnommoC 5.0+DNGV

58.0-V

VsadenifedsiegatlovedomnommoC:1ETON

VsiNI_BFn,NI_BFdnaKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON

.V3.0+

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C

TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

XAM

ycneuqerFtuptuO89061zHM

)cc(tij1ETON,rettiJelcyC-ot-elcyC 31sp

emiTllaF/esiRtuptuO%08ot%02073sp

cdoelcyCytuDtuptuO 05%

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsih

T:1ETON

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVtuptuOlaitnereffiD 033Vm

∆V

egnahCedutingaM 05Vm

egatloVtesffO 03.1V

∆V

egnahCedutingaM 05Vm

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

CYCLE-TO-CYCLE JITTER

DIFFERENTIAL INPUT LEVEL3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

3.3V

CMR

Cross Points

GND

CLK,

FB_IN

nCLK,

nFB_IN

VDD

Clock

Outputs 20%

80% 80%

20%

SWING

DIFFERENTIAL OUTPUT VOLTAGE SETUP

Pulse Width

tPERIOD

tPW

tPERIOD

odc =

QA0,

QA1

nQA0,

nQA1

➤

QA0,

QA1

nQA0,

nQA1

jit(cc) =

cycle n –

cycle n+1

1000 Cycles

cycle n

cycle n+1

SCOPE

nQx

LVDS

POWER SUPPLY

Float GND

OFFSET VOLTAGE SETUP

OUTPUT RISE/FALL TIME

➤

100

out

LVDS

DC Input VOD/∆ VOD

VDD

out

LVDS

DC Input

➤

/∆ V

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

APPLICATION INFORMATION

Figure 2

shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

0.1u R2

Single Ended Clock Input

CLK

nCLK

VDD

POWER SUPPLY FILTERING T ECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS874002 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VDD, VDDA, and VDDO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 1

illustrates how

a 10Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each VDDA pin. FIGURE 1. POWER SUPPLY FILTERING

10Ω

VDDA

10µF

.01µF

3.3V

.01µF

VDD

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both VSWING and VOH must meet the

VPP and VCMR input requirements. Figures 3A to 3D show inter-

face examples for the HiPerClockS CLK/nCLK input driven by

the most common driver types. The input interfaces suggested

FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

here are examples only. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

For example in

Figure 3A,

the input termination applies for ICS

HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

from another vendor, use their termination recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

Zo = 50 Ohm

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

LVDS DRIVER T ERMINATION

A general LVDS interface is shown in

Figure 4.

In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

100 Ohm Differiential Transmission Line

100

3.3V

LVDS_Driv er

3.3V

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

un-used outputs.

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS874002 is: 1216

TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP

TABLE 7. PACKAGE DIMENSIONS

LOBMYS sretemilliM

NIMXAM

N02

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D04.606.6

ECISAB04.6

1E03.405.4

eCISAB56.0

L54.057.0

α°

0°8

aaa--01.0

Reference Document: JEDEC Publication 95, MO-153

Integrated

Circuit

Systems, Inc.

874002AG www.icst.com/products/hiperclocks.html REV. A JANUARY 19, 2005

ICS874002

PCI EXPRESS™

JITTER ATTENUATOR

PRELIMINARY

TABLE 8. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

The aforementioned trademarks, HiPerClockS™ and PCI ExpresS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

GA200478SCIGA200478SCIPOSSTdaeL02ebutC°07otC°0

TGA20

0478SCIGA200478SCIPOSSSTdaeL02leer&epat0052C°07otC°0