1
Precision, Low Noise FGA™ Voltage References
ISL21007
The ISL21007 FGA™ voltage references are extremely low
power, high precision, and low noise voltage references
fabricated on Intersil’s proprietary Floating Gate Analog
technology. The ISL21007 features very low noise (4.5µVP-P for
0.1Hz to 10Hz) and very low operating current (150µA, Max). In
addition, the ISL21007 family features guaranteed initial
accuracy as low as ±0.5mV.
This combination of high initial accuracy, low drift, and low
output noise performance of the ISL21007 enables versatile
high performance control and data acquisition applications
with low power consumption.
Available Options
Features
Reference Output Voltage . . . .1.250V, 2.048V, 2.500V, 3.000V
Initial Accuracy . . . . . . . . . . . . . . . . . . . . . . . ±0.5mV (B grade)
Input Voltage Range
ISL21007-12, 20, 25. . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
ISL21007-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2V to 5.5V
Low Output Voltage Noise. . . . . . . . 4.5µVP-P (0.1Hz to 10Hz)
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 150µA (Max)
Temperature Coefficient . . . . . . . . . . . . . . 3ppm/°C (B grade)
Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC
Pb-Free (RoHS Compliant)
Applications
High Resolution A/Ds and D/As
Digital Meters
Bar Code Scanners
•Basestations
Battery Management/Monitoring
Industrial/Instrumentation Equipment
Related Literature
AN1533, “X-Ray Effects on Intersil FGA References”
AN1494, “Reflow and PC Board Assembly Effects on Intersil
FGA References”
Pin Configuration
ISL21007
(8 LD SOIC)
TOP VIEW
PART
NUMBER
VOUT
OPTION
(V)
INITIAL
ACCURACY
(mV)
TEMPCO.
(ppm/°C)
ISL21007BFB812Z 1.250 ±0.5 3
ISL21007CFB812Z 1.250 ±1.0 5
ISL21007DFB812Z 1.250 ±2.0 10
ISL21007BFB820Z 2.048 ±0.5 3
ISL21007CFB820Z 2.048 ±1.0 5
ISL21007DFB820Z 2.048 ±2.0 10
ISL21007BFB825Z 2.500 ±0.5 3
ISL21007CFB825Z 2.500 ±1.0 5
ISL21007DFB825Z 2.500 ±2.0 10
ISL21007BFB830Z 3.000 ±0.5 3
ISL21007CFB830Z 3.000 ±1.0 5
ISL21007DFB830Z 3.000 ±2.0 10
GND or NC
VIN
DNC
GND
1
2
3
4
8
7
6
5
DNC
DNC
VOUT
TRIM
July 14, 2011
FN6326.8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2007, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL21007
2FN6326.8
July 14, 2011
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
VOUT OPTION
(V) GRADE
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free) PKG. DWG. #
ISL21007BFB812Z 21007BF Z12 1.250 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007CFB812Z 21007CF Z12 1.250 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007DFB812Z 21007DF Z12 1.250 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007BFB820Z 21007BF Z20 2.048 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007CFB820Z 21007CF Z20 2.048 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007DFB820Z 21007DF Z20 2.048 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007BFB825Z 21007BF Z25 2.500 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007CFB825Z 21007CF Z25 2.500 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007DFB825Z 21007DF Z25 2.500 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007BFB830Z 21007BF Z30 3.000 ±0.5mV, 3ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007CFB830Z 21007CF Z30 3.000 ±1.0mV, 5ppm/°C -40 to +125 8 Ld SOIC M8.15
ISL21007DFB830Z 21007DF Z30 3.000 ±2.0mV, 10ppm/°C -40 to +125 8 Ld SOIC M8.15
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL21007. For more information on MSL please see techbrief TB363.
ISL21007
3FN6326.8
July 14, 2011
Typical Application Circuit
Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
1 GND or NC Ground or No Connection
2 VIN Power Supply Input Connection
4GNDGround
5 TRIM Allows user trim VOUT ±2.5%
6 VOUT Voltage Reference Output Connection
3, 7, 8 DNC Do Not Connect; Internal Connection - Must Be Left Floating
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC
C1
0.001µF
C1
10µF
LOW NOISE DAC OUTPUT
ISL21007-12, 20, 25, 30
GND
GND
NC
NC
NC
TRIM
VOUT
VIN
1
2
3
4
8
7
6
5
+3V
X79000
SCK
A0
A1
A2
SI
SO
RDY
UP
DOWN
OE
CS
CLR
VCC
VH
VL
VREF
VSS
VOUT
VBUF
VFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SPI BUS
ISL21007
4FN6326.8
July 14, 2011
Absolute Voltage Ratings Thermal Information
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V
Max Voltage VOUT to GND (10s). . . . . . . . . . . . . . . . . . . . . . -0.5V to VOUT + 1
Voltage on “DNC” pins . . . . . . . . . No connections permitted to these pins.
ESD Rating
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600V
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Environmental Operating Conditions
X-Ray Exposure (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mRem
Thermal Resistance (Typical, Note 5) θJA (°C/W)
8 Ld SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.12
Continuous Power Dissipation (Note 5) . . . . . . . . . . . . . . . . . . . .TA = +70°C
8 Ld SOIC Derate 5.88mW/°C above +70°C. . . . . . . . . . . . . . . . . . 471mW
Pb-Free Reflow Profile (Note 6). . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted,
all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTES:
4. Measured with no filtering, distance of 10” from source, intensity set to 55kV and 70mA current, 30s duration. Other exposure levels should be
analyzed for Output Voltage drift effects. See “Applications Information” on page 16.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. Post-reflow drift for the ISL21007 devices will range from 100µV to 1.0mV based on experimental results with devices on FR4 double sided boards.
The design engineer must take this into account when considering the reference voltage after assembly.
Common Electrical Specifications (ISL21007-12, -20, -25, -30) TA = -40°C to +125°C, unless otherwise
specified. Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
VOA VOUT Accuracy @ TA = +25°C ISL21007B -0.5 +0.5 mV
ISL21007C -1.0 +1.0 mV
ISL21007D -2.0 +2.0 mV
TC VOUT Output Voltage Temperature
Coefficient (Note NOTES:)
ISL21007B 3 ppm/°C
ISL21007C 5ppm/°C
ISL21007D 10 ppm/°C
IIN Supply Current 75 150 µA
Trim Range ±2.0 ±2.5 %
tRTurn-on Settling Time VOUT = ±0.1% 120 µs
Ripple Rejection f = 10kHz 60 dB
eNOutput Voltage Noise 0.1Hz f 10Hz 4.5 µVP-P
VNBroadband Voltage Noise 10Hz f 1kHz 2.2 µVRMS
Noise Density f = 1kHz 60 nV/Hz
Electrical Specifications (ISL21007-12, VOUT = 1.250V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise
specified. Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
VIN Input Voltage Range 2.7 5.5 V
VOUT Output Voltage 1.250 V
ΔVOUT /ΔVIN Line Regulation 2.7V < VIN < 5.5V 100 700 µV/V
ISL21007
5FN6326.8
July 14, 2011
ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA IOUT 7mA 10 100 µV/mA
Sinking: -7mA IOUT 0mA 20 150 µV/mA
ISC Short Circuit Current TA = +25°C, VOUT tied to GND 40 mA
ΔVOUT/ΔTAThermal Hysteresis (Note 8) ΔTA = +165°C 50 ppm
ΔVOUT/Δt Long Term Stability (Note 9) TA = +25°C 100 ppm
Electrical Specifications (ISL21007-12, VOUT = 1.250V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise
specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
Electrical Specifications (ISL21007-20, VOUT = 2.048V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise
specified. Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
VIN Input Voltage Range 2.7 5.5 V
VOUT Output Voltage 2.048 V
ΔVOUT /ΔVIN Line Regulation 2.7V < VIN < 5.5V 50 200 µV/V
ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA IOUT 7mA 10 100 µV/mA
Sinking: -7mA IOUT 0mA 20 150 µV/mA
ISC Short Circuit Current TA = +25°C, VOUT tied to GND 50 mA
ΔVOUT/ΔTAThermal Hysteresis (Note 8) ΔTA = +165°C 50 ppm
ΔVOUT/Δt Long Term Stability (Note 9) TA = +25°C 75 ppm
Electrical Specifications (ISL21007-25, VOUT = 2.500V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
VIN Input Voltage Range 2.7 5.5 V
VOUT Output Voltage 2.500 V
ΔVOUT /ΔVIN Line Regulation 2.7V < VIN < 5.5V 50 200 µV/V
ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA IOUT 5mA 10 100 µV/mA
Sinking: -5mA IOUT 0mA 20 150 µV/mA
ISC Short Circuit Current TA = +25°C, VOUT tied to GND 50 mA
ΔVOUT/ΔTAThermal Hysteresis (Note 8) ΔTA = +165°C 50 ppm
ΔVOUT/Δt Long Term Stability (Note 9) TA = +25°C 50 ppm
Electrical Specifications (ISL21007-30, VOUT = 3.000V) VIN = 5.0V, TA = -40°C to +125°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
VIN Input Voltage Range 3.2 5.5 V
VOUT Output Voltage 3.000 V
ΔVOUT /ΔVIN Line Regulation 3.2V < VIN < 5.5V 50 200 µV/V
ΔVOUT/ΔIOUT Load Regulation Sourcing: 0mA IOUT 7mA 10 100 µV/mA
Sinking: -7mA IOUT 0mA 20 150 µV/mA
ISL21007
6FN6326.8
July 14, 2011
ISC Short Circuit Current TA = +25°C, VOUT tied to GND 50 mA
ΔVOUT/ΔTAThermal Hysteresis (Note 8) ΔTA = +165°C 50 ppm
ΔVOUT/Δt Long Term Stability (Note 9) TA = +25°C 50 ppm
NOTES:
7. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the
temperature range; in this case, -40°C to +125°C = +165°C.
8. Thermal Hysteresis is the change of VOUT measured at TA = +25°C after temperature cycling over a specified range, ΔTA. VOUT is read initially at
TA = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference between
the initial VOUT reading and the second VOUT reading is then expressed in ppm. For Δ TA = +165°C, the device under test is cycled from +25°C to
+125°C to -40°C to +25°C.
9. Long term drift is logarithmic in nature and diminishes over time. Drift after the first 1000 hours will be approximately 10ppm/(1kHrs).
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications (ISL21007-30, VOUT = 3.000V) VIN = 5.0V, TA = -40°C to +125°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10) UNIT
ISL21007
7FN6326.8
July 14, 2011
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)
FIGURE 2. IIN vs VIN (3 UNITS) FIGURE 3. IIN vs VIN OVER TEMPERATURE
FIGURE 4. LINE REGULATION (3 UNITS) FIGURE 5. LINE REGULATION OVER TEMPERATURE
FIGURE 6. LOAD REGULATION OVER TEMPERATURE FIGURE 7. VOUT vs TEMPERATURE (3 UNITS)
0
20
40
60
80
100
120
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VIN (V)
IIN (µA)
UNIT 3
UNIT 1
UNIT 2
60
65
70
75
80
85
90
95
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V)
IIN (µA)
+125°C
+25°C
-40°C
1.24980
1.24985
1.24990
1.24995
1.25000
1.25005
1.25010
1.25015
VOUT (V)
(NORMALIZED TO 1.250V AT VIN = 3.0V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V)
UNIT 3
UNIT 1
UNIT 2
-300
-250
-200
-150
-100
-50
0
50
100
150
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VIN (V)
ΔVO (µV)
(NORMALIZED TO VIN = 3.0V)
+125°C
+25°C -40°C
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
-7 -6 -5 -4 -3 -2 -1 0 1
SINKING SOURCING
ΔVOUT (mV)
234567
OUTPUT CURRENT (mA)
+125°C
+25°C
-40°C
1.24975
1.24980
1.24985
1.24990
1.24995
1.25000
1.25005
1.25010
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
VOUT (V)
UNIT 2
UNIT 1
UNIT 3
ISL21007
8FN6326.8
July 14, 2011
FIGURE 8. PSRR vs CAPACITIVE LOADS FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FIGURE 10. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 11. TURN-ON TIME
FIGURE 12. ZOUT vs FREQUENCY FIGURE 13. VOUT NOISE, 0.1Hz TO 10Hz
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) (Continued)
-100
-80
-60
-40
-20
0
1.00E+00 1.00E+02 1.00E+04 1.00E+0
FREQUENCY (Hz)
PSRR (dB)
1nF LOAD
100nF LOAD
10nF LOAD
1µF LOAD
NO LOAD
Y: 10µs/DIV
X: 200mV/DIV
ΔVIN = -0.3V
ΔVIN = +0.3V
Y: 10µs/DIV
X: 200mV/DIV
ΔVIN = -0.3V
ΔVIN = +0.3V
VIN
VOUT = 1.25V
X: 20µs/DIV
Y: 1V/DIV
0
20
40
60
80
100
120
140
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
FREQUENCY (Hz)
ZOUT (Ω)
NO LOAD
1nF
10nF
100nF
2mV/DIV
GAIN IS x1000,
NOISE IS 4.5µVP-P
ISL21007
9FN6326.8
July 14, 2011
FIGURE 14. LOAD TRANSIENT RESPONSE
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) (Continued)
NO OUTPUT CAPACITANCE
+7mA
-7mA
X: 50µs/DIV
Y: 1V/DIV
Typical Performance Curves (ISL21007-20) (REXT = 100kΩ)
FIGURE 15. IIN vs VIN (3 UNITS) FIGURE 16. IIN vs VIN OVER TEMPERATURE
FIGURE 17. LINE REGULATION (3 UNITS) FIGURE 18. LINE REGULATION OVER TEMPERATURE
65
70
75
80
85
90
95
2.73.13.53.94.34.75.15.5
VIN (V)
IIN (µA)
UNIT 3
UNIT 2
UNIT 1
50
55
60
65
70
75
80
85
90
95
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VIN (V)
IIN (uA)
+125°C
-40°C
+25°C
2.04790
2.04795
2.04800
2.04805
2.04810
2.04815
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN(V)
VOUT (V) NORMALIZED TO 2.048V AT
VIN = 3.0V
UNIT 1
UNIT 3
UNIT 2
2.04795
2.04800
2.04805
2.04810
2.04815
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN(V)
+125°C
+25°C
-40°C
VOUT (V)
(NORMALIZED TO 2.048V AT VIN = 3V)
ISL21007
10 FN6326.8
July 14, 2011
FIGURE 19. LOAD REGULATION OVER TEMPERATURE FIGURE 20. VOUT vs TEMPERATURE (3 UNITS)
FIGURE 21. PSRR vs CAPACITIVE LOADS FIGURE 22. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FIGURE 23. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 24. TURN-ON TIME
Typical Performance Curves (ISL21007-20) (REXT = 100kΩ) (Continued)
-1.2
-0.8
-0.4
0.0
0.4
0.0
1.2
1.6
-7 -6 -5 -4 -3 -2 -1
Δ VOUT (mV) NORMALIZED TO 0mA
0 123456 7
+25°C
-40°C
+125°C
SINKING SOURCINGOUTPUT CURRENT (mA)
2.0472
2.0476
2.0480
2.0484
2.0488
2.0492
2.0496
-40-25-10 5 203550658095110125
TEMPERATURE (°C)
VOUT(V) NORMALIZED TO 2.048V AT +25°C
UNIT 2 UNIT 1
UNIT 3
-100
-80
-60
-40
-20
0
1.0E+01 1.0E+03 1.0E+05
FREQUENCY (Hz)
PSRR (dB)
100nF LOAD
10nF LOAD
1µF LOAD
NO LOAD
Y: 10µs/DIV
X: 200mV/DIV
ΔVIN = -0.3V
ΔVIN = +0.3V
Y: 10µs/DIV
X: 200mV/DIV
ΔVIN = -0.3V
ΔVIN = +0.3V
X: 100µs/DIV
Y: 2V/DIV
VIN
VOUT = 2.048V
ISL21007
11 FN6326.8
July 14, 2011
FIGURE 25. ZOUT VS FREQUENCY FIGURE 26. VOUT NOISE, 0.1Hz TO 10Hz
FIGURE 27. LOAD TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 28. LOAD TRANSIENT RESPONSE, NO CAPACITIVE LOAD
Typical Performance Curves (ISL21007-20) (REXT = 100kΩ) (Continued)
0
20
40
60
80
100
120
140
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
FREQUENCY (Hz)
ZOUT (Ω)
NO LOAD
1nF
10nF
100nF
GAIN IS x1000,
NOISE IS 4.5µVP-P
2mV/DIV
X: 20µs/DIV
Y: 200mV/DIV
+7mA
-7mA
X: 20µs/DIV
Y: 200mV/DIV +7mA
-7mA
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)
FIGURE 29. IIN vs VIN (3 UNITS) FIGURE 30. IIN vs VIN OVER TEMPERATURE
0
20
40
60
80
100
120
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VIN (V)
IIN (µA)
UNIT 3
UNIT 2
UNIT 1
60
65
70
75
80
85
90
95
100
2.5 3.0 4.0 4.5 5.0 5.5
VIN (V)
IIN (µA)
3.5
+125°C
+25°C
-40°C
ISL21007
12 FN6326.8
July 14, 2011
FIGURE 31. LINE REGULATION (3 UNITS) FIGURE 32. LINE REGULATION OVER TEMPERATURE
FIGURE 33. LOAD REGULATION OVER TEMPERATURE FIGURE 34. VOUT vs TEMPERATURE (3 UNITS)
FIGURE 35. PSRR vs CAPACITIVE LOADS FIGURE 36. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued)
2.4996
2.4997
2.4998
2.4999
2.5000
2.5001
2.5002
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V)
VOUT (V)
(NORMALIZED TO 2.500V AT VIN = 3V)
UNIT 1
UNIT 2
UNIT 3
-400
-350
-300
-250
-200
-150
-100
-50
0
50
100
2.5 3.0 3.5 4.5 5.0 5.5
VIN (V)
ΔVO (µV)
(NORMALIZED TO VIN = 3.0V)
4.0 6.0
+125°C
+25°C
-40°C
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
-7 -2 1 2 3 4 5 6 7
ΔVOUT (mV)
-6 -5 -4 -3 -1 0
+125°C
-40°C
+25°C
SINKING SOURCINGOUTPUT CURRENT (mA)
2.4993
2.4994
2.4995
2.4996
2.4997
2.4998
2.4999
2.5000
2.5001
2.5002
2.5003
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
V
OUT
(V)
UNIT 1
UNIT 2
UNIT 3
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
1.E+00 1.E+02 1.E+04 1.E+06
FREQUENCY (Hz)
PSRR (dB)
10nF
NO LOAD
1nF
100nF
1µF
Y: 10µs/DIV
X: 200mV/DIV
ΔVIN = -0.3V
ΔVIN = +0.3V
ISL21007
13 FN6326.8
July 14, 2011
FIGURE 37. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 38. TURN-ON TIME
FIGURE 39. ZOUT vs FREQUENCY FIGURE 40. VOUT NOISE, 0.1Hz TO 10Hz
FIGURE 41. LOAD TRANSIENT RESPONSE
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued)
Y: 10µs/DIV
X: 200mV/DIV
ΔVIN = -0.3V
ΔVIN = +0.3V
VIN
VOUT = 2.5V
X: 20µs/DIV
Y: 1V/DIV
0
20
40
60
80
100
120
140
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
FREQUENCY (Hz)
ZOUT (Ω)
NO LOAD
1nF
10nF
100nF
2mV/DIV
GAIN IS x1000,
NOISE IS 4.5µVP-P
NO OUTPUT CAPACITANCE
+5mA
-5mA
X: 50µs/DIV
Y: 500mV/DIV
ISL21007
14 FN6326.8
July 14, 2011
Typical Performance Curves (ISL21007-30) (REXT = 100kΩ)
FIGURE 42. IIN vs VIN (3 UNITS) FIGURE 43. IIN vs VIN OVER TEMPERATURE
FIGURE 44. LINE REGULATION (3 UNITS) FIGURE 45. LINE REGULATION OVER TEMPERATURE
FIGURE 46. LOAD REGULATION OVER TEMPERATURE FIGURE 47. VOUT vs TEMPERATURE (3 UNITS)
0
20
40
60
80
100
120
3.2 3.7 4.2 4.7 5.2
VIN (V)
IIN (µA)
UNIT 3
UNIT 2
UNIT 1
0
20
40
60
80
100
120
3.2 3.7 4.2 4.7 5.2
VIN (V)
IIN (µA)
+125°C
+25°C -40°C-40°C
2.9955
2.9965
2.9975
2.9985
2.9995
3.0005
3.2 3.6 4.0 4.4 4.8 5.2 5.6
VIN (V)
VOUT(V) NORMALIZED TO 3.0V AT
5.0VIN
UNIT 3
UNIT 2
UNIT 1
2.994
2.995
2.996
2.997
2.998
2.999
3.000
3.001
3.2 3.6 4.0 4.4 4.8 5.2 5.6
VIN (V)
VOUT (V) NORMALIZED TO 3.0V AT
5.0VIN
+125°C
-40°C
+25°C
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
-7 -6 -5 -4 -3 -2 -1
SINKING LOAD (mA) SOURCING
Δ VOUT (mV) NORMALIZED TO
0mA
01 234 56 7
-40°C
+25°C
+125°C
2.9990
2.9992
2.9994
2.9996
2.9998
3.0000
3.0002
3.0004
3.0006
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
VOUT (V) NORMALIZED TO 3.0V AT +25°C
UNIT 3
UNIT 2
UNIT 1
ISL21007
15 FN6326.8
July 14, 2011
FIGURE 48. PSRR vs CAPACITIVE LOADS FIGURE 49. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FIGURE 50. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 51. TURN-ON TIME
FIGURE 52. ZOUT vs FREQUENCY FIGURE 53. VOUT NOISE, 0.1Hz TO 10Hz
Typical Performance Curves (ISL21007-30) (REXT = 100kΩ) (Continued)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
1.E+00 1.E+02 1.E+04 1.E+06
FREQUENCY (Hz)
PSRR (dB)
10nF
NO LOAD
1nF
100nF
1µF
VIN (DC) = 5.0V
VIN (AC) = 50mVP-P
Y: 10µs/DIV
X: 200mV/DIV
ΔVIN = -0.5V
ΔVIN = +0.5V
Y: 10µs/DIV
X: 200mV/DIV
ΔVIN = -0.5V
ΔVIN = +0.5V
VIN = 5.0V
VOUT = 3.0V
20µs/DIV
1V/DIV
0
20
40
60
80
100
120
140
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
FREQUENCY (Hz)
ZOUT (Ω)
NO LOAD
1nF
10nF
100nF
2mV/DIV
GAIN IS x1000,
NOISE IS 4.5µVP-P
ISL21007
16 FN6326.8
July 14, 2011
Applications Information
FGA Technology
The ISL21007 voltage reference uses floating gate technology to
create references with very low drift and supply current.
Essentially, the charge stored on a floating gate cell is set
precisely in manufacturing. The reference voltage output itself is
a buffered version of the floating gate voltage. The resulting
reference device has excellent characteristics which are unique
in the industry: very low temperature drift, high initial accuracy,
and almost zero supply current. Also, the reference voltage itself
is not limited by voltage bandgaps or zener settings, so a wide
range of reference voltages can be programmed (standard
voltage settings are provided, but customer-specific voltages are
available).
The process used for these reference devices is a floating gate
CMOS process, and the amplifier circuitry uses CMOS transistors
for amplifier and output transistor circuitry. While providing
excellent accuracy, there are limitations in output noise level and
load regulation due to the MOS device characteristics. These
limitations are addressed with circuit techniques discussed in
other sections.
Micropower Operation
The ISL21007 consumes extremely low supply current due to the
proprietary FGA technology. Low noise performance is achieved
using optimized biasing techniques. Supply current is typically
75µA and noise is 4.5µVP-P benefitting precision, low noise
portable applications such as handheld meters and instruments.
Data Converters in particular can utilize the ISL21007 as an
external voltage reference. Low power DAC and ADC circuits will
realize maximum resolution with lowest noise.
Handling and Board Mounting
FGA references provide excellent initial accuracy and low
temperature drift at the expense of very little power drain. There
are some precautions to take to insure this accuracy is not
compromised. Excessive heat during solder reflow can cause
excessive initial accuracy drift, so the recommended +260°C
max temperature profile should not be exceeded. Expect up to
1mV drift from the solder reflow process.
FGA references are susceptible to excessive X-radiation like that
used in PC board manufacturing. Initial accuracy can change
10mV or more under extreme radiation. If an assembled board
needs to be X-rayed, care should be taken to shield the FGA
reference device.
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting
location should be reviewed. Placing the device in areas subject to
slight twisting can cause degradation of the accuracy of the
reference voltage due to die stresses. It is normally best to place the
device near the edge of a board, or the shortest side, as the axis of
bending is most limited at that location. Obviously, mounting the
device on flexprint or extremely thin PC material will likewise cause
loss of reference accuracy.
Board Assembly Considerations
FGA references provide high accuracy and low temperature drift
but some PC board assembly precautions are necessary. Normal
Output voltage shifts of 100µV to 1mV can be expected with Pb-
free reflow profiles or wave solder on multi-layer FR4 PC boards.
Precautions should be taken to avoid excessive heat or extended
exposure to high reflow or wave solder temperatures, this may
reduce device initial accuracy.
Post-assembly x-ray inspection may also lead to permanent
changes in device output voltage and should be minimized or
avoided. If x-ray inspection is required, it is advisable to monitor
the reference output voltage to verify excessive shift has not
occurred. If large amounts of shift are observed, it is best to add
an X-ray shield consisting of thin zinc (300µm) sheeting to allow
clear imaging, yet block x-ray energy that affects the FGA
reference.
Special Applications Considerations
In addition to post-assembly examination, there are also other X-
ray sources that may affect the FGA reference long term
accuracy. Airport screening machines contain X-rays and will
FIGURE 54. LOAD TRANSIENT RESPONSE
Typical Performance Curves (ISL21007-30) (REXT = 100kΩ) (Continued)
+7mA
-7mA
100µs/DIV
200mV/DIV
ISL21007
17 FN6326.8
July 14, 2011
have a cumulative effect on the voltage reference output
accuracy. Carry-on luggage screening uses low level X-rays and is
not a major source of output voltage shift, however, if a product is
expected to pass through that type of screening over 100 times,
it may need to consider shielding with copper or aluminum.
Checked luggage X-rays are higher intensity and can cause
output voltage shift in much fewer passes, thus devices expected
to go through those machines should definitely consider
shielding. Note that just two layers of 1/2 ounce copper planes
will reduce the received dose by over 90%. The leadframe for the
device which is on the bottom also provides similar shielding.
If a device is expected to pass through luggage X-ray machines
numerous times, it is advised to mount a 2-layer (minimum) PC
board on the top, along with a ground plane underneath, which will
effectively shield it from 50 to 100 passes through the machine.
Since these machines vary in X-ray dose delivered, it is difficult to
produce an accurate maximum pass recommendation.
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically
4.5µVP-P
. The noise measurement is made with a bandpass filter
made of a 1-pole high-pass filter with a corner frequency at 0.1Hz
and a 2-pole low-pass filter with a corner frequency at 12.6Hz to
create a filter with a 9.9Hz bandwidth. Noise in the 10kHz to 1MHz
bandwidth is approximately 40µVP-P with no capacitance on the
output. This noise measurement is made with a 2 decade
bandpass filter made of a 1-pole high-pass filter with a corner
frequency at 1/10 of the center frequency and 1-pole low-pass
filter with a corner frequency at 10 times the center frequency.
Load capacitance up to 1000pF can be added but will result in
only marginal improvements in output noise and transient
response. The output stage of the ISL21007 is not designed to
drive heavily capacitive loads, so for load capacitances above
0.001µF, the noise reduction network shown in Figure 55 is
recommended. This network reduces noise significantly over the
full bandwidth. Noise is reduced to less than 20µVP-P from 1Hz to
1MHz using this network with a 0.01µF capacitor and a 2kΩ
resistor in series with a 10µF capacitor. Also, transient response is
improved with higher value output capacitor. The 0.01µF value can
be increased for better load transient response with little sacrifice
in output stability.
Turn-On Time
The ISL21007 devices have low supply current and thus the time
to bias up internal circuitry to final values will be longer than with
higher power references. Normal turn-on time is typically 120µs.
This is shown in Figure 10. Circuit design must take this into
account when looking at power-up delays or sequencing.
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are governed
by the method of measurement. The overwhelming standard for
specifying the temperature drift of a reference is to measure the
reference voltage at two temperatures, take the total variation,
(VHIGH – VLOW), and divide by the temperature extremes of
measurement (THIGH –T
LOW). The result is divided by the nominal
reference voltage (at T = +25°C) and multiplied by 106 to yield
ppm/°C. This is the “Box” method for specifying temperature
coefficient.
Output Voltage Adjustment
The output voltage can be adjusted up or down by 2.5% by placing a
potentiometer from VOUT to ground, and connecting the wiper to the
TRIM pin. The TRIM input is high impedance, so no series resistance
is needed. The resistor in the potentiometer should be a low tempco
(<50ppm/°C) and the resulting voltage divider should have very low
tempco <5ppm/°C. A digital potentiometer such as the ISL95810
provides a low tempco resistance and excellent resistor and tempco
matching for trim applications. See Figure 59 and TB473 for further
information.
VIN = 5.0V
VIN
VO
GND
ISL21007
0.01µF
10µF
2kΩ
0.1µF
10µF
FIGURE 55. HANDLING HIGH LOAD CAPACITANCE
ISL21007
18 FN6326.8
July 14, 2011
Typical Application Circuits
FIGURE 56. PRECISION 2.500V 50mA REFERENCE
FIGURE 57. 2.500V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
FIGURE 58. KELVIN SENSED LOAD
VIN = +5.0V
2N2905
2.5V/50mA
0.001µF
VIN
VOUT
GND
ISL21007
R = 200Ω
VOUT = 2.500V
VIN
VOUT
GND
+2.7 TO 5.5V
0.1µF
0.001µF
VOUT
+
VCC RH
RL
X9119
VSS
SDA
SCL
2-WIRE BUS VOUT
(BUFFERED)
10µF
ISL21007-25
VOUT = 2.500V
EL8178
(UNBUFFERED)
0.1µF
+2.7 TO 5.5V
VIN
VOUT
GND
ISL21007-12
VOUT SENSE
LOAD
+
10µF
EL8178
ISL21007
19
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6326.8
July 14, 2011
For additional products, see www.intersil.com/product_tree
FIGURE 59. OUTPUT ADJUSTMENT USING THE TRIM PIN
Typical Application Circuits (Continued)
0.1µF
+2.7 TO 5.5V
VIN
VOUT
GND
ISL21007-12
10µF
TRIM
2.5V ±2.5%
RL
VSS
SDA
SCL
I2C BUS
VCC RH
ISL95810
ISL21007
20 FN6326.8
July 14, 2011
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/11
DETAIL "A"
TOP VIEW
INDEX
AREA
123
-C-
SEATING PLANE
x 45°
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
SIDE VIEW “A
SIDE VIEW “B”
1.27 (0.050)
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
0.50 (0.20)
0.25 (0.01)
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
0.25 (0.010)
0.19 (0.008)
1.27 (0.050)
0.40 (0.016)
1.27 (0.050)
5.20(0.205)
1
2
3
45
6
7
8
TYPICAL RECOMMENDED LAND PATTERN
2.20 (0.087)
0.60 (0.023)